Semiconductor device and method of manufacturing the same

Abstract

A method of manufacturing a semiconductor device includes receiving a workpiece having a first stack of semiconductor layers in a first region and a second stack of semiconductor layers in a second region; forming a first gate dielectric layer surrounding each layer of the first stack and a second gate dielectric layer surrounding each layer of the second stack; forming a first dipole layer surrounding the first gate dielectric layer and fusing between vertically adjacent portions of the first gate dielectric layer and a second dipole layer surrounding the second gate dielectric layer and fusing between vertically adjacent portions of the second gate dielectric layer; removing the first dipole layer; performing a first anneal on the workpiece after removing the first dipole layer; removing remaining portions of the second dipole layer; and forming a gate electrode layer in the first region and the second region.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device, and more particularly to a semiconductor device using a p-type dipole material. Background Technology

[0002] The electronics industry has experienced a continuous increase in demand for smaller and faster electronic devices, while simultaneously needing to support increasingly complex and sophisticated functions. To meet these demands, the integrated circuit (IC) industry has consistently pursued the manufacture of low-cost, high-performance, and low-power ICs. To date, these goals have been largely achieved by reducing IC size (e.g., the smallest IC feature size), thereby improving production efficiency and reducing related costs. However, this miniaturization also increases the complexity of IC manufacturing processes. Therefore, similar advancements in IC manufacturing processes and technologies are needed to achieve continued progress in IC devices and their performance.

[0003] Nanosheet-based devices (sometimes also called gate-all-around devices, multi-bridge channel devices, etc.) are promising candidates to lead MOS to the next stage of its technical roadmap due to their superior gate control, lower leakage current, and full compatibility with FinFET devices. However, the complex device structure and reduced spacing between features can make achieving certain functionalities challenging, such as providing multiple threshold voltages without penalizing other performance characteristics. Therefore, while conventional techniques often perform as intended, they are not entirely satisfactory in every respect. Summary of the Invention

[0004] This disclosure provides a method for manufacturing a semiconductor device. The method includes receiving a workpiece having a first stack of multiple first semiconductor layers in a first region and a second stack of multiple second semiconductor layers in a second region; forming a first gate dielectric layer and a second gate dielectric layer, the first gate dielectric layer surrounding each of the multiple first semiconductor layers of the first stack, and the second gate dielectric layer surrounding each of the multiple second semiconductor layers of the second stack; forming a first dipole layer and a second dipole layer, the first dipole layer surrounding the first gate dielectric layer and fused between vertically adjacent portions of the first gate dielectric layer, and the second dipole layer surrounding the second gate dielectric layer and fused between vertically adjacent portions of the second gate dielectric layer; removing the first dipole layer; performing a first annealing on the workpiece after removing the first dipole layer; removing the remaining portion of the second dipole layer; and forming a gate electrode layer in the first region and the second region.

[0005] This disclosure provides a method for manufacturing a semiconductor device. The method includes receiving a semiconductor device having a plurality of substrate regions, each of the plurality of substrate regions having a stack of a plurality of channel layers thereon; forming a plurality of interface layers that surround each of the channel layers in each of the plurality of substrate regions; forming a plurality of gate dielectric layers that surround each of the interface layers in each of the plurality of substrate regions; forming a first dipole layer that surrounds a plurality of gate dielectric layers in a first subset of the plurality of substrate regions, wherein the first dipole layer has a p-type dipole material and fills the space between perpendicularly adjacent channel layers; performing a first thermal processing step to form a plurality of first-doped gate dielectric layers in the first subset of the plurality of substrate regions; removing the remaining portion of the first dipole layers; and forming gate electrode layers surrounding the plurality of first-doped gate dielectric layers.

[0006] This disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate; a first stack of a plurality of first channel layers and a second stack of a plurality of second channel layers, located on the semiconductor substrate; a first gate dielectric layer, comprising a plurality of thin layers surrounding the first stack of the plurality of first channel layers, the first gate dielectric layer comprising a p-type dipole material; a second gate dielectric layer, comprising a plurality of thin layers surrounding the second stack of the plurality of second channel layers, the second gate dielectric layer comprising an n-type dipole material; and a gate electrode located on the first gate dielectric layer and on the second gate dielectric layer. Attached Figure Description

[0007] This disclosure will be better understood from the following embodiments and accompanying drawings. It should be emphasized that, in accordance with industry standard practice, the various features are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of illustration.

[0008] Figure 1 This is a flowchart illustrating a method for manufacturing a semiconductor device according to various embodiments of the present disclosure.

[0009] Figure 2A This is a schematic top view of a portion of a semiconductor device as shown in various embodiments of the present disclosure.

[0010] Figure 2B and Figure 2C As shown in the embodiments of this disclosure, Figure 2A A schematic cross-sectional view of a portion of a semiconductor device.

[0011] Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 and Figure 13 As shown in the various forms disclosed herein, Figure 2A A portion of a semiconductor device is manufactured at multiple process stages (e.g., with... Figure 1 A schematic cross-sectional view of the process stages related to the method.

[0012] Figure 14 This is a flowchart illustrating a method for manufacturing a semiconductor device according to various embodiments of the present disclosure.

[0013] Figure 15 , Figure 16A , Figure 16B , Figure 16C , Figure 17A , Figure 17B , Figure 17C and Figure 18 As shown in the various forms disclosed herein, Figure 2A A portion of a semiconductor device is manufactured at multiple process stages (e.g., with... Figure 14 A schematic cross-sectional view of the process stages related to the method.

[0014] Figure 19A and Figure 19B The relationship between critical voltage regulation capability and custom program parameters is shown.

[0015] Figure 19C According to embodiments of this disclosure, an elemental distribution within a specific thin layer of a semiconductor device is shown.

[0016] The reference numerals in the attached figures are explained as follows: 100: Method 102~122: Operation A1: Route A2: Route 200: Semiconductor devices 200A: Equipment Area 200B: Equipment Area 204A: Active Zone 204B: Active Zone 206A: Gate region 206B: Gate region 231: Dielectric fins A1-A1, B1-B1: line segments A2-A2, B2-B2: line segments 202: Substrate 215: Channel Layer 230: Isolation Features 232: Dielectric Pad 233: Dielectric filling layer 234: Dielectric cap 247: Gate spacer 255: Internal spacers 260: S / D characteristics 268: Contact Etching Stop Layer 270: ILD layer 275: Gate Trench 277A: Clearance 277B: Gap d0: Distance d3: Distance h0: Vertical spacing h1: Size H1: Distance t0: Width dimension t1: Thickness dimension t2: Thickness dimension w0: Horizontal width w1: Size w2: Horizontal spacing w3: Horizontal spacing 280: Interface Layer 282: High k-value gate dielectric layer 284: Dipole layer 288: Dielectric layer 290: Patterned photoresist 600: Heat treatment process 282': High k-value gate dielectric layer 285: High k-value gate dielectric layer 287: Overlay 286: Gate electrode layer 300A, 300A': Area 300B, 300B': Area 500: Methods 502~506: Operation 508A~512A: Operation 508B~512B: Operation 514~518: Operation 400: Semiconductor Device 402a: Equipment Area 402b: Equipment Area 1402A, 1402A': Subregions 1402B, 1402B': Subregion 284a: Dipole layer 288': Hard mask layer 282'': High k-value gate dielectric layer 600A: Heat treatment process 284b: Dipole layer 600B: Heat treatment process 295: Boundary Surface 297: Boundary Surface 299: Artificial Plane Detailed Implementation

[0017] The following disclosure provides numerous different embodiments or examples for implementing various features of this disclosure. Specific examples of the components and arrangements of this disclosure are described below for simplification. Naturally, these examples are not intended to limit this disclosure. For example, if the description states that a first feature is formed on or above a second feature, it may include embodiments where the first and second features are in direct contact, or embodiments where an additional feature is formed between the first and second features, so that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples of this disclosure. This repetition is for simplification and clarity and does not inherently define the relationships between the various embodiments and / or configurations discussed.

[0018] Furthermore, this disclosure may use spatial relative terms, such as "below," "below," "lower than," "above," "higher than," and similar words, to describe the relationship between one element or feature and other elements or features in the figures. In addition to the orientations depicted in the figures, spatial relative terms are also intended to cover different orientations of the device in use or operation. The device may be turned to different orientations (rotated 90 degrees or other orientations), and the spatial relative terms used herein will be interpreted accordingly. Furthermore, when a number or range of numbers is described using terms such as "about," "approximately," etc., unless otherwise stated, this term covers a number within a specific variation (e.g., + / - 10% or other variation) according to the knowledge of a person skilled in the art in the particular field described herein. For example, the term "about 5 nanometers (nm)" can cover a size range from 4.5 nm to 5.5 nm, from 4.0 nm to 5.0 nm, etc.

[0019] This disclosure relates to integrated circuits (ICs) and semiconductor devices, and methods for forming the same. Specifically, this disclosure relates to semiconductor devices having multiple threshold voltages (Vt) (hereinafter referred to as multiple Vt devices). As advanced technology nodes continue to shrink, developing such multiple Vt devices becomes increasingly challenging. For example, dipole materials are sometimes embedded in the gate dielectric layer in different configurations (e.g., at the interface between the gate dielectric layer and the interface layer) to provide the desired multiple threshold voltages. For instance, p-type dipole material doped into the gate dielectric layer of a p-type transistor reduces the threshold voltage of the p-type transistor, while p-type dipole material doped into the gate dielectric layer of an n-type transistor increases the threshold voltage of the n-type transistor. Similarly, n-type dipole material doped into the gate dielectric layer of an n-type transistor reduces the threshold voltage of the n-type transistor, while n-type dipole material doped into the gate dielectric layer of a p-type transistor increases the threshold voltage of the p-type transistor. To achieve these different configurations, dipole layers (including dipole materials) are patterned with the assistance of hard masking layers and photoresist. While n-type dipoles are commonly used in such applications, implementing p-type dipoles in the same manner is challenging. Suitable p-type dipoles include alumina (Al₂O₃). However, the solubility of alumina in acidic and alkaline wet etching chemicals makes most conventional hard masking materials unsuitable for patterning Al₂O₃-based dipole layers. This challenge is further amplified by the extremely narrow process windows of nanosheet-based devices. In other words, the challenge of implementing Al₂O₃ in the gate dielectric layer as a dipole material remains. Therefore, this disclosure provides structures and methods to address these challenges. Additional process considerations are also addressed in this disclosure.

[0020] Figure 1 This is a flowchart illustrating a method 100 for manufacturing a semiconductor device according to various embodiments of the present disclosure. In some embodiments, the semiconductor device manufactured by method 100 includes a nanosheet-based transistor. It should be noted that the term "nanosheet-based device" broadly encompasses devices comprising multiple channel layers stacked on top of each other, regardless of the aspect ratio of these channel layers. In other words, the term "nanosheet-based device" includes devices having channel layers having nanosheets, nanowires, nanorods, or any other suitable shape. They are sometimes also referred to as gate-all-around (GAA) devices, multi-bridge channel (MBC) devices, or other similar names. Additional operations may be provided before, during, or after method 100, and in additional embodiments of method 100, some of the operations described below may be removed, replaced, or eliminated. The following is combined with Figures 2A to 12 Description method 100. Figure 2A This is a schematic top view of a portion of a semiconductor device 200 during a manufacturing stage related to method 100, as shown in various embodiments of this disclosure. Figures 2B to 12 This is a schematic cross-sectional view of a portion of a semiconductor device 200 during a manufacturing stage related to method 100, as shown in various embodiments of this disclosure.

[0021] In this embodiment, semiconductor device 200 is a multi-gate (or multi-gate) device. Those skilled in the art will recognize that other examples of semiconductor devices can benefit from the features of this disclosure. Semiconductor device 200 may be included in a microprocessor, memory, and / or other IC device. In some embodiments, semiconductor device 200 is part of an IC chip, a system-on-a-chip (SoC), or a portion thereof, which includes various passive or active microelectronic devices such as resistors, capacitors, inductors, diodes, p-type field-effect transistors (PFETs), n-type field-effect transistors (NFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high-voltage transistors, high-frequency transistors, other suitable components, or combinations thereof. In some embodiments, the semiconductor device 200 is included in non-volatile memory, such as non-volatile random-access memory (NVRAM), flash memory, electrically erasable programmable read-only memory (EEPROM), electronically programmable read-only memory (EPROM), other suitable memory types, or combinations thereof. For clarity, Figures 2A to 12The invention has been simplified to better understand the inventive concept of this disclosure. Additional features may be added to the semiconductor device 200, and in other embodiments of the semiconductor device 200, some of the features described below may be replaced, modified, or eliminated. The manufacture of the semiconductor device 200 is described below in conjunction with embodiments of method 100.

[0022] In operation 102, method 100 ( Figure 1 The initial structure (or working part) of a semiconductor device 200 is provided or is provided, a portion of which is shown in one embodiment. Figures 2A to 2C In China. Specifically, Figure 2A The displayed semiconductor device 200 includes two device regions 200A and 200B (or referred to as regions 200A and 200B). Device region 200A includes an active region 204A and a gate region 206A substantially perpendicular to the active region 204A. The active region 204A includes a pair of source / drain (S / D) regions and a channel region between the pair of S / D regions. The gate region 206A engages the channel region. Device region 200A further includes dielectric fins 231, which are substantially parallel to the active region 204A and longitudinally oriented, and located on both sides of the active region 204A. The gate region 206A extends along the "y" direction between the two dielectric fins 231. Similarly, device region 200B includes an active region 204B and a gate region 206B substantially perpendicular to the active region 204B. The active region 204B includes a pair of S / D regions and a channel region between the pair of S / D regions. The gate region 206B connects to the channel region. The device region 200B further includes dielectric fins 231, which are generally parallel to the active region 204B in a longitudinal direction and located on both sides of the active region 204B. The gate region 206B extends along the "y" direction between the two dielectric fins 231.

[0023] Figure 2B A cross-sectional view of a semiconductor device 200 is shown according to one embodiment, where device regions 200A and 200B are respectively along... Figure 2A The cross-sectional views of line segments A1-A1 and B1-B1. Figure 2C A cross-sectional view of a semiconductor device 200 is shown according to one embodiment, where device regions 200A and 200B are respectively along... Figure 2A Cross-sectional views of line segments A2-A2 and B2-B2. Figure 2B and Figure 2CThe embodiments shown are nanosheet-based devices, wherein their channel layers 215 are nanoscale sheets. For clarity, device regions 200A and 200B are shown with the same configuration to better understand the inventive concept of this disclosure. In various embodiments, device regions 200A and 200B may have different configurations. For example, they may have different numbers of channels, and / or their channel layers 215 may have different shapes or sizes. As another example, either device region 200A or 200B may be a nanowire FET (i.e., the channel layer 215 is a nanoscale wire or a nanoscale rod) or a nanosheet FET. And, as described below, device regions 200A and 200B are fabricated in different ways to form transistors with different characteristics (e.g., different threshold voltages).

[0024] Reference Figures 2B to 2C The semiconductor device 200 includes a substrate 202 (e.g., a wafer). In the illustrated embodiment, the substrate 202 includes silicon. Alternatively or additionally, the substrate 202 includes another elemental semiconductor, such as germanium; includes compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; includes alloy semiconductors, such as silicon germanium (SiGe), GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or includes combinations thereof. Alternatively, the substrate 202 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate.

[0025] Each of device regions 200A and 200B further includes a pair of S / D features 260. For an n-type transistor, the S / D feature 260 is n-type. For a p-type transistor, the S / D feature 260 is p-type. The S / D feature 260 can be formed by epitaxially growing a semiconductor material (e.g., Si, SiGe) to fill trenches in the semiconductor device 200, for example, by using chemical vapor deposition (CVD) techniques (e.g., vapor phase epitaxy), molecular beam epitaxy, other suitable epitaxial growth processes, or combinations thereof. Therefore, the S / D feature 260 can also be interchangeably referred to as epitaxial S / D feature 260 or epitaxial feature 260. The S / D feature 260 is doped with appropriate n-type dopant and / or p-type dopant. For example, for an n-type transistor, S / D feature 260 may include silicon and be doped with carbon, phosphorus, arsenic, other n-type dopants or combinations thereof; for a p-type transistor, S / D feature 260 may include silicon germanium or germanium and be doped with boron, other p-type dopants or combinations thereof.

[0026] Each of device regions 200A and 200B further includes a stack of semiconductor layers 215, which are suspended above substrate 202 and connected to a pair of S / D features 260. The stack of semiconductor layers 215 serves as a transistor channel for each transistor. Therefore, semiconductor layer 215 is also referred to as channel layer 215. Channel layer 215 is exposed in gate trench 275 because dummy gates are provided from the corresponding gate regions 206A and 206B. Figure 2A The channel layer 215 may comprise monocrystalline silicon. Alternatively, the channel layer 215 may comprise germanium, silicon-germanium, or one or more other suitable semiconductor materials. Initially, the channel layer 215 is formed as part of a semiconductor layer stack comprising the channel layer 215 and other semiconductor layers of different materials. Using one or more photolithography processes, including dual patterning or multi-patterning processes, the semiconductor layer stack is patterned into a fin shape protruding above the substrate 202. After the gate trench 275 is formed, the semiconductor layer stack is selectively etched to remove other semiconductor layers, leaving the channel layer 215 suspended above the substrate 202 and between the corresponding S / D features 260. The channel layers 215 are separated from each other and from the substrate 202 by gaps 277A.

[0027] In some embodiments, each channel layer 215 has nanoscale dimensions and may therefore be referred to as a nanostructure. For example, in some embodiments, each channel layer 215 may have a length of about 10 nm to about 300 nm (along the "x" direction, which is perpendicular to the plane defined by the "y" and "z" directions), a width of about 10 nm to about 80 nm (along the "y" direction), and a height of about 4 nm to about 8 nm (along the "z" direction). In some embodiments, the vertical spacing h0 of the gaps 277A between the channel layers 215 (along the "z" direction) may be about 6 nm to about 15 nm. Therefore, depending on the relative dimensions, the channel layer 215 may be referred to as a "nanowire" or "nanosheet," which generally refers to a channel layer suspended in a manner that allows a high-k metal gate to physically wrap around the channel layer. In some embodiments, the channel layer 215 may be cylindrical (e.g., nanowire), rectangular (e.g., nanorod), sheet-like (e.g., nanosheet), or have other suitable shapes.

[0028] Semiconductor device 200 further includes isolation features 230 to isolate various regions, such as various active regions 204A and 204B. Isolation features 230 include silicon oxide, silicon nitride, silicon oxynitride, other suitable isolation materials (e.g., silicon, oxygen, nitrogen, carbon, or other suitable isolation components), or combinations thereof. Isolation features 230 may include different structures, such as shallow trench isolation (STI) structures, deep trench isolation (DTI) structures, and / or local oxidation of silicon (LOCOS) structures. Isolation features 230 may include multiple insulating material layers.

[0029] The semiconductor device 200 further includes a gate spacer 247 adjacent to the S / D feature 260. The gate spacer 247 may include silicon, oxygen, carbon, nitrogen, other suitable materials, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride (SiON), silicon carbide, silicon carbonitride (SiCN), silicon carbon oxynitride (SiOC), silicon carbon oxynitride (SiOCN)). In some embodiments, the gate spacer 247 includes a multilayer structure, such as a first dielectric layer comprising silicon nitride and a second dielectric layer comprising silicon oxide. The semiconductor device 200 further includes an internal spacer 255 vertically spaced between adjacent channel layers 215 and adjacent to the S / D feature 260. The internal spacer 255 may include a dielectric material, including silicon, oxygen, carbon, nitrogen, other suitable materials, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or silicon carbon oxynitride). In some embodiments, the internal spacer 255 includes a low-k dielectric material. Gate spacers 247 and internal spacers 255 are formed by deposition (e.g., CVD, physical vapor deposition (PVD), atomic layer deposition (ALD), etc.) and etching processes (e.g., dry etching). A gate trench 275 is provided between the gate spacers 247 and the internal spacers 255 on both sides along the "x" direction. Further, the distance between the gate spacers 247 on both sides of the gate trench 275 has a distance d3 that defines the gate length. In some embodiments, the distance d3 is greater than about 10 nm, for example, from about 15 nm to about 50 nm. If the distance d3 is too small, subsequently formed thin layers (e.g., sacrificial layers described below) will be difficult to remove, and their residue may interfere with the desired performance. In other words, a larger distance d3 increases the process window and allows material to more easily penetrate the interior and deeper regions between and around the channel layers 215. If the distance d3 is too large, it may unnecessarily increase the chip footprint.

[0030] Semiconductor device 200 also includes a contact etch stop layer (CESL) 268 disposed over isolation feature 230, S / D feature 260, and gate spacer 247. CESL 268 comprises silicon and nitrogen, such as silicon nitride or silicon oxynitride. CESL 268 can be formed by a deposition process, such as by CVD or other suitable methods. Semiconductor device 200 also includes an inter-level dielectric (ILD) layer 270 above CESL 268. ILD layer 270 comprises a dielectric material, such as oxides formed from silicon oxide, silicon nitride, silicon oxynitride, tetraethyl orthosilicate (TEOS), phosphosilicate glass (PSG), borosilicate glass (BPSG), low-k dielectric materials, other suitable dielectric materials, or combinations thereof. The ILD layer 270 can be formed by a deposition process, such as by CVD, flowable CVD (FCVD), or other suitable methods.

[0031] Dielectric fins 231 (sometimes interchangeably referred to as hybrid fins 231) are disposed above the isolation feature 230. Figure 2CIn the illustrated embodiment, the dielectric fin 231 includes a dielectric liner 232, a dielectric filler layer 233 above the dielectric liner 232, and a dielectric helmet 234 above the dielectric liner 232 and the dielectric filler layer 233. In one embodiment, the dielectric liner 232 includes a low-k dielectric material, such as dielectric materials comprising Si, O, N, and C. Exemplary low-k dielectric materials include fluorosilicate glass (FSG), carbon-doped silicon oxide, xerogel, aerogel, amorphous fluorinated carbon, parylene, phenylcyclobutene (BCB), polyimide, or combinations thereof. Low-k dielectric materials generally refer to dielectric materials with a low dielectric constant, such as a dielectric constant lower than that of silicon oxide (k≈3.9). The dielectric pad 232 can be deposited using CVD, PVD, ALD, high-density plasma chemical vapor deposition (HDPCVD), metal-organic chemical vapor deposition (MOCVD), remote plasma chemical vapor deposition (RPCVD), plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), atomic layer chemical vapor deposition (ALCVD), ambient pressure chemical vapor deposition (APCVD), other suitable methods, or combinations thereof. In one embodiment, the dielectric filler layer 233 includes silicon oxide, silicon nitride, silicon oxynitride, oxides formed from TEOS, PSG, BPSG, low-k dielectric materials, other suitable dielectric materials, or combinations thereof. The dielectric filler layer 233 can be deposited using a flow-through CVD (FCVD) process, which includes, for example, depositing a flowable material (e.g., a liquid compound) over a semiconductor device 200 and converting the flowable material into a solid material using suitable techniques such as thermal annealing and / or ultraviolet radiation treatment. Other types of methods can be used to deposit the dielectric filler layer 233. In one embodiment, the dielectric cap 234 comprises a high-k dielectric material, such as HfO2, HfSiO, HfSiO4, HfSiON, HfLaO, HfTaO, HfTiO, HfZrO, or HfAlO. xZrO, ZrO2, ZrSiO2, AlO, AlSiO, Al2O3, TiO, TiO2, LaO, LaSiO, Ta2O3, Ta2O5, Y2O3, SrTiO3, BaZrO, BaTiO3 (BTO), (Ba,Sr)TiO3 (BST), Si3N4, hafnium dioxide-alumina (HfO2-Al2O3) alloys, other suitable high-k dielectric materials, or combinations thereof. High-k dielectric materials generally refer to dielectric materials with a high dielectric constant, such as a dielectric constant greater than that of silicon oxide (k≈3.9). The dielectric cap 234 is formed by any of the processes described herein, such as ALD, CVD, PVD, oxidation-based deposition processes, other suitable processes, or combinations thereof.

[0032] Each dielectric fin 231 has a width dimension t0. In some embodiments, the width dimension t0 is from about 5 nm to about 30 nm. The dielectric fins 231 cut through portions of the gate structure with different gate materials and isolate adjacent device regions. If the width dimension t0 is too small, for example less than about 5 nm, the dielectric fins 231 may be too fragile to withstand subsequent process operations and jeopardize the integrity of the device they protect. Conversely, if the width dimension t0 is too large, for example greater than about 30 nm, the cost associated with the valuable chip coverage they occupy outweighs any potential additional benefits. In some embodiments, the dielectric fins 231 (e.g., dielectric caps 234) extend above the top surface of the channel layer 215, for example, by a distance H1. In some embodiments, the distance H1 is from about 5 nm to about 50 nm. If the distance H1 is too small, for example less than 5 nm, there may not be sufficient margin to ensure proper isolation between adjacent gate portions. Conversely, if the distance H1 is too large, the additional height does not provide sufficient benefit to offset their material and process costs. Gate trench 275 is provided between opposing dielectric fins 231 along the "y" direction. In some embodiments, adjacent dielectric fins 231 are separated by a distance d0. Therefore, gate trench 275 has a lateral width equal to the distance d0. In some embodiments, the distance d0 is about 20 nm to about 100 nm.

[0033] The gate trench 275 further includes a gap 277A, which is located between vertically adjacent channel layers 215. The gap 277A has a vertical spacing h0. In some embodiments, the vertical spacing h0 is from about 6 nm to about 15 nm. If the vertical spacing h0 is too small, for example less than about 6 nm, there may not be enough space to form subsequent thin layers used to form a suitable high-k metal gate structure. For example, as described in more detail below, a dipole layer is formed within the gap 277A. The dipole layer needs to be thick enough to provide sufficient threshold voltage tuning capability. If the vertical spacing h0 is too small, the subsequently formed dipole layers may not meet design requirements. Conversely, if the vertical spacing h0 is too large, for example greater than about 15 nm, their additional volume may not provide a significant enough benefit to justify their chip coverage and / or associated material and process costs. In some embodiments, the upper limit of the vertical spacing h0 may be calculated inversely from the thickness of the subsequently formed dipole layers, as described below.

[0034] The gate trench 275 also includes a gap 277B, located between the sidewall surface of the channel layer 215 and the sidewall surface of the dielectric fin 231. The gap 277B has a lateral width w0. In some embodiments, the lateral width w0 is about 8 nm to about 17 nm. If the lateral width w0 is too small, for example less than about 8 nm, material entering the bottom portion of the gap 277B and / or the gap 277A may be overly restricted. Conversely, if the lateral width w0 is too large, for example greater than about 17 nm, their additional volume may not provide a sufficiently large benefit to justify their chip coverage area and / or associated material and process costs. In some embodiments, the difference Δ1 between the lateral width w0 and the vertical spacing h0 is at least about 1 nm to about 3 nm. If the difference Δ1 is too small, for example less than about 1 nm to about 3 nm, a subsequently formed thin layer may be fused in the gap 277B before being merged in the gap 277A. This can sometimes cut off the diffusion path of material into and out of the gap 277A. Therefore, the subsequently formed electrode layer may not completely fill the gap 277A and may not completely surround the channel layer 215. This could compromise gate control of the channel layer 215. In some embodiments, the difference Δ2 between the gate length d3 and the vertical spacing h0 is at least about 3 nm to about 5 nm. If the difference Δ2 is too small, for example less than about 3 nm to about 5 nm, the subsequently formed thin layer may similarly fuse across the dimensions defined by the internal spacers, hindering complete filling of the gap 277A. As mentioned above, the vertical spacing h0 can be calculated in reverse from the thickness of the subsequently formed dipole layer. In some embodiments, the lateral width w0 can also be calculated from the difference Δ1 and the vertical spacing h0, taking into account additional factors such as the difference Δ2.

[0035] In operation 104, method 100 ( Figure 1 An interface gate dielectric layer 280 (or simply interface layer 280) is formed on the surface of the channel layer 215 exposed in the gate trench 275, such as... Figure 3 As shown. Figures 3 to 12 The device areas 200A and 200B are shown at different process stages and along respectively. Figure 2A The cross-sectional views of line segments A2-A2 and B2-B2. (The text then abruptly shifts to a different topic:) ...to... Figure 3 In the illustrated embodiment, the interface layer 280 surrounds each channel layer 215 and partially fills the gap 277A. In this embodiment, the interface layer 280 is disposed on the semiconductor surface exposed in the gate trench 275, such as the surface of the channel layer 215 and the substrate 202, rather than on the dielectric surface exposed in the gate trench 275 (e.g., isolation feature 230, gate spacer 247, and dielectric fin 231). For example, the interface layer 280 may be formed by an oxidation process (e.g., thermal oxidation or chemical oxidation), in which the semiconductor surface reacts with oxygen to form a semiconductor oxide as the interface layer 280. In this oxidation process, the dielectric surface does not react with oxygen, therefore the interface layer 280 is not formed on the dielectric surface. In alternative embodiments, the interface layer 280 is disposed not only on the channel layer 215 and the substrate 202, but also on the isolation feature 230, the gate spacer 247, and the dielectric fin 231, for example, by using atomic layer deposition (ALD) or other suitable deposition methods. The interface layer 280 includes a dielectric material, such as SiO2, HfSiO, SiON, other silicon-containing dielectric materials, other suitable dielectric materials, or combinations thereof. In some embodiments, the interface layer 280 has a thickness of about 5 Å to about 15 Å. In some embodiments, the interface layer 280 has a thickness of about 9 Å to about 10 Å. If the interface layer 280 is too thin, its reliability may be insufficient in some cases. If the interface layer 280 is too thick, in some cases, the remaining portion of the gap 277A may be too small to allow the necessary high-k dielectric layer and metal electrode layer to be filled.

[0036] Still in operation 104, method 100 ( Figure 1 Furthermore, a high-k gate dielectric layer 282 (or simply high-k dielectric layer 282) is formed above the interface layer 280 and above other structures exposed in the gate trench 275, such as... Figure 3 As shown. Still refer to Figure 3A high-k gate dielectric layer 282 is disposed above the interface layer 280 and surrounds each channel layer 215. The high-k gate dielectric layer 282 and the interface layer 280 can be collectively referred to as the gate dielectric layer of the semiconductor device 200. The gate dielectric layer partially fills the gap 277A. In this embodiment, the high-k gate dielectric layer 282 is also disposed on the isolation feature 230, the gate spacer 247, and the dielectric fin 231. For example, in one embodiment, the high-k gate dielectric layer 282 is disposed directly on the isolation feature 230, the gate spacer 247, and the dielectric fin 231. The high-k gate dielectric layer 282 comprises a high-k dielectric material, such as HfO2, HfSiO, HfSiO4, HfSiON, HfLaO, HfTaO, HfTiO, HfZrO, or HfAlO. x The high-k gate dielectric layer 282 can be formed by any of the processes described herein, such as ALD, CVD, PVD, oxidation-based deposition processes, other suitable processes, or combinations thereof. In some embodiments, the high-k gate dielectric layer 282 has a thickness of about 1 nm to about 2 nm. In some embodiments, the high-k gate dielectric layer 282 has a thickness of about 1.2 nm to about 1.4 nm. If the high-k gate dielectric layer 282 is too thin, the integrity of the thin layer may not be guaranteed in all cases; while if the high-k gate dielectric layer 282 is too thick, the spacing between the channel layers 215 may be unnecessarily reduced, making the formation of subsequent electrode layers potentially challenging. As described in more detail below, another high-k dielectric layer may subsequently be formed on top of the high-k gate dielectric layer 282. In other words, the high-k gate dielectric layer 282 may be a sublayer of a combined and thicker high-k dielectric layer. Therefore, the high-k gate dielectric layer 282 is interchangeably referred to as the high-k gate dielectric sublayer 282.

[0037] After forming the interface layer 280 and the high-k gate dielectric layer 282 (or high-k gate dielectric sublayer 282), gaps 277A and 277B are partially filled. A gap is left between vertically adjacent channel layers 215, for example, between vertically adjacent surfaces of the high-k gate dielectric layer 282. This gap has a dimension h1 along the z-direction. The dimension h1 is limited by the vertical spacing h0 and the thickness of the high-k gate dielectric layer 282. In some embodiments, the dimension h1 is about 1 nm to about 10 nm. Furthermore, a gap (with a dimension w1 along the y-direction) is left between the sidewall surface of the high-k gate dielectric layer 282 and the sidewall surface of the dielectric fin 231. The dimension w1 is limited by the lateral width w0 and the thickness of the high-k gate dielectric layer 282. In some embodiments, the dimension w1 is about 4 nm to about 13 nm.

[0038] In operation 106, method 100 ( Figure 1 A dipole layer 284 is formed above the high-k gate dielectric layer 282. (See reference...) Figure 4 In both regions 200A and 200B, a dipole layer 284 is deposited over a high-k gate dielectric layer 282 and around each channel layer 215. The dipole layer 284 is also disposed over dielectric fins 231 and isolation features 230. In some embodiments, the dipole layer 284 comprises aluminum oxide. As described in more detail below, aluminum oxide can be a suitable p-type dipole material to tune the threshold voltage of the transistor. However, the application of aluminum oxide as a p-type dipole material in nanosheet-based devices has been challenging due to the lack of suitable hard masks to assist in the patterning of aluminum oxide-based dipole layers. In some embodiments, the dipole layer 284 may have a thickness dimension t1 throughout its entire outline. In some embodiments, the thickness dimension t1 is configured to be equal to or greater than half of dimension h1, such that the dipole layer 284 is fused between vertically adjacent channel layers 215 (e.g., between opposing surfaces of interface layers 280). In other words, gap 277A is filled by the dipole layer 284. As described in detail below, the fusion of dipole layer 284 enables it to function as a hard mask layer in subsequent patterning operations. Therefore, although dipole layer 284 has thickness on its outer surfaces (e.g., on the top surface of the topmost channel layer 215, on the sidewall surfaces of all channel layers 215, on the sidewall surfaces of dielectric fins 231, and on the top surface of dielectric fins 231), dipole layer 284 has a thickness exceeding the thickness dimension t1 between adjacent channel layers 215. In some embodiments, dipole layer 284 is conformal.

[0039] Furthermore, in some embodiments, the thickness dimension t1 is configured to be less than half of the dimension w1. Therefore, an opening is left between the channel layer 215 and the dielectric fin 231. For example, as... Figure 4 As shown, the lateral spacing between the portion of the dipole layer 284 on the dielectric fin 231 and the portion on the sidewall surface of the channel layer 215 is lateral spacing w2. In some embodiments, the lateral spacing w2 is configured to be at least 1 nm. If the lateral spacing w2 is too small, for example less than 1 nm, the etching chemicals required in subsequent etching operations may not reach the bottom of the gap 277B. In some embodiments, the thickness dimension t1 of the dipole layer 284 is from about 1 nm to about 4 nm. In some embodiments, the thickness dimension t1 of the dipole layer 284 is from 1.5 nm to about 2.5 nm. If the thickness dimension t1 is too small, fusion between vertically adjacent channel layers 215 may not be achieved. Furthermore, having a relatively large thickness dimension t1 reduces the complexity of controlling the critical voltage. This will be described in more detail below. Conversely, if the thickness dimension t1 is too large, the lateral spacing w2 may become too small.

[0040] The dipole layer 284 can be formed using any suitable method. In some embodiments, the dipole layer 284 can be deposited using ALD, CVD, PVD, or other suitable processes. In some embodiments, deposition can be performed using volatile aluminum compounds such as trimethylaluminum, triisobutylaluminum, tris(dimethylamido)aluminum(III), aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedionate), other suitable aluminum precursors, or combinations thereof. In some embodiments, water, oxygen, plasma, water plasma, other suitable reactants, or combinations thereof can also be used. In some embodiments, the deposition of the dipole layer can be performed at a temperature of about 200 degrees Celsius (°C) to about 400 degrees Celsius. In some embodiments, the thickness dimension t1 can be controlled by controlling the number of cycles of the deposition operation. In some embodiments, the number of ALD cycles can be greater than 15 cycles. If the number of deposition cycles is too small, the thickness dimension t1 may not be optimized (as described above).

[0041] In operation 108, method 100 ( Figure 1 ) proceeded to the recessed dipole layer 284 ( Figure 5This causes portions of the dipole layer 284 on the sidewall surface of the channel layer 215 and on the sidewall surface of the dielectric fin 231 to be recessed. Therefore, the thickness of these portions of the dipole layer 284 decreases from thickness dimension t1 to thickness dimension t2, and the lateral dimension of the gap 277B widens from lateral spacing w2 to lateral spacing w3. Furthermore, the dipole layer 284 on the top surface of the stacked channel layers 215 also decreases from thickness dimension t1 to thickness dimension t2. In some embodiments, thickness dimension t2 is from about 1.5 nm to about 2 nm. In some embodiments, the remaining portions of the dipole layer 284 protect the high-k gate dielectric layer 282 in subsequent etching operations. If the thickness dimension t2 is too small, for example less than about 1.5 nm, any irregularity in such etching operations could damage the high-k gate dielectric layer 282; conversely, if the thickness dimension t2 is too large, for example greater than about 2 nm, the lateral spacing w3 may be too small. For example, in some embodiments, the lateral spacing w3 may be at least about 2 nm. If the thickness dimension t2 is too large, or the lateral spacing w2 is too small, for example less than 2 nm, the subsequently deposited material may not be able to reach the bottom of the gap 277B, which may cause defects and voids to form therein, thus negatively affecting subsequent processes.

[0042] Any suitable etching method and etching chemicals can be used to recess the dipole layer 284. In some embodiments, the recessing operation may be a wet etching operation, and a wet etching chemical, such as ammonium hydroxide, may be used. Alternatively, the etching operation may be performed using a wet etching chemical selected from tetramethyl ammonium hydroxide, tetraethyl ammonium hydroxide, tetra-n-butyl ammonium hydroxide, ammonium fluoride, tetrabutyl ammonium fluoride, other suitable etching chemicals, or combinations thereof. Thus, the outer surface of the dipole layer 284 can be recessed. For example, the dipole layer 284 is recessed on the sidewall surface of the dielectric fin 231, the top surface of the topmost channel layer 215, and the sidewall surface of the channel layer 215. However, the dipole layer 284 between vertically adjacent channel layers 215 is not substantially recessed beyond its outermost edge, for example, because any contact between the dipole layer 284 and the wet etching chemicals during operation is limited to the surface. Therefore, the entire gap 277A remains filled with the dipole layer 284, while the outer surface of the stacked channel layers 215 remains covered by the dipole layer 284. Thus, the dipole layer 284 can serve as a hard mask layer in subsequent patterning operations.

[0043] In operation 110, method 100 ( Figure 1 ) enters the dielectric layer 288 formed in the gate trench 275 ( Figure 6 As shown in the figure, dielectric layer 288 also fills gap 277B (with...). Figure 5 (Comparison). In some embodiments, dielectric layer 288 includes a bottom anti-reflective coating (BAC) material. Dielectric layer 288 is used to protect the channel layer and various thin layers formed thereon from subsequent etching reactions. In one embodiment, dielectric layer 288 is formed by spin coating BARC material over semiconductor device 200 and filling gate trench 275. In some embodiments, BARC material is baked (e.g., at a temperature in the range of about 100°C to about 200°C) to induce cross-linking within BARC material. In some embodiments, dielectric layer 288 has a top surface extending above the top surface of dielectric fin 231 (including thin layers formed thereon).

[0044] Patterned photoresist 290 is formed to cover device region 200B while leaving exposed device region 200A. In operation 112, method 100 ( Figure 1 ) enters the dipole layer 284 in the removal device region 200A ( Figure 7 For example, an anisotropic etching operation can be used to transfer the pattern of the patterned photoresist 290 to the dielectric layer 288. In some embodiments, the etching operation performs a dry etching process, such as a plasma etching process, a reactive ion etching process, other suitable dry etching methods, or a combination thereof. Thus, at the end of the dry etching process, device region 200A is exposed, while device region 200B remains covered by the dielectric layer 288. Subsequently, in some embodiments, a wet etching process is performed to remove the dipole layer 284 currently exposed in device region 200A. The wet etching process may be similar to that already referred to Figure 5 The wet etching process is described. For example, ammonium hydroxide may be used in the wet etching process. Alternatively, tetramethylammonium hydroxide, tetraethylammonium hydroxide, tetra-n-butylammonium hydroxide, ammonium fluoride, tetrabutylammonium fluoride, other suitable etching chemicals, or combinations thereof may be used in the wet etching process. At the end of the wet etching process, the gate trench 275 in device region 200A, together with gaps 277A and 277B, are restored to their original state. Figure 3 The respective dimensions in each stage of the manufacturing process. For example, each gap 277A has a height dimension h1 (e.g., Figure 3 (as shown); and each gap 277B has a width dimension w1 (as shown). Figure 3(As shown in the diagram). In some embodiments, the wet etching operation is configured to completely remove the dipole layer 284 in the device region. Therefore, no dipole layer 284 remains in these openings; the high-k gate dielectric layer 282 is again exposed in the gate trench 275 of the device region 200A. Meanwhile, with Figure 6 Compared to the previous process stage, the dipole layer 284 and the high-k gate dielectric layer 282 in device region 200B remain unchanged. The dielectric layer 288 is then removed using any suitable method. In some embodiments, the removal of the dielectric layer 288 may be performed at a temperature of about 100°C to about 300°C. At excessively low temperatures, such as below about 100°C, residues from the dielectric layer 288 may remain and cause problems in subsequent depositions; while if the temperature is too high, such as above about 300°C, any benefits may be offset by process costs.

[0045] Therefore, at this stage of the process, the dipole layer 284 is efficiently patterned such that the dipole layer 284 exists in device region 200B but not in device region 200A. In some other embodiments that do not implement the methods described herein, for example, in... Figure 4 In a process stage where the dipole layer 284 is not fused and fills the gap 277A, the dielectric layer 288 may penetrate into the region between vertically adjacent channel layers 215. Due to the lack of a process window, subsequent removal of those portions of the dielectric layer 288 can be quite challenging. This can potentially create defects that degrade device characteristics. In other words, without implementing the methods described herein, the lack of a suitable hard masking material for patterning alumina hinders its use as a dipole material, thereby substantially limiting the supply range associated with p-type dipoles.

[0046] In operation 114, method 100 ( Figure 1 The process then proceeds to heat treatment process 600 (or annealing process 600). Figure 8The thermal processing 600 provides the thermal energy required for the migration of elements from the dipole layer 284 to the high-k gate dielectric layer 282, which is connected to it. Therefore, some portions of the high-k gate dielectric layer 282 (e.g., portions in device region 200B) include a dipole material (e.g., alumina) from the dipole layer 284. Furthermore, the thermal processing 600 further drives the dipole material through the high-k gate dielectric layer 282 toward the interface between the high-k gate dielectric layer 282 and the interface layer 280. It has been found that the relative magnitude of the oxygen surface density σ between the dipole material and the material of the interface layer 280 determines the orientation and size of the resulting dipoles. In the illustrated embodiment, the dipole material here includes alumina, and the interface layer here includes silicon oxide. Alumina has a higher oxygen surface density than silicon oxide. Therefore, the thermal processing drives negatively charged oxygen atoms into the interface layer 280. Therefore, the net positive charge remains within the high-k gate dielectric layer 282, and dipole pointing (from positive to negative) is generated at the interface between the high-k gate dielectric layer 282 and the interface layer 280. Compared with other dipole materials, aluminum oxide can provide larger dipoles, thus more effectively tuning the critical voltage. Furthermore, it has been found that aluminum atoms diffusing into the high-k gate dielectric layer 282 are well confined within the boundaries of the high-k gate dielectric layer 282, as in the reference layer. Figure 19C A more detailed description follows. Therefore, the minimal amount of aluminum diffusing toward channel layer 215 (if any) raises concerns about a breakthrough.

[0047] Any suitable method can be performed for the heat treatment process 600. For example, the heat treatment process 600 may perform soap annealing, spike annealing, laser annealing, other processing methods, or combinations thereof. In some embodiments, the heat treatment process 600 implements a temperature of about 850°C to about 900°C. If the temperature is too low, dipole migration may be too inefficient; while if the temperature is too high, migration may be difficult to control. (See also...) Figure 9 At the end of the heat treatment process 600, the high-k gate dielectric layer 282 in device region 200B includes a dipolar material (e.g., alumina) from the dipolar layer 284, and is therefore referred to as the modified high-k gate dielectric layer 282'. Meanwhile, the high-k gate dielectric layer 282 in device region 200A, lacking dipolar material, was not modulated during the heat treatment process 600. Subsequently, in operation 116 ( Figure 1Method 100 proceeds to remove any remaining portion of the dipole layer 284 on the surface of the modulated high-k gate dielectric layer 282' still present in device region 200B. In some embodiments, the removal of the remaining portion of the dipole layer 284 may be performed using wet etching chemicals, similar to those described above with reference to operations 108 and / or 112. Therefore, at this stage of the process, the gap 277A between vertically adjacent channel layers 215 is reformed in region 200B; and the gap 277B between the sidewall surfaces of the channel layers 215 and the sidewall surfaces of the dielectric fins is also reformed in device region 200B. In some embodiments, the dimensions of gaps 277A and 277B are restored to a size similar to... Figure 3 The numerical value. In other words, at this stage of the process, the gap 277A between the device regions 200A and 200B can have a height dimension h1; while the gap 277B between the device regions 200A and 200B can have a lateral dimension w1.

[0048] In some embodiments, refer to Figure 1 Route A1, method 100 proceeds to execution operation 118 to form another high-k gate dielectric layer 285, the high-k gate dielectric layer 285 surrounding the unmodulated high-k gate dielectric layer 282 in device region 200A and the modulated high-k gate dielectric layer 282' in device region 200B. Figure 10 Therefore, the dipole material within the modulated high-k gate dielectric layer 282' is defined (or sandwiched) between the two thin layers, the modulated high-k gate dielectric layer 282' and the high-k gate dielectric layer 285. In some embodiments, the high-k gate dielectric layer 285 is purely for confining any outward diffusion of the dipole element. In these embodiments, the high-k gate dielectric layer 285 may include a suitable high-k dielectric material (e.g., hafnium oxide) and may have a thickness of about 0.3 nm to about 0.4 nm. In some other embodiments, the high-k gate dielectric layer 285 may undergo a process similar to that of the high-k gate dielectric layer 282. In other words, a portion of the high-k gate dielectric layer 285 may be modulated with a dipole material. In some embodiments, the modulated portion (and only this portion) of the high-k gate dielectric layer 285 covers the modulated high-k gate dielectric layer 282' in the device region 200B. Therefore, the high-k gate dielectric layer 282 / modulated high-k gate dielectric layer 282' and high-k gate dielectric layer 285 can be considered as similar sublayers to other adjacent high-k dielectric layers. In these embodiments, the thickness of the high-k gate dielectric layer 285 may be similar to the thickness of the high-k gate dielectric layer 282 described above. However, in some embodiments, the formation of the high-k gate dielectric layer 285 is omitted.

[0049] Next, a capping layer 287 is formed to cover the high-k gate dielectric layer 282 / modulated high-k gate dielectric layer 282' (and also cover the high-k gate dielectric layer 285 if it exists). Figure 11 In some embodiments, the capping layer comprises titanium nitride, tantalum nitride, other suitable capping materials, or a combination thereof. Then, method 100 proceeds to... Figure 1 Operation 120 to form a gate electrode layer 286 surrounding the high-k gate dielectric layer. Figure 12 In some embodiments, the gate electrode layer 286 may include a p-type work function metal, such as TiN, TaN, TaSN, TiSiN, Ru, Mo, Al, WN, WCN, ZrSi2, MoSi2, TaSi2, NiSi2, other p-type work function materials, or combinations thereof. In some embodiments, the gate electrode layer 286 may include an n-type work function metal, such as Ti, Al, Ag, Mn, Zr, TiC, TiAl, TiAlC, TiAlSiC, TiAlN, TaC, TaCN, TaSiN, TaAl, TaAlC, TaSiAlC, TiAlN, other n-type work function materials, or combinations thereof. In some embodiments, the gate electrode layer 286 in device region 200A may be the same as the gate electrode layer 286 in device region 200B. In other embodiments, the gate electrode layer 286 in device region 200A may be different from the gate electrode layer 286 in device region 200B. Furthermore, the gate electrode layer 286 may further include a bulk metal material, such as copper, tungsten, or other suitable metal materials. The bulk metal material may additionally include other metals, metal oxides, metal nitrides, other suitable materials, or combinations thereof. In some embodiments, a chemical mechanical polishing (CMP) process is performed to planarize the top surface of the semiconductor device 200.

[0050] Alternatively or additionally, refer back to Figure 1 Route A2, method 100, can lead to repeating operations 106-116 before operation 118. This is in Figure 13 Further explanation is provided below. Figure 13 Regions 300A, 300A', 300B, and 300B' are shown, wherein regions 300A and 300A' have both undergone the same process as described in region 200A of the aforementioned reference device. Therefore, both regions 300A and 300A' include the same process as described in region 200A of the aforementioned reference device. Figure 9 The device features are the same as those in device region 200A. Furthermore, both regions 300B and 300B' have undergone the same process as described in the aforementioned reference device region 200B. Therefore, both regions 300B and 300B' include the same... Figure 9The device features are the same as those in device region 200B. In the second cycle of operations 106-116, the masking layer of operation 110 is configured to be offset from the masking layer in the first cycle. For example, in the second cycle of operations 106-116, another dipole layer 284' (not shown in the figures, but given the reference numeral 284' for clarity) (which may also be an alumina layer with the same or different thickness as dipole layer 284) is formed on regions 300A, 300A', 300B, and 300B'. Dipole layer 284' may also be recessed to provide an improved process window. In the second operation 110, a masking layer is formed to cover regions 300A' and 300B', while leaving regions 300A and 300B exposed (in contrast, regions 300B and 300B' were covered in the first operation 110). Therefore, subsequent process operations remove dipole layer 284' from regions 300A and 300B, while retaining dipole layer 284' in regions 300A' and 300B'. After completing the second operations 114 and 116, region 300A does not include dipole material from dipole layer 284, nor does it include dipole material from dipole layer 284'; region 300A' does not include dipole material from dipole layer 284, but includes dipole material from dipole layer 284'; region 300B includes dipole material from dipole layer 284, but does not include dipole material from dipole layer 284'; region 300B' includes dipole material from dipole layer 284, and also includes dipole material from dipole layer 284'. Therefore, up to four different dipole configurations can be achieved in regions 300A, 300A', 300B, and 300B'. After subsequent transistor fabrication processes, transistors with up to four different Vt values ​​can be realized. Naturally, the same or similar further processes can be performed to provide a supply of even more different threshold voltages.

[0051] Not limited by theory, the critical voltage of a transistor is affected by the concentration of a dipole material (e.g., aluminum oxide) within the high-k gate dielectric layer 282 (e.g., with hafnium dioxide). For example, the change in flat-band voltage (ΔV) fb The concentration of the dipole material is linearly related to the ratio of aluminum concentration to hafnium concentration. In some embodiments, the concentration of the dipole material is affected by the temperature used in the heat treatment process 600, and also by the thickness of the dipole layer 284 connected to the high-k gate dielectric layer 282 prior to the heat treatment process 600. Figure 19A This shows the change in flat band voltage (ΔV) fbExemplary relationships between the temperature of the heat treatment operation and the capacitance-equivalent thickness (ΔCET) are presented. For example, at an annealing temperature T1 of approximately 730°C to approximately 770°C, the critical voltage of the p-type transistor decreases by approximately 15 mV (mV) to approximately 20 mV. Simultaneously, the change in capacitance-equivalent thickness (ΔCET) adjusts the thickness by approximately 0.2 Å to approximately 0.3 Å. For example, at an annealing temperature T2 of approximately 830°C to approximately 870°C, the critical voltage of the p-type transistor decreases by approximately 35 mV to approximately 40 mV. Simultaneously, the change in capacitance-equivalent thickness (ΔCET) adjusts the thickness by approximately 0.4 Å to approximately 0.5 Å. For example, at an annealing temperature T3 of approximately 880°C to approximately 920°C, the critical voltage of the p-type transistor decreases by approximately 75 mV to approximately 85 mV. Simultaneously, the change in equivalent capacitance thickness (ΔCET) adjusts the thickness from approximately 0.65 Å to approximately 0.75 Å. In some embodiments, the annealing operation may be a single-step annealing operation. Alternatively, the annealing operation may be a multi-step annealing operation, wherein each step may be performed at the same or different annealing temperatures. In some embodiments, the change in flat band voltage (ΔV) fb The variation is further affected by the duration of the annealing operation. Generally, a longer duration allows more dipole material to migrate into the high-k gate dielectric layer 282. In some embodiments, the duration can be from about 1 second to about 1 hour. In some embodiments, the duration can be from about 10 seconds to about 60 seconds. If the duration is too short, insufficient dipole material may migrate into the high-k gate dielectric layer 282. If the duration is too long, any additional benefit may be offset by the additional cost. In some embodiments, the duration can be adjusted within these ranges to adjust the amount of dipole material migrating into the high-k gate dielectric layer 282. For example, a longer duration typically allows a larger amount of dipole material to migrate into the high-k gate dielectric layer 282, while a shorter duration typically allows a smaller amount of dipole material to migrate into the high-k gate dielectric layer 282.

[0052] Figure 19B The graph shows the change in the number of deposition cycles of dipole layer 284 as a function of the flat-band voltage (ΔV). fb The exemplary relationship between ) and the exemplary relationship between the number of deposition cycles of dipole layer 284 and the change in capacitance equivalent thickness (ΔCET). As shown in the figure, in approximately 1 to approximately 3 deposition cycles, ΔV fb The voltage was adjusted by approximately 25 mV to approximately 30 mV. Simultaneously, ΔCET was adjusted by approximately 0.1 Å to approximately 0.2 Å. Over approximately 3 to 5 deposition cycles, ΔV... fbThe voltage was adjusted from approximately 32 mV to approximately 37 mV. Simultaneously, ΔCET was adjusted from approximately 0.3 Å to approximately 0.4 Å. Over approximately 7 to approximately 9 deposition cycles, ΔV... fb The voltage was adjusted from approximately 35 mV to approximately 40 mV. Simultaneously, ΔCET was adjusted from approximately 0.4 Å to approximately 0.5 Å. Over approximately 25 to approximately 30 deposition cycles, ΔV... fb It was adjusted by approximately 40 mV to approximately 45 mV. Simultaneously, ΔCET was adjusted by approximately 0.4 angstroms to approximately 0.5 angstroms. Therefore, as... Figure 19B As shown, although the number of deposition cycles initially significantly affects the critical voltage adjustment, its effect quickly saturates. When the number of cycles exceeds approximately 15, ΔV fb Any change in ΔCET becomes negligible. In some embodiments, the deposition of the dipole layer 284 is configured to perform more than 15 cycles. Therefore, the annealing temperature essentially determines ΔV. fb Or ΔCET. This significantly simplifies the design of multiple Vt devices. In other words, when the thickness of the dipole layer 284 exceeds the saturation level, the critical voltage can be adjusted by adjusting the annealing temperature of the heat treatment process (e.g., heat treatment process 600). As mentioned above, in some embodiments, the annealing temperature is from about 850°C to about 900°C to provide a critical voltage of about 40mV to about 80mV. It should be noted that different annealing temperatures can be implemented if the target critical voltage adjustment range is different, for example, referring to... Figure 19A Implementation.

[0053] Therefore, the number of deposition cycles, annealing temperature, and annealing duration collectively determine the concentration of the dipolar material. The above disclosure describes first employing a specific number of deposition cycles (e.g., the number of oversaturation deposition cycles), and then adjusting the critical voltage primarily based on the annealing temperature. Alternatively, the annealing temperature can be determined first based on certain design requirements, allowing the adjustment of the number of deposition cycles to be used as the primary method for adjusting the critical voltage. Similarly, the annealing duration can be used alone or in combination with other parameters to fine-tune the critical voltage. Regardless of the specific method, these methods enable control of the concentration of the dipolar material within the high-k gate dielectric layer 282'. This concentration can be expressed as the ratio of dipolar elements (e.g., aluminum) to the metal elements of the high-k gate dielectric layer 282. Figure 19CThe diagram shows concentration profiles of various elements in an apparatus manufactured according to embodiments of the present disclosure, based on Energy Dispersive X-ray spectroscopy (EDS) data. In this example, the high-k gate dielectric layer 282 comprises hafnium oxide, and the dipolar element is aluminum. Therefore, most of the hafnium element is located within the boundary surfaces 295 and 297 of the high-k gate dielectric layer 282'. Similarly, most of the aluminum element is also located within the boundary surfaces 295 and 297. In some embodiments, the ratio of aluminum concentration (based on EDS signal intensity assessment) to hafnium concentration (based on EDS signal intensity assessment) at boundary surfaces 295 and 297 can each be configured to be from about 1:4 to about 1:1.5. In some embodiments, the ratio of aluminum concentration to hafnium concentration can each be configured to be from about 1:3 to about 1:2. In some embodiments, the ratio of aluminum concentration to hafnium concentration at the artificial plane 299 may be configured to be from about 1:8 to about 1:3, wherein the artificial plane 299 cuts through the high-k gate dielectric layer 282' at an intermediate thickness. In some embodiments, the ratio of aluminum concentration to hafnium concentration at the artificial plane 299 may be configured to be from about 1:6 to about 1:4. If the concentration of the dipole material (or the ratio of the dipole material to the metal elements of the high-k gate dielectric layer 282) is too small, the critical voltage regulation capability may be insufficient. Conversely, if the concentration (or ratio) is too large, any additional benefit may not justify the additional cost.

[0054] In some embodiments, the above method is performed to form a p-type dipole within the high-k gate dielectric layer 282 of the transistor, for example, to lower the threshold voltage of the p-type transistor or increase the threshold voltage of the n-type transistor. In some embodiments, the above method may be implemented in conjunction with the formation of an n-type dipole on the same device. Figure 14 A flowchart of method 500 is provided according to this disclosure. Figure 15 The portion of method 500 relating to the formation of an n-type dipole on semiconductor device 400 is shown; while Figures 16A to 16C The portion of method 500 related to the formation of a p-type dipole on semiconductor device 400 is shown. Semiconductor device 400 includes device region 402a and device region 402b, each similar to... Figures 2B to 2CThe substrate 202. Device regions 402a and 402b may include the same or different dopant types. Furthermore, device regions 402a and 402b may be adjacent to or far from each other. Device region 402a further includes sub-regions 1402A and 1402A', each of which is configured for transistors with different threshold voltages; and device region 402b further includes sub-regions 1402B and 1402B', each of which is configured for transistors with different threshold voltages.

[0055] Now refer to Figure 15 In operation 502 ( Figure 14 In method 500, a semiconductor device 400 having device regions 402a and 402b is received or provided. Each of the device regions 402a and 402b includes sub-regions 1402A, 1402A' and 1402B, 1402B', respectively. Each of the sub-regions 1402A, 1402A' and 1402B, 1402B' includes initial structures formed thereon, these initial structures being similar to those described above. Figures 2A to 2C The structures described above. Therefore, the following diagrams have been further simplified, illustrating only the relevant parts of the structures. For example, in the following diagrams, only the channel layer 215, the interface layer 280, the high-k gate dielectric layer 282, the dipole layer (described below), and the masking layer are shown. In operation 504 of method 500 ( Figure 15 The interface layer 280 is formed to surround each channel layer 215 in each substrate region. In operation 506 of method 500 ( Figure 15 A high-k gate dielectric layer 282 is formed to surround each interface layer 280 in each substrate region. The interface layer 280 and the high-k gate dielectric layer 282 may be similar to those previously described with reference to method 100.

[0056] At this stage of the process, the processes for device regions 402a and 402b diverge. In some embodiments, method 500 proceeds to process device region 402a by introducing an n-type dipole layer 284a, as... Figures 16A to 16C As shown and with Figure 14 This relates to operations 508A-512A; while in other embodiments, method 500 proceeds to process device region 402b by introducing a p-type dipole layer 284b, as... Figures 17A to 17C As shown and with Figure 14 This relates to the operation of 508B-512B.

[0057] In some embodiments, device region 402a is processed before device region 402b. In other words, Figure 14 The execution of operations 508A-512A predates... Figure 14 Operations 508B-512B. This can be referred to as the "p-dipole post-processing" method. For example, a masking element is formed to cover device region 402b, such that all operations are directed at device region 402a. In operation 508A, method 500 ( Figure 14 ) enters the dipole layer 284a that forms around the surface of the high-k gate dielectric layer 282 and is connected to the surface of the high-k gate dielectric layer 282. Figure 16A In some embodiments, the dipole layer 284a is an n-type dipole layer and includes an n-type dipole material. For example, the dipole layer 284a includes lanthanum oxide (La2O3), yttrium oxide (Y2O3), other suitable n-type dipole materials, or combinations thereof. Furthermore, a hard mask layer 288' is formed around the dipole layer 284a. The hard mask layer 288' includes a suitable hard mask material. In some embodiments, the hard mask material may be aluminum oxide. Subsequently, a dielectric layer 288 is formed over the device region 402a and patterned to cover only the sub-region 1402A', while simultaneously exposing the sub-region 1402A in the gate trench 275. A similar dielectric layer can be used. Figure 6 The described method forms a patterned dielectric layer 288. (See reference...) Figure 16B The etching operation removes the portion of the hard mask layer 288' exposed in the gate trench 275, as well as the portion of the dipole layer 284a beneath it. Therefore, the high-k gate dielectric layer 282 in sub-region 1402A becomes exposed. Simultaneously, the portion of the hard mask layer 288' covered by the patterned dielectric layer 288 and the portion of the dipole layer 284a covered by the patterned dielectric layer 288 remain intact. Subsequently, the patterned dielectric layer 288 can be removed using a suitable method (e.g., an ashing operation), and the hard mask layer 288' can be removed using a suitable method (e.g., wet etching). Thus, the dipole layer 284a exists in sub-region 1402A' and is exposed in the gate trench 275, but is not present in sub-region 1402A. In operation 510A, a thermal processing process 600A is performed on device 400. Figure 16C In this way, the dipole material in the dipole layer 284a is thermally driven into the portion of the high-k gate dielectric layer 282 within subregion 1402A'. The high-k gate dielectric layer 282 thus modulated is referred to as "high-k gate dielectric layer 282". The modulated high-k gate dielectric layer 282" can be similar to the one described above. Figure 9The high-k gate dielectric layer 282' differs in that it uses a different dipole material. In other words, the modulated high-k gate dielectric layer 282' comprises an n-type dipole material instead of a p-type dipole material (e.g., aluminum oxide). Because there is no dipole layer 284a in sub-region 1402A, the high-k gate dielectric layer 282 there remains unmodulated. In some embodiments, the heat treatment process 600A may be performed at temperatures from about 600°C to about 750°C. If the temperature is too low, the amount of dipole material driven into the high-k gate dielectric layer 282 may be too small to achieve effective threshold voltage adjustment; while if the temperature is too high, the migration behavior may be difficult to control. Afterwards, any remaining portion of the dipole layer 284a is removed using a suitable method. Figure 14 Operation 512A).

[0058] The above-described process provides gate dielectric layers with different configurations for various sub-regions. These sub-regions provide different threshold voltages for the transistors after the gate electrode layers are subsequently formed thereon. In some embodiments, operations 508A-512A are repeated, albeit in different subsets of the device region (or sub-region). Furthermore, the dipole material, annealing temperature, and / or duration, as well as the etching parameters implemented in the dipole layer 284a, may differ from the first cycle of operations 508A-512A. Therefore, some portions of the gate dielectric layer may further differentiate in terms of their dipole configurations. In some embodiments, operations 508A-512A are repeated twice before further processing is performed.

[0059] In some embodiments, method 500 proceeds to process device region 402b, for example, while simultaneously covering the processed device region 402a under a masking element. In some embodiments, this part of the process is similar to that described above. Figure 1 and Figures 3 to 12 The aforementioned processes. Therefore, the subsequent description is simplified. In some embodiments, method 500 proceeds to forming another dipole layer 284b in device region 402b. Figure 14 (Operation 508B). The dipole layer 284b is formed to be directly connected to the high-k gate dielectric layer 282. In some embodiments, the dipole layer 284b may be similar to that described above. Figures 4 to 8 The dipole layer 284, and can undergo the process described above (see reference). Figures 4 to 8The same process is described. In some embodiments, dipole layer 284b differs from dipole layer 284a. For example, dipole layer 284b may comprise aluminum oxide. Furthermore, the thickness of dipole layer 284b may be configured to be greater than half the vertical spacing between vertically adjacent portions of the high-k gate dielectric layer 282. Therefore, dipole layer 284b is fused within the spacing between channel layers. Further, the outer surface of dipole layer 284b may be recessed (similar to...). Figure 1 (Operation 108). For example, the dipole layer 284b on the sidewall surface of the dielectric fin 231, the top surface of the top channel layer 215, and the sidewall surface of the channel layer 215 is recessed. However, the dipole layer 284b between vertically adjacent channel layers 215 is not substantially recessed beyond the outermost edge. Therefore, the dipole layer 284b can serve as a hard mask layer in subsequent patterning operations. The device is then patterned (similar to...). Figure 1 Operations 110-112) Figures 17A to 17B Subsequently, method 500 proceeds to annealing the semiconductor device 400 in a heat treatment process 600B, thereby driving the dipole material of the dipole layer 284b into the portion of the high-k gate dielectric layer 282 connected to it. In some embodiments, the temperature implemented in heat treatment process 600B may be higher than the temperature of heat treatment process 600A. Without theoretical limitations, diffusion of alumina may be more difficult than that of lanthanum oxide and requires higher temperatures. In some embodiments, the temperature of heat treatment process 600B may be implemented at approximately 850°C to approximately 900°C. In other words, the temperature of heat treatment process 600B may be approximately 100°C to approximately 300°C higher than the temperature of heat treatment process 600A. If the temperature is too low or the temperature difference is too small, the amount of dipole material driven into the high-k gate dielectric layer 282 may be too small, thus failing to achieve effective threshold voltage adjustment; while if the temperature is too high or the temperature difference is too large, the migration behavior may be difficult to control. Then, using appropriate methods, remove any remaining portions of the still-existing dipole layer 284b. Figure 14 Operation 512B).

[0060] exist Figure 17C In the illustrated embodiment, a dipole material is driven into a portion of the high-k gate dielectric layer 282 within sub-region 1402B', but not into a portion of the high-k gate dielectric layer 282 within sub-region 1402B. In this way, the high-k gate dielectric layer 282 remains unmodulated in sub-region 1402B, but is transformed into a modulated high-k gate dielectric layer 282' in sub-region 1402B'. In some embodiments, the modulated high-k gate dielectric layer 282' is similar to that described above. Figure 9The high-k gate dielectric layer 282' is described. Therefore, sub-region 1402B includes the unmodified high-k gate dielectric layer 282, while sub-region 1402B' includes the modulated high-k gate dielectric layer 282'. Similarly, operations 508B-512B can be repeated to provide a gate dielectric layer portion with a further variation in the dipole material composition. In operations 514-518, method 500 proceeds to forming another high-k gate dielectric layer 285 to cover the modulated high-k gate dielectric layers 282', 282' and the unmodulated high-k gate dielectric layer 282. A capping layer 287 is formed over the high-k gate dielectric layer 285, and a gate electrode layer 286 or 286' is formed over the capping layer 287. Additional thin layers may be formed to complete the fabrication of the device. Figure 18 ).

[0061] The foregoing description provides for processing the n-type dipole in device region 402a before processing the p-type dipole in device region 402b. In some alternative embodiments, the processing of device region 402b is earlier than that of device region 402a. In other words, Figure 14 Operations 508B-512B were executed earlier than Figure 14 The operation is described in 508A-512A. This can be referred to as the "p-dipole first" method. In some embodiments, the "p-dipole later" method offers many advantages over the "p-dipole first" method. For example, in some embodiments, forming the p-dipole layer first may negatively affect the tuning capability of the n-type dipole; this negative effect does not exist in the "p-dipole later" method. Furthermore, the heat treatment process in the "p-dipole later" method provides a flat band voltage (Vp) of approximately 40mV to approximately 90mV. fbThe adjustment capability is significantly improved compared to the "p-dipole first" method, where the same thermal processing provides only about 10mV to about 30mV. Furthermore, the "p-dipole post-processing" method offers reduced risks in terms of n-dipole gate filling, DC% loss, and leakage current compared to the "p-dipole first" method. Further manufacturing operations can be provided to complete the fabrication of semiconductor device 200 or semiconductor device 400. For example, source / dipole contacts, vias, metal lines, passivation features, and other suitable features can be formed to complete the IC. While not intended to be limiting, one or more embodiments of this disclosure provide numerous benefits for semiconductor devices and their formation. For example, using embodiments of this disclosure, alumina can be implemented as a p-type dipole material and used in combination with an n-type dipole material to provide an additional critical voltage supply. For example, in some embodiments, lanthanum oxide can be implemented in one or more cycles of operation 508A-512A; while alumina can be implemented in one or more cycles of operation 508B-512B. Therefore, the number of available critical voltages is increased compared to methods that only implement lanthanum oxide. This improves the overall performance of the device. Furthermore, embodiments of this disclosure enable multiple Vt supplies that were previously difficult to provide. For example, embodiments of this disclosure provide a critical voltage adjustable range greater than about 300 mV to about 400 mV. For example, in some embodiments, the methods described herein can provide a critical voltage adjustable range of about 300 mV to about 550 mV, for example, about 400 mV to about 500 mV. Achieving such a wide adjustable range can be quite challenging in schemes that do not implement the methods described herein. Moreover, the implementation of the p-type dipole according to embodiments of this disclosure enables the manufacture of devices that were previously difficult to manufacture. For example, by implementing a p-dipole as described herein, a PFET (e.g., eLVT devices and xLVT devices) with extremely low threshold voltage can be realized. Similarly, by implementing a p-dipole as described herein, an NFET (e.g., S_LLVT-1 devices and S_LLVT-2 devices) with ultra-low leakage current can be realized.

[0062] Although not explicitly described, those skilled in the art will understand that the embodiments of this disclosure can be applied to other types of devices, such as FinFETs, planar MOSFETs, other multi-gate FETs, or other similar devices. Those devices are also included within the scope of this disclosure.

[0063] In one exemplary embodiment, this disclosure relates directly to a method of manufacturing a semiconductor device. The method includes receiving a workpiece having a first stack of a plurality of first semiconductor layers in a first region and a second stack of a plurality of second semiconductor layers in a second region; forming a first gate dielectric layer and a second gate dielectric layer, the first gate dielectric layer surrounding each of the plurality of first semiconductor layers in the first stack, and the second gate dielectric layer surrounding each of the plurality of second semiconductor layers in the second stack; forming a first dipole layer and a second dipole layer, the first dipole layer surrounding the first gate dielectric layer and fused between vertically adjacent portions of the first gate dielectric layer, and the second dipole layer surrounding the second gate dielectric layer and fused between vertically adjacent portions of the second gate dielectric layer; removing the first dipole layer; performing a first annealing on the workpiece after removing the first dipole layer; removing the remaining portion of the second dipole layer; and forming a gate electrode layer in the first and second regions.

[0064] In one embodiment of the method for manufacturing the semiconductor device described above, a first annealing of the workpiece drives the dipole material of the second dipole layer into the second gate dielectric layer. In another embodiment, the second dipole layer comprises a first oxide material having a first oxygen surface density, and the second gate dielectric layer comprises a second oxide material having a second oxygen surface density, wherein the first oxygen surface density is greater than the second oxygen surface density.

[0065] In one embodiment of the method for manufacturing the semiconductor device described above, each of the first dipole layer and the second dipole layer comprises aluminum oxide, and each of the first gate dielectric layer and the second gate dielectric layer comprises hafnium oxide.

[0066] In one embodiment, forming the second dipole layer includes forming a precursor layer surrounding the second gate dielectric layer; and recessing the precursor layer to form the second dipole layer. In a further embodiment, the recess in the precursor layer expands the lateral dimension of the opening between the second stack of the second semiconductor layer and the adjacent dielectric fin.

[0067] In one embodiment, the method of manufacturing the semiconductor device further includes forming a bottom anti-reflective coating (BARC) layer covering a second stack of multiple second semiconductor layers before removing the first dipole layer; the bottom anti-reflective coating having openings in the first stack exposing the multiple first semiconductor layers; wherein the bottom anti-reflective coating is directly connected to the second dipole layer.

[0068] In one embodiment, removal of the first dipole layer includes etching with ammonium hydroxide. In another embodiment, the first annealing is performed at a temperature of about 850 degrees Celsius to about 900 degrees Celsius. In yet another embodiment, adjacent second semiconductor layers of a second stack of a plurality of second semiconductor layers are perpendicularly separated from each other by a first distance; the second dipole layer has a thin layer thickness on the sidewall surface of the second dipole layer; and the thin layer thickness is equal to or greater than half of the first distance.

[0069] In one embodiment, receiving a workpiece includes receiving a third stacked workpiece having a plurality of third semiconductor layers in a third region, and the execution of a first annealing includes execution at a first temperature, and the method of manufacturing the semiconductor device further includes forming a third gate dielectric layer surrounding each of the plurality of third semiconductor layers in the third stack; forming a third dipole layer surrounding the third gate dielectric layer; and performing a second annealing on the workpiece at a second temperature; wherein the first temperature is greater than the second temperature; and wherein the second dipole layer comprises aluminum and the third dipole layer comprises lanthanum oxide.

[0070] In another exemplary embodiment, this disclosure relates to a method of manufacturing a semiconductor device. The method includes receiving a semiconductor device having a plurality of substrate regions, each of the plurality of substrate regions having a stack of a plurality of channel layers thereon; forming a plurality of interface layers that surround each of the channel layers in each of the plurality of substrate regions; forming a plurality of gate dielectric layers that surround each of the interface layers in each of the plurality of substrate regions; forming a first dipole layer that surrounds a plurality of gate dielectric layers in a first subset of the plurality of substrate regions, wherein the first dipole layer has a p-type dipole material and fills the space between perpendicularly adjacent channel layers; performing a first thermal processing step to form a plurality of first-doped gate dielectric layers in the first subset of the plurality of substrate regions; removing the remaining portion of the first dipole layer; and forming gate electrode layers surrounding the plurality of first-doped gate dielectric layers.

[0071] In one embodiment, the p-type dipole material is aluminum oxide. In one embodiment, the method of manufacturing the semiconductor device further includes forming a second dipole layer that surrounds a plurality of gate dielectric layers in a second subset of a plurality of substrate regions, wherein the second dipole layer has an n-type dipole material; performing a second heat treatment process to form a plurality of second doped gate dielectric layers in the second subset of the plurality of substrate regions; and removing the remaining portion of the second dipole layer. In a further embodiment, the p-type dipole material is aluminum oxide, and the n-type dipole material is lanthanum oxide. In another further embodiment, the formation of the second dipole layer is performed after performing a first heat treatment process.

[0072] In yet another exemplary embodiment, this disclosure relates to a semiconductor device. The semiconductor device includes a semiconductor substrate; a first stack of a plurality of first channel layers and a second stack of a plurality of second channel layers, located on the semiconductor substrate; a first gate dielectric layer, comprising a plurality of thin layers surrounding the first stack of the plurality of first channel layers, the first gate dielectric layer comprising a p-type dipole material; a second gate dielectric layer, comprising a plurality of thin layers surrounding the second stack of the plurality of second channel layers, the second gate dielectric layer comprising an n-type dipole material; and a gate electrode located on the first gate dielectric layer and on the second gate dielectric layer.

[0073] In one embodiment, the p-type dipole material is aluminum oxide, and the n-type dipole material is lanthanum oxide. In a further embodiment, the first gate dielectric layer includes hafnium oxide, and the ratio of aluminum concentration to hafnium concentration in the first gate dielectric layer is approximately 1:3 to approximately 1:2 at the surface of the first gate dielectric layer.

[0074] In another embodiment, the first gate dielectric layer includes a gate dielectric material having a first metal element, and the p-type dipole material includes a second metal element, and the concentration ratio of the second metal element to the first metal element is about 1:6 to about 1:4 at an intermediate thickness of the first gate dielectric layer.

[0075] The foregoing outlines the features of various embodiments or examples to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that they can easily design or modify other processes and structures based on this disclosure to achieve the same purpose and / or obtain the same advantages as the embodiments or examples described herein. Those skilled in the art should also understand that these equivalent structures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to this disclosure without departing from its spirit and scope.

Claims

1. A method for manufacturing a semiconductor device, comprising: A workpiece is received, the workpiece having a first stack of a plurality of first semiconductor layers in a first region and a second stack of a plurality of second semiconductor layers in a second region; A first gate dielectric layer and a second gate dielectric layer are formed, wherein the first gate dielectric layer surrounds each of the first semiconductor layers in the first stack, and the second gate dielectric layer surrounds each of the second semiconductor layers in the second stack. A first dipole layer and a second dipole layer are formed, wherein the first dipole layer surrounds the first gate dielectric layer and is fused between vertically adjacent portions of the first gate dielectric layer, and the second dipole layer surrounds the second gate dielectric layer and is fused between vertically adjacent portions of the second gate dielectric layer. The first dipole layer and the second dipole layer are recessed to reduce the thickness of the first dipole layer and the second dipole layer. After the first dipole layer and the second dipole layer are recessed, the first dipole layer is selectively removed. After selectively removing the first dipole layer, a first annealing is performed on the workpiece. After performing the first annealing described above, remove the remaining portion of the second dipole layer; and A gate electrode layer is formed in the first region and the second region.

2. The method of manufacturing a semiconductor device as claimed in claim 1, wherein the first annealing of the workpiece drives a dipole material of the second dipole layer into the second gate dielectric layer.

3. The method of manufacturing a semiconductor device as claimed in claim 1, wherein the second dipole layer comprises a first oxide material having a first oxygen surface density, and the second gate dielectric layer comprises a second oxide material having a second oxygen surface density, wherein the first oxygen surface density is greater than the second oxygen surface density.

4. The method for manufacturing a semiconductor device as claimed in claim 1, wherein: Each of the first dipole layer and the second dipole layer comprises aluminum oxide; and Each of the first gate dielectric layer and the second gate dielectric layer comprises hafnium oxide.

5. The method for manufacturing a semiconductor device as claimed in claim 1, wherein the formation of the second dipole layer comprises: A precursor layer is formed around the second gate dielectric layer described above; as well as The aforementioned precursor layer is recessed to form the aforementioned second dipole layer.

6. The method of manufacturing a semiconductor device as claimed in claim 5, wherein the recess in the precursor layer expands a lateral dimension of an opening between the second stack of the second semiconductor layer and an adjacent dielectric fin.

7. The method of manufacturing a semiconductor device as claimed in claim 1, further comprising: Before removing the first dipole layer, a bottom anti-reflective coating is formed on the second stack covering the second semiconductor layer, the bottom anti-reflective coating having an opening in the first stack exposing the first semiconductor layer; The aforementioned bottom anti-reflective coating is directly connected to the aforementioned second dipole layer.

8. The method of manufacturing a semiconductor device as claimed in claim 1, wherein the removal of the first dipole layer comprises etching with ammonium hydroxide.

9. The method of manufacturing a semiconductor device as claimed in claim 1, wherein the first annealing is performed at a temperature of 850 degrees Celsius to 900 degrees Celsius.

10. The method of manufacturing a semiconductor device as claimed in claim 1, wherein: The adjacent second semiconductor layers of the aforementioned second stack are perpendicularly separated from each other by a first distance; The second dipole layer has a thin layer thickness on one sidewall surface of the second dipole layer; and The thickness of the aforementioned thin layer is equal to or greater than half of the aforementioned first distance.

11. The method of manufacturing a semiconductor device as claimed in claim 1, wherein: Receiving the aforementioned workpiece includes receiving the aforementioned workpiece in a third stack having a plurality of third semiconductor layers in a third region; as well as The aforementioned first annealing is performed at a first temperature; The manufacturing method of the aforementioned semiconductor device further includes: A third gate dielectric layer is formed, the third gate dielectric layer surrounding each of the third semiconductor layers in the third stack; A third dipole layer is formed, the third dipole layer surrounding the third gate dielectric layer; and A second annealing is performed on the above-mentioned workpiece at a second temperature; Wherein the first temperature is greater than the second temperature; and The second dipole layer mentioned above includes aluminum, while the third dipole layer mentioned above includes lanthanum oxide.

12. A method for manufacturing a semiconductor device, comprising: A semiconductor device receiving a semiconductor device having a plurality of substrate regions, each of said substrate regions having a stack of a plurality of channel layers thereon; Multiple interface layers are formed, each of the aforementioned channel layers enclosing each of the aforementioned channel layers surrounding the aforementioned substrate region; Multiple gate dielectric layers are formed, wherein each of the aforementioned interface layers surrounds each of the aforementioned substrate regions; A first dipole layer is formed, wherein the first dipole layer encloses the gate dielectric layer in a first subset surrounding the substrate region, wherein the first dipole layer has a p-type dipole material and fills the gap between the vertically adjacent channel layers. The first dipole layer is recessed to reduce its thickness. A first thermal processing step is performed to form a plurality of first doped gate dielectric layers in the first subset of the substrate region. Remove the remaining portion of the first dipole layer described above; as well as A gate electrode layer is formed surrounding the first doped gate dielectric layer.

13. The method for manufacturing a semiconductor device as claimed in claim 12, wherein the p-type dipole material is aluminum oxide.

14. The method of manufacturing a semiconductor device as claimed in claim 12, further comprising: A second dipole layer is formed, wherein the second dipole layer encloses the gate dielectric layer in a second subset surrounding the substrate region, wherein the second dipole layer has an n-type dipole material. Perform a second thermal processing step to form a plurality of second doped gate dielectric layers in the second subset of the substrate region; and Remove the remaining portion of the second dipole layer described above.

15. The method for manufacturing a semiconductor device as claimed in claim 14, wherein the p-type dipole material is aluminum oxide and the n-type dipole material is lanthanum oxide.

16. The method of manufacturing a semiconductor device as claimed in claim 14, wherein the formation of the second dipole layer is performed after the first heat treatment process is executed.

17. A semiconductor device, comprising: A semiconductor substrate; A first stack of multiple first channel layers and a second stack of multiple second channel layers are located on the semiconductor substrate; A first gate dielectric layer, a thin layer of the first stack surrounding the first channel layer, the first gate dielectric layer comprising a p-type dipole material; A second gate dielectric layer, a thin layer surrounding the second channel layer of the second stack, the second gate dielectric layer comprising an n-type dipole material; and A gate electrode is located on the first gate dielectric layer and on the second gate dielectric layer.

18. The semiconductor device of claim 17, wherein the p-type dipole material is aluminum oxide and the n-type dipole material is lanthanum oxide.

19. The semiconductor device of claim 18, wherein the first gate dielectric layer comprises hafnium oxide, and the ratio of aluminum concentration to hafnium concentration in the first gate dielectric layer is 1:3 to 1:2 at the surface of the first gate dielectric layer.

20. The semiconductor device of claim 17, wherein the first gate dielectric layer comprises a gate dielectric material having a first metal element, and the p-type dipole material comprises a second metal element, and the concentration ratio of the second metal element to the first metal element is 1:6 to 1:4 at an intermediate thickness of the first gate dielectric layer.

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