Method of manufacturing a semiconductor device

Abstract

The present disclosure provides a method for manufacturing a semiconductor device, comprising: forming a stack structure on a first region of a semiconductor layer, the stack structure comprising a first gate dielectric layer and a sacrificial layer; forming a trench and an insulating layer in the trench on the first region and a second region of the semiconductor layer, the first region and the second region being connected or separated; forming a protective layer on sidewalls of the trench exposed in the second region; forming a protective layer on the sidewalls of the exposed trench; and wet etching the sacrificial layer in the first region, wherein the protective layer protects the sidewalls of the trench during the wet etching. The method protects the semiconductor layer from damage during the wet etching step by first forming a protective layer on the exposed semiconductor layer before performing the wet etching process to remove the sacrificial layer.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a method for manufacturing a semiconductor device. Background Technology

[0002] With the rapid development of very large-scale integrated circuits (VLSI), the integration density of semiconductor chips is becoming increasingly higher. The manufacturing process of semiconductor components involves numerous complex steps to form the desired semiconductor devices. Metal-oxide-semiconductor (MOSFET) transistors are an important basic component in integrated circuits, primarily composed of a semiconductor layer, a gate dielectric layer, a gate conductor, and source / drain doped regions. Complementary metal-oxide-semiconductor (CMOS) transistors are widely used because they can simultaneously incorporate both N-channel and P-channel field-effect transistors.

[0003] However, when a semiconductor device includes planar gate and trench gate structures, during the manufacturing process, the semiconductor layer in the trench gate region may come into contact with some etchants, causing changes in the morphology of the semiconductor layer, which in turn affects the device formed subsequently.

[0004] Therefore, it is hoped that the manufacturing methods of semiconductor devices can be further improved to effectively address the aforementioned problems. Summary of the Invention

[0005] The purpose of this disclosure is to provide an improved method for manufacturing a semiconductor device, which protects the semiconductor layer from damage during the wet etching step by first forming a protective layer on the exposed semiconductor layer and then performing a wet etching process to remove the sacrificial layer.

[0006] A method for manufacturing a semiconductor device according to an embodiment of this disclosure includes: forming a stacked structure on a first region of a semiconductor layer, including a first gate dielectric layer and a sacrificial layer; forming a trench and an insulating layer located in the trench in the first region and a second region of the semiconductor layer, wherein the first region and the second region of the semiconductor layer are connected or separated; forming a sidewall in the second region that exposes at least a portion of the trench; forming a protective layer on the exposed sidewall of the trench; and wet etching the sacrificial layer located in the first region, wherein, during the wet etching process, the protective layer protects the sidewall of the trench.

[0007] Optionally, the first region is a high-voltage device region, and the second region is a low-voltage device region.

[0008] Optionally, the method further includes doping the semiconductor layer through the trench in the second region to form a doped region, wherein the protective layer protects the sidewalls of the trench during the doping process.

[0009] Optionally, in the second region, the protective layer is also formed on the surface of the semiconductor layer, wherein the protective layer also protects the surface of the semiconductor layer during the wet etching and doping processes.

[0010] Optionally, the step of forming the trench includes: forming a first gate dielectric layer on a first region and a second region of the semiconductor layer; forming a sacrificial layer on the surface of the first gate dielectric layer; and etching the first gate dielectric layer and the semiconductor layer through the sacrificial layer to form the trench in the first region and the second region, respectively.

[0011] Optionally, the step of forming the stacked structure includes removing the first gate dielectric layer and the sacrificial layer on the second region, and retaining the first gate dielectric layer and the sacrificial layer on the first region as the stacked structure.

[0012] Optionally, in the first region, the insulating layer serves as a trench isolation layer penetrating the first gate dielectric layer.

[0013] Optionally, the step of forming a sidewall that exposes at least a portion of the trench includes: in the second region, removing at least a portion of the insulating layer in the trench to expose the sidewall, wherein the insulating layer at the bottom of the trench in the second region is retained, wherein the retained insulating layer is connected to the protective layer located on the sidewall of the trench.

[0014] Optionally, it further includes: in the second region, removing the protective layer and the insulating layer at the bottom of the trench to re-expose the trench; and in the second region, forming a second gate dielectric layer covering the inner surface of the trench.

[0015] Optionally, a first gate conductor is formed on the surface of the first gate dielectric layer, and a second gate conductor is formed inside the trench in the second region.

[0016] Optionally, the semiconductor layer is made of silicon, and in the step of forming the protective layer, the semiconductor layer is oxidized by a thermal oxidation process to form the protective layer.

[0017] Optionally, the thermal oxidation process includes a dry oxidation process and / or a wet oxidation process, the material of the sacrificial layer includes silicon nitride, and in the step of forming the protective layer, the oxidation rate of the sacrificial layer is less than the oxidation rate of the semiconductor layer.

[0018] Optionally, the etchant used in the wet etching includes phosphoric acid.

[0019] According to the semiconductor device manufacturing method provided in the embodiments of this disclosure, before removing the sacrificial layer in the first region, a protective layer is first formed on the exposed semiconductor layer in the second region, and then a wet etching process is performed to remove the sacrificial layer. The protective layer protects the semiconductor layer from damage, thereby improving the problem of morphological changes in the semiconductor layer during the wet etching process to remove the sacrificial layer.

[0020] Furthermore, since the semiconductor layer in the second region needs to be doped after the sacrificial layer removal step, even though the incident energy of the dopant impurities is very high in this step, there is still a protective layer to protect the semiconductor layer, thereby reducing the risk of damage to the semiconductor layer during the doping step.

[0021] This manufacturing method preserves the insulating layer at the bottom of the trench in the second region, which also serves as a protective layer, thereby protecting the semiconductor layer during wet etching and doping steps.

[0022] Furthermore, in the second region, since the retained insulation layer already covers the bottom of the trench (or the deepest part of the trench), the protective layer only needs to be formed on the shallower part of the trench sidewalls, thus reducing the difficulty of making the protective layer.

[0023] This manufacturing method uses a thermal oxidation process to form a protective layer. The high temperature results in a high-quality protective layer, which can more effectively prevent the etchant from entering the semiconductor layer during the wet etching step.

[0024] Furthermore, since the protective layer formed by the thermal oxidation process is very thin, the morphology of the semiconductor layer surface and the inner surface of the trench will hardly change due to the protective layer. Therefore, after the protective layer is removed, the inner surface of the trench is still relatively flat, which is more conducive to forming a gate dielectric layer with better consistency on the inner surface of the trench.

[0025] Furthermore, in dry oxidation and / or wet oxidation processes, the sacrificial layer of silicon nitride material has a relatively high oxidation selectivity compared to the semiconductor layer of silicon material. Therefore, after a protective layer is formed on the surface of the semiconductor layer, the sacrificial layer is hardly affected, and in subsequent wet etching steps, the sacrificial layer is easily removed relative to the protective layer.

[0026] Therefore, the method for manufacturing semiconductor devices according to embodiments of this disclosure improves product yield and reliability. Attached Figure Description

[0027] The above and other objects, features and advantages of this disclosure will become clearer from the following description of embodiments of this disclosure with reference to the accompanying drawings.

[0028] Figure 1 This is a first structural schematic diagram of a semiconductor device manufacturing method in the first embodiment of this disclosure.

[0029] Figure 2 This is a schematic diagram of the second structure of the semiconductor device manufacturing method in the first embodiment of this disclosure.

[0030] Figure 3 This is a schematic diagram of the third structure of the semiconductor device manufacturing method in the first embodiment of this disclosure.

[0031] Figure 4 This is a schematic diagram of the fourth structure of the semiconductor device manufacturing method in the first embodiment of this disclosure.

[0032] Figure 5 This is a fifth structural schematic diagram of the semiconductor device manufacturing method in the first embodiment of this disclosure.

[0033] Figure 6 SEM image of the substrate damaged during the sacrificial layer removal step.

[0034] Figure 7 This is a schematic diagram of the sixth structure of the semiconductor device manufacturing method in the first embodiment of this disclosure.

[0035] Figure 8 This is a schematic diagram of the seventh structure of the semiconductor device manufacturing method in the first embodiment of this disclosure.

[0036] Figure 9 This is a schematic diagram of the eighth structure of the semiconductor device manufacturing method in the first embodiment of this disclosure.

[0037] Figure 10 This is a schematic diagram of the first structure of the semiconductor device manufacturing method in the second embodiment of this disclosure.

[0038] Figure 11 This is a schematic diagram of the second structure of the semiconductor device manufacturing method in the second embodiment of this disclosure.

[0039] Figure 12 This is a schematic diagram of the third structure of the semiconductor device manufacturing method in the second embodiment of this disclosure.

[0040] Figure 13 This is a schematic diagram of the fourth structure of the semiconductor device manufacturing method in the second embodiment of this disclosure.

[0041] Figure 14 This is a schematic diagram of the fifth structure of the semiconductor device manufacturing method in the second embodiment of this disclosure. Detailed Implementation

[0042] The present disclosure will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown. For simplicity, a semiconductor structure obtained after several steps can be depicted in a single figure.

[0043] It should be understood that when describing the structure of a device, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above another layer or region, or that there are other layers or regions between it and another layer or region. Furthermore, if the device is flipped, that layer or region will be located "below" or "under" another layer or region.

[0044] Many specific details of this disclosure, such as the structure, materials, dimensions, processing methods, and techniques of the devices, are described below to provide a clearer understanding of this disclosure. Of course, this disclosure may also be implemented without following these specific details.

[0045] The present disclosure will now be described in more detail with reference to the accompanying drawings. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown. For simplicity, a semiconductor structure obtained after several steps can be depicted in a single figure.

[0046] When forming a semiconductor device that includes both planar gate and trench gate structures, the first embodiment of this disclosure is manufactured through the following steps.

[0047] like Figure 1 As shown, an isolation layer 102 is formed on the surface of the semiconductor layer 101, and a sacrificial layer 103 is formed on the surface of the isolation layer 102.

[0048] In this step, for example, chemical vapor deposition (CVD) and / or physical vapor deposition (PVD) processes are used to sequentially deposit an isolation layer 102 and a sacrificial layer 103 on the semiconductor layer 101 along the thickness direction of the semiconductor layer 101.

[0049] In this embodiment, the semiconductor layer 101 is, for example, a silicon substrate, or a silicon substrate with an epitaxial layer, etc. The material of the isolation layer 102 includes, but is not limited to, silicon oxide, and the material of the sacrificial layer 103 includes, but is not limited to, silicon nitride. In the subsequent step of removing the sacrificial layer 103, the etching rate of the sacrificial layer 103 needs to be greater than the etching rate of the isolation layer 102. The semiconductor layer 101 has a first region and a second region, wherein the first region and the second region of the semiconductor layer 101 can be adjacent or separated. In some specific embodiments, the first region of the semiconductor layer 101 is a high-voltage device region HV, and the second region of the semiconductor layer 101 is a low-voltage device region, wherein the second region includes a first low-voltage device region LV and a second low-voltage device region LLV.

[0050] Furthermore, multiple through-holes 103a are formed in the sacrificial layer 103, such as Figure 1 As shown.

[0051] In this embodiment, for example, a dry etching process is used to form a plurality of vias 103a. The plurality of vias 103a correspond to the first region and the second region of the semiconductor layer 101, respectively, namely, the high voltage device region HV, the first low voltage device region LV and the second low voltage device region LLV.

[0052] Furthermore, a plurality of trenches 105 are formed extending from the surface of the isolation layer 102 into the semiconductor layer 101, such as... Figure 2 As shown.

[0053] In this step, for example, a dry etching process is used to etch the isolation layer 102 and the semiconductor layer 101 through multiple vias 103a in the sacrificial layer 103 to form multiple trenches 105. In this embodiment, the sacrificial layer 103 with multiple vias 103a serves as a hard mask for etching the isolation layer 102 and the semiconductor layer 101.

[0054] Furthermore, each trench is filled with an insulating layer 104, such as Figure 3 As shown.

[0055] In this step, for example, an insulating layer 104 is deposited on the surface of the sacrificial layer 103 using CVD and / or PVD processes. This insulating layer 104 also fills multiple trenches 105 and multiple vias 103a. Then, for example, etching or chemical mechanical polishing (CMP) processes are used to remove the deposited insulating layer 104 on the surface of the sacrificial layer 103. In this embodiment, the material of the insulating layer 104 includes, but is not limited to, silicon oxide.

[0056] Furthermore, in the second region, the isolation layer 102 and the sacrificial layer 103 are removed to expose the surface of the semiconductor layer 101, such as... Figure 4As shown, the remaining isolation layer 102 in the first region serves as the first gate dielectric layer 102a (planar gate dielectric layer), and the remaining insulating layer 104 inside the trench 105 in the first region serves as a trench isolation structure.

[0057] Furthermore, in the second region, at least a portion of the insulation layer 104 inside the trench 105 is removed to expose at least a portion of the sidewalls of the trench 105, such as... Figure 4 As shown. In some specific embodiments, the insulating layer 104 at the bottom of the trench 105 in the second region is retained.

[0058] In some other embodiments, the insulating layer 104 within the trench 105 in the second region may be completely removed as needed.

[0059] Furthermore, a wet etching process is used to remove the sacrificial layer located in the first region to expose the first gate dielectric layer 102a, such as... Figure 5 As shown.

[0060] In this step, the etchant used in the wet etching process includes phosphoric acid. In the second region, because the surface of the semiconductor layer 101 and the sidewalls of the trench 105 are exposed, they come into direct contact with the phosphoric acid, causing defects 10a, 10b, and 10c to appear in the semiconductor layer 101. This results in uneven and irregular morphology of the semiconductor layer 101, especially the contour of the trench 105. Figure 6 As shown.

[0061] Furthermore, a protective layer 106 is formed in the second region of the semiconductor layer 101, such as... Figure 7 As shown.

[0062] In this step, for example, a protective layer 106 is formed by a thermal oxidation process, and the exposed portions of the surface of the semiconductor layer 101 in the second region and the inner surface of the trench 105 in the previous step are covered by the protective layer 106.

[0063] Furthermore, the semiconductor layer 101 is doped to form multiple doped regions 110, 120, 130, and 140, such as... Figure 8 As shown.

[0064] In this step, the first gate dielectric layer 102a and the protective layer 106 can reduce the damage to the semiconductor layer 101 caused by the high-energy injection of doped impurities.

[0065] Furthermore, in the second region, the protective layer 106 and the remaining insulating layer 104 are removed, re-exposing the inner surface of the trench 105, as shown below. Figure 9As shown. In the aforementioned wet etching step to remove the sacrificial layer 103, damage has already been caused to the surface of the semiconductor layer 101 in the second region and the interior of the trench 105. At this point, the sidewalls of the trench 105 are not smooth, with a slope at defect 10b and a step at defect 10c. Therefore, during the subsequent formation of the trench gate dielectric layer, the consistency of the trench gate dielectric layer is poor due to the presence of defects 10b and 10c. Furthermore, since the trench gate dielectric layer in this embodiment corresponds to a low-voltage device and is very thin, the poor surface smoothness of the inner surface of the trench 105 has a greater impact on the very thin trench gate dielectric layer.

[0066] Therefore, this disclosure provides a second embodiment, which, compared to the first embodiment described above, can protect the semiconductor layer from damage by the etchant during the wet etching step of removing the sacrificial layer.

[0067] Figures 10 to 14 The present disclosure provides cross-sectional schematic diagrams of some stages of a method for manufacturing a semiconductor device according to a second embodiment.

[0068] In the formation of such Figure 4 Following the semiconductor structure shown, a protective layer 106 is formed, such as... Figure 10 As shown.

[0069] In this step, for example, the semiconductor layer 101 in the second region is oxidized by a thermal oxidation process to form a protective layer 106, wherein the thermal oxidation process is performed in a furnace tube (FUR). Thermal oxidation processes generally include dry oxidation, vapor oxidation, and wet oxidation. In this disclosure, to ensure the film quality of the protective layer 106, it is preferable to use a combination of dry and wet oxidation to form the protective layer 106. Alternating dry and wet oxidation can also be used to form the protective layer 106. The advantage of forming the protective layer 106 using a dry or wet oxidation process is that the oxidation selectivity of the semiconductor layer 101 (silicon substrate) relative to the silicon nitride sacrificial layer 103 is higher; that is, the oxidation rate of the sacrificial layer 103 is lower than the oxidation rate of the semiconductor layer 101. Furthermore, forming the protective layer 106 using a dry or wet oxidation process allows for a very thin protective layer 106, resulting in minimal impact on the sidewall profile of the trench 105 in the second region of the semiconductor layer 101 after the subsequent removal of the protective layer 106. Of course, the embodiments disclosed herein are not limited to this, and the protective layer 106 can also be formed by other processes as needed, such as deposition processes, etc.

[0070] Further, the sacrificial layer 103 located in the first region is wet-etched to expose the first gate dielectric layer 102a, as shown below. Figure 11 As shown.

[0071] In this step, the etchant used in the wet etching process includes, but is not limited to, phosphoric acid. In this embodiment, the protective layer 106 can protect the second region of the semiconductor layer 101 from damage during the wet etching process, thereby improving the problem of morphological changes in the semiconductor layer 101 during the wet etching process to remove the sacrificial layer 103.

[0072] Furthermore, the semiconductor layer 101 is doped to form multiple doped regions 110, 120, 130, and 140, such as... Figure 11 As shown.

[0073] In this step, the first gate dielectric layer 102a and the protective layer 106 serve as a protective structure to reduce the damage to the semiconductor layer 101 caused by the high-energy injection of doped impurities. In this embodiment, doped regions 110 and 120 serve as high-voltage well regions located in the high-voltage device region HV, and are separated by a trench isolation structure; doped region 130 serves as a first low-voltage well region located in the first low-voltage device region LV; and doped region 140 serves as a second low-voltage well region located in the second low-voltage device region LLV. Of course, the number, junction depth, and doping type of doped regions can be set as needed, as well as the source / drain regions of the CMOS device can be formed in each well region. The doping steps of this embodiment are not limited to these. The focus described here is that the protective layer 106 can protect the semiconductor layer 101 in the doping step. For the high-voltage device region HV, the first low-voltage device region LV, and the second low-voltage device region LLV, whether each doped region is formed simultaneously, or the formation order of each doped region in the entire manufacturing process, can be set as needed.

[0074] Furthermore, in the second region, the protective layer 106 and the remaining insulating layer 104 are removed, re-exposing the inner surface of the trench 105, as shown below. Figure 12 As shown.

[0075] Furthermore, in the second region, a second gate dielectric layer 150, 160 is formed on the inner surface of the covering trench 105, as shown below. Figure 13 As shown.

[0076] In this embodiment, the thickness of the second gate dielectric layer 150 located in the first low-voltage device region LV is greater than the thickness of the second gate dielectric layer 160 located in the second low-voltage device region LLV.

[0077] Further, first gate conductors (planar gate conductors) 171 and 172 are formed on the first gate dielectric layer 102a, and second gate conductors (trench gate conductors) 173 and 174 are formed in the trenches of the first low-voltage device region LV and the second low-voltage device region LLV, respectively. Figure 14 As shown.

[0078] This disclosure also includes a method for forming a 3D memory device or a CMOS device, which can form a corresponding 3D memory device or CMOS device based on a semiconductor device obtained according to the semiconductor device manufacturing method described above. Furthermore, the thicknesses of the first gate dielectric layer 110a and the second gate dielectric layers 150 and 160 can be determined according to the characteristics of the 3D memory device or CMOS device to be formed, so as to meet the operating voltage requirements of different 3D memory devices or CMOS devices.

[0079] According to the semiconductor device manufacturing method provided in the embodiments of this disclosure, before removing the sacrificial layer in the first region, a protective layer is first formed on the exposed semiconductor layer in the second region, and then a wet etching process is performed to remove the sacrificial layer. The protective layer protects the semiconductor layer from damage, thereby improving the problem of morphological changes in the semiconductor layer during the wet etching process to remove the sacrificial layer.

[0080] Furthermore, since the semiconductor layer in the second region needs to be doped after the sacrificial layer removal step, even though the incident energy of the dopant impurities is high in this step, the protective layer can still be doped, thereby reducing the risk of damage to the semiconductor layer during the doping step.

[0081] This manufacturing method preserves the insulating layer at the bottom of the trench in the second region, which also protects the semiconductor layer during wet etching and doping steps.

[0082] Furthermore, in the second region, since the retained insulation layer already covers the bottom of the trench (or the deepest part of the trench), the protective layer only needs to be formed on the shallower part of the trench sidewalls, thus reducing the difficulty of making the protective layer.

[0083] This manufacturing method uses a thermal oxidation process to form a protective layer. The high temperature results in a high-quality protective layer, which can more effectively prevent the etchant from entering the semiconductor layer during the wet etching step.

[0084] Furthermore, since the protective layer formed by the thermal oxidation process is very thin, the morphology of the semiconductor layer surface and the inner surface of the trench will hardly change due to the protective layer. Therefore, after the protective layer is removed, the inner surface of the trench is still relatively flat, which is more conducive to forming a gate dielectric layer with better consistency on the inner surface of the trench.

[0085] Furthermore, in dry oxidation and / or wet oxidation processes, the sacrificial layer of silicon nitride material has a relatively high oxidation selectivity compared to the semiconductor layer of silicon material. Therefore, after a protective layer is formed on the surface of the semiconductor layer, the sacrificial layer is hardly affected, and in subsequent wet etching steps, the sacrificial layer is easily removed relative to the protective layer.

[0086] Therefore, the method for manufacturing semiconductor devices according to embodiments of this disclosure improves product yield and reliability.

[0087] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, it should be understood that various technical means can be used to form layers and regions of the desired shape. Furthermore, methods not entirely identical to those described above can be designed to form the same structure. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be advantageously combined.

[0088] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A method for manufacturing a semiconductor device, comprising: A stacked structure is formed on a first region of the semiconductor layer, including a first gate dielectric layer and a sacrificial layer; Trenches and insulating layers located in the trenches are formed in a first region and a second region of the semiconductor layer, wherein the first region and the second region are connected or separated. A sidewall is formed in the second region that exposes at least a portion of the trench; A protective layer is formed on the exposed sidewalls of the trench; as well as Wet etching is performed on the sacrificial layer located in the first region. The semiconductor layer is made of silicon. In the step of forming the protective layer, the semiconductor layer is oxidized by a thermal oxidation process to form the protective layer. In the step of forming the protective layer, the oxidation rate of the sacrificial layer is less than the oxidation rate of the semiconductor layer, so that the protective layer protects the sidewalls of the trench during the wet etching process.

2. The manufacturing method according to claim 1, wherein, The first region is the high-voltage device region, and the second region is the low-voltage device region.

3. The manufacturing method according to claim 1 further includes doping the semiconductor layer through the trench in the second region to form a doped region. in, During the doping process, the protective layer protects the sidewalls of the trench.

4. The manufacturing method according to claim 3, wherein, In the second region, the protective layer is also formed on the surface of the semiconductor layer. During the wet etching and doping processes, the protective layer also protects the surface of the semiconductor layer.

5. The manufacturing method according to claim 1, wherein, The steps for forming the trench include: An isolation layer is formed on the first and second regions of the semiconductor layer; A sacrificial layer with multiple through holes is formed on the surface of the isolation layer; and The isolation layer and the semiconductor layer are etched through multiple vias of the sacrificial layer to form the trenches in the first region and the second region, respectively.

6. The manufacturing method according to claim 5, wherein, The step of forming the stacked structure includes removing the isolation layer and the sacrificial layer on the second region, and retaining the isolation layer on the first region as the first gate dielectric layer.

7. The manufacturing method according to claim 6, wherein, In the first region, the insulating layer acts as a trench isolation layer that penetrates the first gate dielectric layer.

8. The manufacturing method according to claim 1, wherein, The step of forming sidewalls that expose at least a portion of the trench includes: in the second region, removing at least a portion of the insulating layer in the trench to expose the sidewalls, wherein the insulating layer at the bottom of the trench in the second region is retained. The retained insulating layer is connected to the protective layer located on the sidewall of the trench.

9. The manufacturing method according to claim 8, further comprising: In the second region, the protective layer and the insulating layer at the bottom of the trench are removed to re-expose the trench; as well as In the second region, a second gate dielectric layer is formed on the inner surface covering the trench.

10. The manufacturing method according to claim 9, further comprising: A first gate conductor is formed on the surface of the first gate dielectric layer, and a second gate conductor is formed inside the trench in the second region.

11. The manufacturing method according to any one of claims 1-10, wherein, The thermal oxidation process includes dry oxidation and / or wet oxidation processes, and the material of the sacrificial layer includes silicon nitride.

12. The manufacturing method according to any one of claims 1-10, wherein, The wet etching agent includes phosphoric acid.

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