Semiconductor package and method of manufacturing a semiconductor package

Abstract

Embodiments of the present invention provide a semiconductor package including a packaged semiconductor device and a redistribution structure. The packaged semiconductor device includes a semiconductor device encapsulated by an encapsulation material. The redistribution structure overlies the packaged semiconductor device and includes a plurality of vias and a redistribution line. The plurality of vias are located on different layers of the redistribution structure and are connected to each other by a plurality of conductive lines, wherein an angle between two adjacent ones of the plurality of conductive lines as viewed from a top view is greater than zero. The redistribution line is disposed under the plurality of conductive lines and connects a corresponding one of the plurality of vias and is electrically connected to the semiconductor device through the plurality of vias.

Description

Technical Field

[0001] This invention relates to a semiconductor packaging and a method for manufacturing a semiconductor package. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers on a semiconductor substrate, and then using photolithography to pattern these material layers to form circuit components and elements. Many integrated circuits are typically fabricated on a single semiconductor wafer. Wafer dies can be processed and packaged at the wafer level, and various technologies have been developed for wafer-level packaging. Summary of the Invention

[0003] This invention provides a semiconductor package comprising an encapsulated semiconductor device and a redistribution structure. The encapsulated semiconductor device comprises a semiconductor device encapsulated by an encapsulating material. The redistribution structure covers the encapsulated semiconductor device and includes a plurality of vias and redistribution lines. The plurality of vias are located on different layers of the redistribution structure and are interconnected by a plurality of conductive lines, wherein, from a top view, the angle between any two adjacent conductive lines is greater than zero. The redistribution lines are disposed below the plurality of conductive lines and connect to a corresponding via, and are electrically connected to the semiconductor device through the plurality of vias.

[0004] This invention provides a semiconductor package comprising a semiconductor device and a redistribution structure. The redistribution structure covers the semiconductor device and includes a plurality of vias and redistribution lines. The vias are located on different layers of the redistribution structure and are interconnected by a plurality of conductive lines. The redistribution lines are disposed beneath the plurality of conductive lines and connect to a corresponding via among the plurality of vias, wherein the horizontal distance between one of the plurality of vias connected to the semiconductor device and the nearest edge of the semiconductor device is shorter than the horizontal distance between another of the plurality of vias connecting the redistribution lines and the nearest edge of the semiconductor device.

[0005] This invention provides a method for manufacturing a semiconductor package comprising the following steps: Forming a redistribution structure, wherein the redistribution structure includes a plurality of vias interconnected by a plurality of conductive lines and redistribution lines connected to a semiconductor device through the plurality of vias, and, in a top view, the angle between any two adjacent conductive lines is greater than zero; bonding a semiconductor device to a first side of the redistribution structure; providing an encapsulating material over the redistribution structure to encapsulate the semiconductor device; and bonding a substrate to a second side of the redistribution structure opposite to the first side. Attached Figure Description

[0006] The following detailed description, taken in conjunction with the accompanying drawings, will best convey the various aspects of this disclosure. It should be noted that, in accordance with industry standard practice, the features are not drawn to scale. In fact, the dimensions of the features may be arbitrarily increased or decreased for clarity of explanation.

[0007] Figure 1 A schematic cross-sectional view of a semiconductor package according to some embodiments of the present disclosure is shown.

[0008] Figure 2 A partially enlarged view of a semiconductor package according to some embodiments of the present disclosure is shown.

[0009] Figure 3 A perspective view of a portion of a semiconductor package according to some embodiments of the present disclosure is shown.

[0010] Figure 4 Show Figure 3 A top view of a portion of the semiconductor package shown.

[0011] Figure 5 Show Figure 4 The image shows a top view of a portion of a semiconductor package after thermal expansion.

[0012] Figure 6 A perspective view of a portion of a semiconductor package according to some embodiments of the present disclosure is shown.

[0013] Figure 7 Show Figure 6 A top view of a portion of the semiconductor package shown.

[0014] Figure 8 Show Figure 7 The image shows a top view of a portion of a semiconductor package after thermal expansion.

[0015] Figures 9 to 19 A cross-sectional view is shown of an intermediate stage in the manufacture of a semiconductor package according to some embodiments of the present disclosure.

[0016] Figures 20 to 24 A cross-sectional view is shown of an intermediate stage in the manufacture of a semiconductor package according to some embodiments of the present disclosure.

[0017] Explanation of icon numbers

[0018] 100, 100a: Semiconductor packaging;

[0019] 101, 103: Carrier;

[0020] 102, 104: Adhesive layer;

[0021] 105: Encapsulated semiconductor devices;

[0022] 106: Cutting strip;

[0023] 110, 110a, 110b: Semiconductor devices;

[0024] 112, 140: Substrate;

[0025] 113: Padding;

[0026] 114: Through hole;

[0027] 116a, 1221, 1241, 1261: Dielectric layers;

[0028] 120: Rewiring structure;

[0029] 122, 124, 126: Through holes;

[0030] 123, 127: Conductive wires;

[0031] 125, 128, 1222: Rewiring;

[0032] 130: Packaging materials;

[0033] 150: Conductive bump;

[0034] 152: Copper seed layer;

[0035] 154: Nickel layer;

[0036] 156: Solder layer;

[0037] 160: Connector;

[0038] 162: Integrated passive components;

[0039] 170, 180: Bottom filling material;

[0040] A1, A2, A3: Length direction;

[0041] D1, D2, D3: Diameter;

[0042] DL: Cutting line;

[0043] E1: Edge;

[0044] F: Tension;

[0045] L1: Length;

[0046] PK: Packaging structure;

[0047] PK1: Packaging;

[0048] S1: First side;

[0049] S2: Second side;

[0050] W1: Width;

[0051] θ, θ1, θ1': angle, included angle. Detailed Implementation

[0052] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these components and arrangements are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature over or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature may be formed between the first and second features so that the first and second features are not in direct contact. Additionally, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0053] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” and similar spatial relative terms are used herein to describe the relationship between one element or feature and another element(s) shown in the diagrams. In addition to the orientations depicted in the diagrams, the spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein shall be interpreted accordingly.

[0054] A semiconductor package and a method of manufacturing a semiconductor package are provided according to various exemplary embodiments. Before specifically presenting the illustrated embodiments, certain advantageous features and aspects of embodiments of the present disclosure will be generally described. The following describes a semiconductor package comprising at least one semiconductor device, which is bonded to a redistribution structure to form a package structure, and the package structure is then bonded to a substrate. In some embodiments, a coefficient of thermal expansion (CTE) mismatch may exist between a material typically used for the semiconductor device (e.g., silicon) and a material used for the substrate (e.g., Ajinomoto build-up film (ABF), glass fiber). This CTE mismatch between materials can cause thermal stress in the redistribution structure, particularly during thermal cycling. For example, during temperature changes, the different rates of expansion and contraction caused by the CTE mismatch between the semiconductor device and the substrate generate stress on the redistribution within the redistribution structure. Stress is particularly problematic for redistribution extending above the die edge (viewed from top view). In some embodiments, a plurality of vias are respectively disposed on different layers of the redistribution structure and connected to each other by a plurality of conductive lines, wherein, viewed from a top view, the angle between any two adjacent conductive lines is greater than zero. Therefore, the redistribution is connected to the bottommost via. Thus, during thermal cycling, some thermal stress between the redistribution and the semiconductor device can be relieved by changing the angle between the conductive lines, and the additional dielectric layer (added to form at least one via) also provides greater flexibility to the redistribution structure. Intermediate stages of forming a semiconductor package are shown according to some embodiments. Some variations of some embodiments are discussed. Similar reference numerals are used to denote similar elements throughout the views and illustrative embodiments.

[0055] Figure 1 A schematic cross-sectional view of a semiconductor package according to some embodiments of the present disclosure is shown. Reference Figure 1In some embodiments, semiconductor package 100 may include encapsulated semiconductor device 105 and redistribution structure 120. Encapsulated semiconductor device 105 includes at least one semiconductor device 110 encapsulated by encapsulation material 130. In this embodiment, two semiconductor devices 110 are shown herein, but more or fewer semiconductor devices 110 may be used in semiconductor package 100. This disclosure is not limited thereto. In some embodiments, the semiconductor device 110 may include logic dies (e.g., central processing units, microcontrollers, etc.), memory dies (e.g., dynamic random access memory (DRAM) dies, static random access memory (SRAM) dies, etc.), power management dies (e.g., power management integrated circuit (PMIC) dies), radio frequency (RF) dies, sensor dies, micro-electro-mechanical system (MEMS) dies, signal processing dies (e.g., digital signal processing (DSP) dies), front-end dies (e.g., analog front-end (AFE) dies), transceiver (TRX) dies, the like, or combinations thereof. Additionally, in some embodiments, the semiconductor device 110 may have different dimensions (e.g., different heights and / or surface areas), and in other embodiments, the semiconductor device 110 may have the same dimensions (e.g., the same height and / or surface area). In some embodiments, one of the semiconductor devices 110 may be a logic die, such as a system-on-chip (SOC), a system-on-integrated chip (SoIC), an application-specific integrated circuit (ASIC), or the like. One of the semiconductor devices 110 may be a memory die, such as a DRAM die, an SRAM die, or the like.

[0056] In some embodiments, the semiconductor device 110 may be encapsulated by an encapsulating material 130. In some embodiments, the encapsulating material 130 encapsulates the semiconductor device 110 at least laterally. The encapsulating material 130 may comprise molding compounds, epoxy resins, or resins, etc. In some embodiments, the top surface of the encapsulating material 130 may be coplanar with the back surface of the semiconductor device 110. That is, the encapsulating material 130 may expose the back surface of the semiconductor device 110, which can be achieved, for example, by a polishing process. In an alternative embodiment, the top surface of the encapsulating material 130 may be higher than the back surface of the semiconductor device 110. That is, the encapsulating material 130 covers the back surface of the semiconductor device 110.

[0057] Figure 2 A partially enlarged view of a semiconductor package according to some embodiments of the present disclosure is shown. Figure 3 A perspective view of a portion of a semiconductor package according to some embodiments of the present disclosure is shown. References Figures 1 to 3 In some embodiments, the redistribution structure 120 covers the encapsulated semiconductor device 105 for electrical connection to the semiconductor device 110. In some embodiments, the semiconductor device 105 can be bonded to the redistribution structure 120 via a plurality of conductive bumps 150 using flip-chip bonding technology. In some embodiments, the conductive bumps 150 may be solder balls, metal pillars, controlled collapse chip connection (C4) bumps, microbumps, bumps formed by electroless nickel-electroless palladium-immersion gold technique (ENEPIG), combinations thereof (e.g., metal pillars with solder balls attached), or the like. In this embodiment, the conductive bumps 150 may be microbumps, but this disclosure is not limited thereto. In other embodiments, the redistribution structure 120 may be formed over the encapsulated semiconductor device 105 without bonding the conductive bumps 150.

[0058] The redistribution structure 120 can be formed, for example, by depositing a conductive layer or patterning the conductive layer to form a plurality of redistributions (e.g., redistribution 125) and at least one conductive line (e.g., conductive line 123, conductive line 127). The redistributions and conductive lines are at least partially formed by a dielectric layer (e.g., Figure 2The dielectric layers 1221, 1241, and 1261 shown in the diagram cover and fill the gaps between the redistribution lines and the conductive lines. Vias (e.g., vias 122, 124, and 126) are located on the layers of the redistribution structure 120 and extend through the corresponding dielectric layers to interconnect the redistribution lines and conductive lines at different layers. The materials of the redistribution lines and conductive lines may include metals or metal alloys containing aluminum, copper, tungsten, and / or alloys thereof. "Dielectric" refers to a material with conductivity lower than that of a metallic conductor such as silver, and may refer to transparent semiconductor materials and insulators (including polymers). The dielectric layer may be formed of a dielectric material with conductivity lower than that of a metallic conductor such as silver, and may refer to (transparent) semiconductor materials and insulators (including polymers). For example, the dielectric material may include polymers, oxides, nitrides, carbides, carbonitrides, combinations thereof, and / or multiple layers thereof. The redistribution lines and conductive lines are formed in the dielectric layer and electrically connected to the semiconductor device 110.

[0059] Throughout the description, such as Figure 1 The combined structure shown, including semiconductor device 110, redistribution structure 120, and encapsulation material 130, is called package structure PK. Package structure PK can be in wafer form during manufacturing. Therefore, in package structure PK, semiconductor device 110 is encapsulated by encapsulation material 130, and redistribution structure 120 is disposed on the first side (upper side) of encapsulation material 130.

[0060] In some embodiments, the package structure PK can be bonded to the substrate 140 via a plurality of connectors 160. In some embodiments, the connectors 160 may be solder balls, metal pillars, controlled collapse chip connection (C4) bumps, microbumps, bumps formed by electroless nickel-palladium immersion gold (ENEPIG) technology, combinations thereof (e.g., metal pillars with solder balls attached), or the like. Connectors 160 may contain conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or combinations thereof. In some embodiments, as an example, connectors 160 contain a eutectic material and may include solder bumps or solder balls. In some embodiments, a reflow process may be performed, thereby forming a partially spherical shape for the connectors 160 in some embodiments. Alternatively, connectors 160 may include other shapes. For example, connectors 160 may also include non-spherical conductive connectors. In some embodiments, connectors 160 include metal pillars (e.g., copper pillars) formed by sputtering, printing, electroplating, electroless plating, CVD, or similar operations, with or without solder material on the metal pillars. The metal pillar can be solderless and has generally vertical or tapered sidewalls. In this embodiment, the connector is a C4 protrusion, but this disclosure is not limited thereto.

[0061] In some embodiments, an underfill material 180 may be injected or otherwise formed in the space between the connector 160 and the redistribution structure 120. The underfill material 180 may include, for example, liquid epoxy resin, non-conductive paste (NCP), non-conductive film (NCF), deformable gel, silicone rubber, or the like, and is dispensed between the connector 160 and the redistribution structure 120 and / or pre-laminated on the surface of the substrate 140, and then cured to harden. This underfill material 180 is particularly useful for reducing cracking and protecting the connector 160.

[0062] Generally, a mismatch in coefficient of thermal expansion (CTE) may exist between different materials in semiconductor package 100. This CTE mismatch can cause thermal stress in the rewiring structure 120. For example, during temperature changes, the different rates of expansion and contraction caused by the CTE mismatch between materials typically used in semiconductor device 110 (e.g., silicon) and materials typically used in the substrate (e.g., Ajinomoto film (ABF), glass fiber) generate stress on the rewiring (e.g., rewiring 125) within the rewiring structure 120. This stress can cause cracking of the rewiring (e.g., rewiring 125), particularly around the die edge E1 (e.g., the corner and / or side of semiconductor device 110).

[0063] Therefore, the redistribution structure 120 may include at least one conductive line (e.g., conductive line 123, conductive line 127), a plurality of vias (e.g., vias 122, vias 124, vias 126), and at least one redistribution line (e.g., redistribution line 125) disposed beneath the conductive lines 123 and 127. In some embodiments, the (first) via 122 is the uppermost via connecting the semiconductor device 110 or a conductive bump 150 on the semiconductor device 110. In some embodiments, the conductive bumps 150 are bonded between the semiconductor device 110 and the redistribution structure 120, and each of the conductive bumps 150 may include a solder layer 156 formed over a copper seed layer 152. An optional nickel layer 154 may be present between the solder bumps 156 and the copper seed layer 152, but this disclosure is not limited thereto. The conductive bumps 150 may contain more or fewer layers. The copper seed layer 152 and the nickel layer 154 can serve as the UBM layer and barrier layer for forming the solder layer 156. The solder layer 156 may contain a conductive solder material, such as Sn, Ni, Au, Ag, Cu, Bi, W, Fe, ferrite, alloy, or a combination thereof, or any other suitable material. One of the conductive bumps 150 is bonded to the uppermost via (e.g., via 122) in the via. Therefore, via 122 connects the conductive bump 150 and extends through the (uppermost) dielectric layer (e.g., ...). Figure 2 The dielectric layer 1221 shown is used to connect the conductive bumps 150 on the semiconductor device 110 to the (first) conductive line 123.

[0064] According to some embodiments of this disclosure, the metallization pattern within the redistribution structure 120 may include redistribution 125 (i.e., signal lines) (e.g., providing power, ground, and / or electrical wiring to the semiconductor device 110) and conductive lines between and within the redistribution. In some embodiments, the term "conductive line" herein refers to a conductive feature included for reasons other than electrical wiring. For example, in embodiments, conductive lines 123 and 127 may be electrically insulated from other conductive features (lines) in the package. In other embodiments, conductive line 123 may be electrically connected to the redistribution 125 in other layers. However, in such embodiments, conductive lines 123 and 127 may not provide any electrical wiring to the redistribution 125 within the layer where conductive lines 123 and 127 are disposed.

[0065] In some embodiments, vias 122, 124, and 126 are located on different layers of the redistribution structure 120 and are connected to each other via conductive lines 123 and 127. For example, the (first) via 122 extends through the (uppermost) dielectric layer 1221 closest to the semiconductor device 110, and the (second) via 124 extends through the (lower) dielectric layer 1241 furthest from the semiconductor device 110 and connects to the redistribution line 125. Additionally, the (third) via 126 extends through the intermediate dielectric layer 1261 and is disposed between vias 122 and 124. The redistribution line 125 is disposed below the (first) conductive line 123 and the (second) conductive line 127 and connected to one of the corresponding vias 124. In one embodiment, the conductive line 127 is disposed between the conductive line 123 and the redistribution line 125. Therefore, through-hole 124 connects between conductive line 123 and redundancy line 125, while through-hole 126 connects between conductive line 123 and conductive line 127. In some embodiments, conductive line 123 is configured to extend along its length direction (e.g., Figure 4The length direction A1 shown connects through-holes 122 and 126. In some embodiments, through-holes 122 and 126 are connected to two opposite ends of conductive line 123 along the length direction of conductive line 123, and through-holes 122 and 126 are respectively connected to two opposite surfaces (upper and lower surfaces) of conductive line 123. Similarly, through-holes 126 and 124 are connected to two opposite ends of conductive line 127 along the length direction of conductive line 127, and through-holes 126 and 1264 are respectively connected to two opposite surfaces (upper and lower surfaces) of conductive line 127. Therefore, the redistribution line 125 is electrically connected to the semiconductor device 110 through through-holes 122, 124, 126, and conductive lines 123 and 127. It should be noted that other rewiring (e.g., rewiring 1222) configured to provide power, ground and / or electrical wiring to semiconductor device 110 may also be disposed at the same level (e.g., in the same dielectric layer 1221) as conductive lines 123 and 127.

[0066] According to some embodiments of this disclosure, reference is made to Figure 4 and Figure 5 From a top view, the angle θ1 between any two adjacent conductive lines 123 and 127 is generally greater than zero. For example, measured from a top view, the angle θ1 between the length direction A1 of conductive line 123 and the length direction A3 of conductive line 127 is generally greater than zero. That is, any two adjacent conductive lines 123 and 127 are not parallel or collinear. In one embodiment, the angle θ1 is in the range of approximately 20 degrees to approximately 90 degrees. More precisely, the angle θ1 is greater than or generally equal to 20 degrees and less than or generally equal to 90 degrees. In this embodiment, the rediform line 125 may also include an angle θ2 between it and one of the conductive lines 123 and 127, and the angle θ2 is greater than zero. That is, the rediform line 125 is not parallel or collinear with one of the conductive lines 123 and 127. In some embodiments, the angle θ1 may be approximately 45 degrees. In some embodiments, the angle θ1 may be less than approximately 90 degrees. In some embodiments, viewed from a top view, conductive lines 123 and 127 are routed in a manner not perpendicular to the edge E1 of the semiconductor device 110. This arrangement, compared to conductive lines 123 and 127 that are parallel or collinear with each other, allows for an angle θ1 that helps reduce stress on the rewiring 125 during thermal cycling (heating process). Therefore, this arrangement can help improve the reliability of the rewiring 125.

[0067] According to some embodiments of this disclosure, conductive wire 123 is configured to horizontally connect through-hole 122 and through-hole 126, and conductive wire 127 is configured to horizontally connect through-hole 126 and through-hole 124. Therefore, the widths of conductive wires 123 and 127 are approximately larger than the diameters of through-holes 122, 124, and 126. For example, the ratio of the diameter D1 of through-hole 122 / 124 / 126 to the width W1 of conductive wire 123 / 127 is approximately 0.5 to 0.9 (i.e., 0.5 ≤ D1 / W1 ≤ 0.9). The ratio of the diameter D1 of through-hole 122 / 124 / 126 to the length L1 of conductive wire 123 / 127 is approximately 0.3 to 0.9 (i.e., 0.3 ≤ D1 / L1 ≤ 0.9). Additionally, the size of the conductive bump 150 may be approximately larger than the diameters of through-holes 122, 124, and 126. For example, the ratio of the diameter D2 of the via 122 (which may be the same as the diameter D1) to the diameter D3 of the conductive bump 150 is approximately 0.5 to 0.7 (i.e., 0.5 ≤ D3 / D2 ≤ 0.7). Furthermore, the widths of the conductive lines 123 and 127 are greater than the width of the redistribution line 125, which is configured to provide power, ground, and / or electrical wiring to the semiconductor device 110.

[0068] According to some embodiments of this disclosure, during the heating process, the expansion rate of the material used for substrate 140 is generally greater than that of the material used for semiconductor device 110 (the substrate). Therefore, the redistribution line 125 closer to substrate 140 is subjected to a pulling force F relative to the via 124 of interconnecting semiconductor device 110 toward the edge E1 of semiconductor device 110. The angle θ1 between conductive lines 123 and 127 can be changed (e.g., reduced) during thermal expansion by the arrangement of these angles, which releases some of the stress concentrated on the redistribution line 125. For example, after thermal expansion caused by the heating process, the angle θ1 between conductive lines 123 and 127 can be adjusted from... Figure 4 The angle θ1 shown changes to Figure 5 The angle θ1' shown is generally smaller than angle θ1. Stress on the redistribution line 125 can be transmitted through and distributed above vias 124, 127, 126, 123, and 122 vias 124, 127, 126, 123, and 122. Therefore, this arrangement helps reduce stress on the redistribution line 125 during thermal cycling (heating process) and improves the reliability of the redistribution line 125.

[0069] In one embodiment, the conductive bump 150 that is engaged with the via 122 is the one closest to the edge E1 of the semiconductor device 110. That is, the arrangement of the angle θ1 between conductive lines 123 and 127 can be applied to the via 122 that is engaged with the conductive bump 150 closest to the edge E1, because the stress around the edge E1 is more severe. In another embodiment, the arrangement of the angle θ1 between adjacent conductive lines can be applied to each of the vias that are engaged with each of the conductive bumps 150.

[0070] With this arrangement, stress on the redistribution lines can be transferred and distributed above vias 122, 124, 126, and conductive lines 123 and 127 through and through vias 122, 124, 126, and conductive lines 123 and 127. In other words, during thermal cycling, some of the thermal stress between the redistribution lines and the semiconductor device can be released by changing the angle θ / θ1 between the conductive lines. Furthermore, the additional dielectric layer (added to form at least one via) provides greater flexibility to the redistribution structure. Therefore, this arrangement helps reduce stress on the redistribution lines during thermal cycling (heating process) and improves the reliability of redistribution in semiconductor packages.

[0071] According to some embodiments of this disclosure, refer to the reference. Figure 3 As previously discussed, stress is particularly problematic for redistribution 125 that extends (from a top view) above edge E1 or above the gap between two semiconductor devices 110. Therefore, in some embodiments, the (shortest) horizontal distance D1 between the (uppermost) via (e.g., via 122) connected to the semiconductor device 110 and the nearest edge E1 of the semiconductor device 110 is shorter than the (shortest) horizontal distance D2 between the (bottommost) via 124 connecting the redistribution and the nearest edge E1, where the nearest edge E1 is the edge of the semiconductor device 110 closest to via 122. In other words, via 124 connecting the redistribution 125 is positioned further away from edge E1 than via 122, thereby further reducing stress on the redistribution 125 and improving the reliability of the redistribution 125. In one embodiment, vias 122, 124, and 126 do not overlap each other from a top view.

[0072] Additionally, adding extra layers (e.g., including vias 126, conductive lines 127, and dielectric layer 1261) to the redistribution structure 120 provides another buffer layer because the material of the dielectric layer (e.g., a polymer) provides greater flexibility, thereby further reducing stress on the redistribution 125. Therefore, with the arrangement described above, the stress level on the redistribution 125 can be reduced by approximately 10% or more. That is, compared to a normalized stress level of 1 when there is no angle between the conductive lines and the redistribution (when angles θ and θ1 are 0 degrees), the normalized stress level can be reduced to approximately 0.9 or less when the angle between the conductive lines is between 20 and 90 degrees.

[0073] Figure 6 A perspective view of a portion of a semiconductor package according to some embodiments of the present disclosure is shown. Figure 7 Show Figure 6 A top view of a portion of the semiconductor package shown. Figure 8 Show Figure 7 The image shows a top view of a portion of a semiconductor package after thermal expansion. It should be noted that... Figures 6 to 8 The semiconductor package shown contains and Figures 1 to 5 Many features are identical or similar to those of previously disclosed semiconductor packages. For clarity and simplicity, detailed descriptions of identical or similar features may be omitted, and identical or similar reference numerals denote identical or similar components. The following description... Figures 6 to 8 The semiconductor package shown is Figures 1 to 5 Key differences between previously disclosed semiconductor packages.

[0074] In some embodiments, the redistribution structure 120 may include at least one conductive line (e.g., dashed line 123), a plurality of vias (e.g., via 122, via 124), and at least one redistribution (e.g., redistribution 125). In some embodiments, the (first) via 122 is the uppermost via connecting the semiconductor device 110 or the conductive bump 150 on the semiconductor device 110.

[0075] In some embodiments, the (second) via 124 is located below the (first) via 122 and connects between the conductive line 123 and the redistribution line 125. In other words, the via 122 and via 124 are located on different (dielectric) layers of the redistribution structure 120 and are connected to each other via the conductive line 123. According to some embodiments of this disclosure, the metallization pattern within the redistribution structure 120 may include the redistribution line 125 (i.e., signal line) (e.g., providing power, ground, and / or electrical wiring to the semiconductor device 110) and the conductive lines between and within the redistribution lines. In some embodiments, the conductive line 123 may be electrically insulated from other conductive features (circuit) in the package. In other embodiments, the conductive line 123 may be electrically connected to the redistribution line 125 in other layers. However, in such embodiments, the conductive line 123 may not provide any electrical wiring for the redistribution line 125 within the layer where the conductive line 123 is disposed. In some embodiments, the conductive line 123 is configured for use along its length direction (e.g., Figure 3 The vias 122 and 124 are connected along the length direction A1 shown. In other words, vias 122 and 124 are connected to the two opposite ends of the conductive line 123 along its length direction, and vias 122 and 124 are respectively connected to the two opposite surfaces (upper and lower surfaces) of the conductive line 123. It should be noted that other rewiring (e.g., rewiring 1222) configured to provide power, ground, and / or electrical wiring to the semiconductor device 110 may also be disposed at the same level as the conductive line 123 (e.g., in the same dielectric layer 1221). Reference Figures 6 to 8 In some embodiments, from a top view, the conductive line 123 and the redistribution line 125 contain an angle θ, and the angle θ is approximately greater than zero. For example, measured from a top view, the angle θ between the length direction A1 of the conductive line 123 and the length direction A2 of the redistribution line 125 is greater than zero. In other words, the conductive line 123 and the redistribution line 125 are not parallel or collinear with each other. In one embodiment, the conductive bump 150 that is engaged with the via 122 is the one closest to the edge E1 of the semiconductor device 110. That is, the arrangement of the angle θ between the conductive line 123 and the redistribution line 125 can be applied to the via 122 that is engaged with the conductive bump 150 closest to the edge E1 of the semiconductor device 110 because the stress around the edge E1 is more severe. In another embodiment, the arrangement of the angle θ between the conductive line and the redistribution line can be applied to each via connected to each conductive bump 150.

[0076] In some embodiments, the included angle θ is greater than about 15 degrees, and in some embodiments, the included angle θ may be about 45 degrees. In some embodiments, the included angle θ may be less than about 90 degrees. In some embodiments, viewed from a top view, the conductive line 123 is routed in a manner not perpendicular to the edge E1 of the semiconductor device 110. With this arrangement, the included angle θ can help reduce stress on the redistribution line 125 during thermal cycling (heating process) compared to the conductive lines 123 and redistribution line 125 that are parallel or collinear with each other. Therefore, this arrangement can help improve the reliability of the redistribution line 125.

[0077] According to some embodiments of this disclosure, during the heating process, the expansion rate of the material used for substrate 140 is generally greater than that of the material used for semiconductor device 110 (the substrate). Therefore, the redistribution line 125, which is closer to substrate 140, experiences a pulling force F relative to the via 124 of interconnecting semiconductor device 110 toward the edge E1 of semiconductor device 110. The angle θ between conductive line 123 and redistribution line 125 can be changed (e.g., increased) during thermal expansion by the arrangement of the angle θ between conductive line 123 and redistribution line 125, which releases some of the stress concentrated on redistribution line 125. For example, after thermal expansion caused by the heating process, the angle θ between conductive line 123 and redistribution line 125 can be adjusted from... Figure 7 The included angle θ shown changes to Figure 8 The included angle θ' shown is generally larger than the included angle θ. Stress on the redistribution line 125 can be transmitted through and distributed above the via 124, conductive line 123, and via 122. Therefore, this arrangement helps reduce stress on the redistribution line 125 during thermal cycling (heating process) and improves the reliability of the redistribution line 125.

[0078] According to some embodiments of this disclosure, refer to the reference. Figure 6 As previously discussed, stress is particularly problematic for redistribution 125 (viewed from top view) that extends above edge E1 or above the gap between two semiconductor devices 110. Therefore, in some embodiments, the shortest horizontal distance D1 between via 122 and the edge E1 of the semiconductor device 110 closest to via 122 is shorter than the shortest horizontal distance D2 between via 124 and edge E1. In other words, via 124 connecting redistribution 125 is positioned further away from edge E1 than via 122, thereby further reducing stress on redistribution 125 and improving the reliability of redistribution 125. In one embodiment, via 122 and via 124 do not overlap each other in top view.

[0079] Figures 9 to 19A cross-sectional view is shown illustrating an intermediate stage in the manufacture of a semiconductor package according to some embodiments of the present disclosure. One method (process) for manufacturing the semiconductor package described above is shown below. Reference Figure 9 In some embodiments, the redistribution structure 120 described above is formed on the carrier 101. In some embodiments, the carrier 101 comprises, for example, a silicon-based material (e.g., glass or silicon oxide) or other materials (e.g., aluminum oxide), combinations of these materials, or the like. The carrier 101 is planar to form the redistribution structure 120 thereon and to accommodate the attachment of the semiconductor device 110. Figure 9 Not shown in the text but relative to the following text Figure 11 (Shown and described). In some embodiments, adhesive layer 102 may be placed on carrier 101 to facilitate adhesion of overlay structures (e.g., redistribution structure 120). In embodiments, adhesive layer 102 may comprise a UV adhesive that loses its adhesive properties upon exposure to ultraviolet light. However, other types of adhesives may also be used, such as pressure-sensitive adhesives, radiation-curable adhesives, epoxy resins, Ajinomoto stacked film (ABF), combinations of these adhesives, or the like. Adhesive layer 102 may be placed on carrier 101 in a semi-liquid or gel form that is readily deformable under pressure.

[0080] For reference Figure 5 and Figure 9 A redistribution structure 120 is formed over a carrier 101 and an adhesive layer 102 (if present). In some embodiments, the redistribution structure 120 can be formed by depositing a conductive layer and patterning the conductive layer to form a plurality of redistributions (e.g., redistribution 125, redistribution 128, redistribution 1222) and at least one conductive line (e.g., conductive line 123, conductive line 127). The redistributions and conductive lines are at least partially formed by a dielectric layer (e.g., Figure 5 The dielectric layers 1221, 1241, and 1261 shown herein cover and fill the gaps between the redistribution lines and the conductive lines. Vias (e.g., vias 122, 124, and 126) are located on the layers of the redistribution structure 120 and extend through the corresponding dielectric layers to interconnect the redistribution lines and conductive lines at different layers. The materials of the redistribution lines and conductive lines may comprise metals or metal alloys containing aluminum, copper, tungsten, and / or alloys thereof.

[0081] Specifically, a seed layer, such as copper, titanium, or the like, may be deposited over the carrier 101, for example, by sputtering or another physical vapor deposition (PVD) process. Photoresist is deposited on the seed layer and patterned to expose portions of the seed layer by photolithography. Patterning is used for the metallization layer on the redistribution structure 120. Conductive materials for redistribution and conductive lines, such as copper, aluminum, the like, or combinations thereof, are deposited on the exposed seed layer, for example, by electroless plating, electroplating, or similar operations. The photoresist is removed by ashing and / or rinsing processes. The exposed seed layer is removed, for example, by wet or dry etching. The remaining conductive material forms the metallization layer of the redistribution structure 120 (e.g., Figure 5 The redistribution lines 125, 128, 1222, and conductive lines 123 and 127 are shown. A dielectric layer is deposited over the metallization layer (e.g., Figure 5 The dielectric layers 1221, 1241, and 1261 are shown in the diagram. The dielectric layers may be made of polymers such as polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), similar substances, or combinations thereof. The dielectric layers can be deposited using coating processes, stacking processes, similar processes, or combinations thereof. Acceptable photolithography techniques can be used to form vias through the dielectric layers to the metallization layers (e.g., ...). Figure 5 Through hole 122, through hole 124, through hole 126 shown in ).

[0082] The same or similar processes as described can be used to form subsequent metallization and dielectric layers. Conductive material deposited during the formation of subsequent metallization layers can be deposited in openings in previously formed dielectric layers to form vias for electrical connection to the respective metallization layers. After forming the topmost dielectric layer 1221, vias 122 are formed through the topmost dielectric layer 1221 for coupling connections between the redistribution structure 125 and another semiconductor device, package, die, and / or another substrate. It should be noted that any number of metallization and dielectric layers can be formed, and the redistribution structure 120 is shown as an example in this embodiment.

[0083] like Figure 3 and Figure 7As shown, in some embodiments, the redistribution structure 120 includes vias 122, 126, and 124 connected to each other via conductive lines 123 and 127. Additionally, from a top view, conductive lines 123 and redistribution lines 125 form an angle θ, which is greater than zero. In other words, conductive lines 123 and redistribution lines 125 are not parallel or collinear. In embodiments of the redistribution structure 120 having multiple conductive lines for connecting vias, from a top view, adjacent pairs of conductive lines 123 and 127 form an angle θ1, which is greater than zero. That is, adjacent pairs of conductive lines 123 and 127 are not parallel or collinear. In some embodiments, angle θ1 is generally between about 20 degrees and about 90 degrees.

[0084] For reference Figure 10 In some embodiments, conductive bumps 150 are provided above the redistribution structure 120 after the redistribution structure 120 is formed. In some embodiments, the connector 160 may be a solder ball, a metal pillar, a controlled collapse chip connection (C4) bump, a microbump, a bump formed by electroless nickel-palladium immersion gold (ENEPIG) technology, a combination thereof (e.g., a metal pillar with a solder ball attached), or the like. In this embodiment, the conductive bump is, for example, a microbump, and each of the conductive bumps 150 may include a solder layer formed over a copper seed layer. An optional nickel layer may be present between the solder layer and the copper seed layer. The copper seed layer and the nickel layer may serve as a UBM layer and a barrier layer for forming the solder layer. The solder layer may contain a conductive solder material, such as Sn, Ni, Au, Ag, Cu, Bi, W, Fe, ferrite, alloy, or a combination thereof, or any other suitable material. Those skilled in the art will recognize that many suitable arrangements of materials and layers exist for forming the conductive bumps 150. Any suitable material or material layer that can be used for the conductive bump 150 is fully intended to be included within the scope of the present embodiment. The conductive bump engages with the uppermost via (e.g., via 122) in the via. Thus, via 122 connects the conductive bump 150 and extends through the (uppermost) dielectric layer (e.g., Figure 5 The dielectric layer 1221 shown is used for connection between the conductive bump 150 and the conductive line 123.

[0085] For reference Figure 11In some embodiments, at least one semiconductor device 110 is bonded to a first side S1 of the redistribution structure 120 via conductive bumps 26, for example, using flip-chip bonding technology. In some embodiments, more than one semiconductor device 110 (e.g., two sets of semiconductor devices 110a, 110b) may be placed on the conductive bumps 26 using, for example, a pick-and-place tool. In this embodiment, two sets of semiconductor devices 110a, 110b are shown herein, but more or fewer semiconductor devices 110 may be used in the semiconductor package 100. This disclosure is not limited thereto. For example, in some embodiments, semiconductor device 110a may be a logic die, such as a system-on-a-chip (SOC), integrated system-on-a-chip (SoIC), application-specific integrated circuit (ASIC), or the like. Semiconductor device 110b may be a memory die, such as a DRAM die, SRAM die, or the like. Other types of dies may also be used, such as power management dies (e.g., power management integrated circuit (PMIC) dies), radio frequency (RF) dies, sensor dies, microelectromechanical systems (MEMS) dies, signal processing dies (e.g., digital signal processing (DSP) dies), front-end dies (e.g., analog front-end (AFE) dies), transceiver (TRX) dies, the like, or combinations thereof. Additionally, semiconductor devices 110a and 110b may have different dimensions (e.g., different heights and / or surface areas), and in other embodiments, semiconductor device 110 may have the same dimensions (e.g., the same height and / or surface area). In this embodiment, semiconductor device 110 is bonded to the first side S1 of redistribution structure 120 via a reflow process. During this reflow process, conductive bumps 150 contact the pads (UBM layer) of semiconductor device 110 and redistribution structure 120 to physically and electrically couple semiconductor device 110 to redistribution structure 120. Therefore, the rewiring 125 of the rewiring structure 120 is electrically connected to the semiconductor device 110 through vias 122, 124, and 126 and conductive bumps 150.

[0086] For reference Figure 12 Underfill material 170 is selectively distributed into the gap between semiconductor devices 110a and 110b, the redistribution structure 120, and surrounds the conductive bump 150. In some embodiments, underfill material 170 may extend upward along the sidewalls of semiconductor devices 110a and 110b. Underfill material 170 may be any acceptable material, such as polymers, epoxy resins, molded underfills, or the like. Underfill material 170 may be formed by a capillary flow process after semiconductor devices 110a and 110b are bonded, or may be formed by a suitable deposition method before semiconductor devices 110a and 110b are bonded.

[0087] refer to Figure 13 According to some embodiments, an encapsulating material 130 is provided over the redistribution structure 120 to encapsulate the semiconductor device 110. A thermal process is then performed to set the encapsulating material 130. If an underfill material 170 is applied, a thermal process is also immediately performed subsequently to shape the underfill material 170. The encapsulating material 130 may comprise molding compounds, epoxy resins, or resins, etc. In some embodiments, the top surface of the encapsulating material 130 may be higher than the back surface of the semiconductor device 110. That is, the encapsulating material 130 covers the back surface of the semiconductor device 110.

[0088] Next, a thinning process including polishing can be performed to thin the encapsulation material 130 (and underfill material 170) until the back surface of the semiconductor device 110 is exposed. The resulting structure is illustrated in... Figure 13 Due to the thinning process, the back surface of the semiconductor device 110 is substantially flush with the upper surface of the bottom filler material 170, and is similar to... Figure 13 The upper surface of the encapsulating material 130 shown is generally horizontal. Throughout the description, as... Figure 13 The structure shown, comprising semiconductor device 110 and encapsulation material 130, is referred to as encapsulated semiconductor device 105, which may be in wafer form during the manufacturing process. Therefore, as... Figure 13 The structure shown, which includes semiconductor device 110, encapsulation material 130 and redistribution structure 120, is called package structure PK. The package structure PK may also have a wafer form in the process.

[0089] For reference Figure 14 and Figure 15 The upper side of the encapsulation structure PK is temporarily attached to another carrier 103 via an adhesive layer 104 to support the encapsulation structure PK during subsequent processing. In some embodiments, the carrier 103 may be glass, ceramic, alumina, stainless steel, or another material that provides sufficient temporary support for the encapsulation structure PK during processing. A removal step is performed to remove the carrier 101 from the second side S2 of the redistribution structure 120. In some embodiments, the carrier 101 is separated from the second side S2 of the redistribution structure 120 by causing the adhesive layer 102 to lose or reduce its adhesive strength. The adhesive layer 102 is then removed together with the carrier 101. For example, the adhesive layer 102 may be exposed to UV light to cause the adhesive layer 102 to lose or reduce its adhesive strength, and thus the carrier 101 and the adhesive layer 102 can be removed from the second side S2 of the redistribution structure 120. It should be noted that the orientation in the diagram is shown for illustrative purposes only, and the process can be performed with a structure oriented in another direction.

[0090] exist Figure 16In the diagram, the orientation of the flip-package structure PK is reversed, and a connector 160 is provided above the second side S2 of the redistribution structure 120. Again, the orientation in the diagram is illustrated for illustrative purposes only, and the process can be performed by a structure oriented in another direction. In some embodiments, the connector 160 may be a solder ball, a metal pillar, a controlled collapse die connection (C4) bump, a microbump, a bump formed by electroless nickel-palladium immersion gold (ENEPIG) technology, a combination thereof (e.g., a metal pillar with a solder ball attached), or the like. The connector 160 may contain a conductive material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. In some embodiments, as an example, the connector 160 contains a eutectic material and may include solder bumps or solder balls. In some embodiments, a reflow process may be performed, thereby forming the connector 160 into a partially spherical shape in some embodiments. Alternatively, the connector 160 may include other shapes. For example, the connector 160 may also include a non-spherical conductive connector. In some embodiments, the connector 160 includes a metal pillar (e.g., a copper pillar) formed by sputtering, printing, electroplating, electroless plating, CVD, or similar operations, with or without solder material. The metal pillar may be solderless and have generally vertical or tapered sidewalls. In this embodiment, the connector is a C4 bump, but this disclosure is not limited thereto.

[0091] For reference Figure 17 The removal step is performed to remove the carrier 103 from the encapsulation structure PK. In some embodiments, the carrier 103 is separated from the encapsulation structure PK by causing the adhesive layer 104 to lose or reduce its adhesive strength. The adhesive layer 104 is then removed together with the carrier 103. For example, the adhesive layer 104 may be exposed to UV light to cause the adhesive layer 104 to lose or reduce its adhesive strength, and thus the carrier 103 and the adhesive layer 104 can be removed from the encapsulation structure PK.

[0092] See Figure 17 and Figure 18 The encapsulation structure PK can then be mounted (e.g., frame mounting) onto the dicing tape 106. It can then be monolithized or cut (e.g., along the dicing line DL). Figure 18 The package structure PK shown herein forms a plurality of packages PK1, each of which can be coupled with... Figure 19 The package PK1 shown is largely the same.

[0093] For reference Figure 19 The package PK1 is bonded to the substrate 140 via connector 160. In some embodiments, the substrate 140 is bonded to a second side S2 of the redistribution structure 120 of the diced package PK1, wherein the second side S2 is opposite to the first side S1 to which the semiconductor device 110 is bonded. At this time, a generally formed Figure 19The semiconductor package 100 is shown. In some embodiments, package PK1 is mounted to substrate 140 by means of connector 160. Substrate 140 may be a package, die, PCB, chip, or another surface. Additionally, although not shown, in some embodiments, an additional die may be mounted on substrate 140 and electrically connected to package PK1 through substrate 140. In some embodiments, substrate 140 is based on an insulating core, such as a glass fiber reinforced resin core. An exemplary core material is glass fiber resin, such as FR4. Alternatives to the core material are bismaleimide-triazine (BT) resin or alternatively other printed circuit board (PCB) materials or layers. Furthermore, substrate 140 may be fabricated using, for example, Ajinomoto coatings (ABF) or other laminates. In alternative embodiments, substrate 140 may be made of semiconductor materials such as silicon, germanium, diamond, or the like. In some embodiments, composite materials may also be used, such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide, gallium indium phosphide, combinations thereof, and the like. Additionally, substrate 140 may be a silicon on insulator substrate (SOI substrate). Typically, an SOI substrate comprises a layer of semiconductor material, such as epitaxial silicon, germanium, silicon germanium, SOI, silicon germanium on insulator (SGOI), or combinations thereof.

[0094] Figures 20 to 24 A cross-sectional view is shown of an intermediate stage in the manufacture of a semiconductor package according to some embodiments of the present disclosure. The configuration of the redistribution structure 120 described above can also be applied to integrated fan-out (InFO) packages to reduce stress in the redistribution structure 120. Therefore, another method (process) for manufacturing a semiconductor package is shown below. Reference Figure 20 In some embodiments, a carrier 101 is provided, and an adhesive layer 102 may be disposed on the carrier 101. In some embodiments, the carrier 101 may be a glass carrier, a ceramic carrier, or the like. The adhesive layer 102 may be a light-to-heat conversion release coating (LTHC) or the like.

[0095] In addition, such as Figure 20At least one semiconductor device 110 shown is disposed on the carrier 101. In some embodiments, the semiconductor device 110 may include a logic die (e.g., a central processing unit, microcontroller, etc.), a memory die (e.g., a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, etc.), a power management die (e.g., a power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a microelectromechanical system (MEMS) die, a signal processing die (e.g., a digital signal processing (DSP) die), a front-end die (e.g., an analog front-end (AFE) die), a transceiver (TRX) die, the like, or combinations thereof. Although one semiconductor device 110 is shown herein, more semiconductor devices may be disposed above the carrier 101 and flush with each other.

[0096] In some embodiments, the carrier 101 may include a plurality of die regions arranged, for example, in an array. Therefore, a plurality of semiconductor devices 110 can be disposed on each die region. With this arrangement, multiple packages can be formed simultaneously. For simplicity and clarity, Figures 20 to 24 The diagram illustrates the manufacturing process of one of the packages. For example, Figure 20 One of the semiconductor devices 110 is shown in the figure.

[0097] In some exemplary embodiments, a plurality of vias 114 (e.g., copper vias) may be formed on the active surface (e.g., the top surface) of the semiconductor device 110 and electrically coupled to a pad 113 on the substrate 112 of the semiconductor device 110. In some embodiments, a dielectric layer 116a may be formed on the active surface (e.g., the top surface) of the semiconductor device 110 and may cover the top surface of the vias 114. In other embodiments, the top surface of the dielectric layer 116a may be substantially co-horizontal with the top surface of the vias 114. Alternatively, the dielectric layer 116a may be omitted, and the conductive vias 114 may protrude from the active surface of the semiconductor device 110.

[0098] For reference Figure 21 The semiconductor device 110 on the carrier 101 is encapsulated by the encapsulating material 130. In other words, the encapsulating material 130 is provided over the carrier 101 to encapsulate the semiconductor device 110. In some embodiments, the encapsulating material 130 may comprise molding compounds, epoxy resins, or resins, etc. In some embodiments, the top surface of the encapsulating material 130 may be higher than the top surface of the dielectric layer 116a. That is, the encapsulating material 130 covers the top surface of the dielectric layer 116a.

[0099] Next, a thinning process including polishing can be performed to thin the encapsulating material 130 (and dielectric layer 116a) until the top surface of the via 114 is exposed. The resulting structure is illustrated in... Figure 21 This is attributed to the thinning process, such as... Figure 21 As shown, the top surface of the via 114 is substantially horizontal with the top surface of the encapsulating material 130 and the top surface of the dielectric layer 116. Throughout the description, as... Figure 21 The resulting structure, which includes a semiconductor device 110 and an encapsulation material 130, is referred to as an encapsulated semiconductor device 105, which may be in wafer form during the manufacturing process.

[0100] Next, refer to Figure 5 and Figure 22 A redistribution structure 120 is formed over the semiconductor device 110 and the encapsulation material 130. The redistribution structure 120 is electrically connected to the semiconductor device 110. In some embodiments, the redistribution structure 120 is formed over the encapsulated semiconductor device 105 to connect to the via 114 of the semiconductor device 110. In this embodiment, the via 114 of the semiconductor device 110 can be considered as the conductive bump 150 in the previous embodiment, which connects to the via 122 of the redistribution structure 120. In one embodiment, the redistribution structure 120 contacts the via 114 of the semiconductor device 110, the dielectric layer 116, and the encapsulation material 130 without any underfill or bumps. In some embodiments, the redistribution structure 120 can be formed by depositing a conductive layer and patterning the conductive layer to form a plurality of redistributions (e.g., redistribution 125, redistribution 128, redistribution 1222) and at least one conductive line (e.g., conductive line 123, conductive line 127). Rewiring and conductive lines are at least partially composed of a dielectric layer (e.g., Figure 5 The dielectric layers 1221, 1241, and 1261 shown herein cover and fill the gaps between the redistribution lines and the conductive lines. Vias (e.g., vias 122, 124, and 126) are located on the layers of the redistribution structure 120 and extend through the corresponding dielectric layers to interconnect the redistribution lines and conductive lines at different layers. The materials of the redistribution lines and conductive lines may comprise metals or metal alloys containing aluminum, copper, tungsten, and / or alloys thereof.

[0101] Specifically, a seed layer, such as copper, titanium, or the like, may be deposited over the carrier 101, for example, by sputtering or another physical vapor deposition (PVD) process. Photoresist is deposited on the seed layer and patterned to expose portions of the seed layer by photolithography. Patterning is used for the metallization layer on the redistribution structure 120. Conductive materials for redistribution and conductive lines, such as copper, aluminum, the like, or combinations thereof, are deposited on the exposed seed layer, for example, by electroless plating, electroplating, or similar operations. The photoresist is removed by ashing and / or rinsing processes. The exposed seed layer is removed, for example, by wet or dry etching. The remaining conductive material forms the metallization layer of the redistribution structure 120 (e.g., Figure 5The redistribution lines 125, 128, 1222, and conductive lines 123 and 127 are shown. A dielectric layer is deposited over the metallization layer (e.g., Figure 5 The dielectric layers 1221, 1241, and 1261 are shown in the diagram. The dielectric layers may be made of polymers such as polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), similar substances, or combinations thereof. The dielectric layers can be deposited using coating processes, stacking processes, similar processes, or combinations thereof. Acceptable photolithography techniques can be used to form vias through the dielectric layers to the metallization layers (e.g., ...). Figure 5 Through hole 122, through hole 124, through hole 126 shown in ).

[0102] The same or similar processes as described can be used to form subsequent metallization and dielectric layers. Conductive material deposited during the formation of subsequent metallization layers can be deposited in openings in previously formed dielectric layers to form vias for electrical connection to the respective metallization layers. After forming the topmost dielectric layer 1221, vias 122 are formed through the topmost dielectric layer 1221 for coupling connections between the redistribution structure 125 and another semiconductor device, package, die, and / or another substrate. It should be noted that any number of metallization and dielectric layers can be formed, and the redistribution structure 120 is shown as an example in this embodiment.

[0103] like Figure 3 and Figure 7 As shown, in some embodiments, the redistribution structure 120 includes vias 122, 126, and 124 connected to each other by conductive lines 123 and 127. Additionally, from a top view, conductive lines 123 and redistribution lines 125 form an angle θ, which is approximately greater than zero. In other words, conductive lines 123 and redistribution lines 125 are not parallel or collinear. In embodiments of the redistribution structure 120 having multiple conductive lines for connecting vias, from a top view, adjacent pairs of conductive lines 123 and 127 form an angle θ1, which is approximately greater than zero. That is, adjacent pairs of conductive lines 123 and 127 are not parallel or collinear. In some embodiments, angle θ1 is generally between about 20 degrees and about 90 degrees. Furthermore, an under-bump metallurgy (UBM) layer can be formed on the redistribution structure 120 by sputtering, vapor deposition, or electroless plating.

[0104] With this arrangement, compared to parallel or collinear conductive lines and redistribution lines 125, stress on the redistribution line 125 can be transmitted through vias 122 / 124 / 126 and conductive lines 123 / 127 and distributed above them. In other words, during thermal cycling, some thermal stress between the redistribution line and the semiconductor device can be released by changing the angle θ / θ1 between the conductive lines, and the additional dielectric layer (added to form at least one via) also provides greater flexibility to the redistribution structure. Thus, this arrangement can help reduce stress on the redistribution line 125 during thermal cycling (heating process) and improve the reliability of the redistribution line 125 in semiconductor packages such as the integrated fan-out (InFO) package shown herein.

[0105] refer to Figure 23 According to some exemplary embodiments, a plurality of connectors 160 are provided on the redistribution structure 120. In some embodiments, at least one integrated passive device (IPD) 162 may also be provided on the redistribution structure 120. In some embodiments, the connector 160 may be a solder ball, a metal pillar, a controlled collapse chip connection (C4) bump, a microbump, a bump formed by electroless nickel-palladium immersion gold (ENEPIG) technology, a combination thereof (e.g., a metal pillar with a solder ball attached), or the like. The connector 160 may contain a conductive material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. In some embodiments, as an example, the connector 160 contains a eutectic material and may include solder bumps or solder balls. In some embodiments, a reflow process may be performed, thereby forming the connector 160 into a partially spherical shape in some embodiments. Alternatively, the connector 160 may include other shapes. For example, the connector 160 may also include a non-spherical conductive connector. In some embodiments, connector 160 includes metal pillars (e.g., copper pillars) formed by sputtering, printing, electroplating, electroless plating, CVD, or similar operations, with or without solder material. The metal pillars may be solderless and have generally vertical or tapered sidewalls. In this embodiment, the connector is a C4 bump, but this disclosure is not limited thereto. Forming connector 160 may include placing solder balls on redistribution structure 120 and then reflowing the solder balls. In alternative embodiments, forming connector 160 may include performing a plating process to form solder areas on redistribution structure 120 and then reflowing the solder areas. Connector 160 may also include conductive pillars or conductive pillars with solder caps, which may also be formed by plating. IPD 162 can be manufactured using standard wafer fabrication techniques such as thin-film and photolithography processes and can be mounted on redistribution structure 120 by, for example, flip-chip bonding or wire bonding.

[0106] Next, refer to Figure 24 The removal step is performed to remove the carrier 101 from the encapsulated semiconductor device 105. In some embodiments, the carrier 101 is separated from the encapsulated semiconductor device 105 by causing the adhesive layer 102 to lose or reduce its adhesive strength. The adhesive layer 102 is then removed together with the carrier 101. For example, the adhesive layer 102 may be exposed to UV light to cause the adhesive layer 102 to lose or reduce its adhesive strength, and thus the carrier 101 and adhesive layer 102 can be removed from the encapsulation structure PK.

[0107] Next, the resulting structure (including the encapsulated semiconductor device 105 and the redistribution structure 120) can be mounted (e.g., frame mounting) onto dicing tape (e.g., Figure 18 The cut tape shown is then applied. The resulting structure can then be monomerized or cut (e.g., along the cut line DL), thereby forming multiple packages, each of which can be coupled with… Figure 24 The packages shown are largely the same. Next, the cut package is bonded to the substrate 140 via connector 160. At this point, a generally formed package can be formed. Figure 24 The semiconductor package 100a is shown. In some embodiments, the diced package is mounted to a substrate 140 by means of a connector 160, the substrate 140 being a package, die, PCB, chip, or another surface. Additionally, although not shown, in some embodiments, an additional die may be mounted on the substrate 140 and electrically connected to the diced package through the substrate 140. In some embodiments, the substrate 140 is based on an insulating core, such as a glass fiber reinforced resin core. An exemplary core material is glass fiber resin, such as FR4. Alternatives to the core material are bismaleimide-triazine (BT) resin or alternatively other printed circuit board (PCB) materials or layers. Furthermore, for the substrate 140, a laminate of coating (ABF) or other stacks may be used, for example, with Ajinomoto. In alternative embodiments, the substrate 140 may be made of a semiconductor material such as silicon, germanium, diamond, or the like. In some embodiments, composite materials may also be used, such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide, gallium indium phosphide, combinations thereof, and the like. Additionally, substrate 140 may be a silicon-on-insulator (SOI) substrate. Typically, an SOI substrate comprises a layer of semiconductor material, such as epitaxial silicon, germanium, silicon germanium, SOI, silicon germanium-on-insulator (SGOI), or combinations thereof.

[0108] Based on the foregoing discussion, it is evident that this disclosure provides various advantages. However, it should be understood that not all advantages need to be discussed herein, and other embodiments may provide different advantages, and no particular advantage is required for all embodiments.

[0109] Other features and processes may also be included. For example, test structures may be included to assist in verification testing of 3D packaged or 3DIC devices. Test structures may include, for example, test pads formed in redistribution layers or on a substrate that allows for testing of the 3D package or 3DIC, the use of probes and / or probe cards, and the like. Verification tests can be performed on intermediate and final structures. Furthermore, the structures and methods disclosed herein can be combined with test methods incorporated into intermediate verification of known good dies to improve yield and reduce costs.

[0110] According to some embodiments of this disclosure, a semiconductor package includes an encapsulated semiconductor device and a redistribution structure. The encapsulated semiconductor device includes a semiconductor device encapsulated by an encapsulating material. The redistribution structure covers the encapsulated semiconductor device and includes a plurality of vias and redistribution lines. The plurality of vias are located on different layers of the redistribution structure and are interconnected by a plurality of conductive lines, wherein, in a top view, the angle between any two adjacent conductive lines is greater than zero. The redistribution lines are disposed below the plurality of conductive lines and connect to a corresponding via, and are electrically connected to the semiconductor device through the plurality of vias.

[0111] In one embodiment, the semiconductor package further includes a plurality of conductive bumps engaged between the semiconductor device and the redistribution structure, and one of the plurality of conductive bumps is engaged with the uppermost via of the plurality of vias.

[0112] In one embodiment, one of the plurality of conductive bumps is closest to the edge of the semiconductor device.

[0113] In one embodiment, the semiconductor package further includes a substrate and a plurality of connectors, wherein the redistribution structure is bonded to the substrate via the plurality of connectors.

[0114] In one embodiment, the angle is between 20° and 90°.

[0115] In one embodiment, the plurality of through holes do not overlap each other when viewed from a top view.

[0116] In one embodiment, the horizontal distance between one of the plurality of vias bonded to the semiconductor device and the nearest edge of the semiconductor device is shorter than the horizontal distance between another of the plurality of vias connecting the rewiring and the nearest edge of the semiconductor device.

[0117] In one embodiment, viewed from a top view, the angle between one of the plurality of conductive lines and the rewire is greater than zero.

[0118] According to some embodiments of this disclosure, a semiconductor package includes a semiconductor device and a redistribution structure. The redistribution structure overlays the semiconductor device and includes a plurality of vias and redistribution lines. The vias are located on different layers of the redistribution structure and are interconnected by a plurality of conductive lines. Redistribution lines are disposed beneath the plurality of conductive lines and connect to a corresponding via, wherein the horizontal distance between one of the vias connected to the semiconductor device and the nearest edge of the semiconductor device is shorter than the horizontal distance between another via connecting the redistribution lines and the nearest edge of the semiconductor device.

[0119] In one embodiment, it further includes a plurality of conductive bumps joined between the semiconductor device and the redistribution structure, and one of the plurality of conductive bumps is joined to one of the plurality of vias.

[0120] In one embodiment, the semiconductor package further includes a substrate and a plurality of connectors, wherein the redistribution structure is bonded to the substrate via the plurality of connectors.

[0121] In one embodiment, the angle between any two adjacent conductive wires is greater than zero.

[0122] In one embodiment, the angle is between 20° and 90°.

[0123] In one embodiment, the plurality of through holes do not overlap each other when viewed from a top view.

[0124] In one embodiment, viewed from a top view, the angle between one of the plurality of conductive lines and the rewire is greater than zero.

[0125] In one embodiment, the semiconductor package further includes an encapsulation material disposed above the redistribution structure and encapsulating the semiconductor device.

[0126] According to some embodiments of this disclosure, a method for manufacturing a semiconductor package includes the following steps: forming a redistribution structure, wherein the redistribution structure includes a plurality of vias interconnected by a plurality of conductive lines and redistribution lines connected to a semiconductor device through the plurality of vias, and, in a top view, the angle between any two adjacent conductive lines is greater than zero; bonding a semiconductor device to a first side of the redistribution structure; providing an encapsulating material over the redistribution structure to encapsulate the semiconductor device; and bonding a substrate to a second side of the redistribution structure opposite to the first side.

[0127] In one embodiment, the angle is between 20° and 90°.

[0128] In one embodiment, the semiconductor device is bonded to the uppermost of the plurality of vias on the first side of the redistribution structure via a plurality of conductive bumps.

[0129] In one embodiment, the substrate is bonded to the second side of the redistribution structure via a plurality of connectors.

[0130] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures for performing the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor package, comprising: Encapsulated semiconductor devices, including semiconductor devices encapsulated by encapsulation materials; as well as A redistribution structure, covering the encapsulated semiconductor device, includes: Multiple through-holes are located on different layers of the redistribution structure and are connected to each other by multiple conductive lines; as well as A redistribution line is disposed below the plurality of conductive lines and connected to a corresponding one of the plurality of vias, and electrically connected to the semiconductor device through the plurality of vias, wherein, from a top view, the angle between the redistribution line and one of the plurality of conductive lines is greater than zero, and the one of the plurality of conductive lines is adjacent to the redistribution line.

2. The semiconductor package of claim 1 further includes a plurality of conductive bumps joined between the semiconductor device and the redistribution structure, wherein one of the plurality of conductive bumps is joined to the uppermost via of the plurality of vias.

3. The semiconductor package of claim 2, wherein one of the plurality of conductive bumps is closest to the edge of the semiconductor device.

4. The semiconductor package of claim 1, further comprising a substrate and a plurality of connectors, wherein the redistribution structure is bonded to the substrate via the plurality of connectors.

5. The semiconductor package of claim 1, wherein the angle is between 20° and 90°.

6. The semiconductor package of claim 1, wherein, viewed from a top view, the plurality of vias do not overlap each other.

7. The semiconductor package of claim 1, wherein the horizontal distance between one of the plurality of vias bonded to the semiconductor device and the nearest edge of the semiconductor device is shorter than the horizontal distance between another of the plurality of vias connecting the rewiring and the nearest edge of the semiconductor device.

8. The semiconductor package of claim 1, wherein, viewed from a top view, the angle between one of the plurality of conductive lines and the redistribution line is greater than zero.

9. A semiconductor package, comprising: Semiconductor devices; as well as A redistribution structure, covering the semiconductor device, includes: Multiple vias, located on different layers of the redistribution structure and interconnected by multiple conductive lines; and A redistribution line is disposed below the plurality of conductive lines and connected to a corresponding one of the plurality of through holes, wherein, from a top view, the angle between the redistribution line and one of the plurality of conductive lines is greater than zero, and the one of the plurality of conductive lines is adjacent to the redistribution line.

10. The semiconductor package of claim 9, further comprising a plurality of conductive bumps joined between the semiconductor device and the redistribution structure, wherein one of the plurality of conductive bumps is joined to one of the plurality of vias.

11. The semiconductor package of claim 9, further comprising a substrate and a plurality of connectors, wherein the redistribution structure is bonded to the substrate via the plurality of connectors.

12. The semiconductor package of claim 9, wherein the angle between any two adjacent conductive lines is greater than zero.

13. The semiconductor package of claim 12, wherein the angle between two adjacent conductive lines is between 20° and 90°.

14. The semiconductor package of claim 9, wherein, viewed from a top view, the plurality of vias do not overlap each other.

15. The semiconductor package of claim 6, wherein, viewed from a top view, the angle between one of the plurality of conductive lines and the redistribution line is greater than zero.

16. The semiconductor package of claim 9, further comprising an encapsulation material disposed above the redistribution structure and encapsulating the semiconductor device.

17. A method for manufacturing a semiconductor package, comprising: Forming a rewiring structure, The redistribution structure includes multiple vias connected to each other by multiple conductive lines and a redistribution line connected to the semiconductor device through the multiple vias. From a top view, the angle between the redistribution line and one of the multiple conductive lines is greater than zero, and the one of the multiple conductive lines is adjacent to the redistribution line. The semiconductor device is bonded to the first side of the redistribution structure; An encapsulating material is provided over the redistribution structure to encapsulate the semiconductor device; as well as The substrate is bonded to the second side of the redistribution structure opposite to the first side.

18. The method of manufacturing a semiconductor package according to claim 17, wherein the angle is between 20° and 90°.

19. The method of manufacturing a semiconductor package according to claim 17, wherein the semiconductor device is bonded to the uppermost of the plurality of vias on the first side of the redistribution structure by a plurality of conductive bumps.

20. The method of manufacturing a semiconductor package according to claim 17, wherein the substrate is bonded to the second side of the redistribution structure by a plurality of connectors.

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