A multi-value memory

Abstract

This invention discloses a multi-value memory. The multi-value memory includes: multiple memory sub-columns; each memory sub-column includes a floating diffusion region and multiple memory cells; each memory cell includes at least: a charge storage region and a corresponding transfer transistor; each memory sub-column further includes: a reset transistor and a source follower transistor; the source follower transistor is a fin-type field-effect transistor to reduce its size in the row direction. This invention, by designing a novel fin-type field-effect transistor for use in multi-value memory, can increase the chip area of ​​the multi-value memory, thereby achieving high-density storage.

Description

Technical Field

[0001] This invention relates to the field of storage processing, and more particularly to a multi-value memory. Background Technology

[0002] Random access memory (RAM) allows data to be read from or written on demand, and the read / write speed is independent of the data's storage location. This type of memory has the fastest read / write speeds among memory types, but it loses its stored data when power is off, so it is mainly used to store data needed for short periods. Based on the type of information stored, RAM can be further divided into static random access memory (SRAM) and dynamic random access memory (DRAM).

[0003] An existing type of SRAM, such as Figure 1 As shown, its storage cell is a flip-flop composed of six MOS transistors: P0, P1, N0, N1, N2, and N3. It has two stable states and is also called a bistable flip-flop. SRAM offers faster storage speeds and lower power consumption. However, compared to dynamic random access memory (DRAM), SRAM occupies a larger area for the same storage capacity, making it more suitable for applications requiring fast data access with relatively small data volumes.

[0004] An existing type of DRAM, such as Figure 2As shown, its memory cell is a memory circuit composed of a MOSFET M1 and a capacitor C1, where the MOSFET M1 acts as a switch and the capacitor C1 acts as the storage medium. The capacitor C1 in DRAM is generally formed using a stacked or trench configuration. The advantages are a small footprint and the ability to achieve large capacities. The disadvantages are that the manufacturing process is much more complex than logic circuits, and the access speed is slower than SRAM. Another disadvantage of DRAM is that the memory cells are stored based on the charge on the capacitor C1. This charge decreases over time and with temperature, therefore it must be refreshed periodically to maintain the correct information it originally stored. Another drawback of DRAM is the conductive interconnection between capacitor C1 and MOSFET M1, which requires a contact hole. This contact hole needs to contact the silicon surface when interconnecting with the MOSFET. This creates an interface state between the contact hole and the silicon. Electrons in the interface state are more active (the contact hole is made using plasma etching, which damages the chip surface. The presence of the interface state creates numerous defect centers on the surface, making it easier for charge carriers to be captured and released, greatly increasing leakage current). Leakage current is a very difficult problem to control (increased leakage current leads to shorter refresh time and increased power consumption). Furthermore, both DRAM and SRAM exhibit reset noise during read and write operations.

[0005] Semiconductor memory is a type of storage unit that distinguishes logical states by determining the amount of stored charge. It is characterized by low cost and simple structure, and often occupies a high density in chip design. With the continuous development of semiconductor technology, chip design is becoming increasingly complex, leading to larger and larger corresponding storage spaces. As the field of memory technology advances, memory density continues to increase, thus placing higher demands on memory structure design. Summary of the Invention

[0006] To address the above problems, the present invention aims to provide a multi-valued memory that enables a single memory cell to store multiple bits of data. A finned field-effect transistor (FFET) is designed as a source follower transistor for this multi-valued memory, thereby achieving a high-density storage structure. The multi-valued memory includes: Multiple storage sub-columns; Each storage sub-column includes a floating diffusion area and multiple storage cells; The storage unit includes at least: a charge storage region and a corresponding transfer transistor; Each memory sub-column also includes: a reset transistor and a source follower transistor; The source follower transistor is a finned field-effect transistor to reduce the size of the source follower transistor in the row direction.

[0007] In some embodiments, some of the source follower transistors in the storage sub-columns located in the same row are arranged in the first row, and the remaining source follower transistors are arranged in the second row.

[0008] In some embodiments, the source follower transistors corresponding to the odd-numbered and even-numbered storage sub-columns in the same row are respectively disposed in the first row and the second row.

[0009] In some embodiments, a method of forming the source follower transistor includes: Trenches are formed on the substrate; Fill the barrier layer to cover the trench; Etch a portion of the area surrounding the trench to form a shallow trench; An oxide layer is filled to cover the shallow trenches, forming a shallow trench isolation structure; The oxide layer is then mechanically ground until the barrier layer is reached. Remove the barrier layer in the trench; A polycrystalline silicon layer is laid to cover the trench; The polysilicon layer is etched at least partially to form the source follower transistor.

[0010] In some embodiments, the fins of the source follower transistor are sequentially divided into a source region, a channel region, a drain region, and a connection region; The sides and top surface of the source region are not covered with polycrystalline silicon; The sides and top surface of the trench region are wrapped with polycrystalline silicon; The upper side and upper surface of the drain region are not covered with polycrystalline silicon; The sides and top surface of the connection area are covered with polycrystalline silicon.

[0011] In some embodiments, the floating diffusion region of each storage sub-column is a connected structure along the column direction; The transfer transistor has a partially vertical channel, and the transfer of charge between the floating diffusion region and the charge storage region is controlled by the polysilicon gate structure located on both sides of the transfer transistor channel.

[0012] In some embodiments, the floating diffusion region corresponds to the area above the middle region of the charge storage region.

[0013] In some embodiments, at least two storage sub-columns share a single signal write line.

[0014] In some embodiments, when writing to each row of storage cells, a multiplexing method is used to write the signals to be stored to multiple floating diffusion areas corresponding to multiple storage sub-columns in batches. The signals stored in the multiple floating diffusion regions are written into the charge storage region of the multiple storage sub-columns in the same row of the storage cells at once, reducing the inconsistency between adjacent storage cells.

[0015] This invention also provides an electronic information device, including the aforementioned multi-value memory.

[0016] Compared with the prior art, the present invention has the following advantages: (1) The storage unit of the multi-value memory of the present invention is different from the existing memory structure. It can be compatible with the existing CMOS image sensor architecture and the circuit structure is simpler. It uses photodiodes as charge storage areas and realizes multi-value (multi-bit) storage by storing different amounts of charge through photodiodes.

[0017] (2) In the embodiments of the present invention, the source follower transistor is a fin field-effect transistor, which can reduce the size of the source follower transistor in the row direction. In the embodiments of the present invention, the source follower transistors corresponding to the odd-numbered and even-numbered storage sub-columns in the same row are respectively set in the first row and the second row.

[0018] (3) The transfer transistor of the memory cell differs from the traditional structure. Part of the channel of this transfer transistor is vertical, and the source and drain of the transfer transistor are placed from bottom to top. The source / drain regions and the channel are fabricated with epitaxial layers of different concentrations, and the structure is defined by etching. The gate of the transfer transistor does not require photolithography but is prepared through a single deposition-etch-back step with self-alignment. By using the polysilicon gate structure located on both sides of the transfer transistor channel, the transfer of charge between the floating diffusion region and the charge storage region is controlled, reducing the circuit design area and increasing the storage capacity. The fabrication process of the transfer transistor in this embodiment is fully compatible with existing transistor fabrication processes and significantly reduces the number of photomasks required. While increasing the integration density of the transfer transistor, it can reduce the cost of chip fabrication.

[0019] (4) Different storage sub-columns share a signal line. When writing to each row of storage cells, a multiple-choice method is used to write the signals to be stored to multiple floating diffusion areas corresponding to multiple storage sub-columns in batches. The signals stored in the multiple floating diffusion areas are written to the charge storage area of ​​the storage cells in the same row of the multiple storage sub-columns at one time, which reduces the inconsistency between adjacent storage cells and improves the storage speed. Attached Figure Description

[0020] The present invention will be further described by way of exemplary embodiments, which will be described in detail with reference to the accompanying drawings. These embodiments are not limiting, and in these embodiments, the same reference numerals denote the same structures, wherein: Figure 1This is a schematic diagram of the structure of a static random access memory (SRAM). Figure 2 This is a schematic diagram of the structure of a dynamic random access memory; Figure 3 This is a schematic diagram of a multi-value memory module according to an embodiment of the present invention; Figure 4 This is a schematic diagram of the readout circuit of the multi-value memory according to an embodiment of the present invention; Figure 5 This is a schematic diagram of the write circuit of the multi-value memory according to an embodiment of the present invention; Figures 6 to 24 This is a schematic diagram illustrating an exemplary process for forming multiple transfer transistors corresponding to multiple memory cells according to an embodiment of the present invention. Figure 25 This is a schematic diagram of an exemplary layout design of a multi-value memory according to an embodiment of the present invention; Figure 26 This is a schematic diagram of an exemplary source follower transistor according to an embodiment of the present invention; Figures 27 to 36 This is a schematic diagram of an exemplary process for forming a source follower transistor according to an embodiment of the present invention. Detailed Implementation

[0021] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are merely some examples or embodiments of the present invention. For those skilled in the art, these drawings can be applied to other similar scenarios without creative effort. Unless obvious from the context or otherwise specified, the same reference numerals in the drawings represent the same structures or operations.

[0022] This invention provides a multi-value memory that differs from the architecture and implementation of existing dynamic random access memory (DRAM) and static random access memory (SRAM). It enables multi-value (multi-bit) storage while remaining compatible with CMOS image sensor architectures. Combined with... Figures 3 to 6 A multi-value memory according to an embodiment of the present invention is described.

[0023] like Figure 3As shown, the multi-value memory 100 includes a storage area 10, a row decoder 20, and a write / read circuit 30. The storage area 10 includes multiple storage sub-arrays 110. Each storage sub-array 110 includes a floating diffusion region FD and multiple storage cells 130. For example, each storage sub-array 110 may include four storage cells 130. The read circuit 200 includes a reset transistor RST, a source follower transistor SF, and a row select transistor SEL. The reset transistor SF is connected to the reset voltage VDD and the floating diffusion region FD, and is adapted to control the reset of the floating diffusion region FD. The source follower transistor SF is connected to the reset potential VDD, and its gate is connected to the floating diffusion region FD, and is adapted to convert the signal from the floating diffusion region FD and increase its gain to the output terminal. The row select transistor SEL is connected to the source follower transistor SF and the signal acquisition terminal, and is adapted to read the row selection of the control signal. During the readout process, the voltage of the floating diffusion region FD of a certain storage sub-array 110 is reset by the reset transistor RST, and the transfer transistor Tx corresponding to a certain storage cell 130 in the storage sub-array 110 is controlled to transfer the charge stored in the photodiode PD (also known as the charge storage region) of the storage cell 130 to the floating diffusion region FD. The signal voltage of the floating diffusion region FD is read out by the source follower transistor SF. The correlated double sampling operation is completed to obtain the charge value stored in the storage cell 130, which is converted into multi-bit wide data stored in the storage cell 130, and the readout operation of the specific storage cell 130 is completed.

[0024] like Figure 4 As shown, the storage cell 130 includes a photodiode PD and a corresponding transfer transistor Tx. The photodiode PD serves as a charge storage region. The floating diffusion region FD of each storage sub-column 110 is connected along the column direction.

[0025] like Figure 5As shown, the write circuit 300 includes a digital-to-analog converter circuit 321. The digital-to-analog converter circuit is connected to a multiplexer switch 322. The multiplexer switch 322 is connected to multiple multiplexer switches 323. Each multiplexer switch 323 is connected to a switching transistor 324 corresponding to multiple memory sub-columns 110. In some embodiments, at least two memory sub-columns share a signal write line. For example, four memory sub-columns 110 are connected to one multiplexer switch 323 through corresponding switching transistors 324, and the four multiplexer switches 323 are connected to one multiplexer switch 322. When writing to each row of memory cells 130, a multiplexing method can be used to write the signals to be stored in batches to multiple floating diffusion regions 120 corresponding to multiple memory sub-columns 110, and then write the signals stored in the multiple floating diffusion regions FD to the charge storage region of the memory cells 130 in the same row of multiple memory sub-columns 110 at once, thereby reducing the inconsistency between adjacent memory cells. Specifically, through the switching transistor 324, multiplexer 323, and multiplexer 322, the signals to be stored can be temporarily stored sequentially into the floating diffusion regions FD corresponding to different storage sub-columns 110. The signals to be stored can be multi-bit wide data. The signals to be stored can be converted into corresponding charges and temporarily stored in the floating diffusion regions FD. The gates of the transfer transistors Tx corresponding to the storage cells 130 in the same row are connected to the word line. Therefore, by controlling the word line to simultaneously turn on the transfer transistors Tx corresponding to the storage cells 130 in the same row, signals stored in multiple floating diffusion regions FD can be written at once into the charge storage regions of multiple storage sub-columns 110 in the same row of storage cells 130.

[0026] Figures 6 to 24 This is a schematic diagram of an exemplary transfer transistor process for forming a memory cell according to an embodiment of the present invention.

[0027] like Figure 6 As shown, a substrate 401 is provided. In some embodiments, the substrate 401 may be a P-type epitaxial layer epitaxially grown on a single-crystal silicon wafer.

[0028] like Figure 7 As shown, a first hole structure 402 is formed by etching a substrate 401. In some embodiments, the first hole structures 402 are arranged in an array; the shape of the first hole structures 402 can be circular, square, rectangular, or the like. The first hole structures 402 are surrounded by a grid of active regions 403 that are mutually separated.

[0029] like Figure 8As shown, a first doped epitaxial layer 404 is formed by epitaxy of the first hole structure 402, thereby forming a lateral PN junction to realize the charge storage function, that is, the photodiode serves as the charge storage region 404. In some embodiments, a buffer layer (not shown) may also be formed within the holes of the first hole structure 402. In some embodiments, the first doped epitaxial layer 404 has a concentration gradient distribution from bottom to top. In some embodiments, the first hole structure 402 can be formed on a P-type doped substrate 401, and an N-type doped epitaxial layer is used as the first doped epitaxial layer 404 within the first hole structure 402 as the charge storage region. In some embodiments, when the first doped epitaxial layer 404 is formed by epitaxy of the first hole structure 402, the portion of the first doped epitaxial layer 404 covering the active region 403 (not shown) needs to be chemically mechanically polished to expose the grid-like active region 403 and the arrayed charge storage regions 404 (or the first doped epitaxial layer 404).

[0030] like Figure 9 As shown, a second doped epitaxial layer 405 is formed above the first doped epitaxial layer 404. The second doped epitaxial layer 405 can be P-type.

[0031] Figure 10 This is a three-dimensional structural diagram illustrating the process of forming the transfer transistor corresponding to the memory cell. Figure 11 This is a cross-sectional diagram of the corresponding row direction. For example... Figure 10 and 11 As shown, the second doped epitaxial layer 405 is etched to form a second hole structure 406. The remaining portion of the second epitaxial layer 405 between adjacent second hole structures 406 in the row direction serves as a transfer channel 405 for forming a transfer transistor, and the transfer channel 405 is at least partially perpendicular.

[0032] Figure 12 This is a three-dimensional structural diagram illustrating the process of forming the transfer transistor corresponding to the memory cell. Figure 13 This is a cross-sectional diagram of the corresponding row direction. For example... Figure 12 and 13 As shown, an oxide layer 407 is formed on the side and bottom of the second hole structure 406 and on the upper part of the transfer channel.

[0033] Figure 14 This is a three-dimensional structural diagram illustrating the process of forming the transfer transistor corresponding to the memory cell. Figure 15 This is a cross-sectional diagram of the corresponding row direction. For example... Figure 14 and 15 As shown, a polycrystalline silicon layer 408 is laid to fill the second void structure 406. The polycrystalline silicon layer 408 is doped with N-type ions.

[0034] Figure 16This is a three-dimensional structural diagram illustrating the process of forming the transfer transistor corresponding to the memory cell. Figure 17 This is a cross-sectional diagram of the corresponding row direction. For example... Figure 16 As shown in Figure 17, after the polysilicon layer 408 is laid to fill the second hole structure 406, chemical mechanical polishing (CMP) can be used to remove part of the polysilicon layer 408, while ensuring the removal of the oxide layer 407 on the upper part of the transfer channel 405.

[0035] Figure 18 This is a three-dimensional structural diagram illustrating the process of forming the transfer transistor corresponding to the memory cell. Figure 19 This is a cross-sectional diagram of the corresponding row direction. For example... Figure 18 and Figure 19 As shown, by injecting N-type ions, a floating diffusion region 409 can be formed above the vertical transfer channel 405.

[0036] Figure 20 This is a three-dimensional structural diagram illustrating the process of forming the transfer transistor corresponding to the memory cell. Figure 21 This is a cross-sectional diagram of the corresponding column direction. For example... Figure 20 He Ru Figure 21 As shown, where, Figure 21 This is a schematic cross-sectional view along the column direction. Since two adjacent floating diffusion regions 409 are electrically connected along the row direction after N-type ion implantation, an isolation structure is needed between them to isolate them. The upper part of this isolation structure is formed by etching a third hole 410, thus preventing adjacent floating diffusion regions 120 from conducting in the row direction. The shape and size of the third hole 410 can be adjusted according to process requirements.

[0037] Figure 22 This is a three-dimensional structural diagram illustrating the process of forming the transfer transistor corresponding to the memory cell. Figure 23 This is a cross-sectional diagram of the corresponding column direction. Figure 24 This is a cross-sectional diagram of the corresponding row direction. For example... Figure 22 , 23 As shown in Figure 24, to ensure complete isolation between two adjacent floating diffusion regions 409, the polysilicon layer 408 is etched back using an etching process, making the surface of the polysilicon layer 408 lower than the upper surface of the floating diffusion region 409, thereby separating the polysilicon gates 408 of different transfer transistors Tx along the column direction. After the etch-back process, the depth of the third hole 410 continues to increase, thereby increasing the depth of the isolation structure and completing the lower part of the isolation structure, thus isolating the floating diffusion regions 409 of adjacent columns. Furthermore, electrical contact points 411 (such as...) can be formed above the polysilicon 408. Figure 25 As shown in the figure, it is possible to control two adjacent transfer transistors Tx in the row direction using the same electrical contact point 411.

[0038] like Figure 22 and Figure 24 As shown, a portion of the channel 405 of the transfer transistor Tx is vertical. Through the polysilicon 408 located on both sides of the transfer channel 405, the transfer of charge between the transfer transistor Tx and the floating diffusion region 409 and the charge storage region 404 can be controlled. In some embodiments, the floating diffusion region 409 corresponds to the area above the middle region of the charge storage region 404, that is, the floating diffusion region 409 is disposed above the center position of the charge storage region 404. In some embodiments, the floating diffusion region 409 may be offset from the middle region of the charge storage region 404, that is, the floating diffusion region 409 is offset from the center position of the charge storage region 404 to a certain extent.

[0039] Figure 25 This is a schematic diagram 400 illustrating an exemplary layout design of a multi-value memory according to an embodiment of the present invention.

[0040] like Figure 25 As shown, there is an isolation structure between adjacent rows of transfer transistors Tx in the transfer transistor Tx array (dashed box in the figure); there is an isolation structure between the reset transistor RST array (dashed box in the figure) and the transfer transistor Tx array; the source follower transistor array SF can be arranged in two rows. In some embodiments, some source follower transistors SF corresponding to the storage sub-column in the same row are arranged in the first row, and the remaining source follower transistors SF are arranged in the second row. Figure 25 As shown, the source follower transistors SF corresponding to the odd-numbered and even-numbered storage sub-columns in the same row are respectively located in the first and second rows. The left and right transfer transistors Tx can be controlled through the same electrical contact 411; the left and right reset transistors RST can also be controlled through the same electrical contact 411. The floating diffusion region FD can be electrically connected to the electrical contact 504 on the polysilicon gate of the source follower transistor SF through electrical contact 412. The drains of different source follower transistors SF can be electrically connected through electrical contact 503. The sources of different source follower transistors SF can output signals through electrical contact 501.

[0041] Figure 26 This is a schematic diagram 500 of an exemplary source follower transistor according to an embodiment of the present invention.

[0042] like Figure 26 As shown, the source follower transistor SF in this embodiment of the invention is a FinFET (Fin Field-Effect Transistor) structure.

[0043] The source follower transistor SF is formed on the second doped epitaxial layer 405.

[0044] The fins 501 of the source follower transistor SF are sequentially divided into a source region, a channel region, a drain region, and a connection region. The sides and top surface of the source region are not covered with polysilicon 505. The sides and top surface of the channel region are covered with polysilicon 505. The top side and top surface of the drain region are not covered with polysilicon 505. The sides and top surface of the connection region are covered with polysilicon 505. An electrical contact 502 is formed on the source region; an electrical contact 503 is formed on the drain region; and an electrical contact 504 is formed on the connection region.

[0045] The source follower transistor SF in this embodiment differs from the conventional FinFET structure. In a conventional FinFET structure, an electrical contact is formed on the polysilicon 505 above the channel region. However, in this embodiment, no electrical contact is formed on the polysilicon 505 above the channel region. In this embodiment, a connection region is added to one end of the fin 501, communicating with the polysilicon of the connection region via the polysilicon 505 wrapped on the side, and an electrical contact 504 is formed on the polysilicon 505 above the connection region. Through the electrical contact 504, electrical connections can be formed with other components (e.g., the floating diffusion region FD), realizing the electrical connection between the gate of the source follower transistor SF and other components. This design avoids the wiring between the gate of the source follower transistor SF and the floating diffusion region FD intersecting with the wiring between the drain of the source follower transistor SF and other components, thereby reducing wiring complexity.

[0046] Figures 27 to 36 This is a schematic diagram of an exemplary process for forming a source follower transistor according to an embodiment of the present invention.

[0047] like Figure 27 Trench 601 is formed on substrate 405, and fin 501 is formed thereon; wherein, substrate 405 is Figure 9 The second doped epitaxial layer 405 is formed on the substrate 401.

[0048] like Figure 28 As shown, a barrier layer 602 is filled to cover the trench 601. The barrier layer 602 may be silicon nitride.

[0049] like Figure 29 As shown, a portion of the barrier layer 602 above the barrier layer 602 is removed by chemical mechanical polishing. In some embodiments, this step can be omitted.

[0050] like Figure 30 A shallow trench 603 is formed by etching a portion of the area surrounding the trench 601. like Figure 31 An oxide layer 604 is filled to cover the shallow trench 603, forming a shallow trench isolation structure.

[0051] like Figure 32 The oxide layer 604 is ground by chemical mechanical polishing until the barrier layer 602 is reached.

[0052] like Figure 33 Remove the barrier layer 602 in the trench 601.

[0053] like Figure 34 A gate oxide layer 605 is formed in the trench 601.

[0054] like Figure 35 A polycrystalline silicon layer 505 is laid to cover the trench 601.

[0055] like Figure 36 At least partially etch the polysilicon layer to form such a Figure 26 The FinFET 500 in the middle.

[0056] The basic concepts have been described above. It is clear that the detailed disclosure above is merely illustrative and does not constitute a limitation of the present invention. Although not explicitly stated herein, various modifications, improvements, and corrections may be made to the present invention by those skilled in the art. Such modifications, improvements, and corrections are suggested in this invention and therefore remain within the spirit and scope of the exemplary embodiments of the present invention.

[0057] It should be understood that the embodiments described in this invention are merely illustrative of the principles of the invention. Other modifications may also fall within the scope of this invention. Therefore, alternative configurations of the embodiments of this invention are considered as examples and not limitations, and are regarded as consistent with the teachings of this invention. Accordingly, the embodiments of this invention are not limited to those explicitly described and illustrated herein.

Claims

1. A multi-value memory, characterized in that, include: Multiple storage sub-columns; Each storage sub-column includes a floating diffusion area and multiple storage cells; The storage unit includes at least: a charge storage region and a corresponding transfer transistor; the charge storage region adopts a PN junction structure to realize the function of charge storage; Each memory sub-column also includes: a reset transistor and a source follower transistor; The source follower transistor is a fin field-effect transistor to reduce the size of the source follower transistor in the row direction; The floating diffusion region of each storage sub-column has a connected structure along the column direction; The transfer transistor has a partially vertical channel, and the transfer of charge between the floating diffusion region and the charge storage region is controlled by the polysilicon gate structure located on both sides of the transfer transistor channel.

2. The multi-value memory according to claim 1, characterized in that, Some of the source follower transistors in the storage sub-column located in the same row are set in the first row, and the remaining source follower transistors are set in the second row.

3. The multi-value memory according to claim 1, characterized in that, The source follower transistors corresponding to the odd-numbered and even-numbered storage sub-columns in the same row are respectively set in the first and second rows.

4. The multi-value memory according to claim 1, characterized in that, The method of forming the source follower transistor includes: Trenches are formed on the substrate; Fill the barrier layer to cover the trench; Etch a portion of the area surrounding the trench to form a shallow trench; An oxide layer is filled to cover the shallow trenches, forming a shallow trench isolation structure; The oxide layer is then mechanically ground until the barrier layer is reached. Remove the barrier layer in the trench; A polycrystalline silicon layer is laid to cover the trench; The polysilicon layer is etched at least partially to form the source follower transistor.

5. The multi-value memory according to claim 4, characterized in that, The fins of the source follower transistor are sequentially divided into a source region, a channel region, a drain region, and a connection region. The sides and top surface of the source region are not covered with polycrystalline silicon; The sides and top surface of the trench region are wrapped with polycrystalline silicon; The upper side and upper surface of the drain region are not covered with polycrystalline silicon; The sides and top surface of the connection area are covered with polycrystalline silicon.

6. The multi-value memory as described in claim 1, characterized in that, The floating diffusion region corresponds to the area above the middle region of the charge storage region.

7. The multi-value memory as described in claim 1, characterized in that, At least two storage sub-columns share a single signal write line.

8. The multi-value memory as described in claim 7, characterized in that, When writing to each row of storage cells, a multi-way selection method is used to write the signals to be stored to multiple floating diffusion areas corresponding to multiple storage sub-columns in batches. The signals stored in the multiple floating diffusion regions are written into the charge storage region of the multiple storage sub-columns in the same row of the storage cells at once, reducing the inconsistency between adjacent storage cells.

9. An electronic information device, characterized in that, Includes a multi-value memory as described in any one of claims 1 to 8.

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