Semiconductor memory device and method of manufacturing the same

Abstract

The present application relates to a semiconductor memory device and a manufacturing method thereof. A semiconductor memory device includes a gate electrode stack vertically stacked above a substrate and having a curved gate pad, the curved gate pad of the gate electrode stack having a stepped structure; an interlayer dielectric layer covering the curved gate pad; and a plurality of contact plugs respectively coupled to the curved gate pad by penetrating the interlayer dielectric layer, wherein the curved gate pad includes tilted corner portions of different sizes.

Description

Technical Field

[0001] Exemplary embodiments of the present invention relate to semiconductor devices, and more specifically, to a semiconductor memory device and a method of manufacturing the semiconductor memory device. Background Technology

[0002] A growing number of technologies require improved integration levels in semiconductor devices to achieve the superior performance and low prices demanded by consumers. In the case of semiconductor devices, increased integration is particularly crucial, as it is a significant factor in determining product price. To address this requirement, three-dimensional semiconductor memory devices with three-dimensionally arranged memory cells have been proposed. Summary of the Invention

[0003] According to an embodiment of the present invention, a semiconductor memory device includes: a gate electrode stack vertically stacked above a substrate and having a curved gate pad, the curved gate pad having a stepped structure; an interlayer dielectric layer covering the curved gate pad; and a plurality of contact plugs respectively connected to the curved gate pad by penetrating the interlayer dielectric layer, wherein the curved gate pad includes inclined corner portions of different sizes.

[0004] According to another embodiment of the present invention, a semiconductor memory device includes: a substrate; a stack in which a plurality of dielectric layers and a plurality of conductive layers are alternately stacked in a direction perpendicular to the surface of the substrate; a stepped trench penetrating the stack, the stepped trench including a plurality of trenches extending perpendicularly toward the substrate; and an interlayer dielectric layer filling the stepped trench, wherein the plurality of trenches include inclined corner portions of different sizes.

[0005] According to another embodiment of the present invention, a method for manufacturing a semiconductor memory device includes the following steps: forming a stack of multiple sacrificial layers and multiple dielectric layers alternately stacked over a substrate; forming a stepped trench penetrating the stack, the stepped trench including multiple trenches with inclined corner portions of different sizes; forming an interlayer dielectric layer filling the stepped trench; and replacing the sacrificial layers with a conductive layer.

[0006] According to another embodiment of the present invention, a semiconductor memory device includes: a gate electrode stack vertically stacked above a substrate and having a curved gate pad, the curved gate pad having a stepped structure; an interlayer dielectric layer covering the curved gate pad; and a plurality of contact plugs respectively connected to the curved gate pad by penetrating the interlayer dielectric layer, wherein the curved gate pad includes inclined corner portions of different sizes. Attached Figure Description

[0007] Figure 1A It is a schematic layout diagram of a semiconductor memory device shown in a plan view.

[0008] Figure 1B It is along Figure 1A A detailed cross-sectional view of the section cut by line A-A'.

[0009] Figure 1C yes Figure 1B A schematic three-dimensional view of the vertical channel structure shown.

[0010] Figure 2A This is a detailed diagram of the stepped trench in the plan view.

[0011] Figure 2B The corners of the stepped trench are shown in detail in the plan view.

[0012] Figure 2C This is a plan view showing the inclined corner portion of the trench.

[0013] Figure 3A This is a plan view showing the bottom gate electrode and gate pad.

[0014] Figure 3B This is a partial perspective view showing the stack of layers for the gate pads.

[0015] Figures 4A to 4M This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor memory device according to an embodiment of the present invention.

[0016] Figures 5A to 5D It is a planar diagram of the photoresist pattern used in thinning and etching processes.

[0017] Figure 6 A stepped groove according to another embodiment of the invention is shown in the plan view.

[0018] Figure 7 This is a plan view illustrating a semiconductor memory device according to another embodiment of the present invention. Detailed Implementation

[0019] Exemplary embodiments of the invention will now be described in more detail with reference to the accompanying drawings. However, the invention may be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Throughout this disclosure, similar reference numerals denote similar parts in the various drawings and embodiments of the invention.

[0020] The accompanying drawings are not necessarily to scale, and in some cases, the scale may be exaggerated to clearly show the features of the embodiments. When the first layer is referred to as being "on" the second layer or the substrate, it indicates not only that the first layer is formed directly on the second layer or the substrate, but also that a third layer exists between the first layer and the second layer or the substrate.

[0021] Embodiments of the present invention relate to a semiconductor memory device with improved reliability and a method for manufacturing the semiconductor memory device.

[0022] Figure 1A It is a schematic layout diagram of a semiconductor memory device shown in a plan view. Figure 1B It is along Figure 1A A detailed cross-sectional view of the section cut by line A-A'. Figure 1C yes Figure 1B A schematic three-dimensional view of the vertical channel structure shown.

[0023] Reference Figures 1A to 1C The semiconductor memory device 100 may include a vertical three-dimensional (3D) NAND. The semiconductor memory device 100 may include a substrate 101, a buffer layer 102 above the substrate 101, an alternating stack 200 above the buffer layer 102, and a stepped trench TA that vertically penetrates the alternating stack 200.

[0024] Substrate 101 may be a material suitable for semiconductor processing. Substrate 101 may include a semiconductor substrate. For example, substrate 101 may include a silicon substrate, a monocrystalline silicon substrate, a polycrystalline silicon substrate, an amorphous silicon substrate, a silicon-germanium substrate, a monocrystalline silicon-germanium substrate, a polycrystalline silicon-germanium substrate, a carbon-doped silicon substrate, combinations thereof, or multiples thereof. Substrate 101 may also include another semiconductor material such as germanium. Substrate 101 may include a group III / V semiconductor substrate, such as a compound semiconductor substrate such as GaAs. Substrate 101 may include a silicon-on-insulator (SOI) substrate. Buffer layer 102 may include a dielectric material such as silicon oxide.

[0025] The alternating stack 200 may include a cell array region MC and a dummy region DA. The cell array region MC may include stepped regions SA and a central region CA between the stepped regions SA. The stepped regions SA may be defined by stepped grooves TA. The stepped grooves TA may include a plurality of grooves T1, T2, T3 and T4. The central region CA may be disposed between the stepped regions SA in a first direction D1, and the stepped grooves TA may extend in a second direction D2.

[0026] The cell array region MC of the alternating stack 200 may include a gate electrode stack, and the gate electrode stack may include a plurality of dielectric layers 202 and a plurality of gate electrodes 201 alternately stacked in a third direction D3. The cell array region MC may be divided into a plurality of cell regions (or cell strings) by a slit 300 extending in a first direction D1. The slit 300 may include a dielectric material, and the two ends of the slit 300 may partially intersect with a stepped trench TA. According to another embodiment of the invention, the two ends of the slit 300 may be divided into stepped trenches TA in the first direction D1.

[0027] In the central region CA of the cell array region MC, multiple dielectric layers 202 and multiple gate electrodes 201 may alternate, and the dielectric layers 202 and gate electrodes 201 may extend from the central region CA to the stepped region SA. In the stepped region SA, the edges of the gate electrodes 201 (i.e., gate pads 201P) may be provided. The gate pads 201P may have a stepped structure in which the gate pads 201P are vertically stacked on a third direction D3.

[0028] The cell array region MC may also include multiple vertical channel structures 203 penetrating the central region CA. (See reference...) Figure 1C The vertical channel structure 203 can penetrate the alternating stack 200 including a gate electrode 201 and a dielectric layer 202. The vertical channel structure 203 may include a vertical channel layer 211, a tunnel dielectric layer 212, a charge trapping layer 213, and a barrier layer 214. A core dielectric layer 215 may be formed within the vertical channel layer 211. The barrier layer 214 may include silicon oxide, a high-k material, or a combination thereof. For example, the barrier layer 214 may include silicon oxide, aluminum oxide, hafnium oxide, zirconium oxide, or a combination thereof. The charge trapping layer 213 may include a charge trapping dielectric material such as silicon nitride. The charge trapping layer 213 may be conformally formed over the barrier layer 214. The tunnel dielectric layer 212 may include silicon oxide. The vertical channel layer 211 may be formed over the tunnel dielectric layer 212. The vertical channel layer 211 may include a semiconductor material. For example, the vertical channel layer 211 may include one of a polycrystalline semiconductor material, an amorphous semiconductor material, and a single-crystal semiconductor material. The channel layer 211 may include silicon (Si), germanium (Ge), silicon-germanium (SiGe), III-V compounds, or II-VI compounds. The channel layer 211 may include polycrystalline silicon. At least one or more other layers, including the core dielectric layer 215, may be further formed over the channel layer 211.

[0029] Contact plugs 500 can land on gate pads 201P disposed in a stepped region SA. Contact plugs 500 can penetrate the interlayer dielectric layer 400 and can be connected to the gate pads 201P of the stepped region SA. The stepped region SA, provided by the stepped trench TA, can have a stepped structure with a gradually increasing length from the uppermost gate pad 201P to the lowermost gate pad 201P. The interlayer dielectric layer 400 can fill the stepped trench TA, and the gate pads 201P of the stepped region SA can be covered by the interlayer dielectric layer 400.

[0030] The gate pad 201P of the stepped region SA can be defined by a stepped trench TA. The width of the stepped trench TA in the first direction D1 can be smaller than its width in the second direction D2.

[0031] The dummy region DA of the alternating stack 200 can be spaced apart from the stepped region SA by a stepped trench TA. In the dummy region DA, dielectric layers OL1 to OL4 and sacrificial layers NL1 to NL4 can be alternately stacked. According to another embodiment of the invention, the sacrificial layers NL1 to NL4 in the dummy region DA can be replaced with the same material as the gate electrode 201 in the central region CA.

[0032] The stepped trench TA may include multiple trenches T1 to T4. The trenches T1 to T4 are integrated stepped trenches TA extending toward the substrate 101 in the depth direction (i.e., the third direction D1). The trenches T1 to T4 may have different widths, and the width of the trenches T1 to T4 may gradually increase from the lowest trench T1 to the highest trench T4. For example, the trenches T1 to T4 may be multi-level trenches having a first trench T1, a second trench T2, a third trench T3, and a fourth trench T4. The second trench T2 may be located at a higher height than the first trench T1, and the third trench T3 may be located at a higher height than the second trench T2. The fourth trench T4 may be located at a higher height than the third trench T3. The lowest first trench T1 may have the smallest width, and the highest fourth trench T4 may have the largest width.

[0033] Figure 2A This is a detailed diagram of the stepped trench in the plan view. Figure 2B The corners of the stepped trench are shown in detail in the plan view. Figure 2A and Figure 2B For the sake of convenience, the slit 300 will be omitted.

[0034] The stepped trenches T1 to T4 of the stepped trench TA may provide multiple stepped sidewalls ST1, ST2, ST3, and ST4. The stepped sidewalls ST1, ST2, ST3, and ST4 may include multiple steps that move downwards toward the substrate 101. The stepped sidewalls ST1, ST2, ST3, and ST4 may be interconnected. The first stepped sidewall ST1 and the second stepped sidewall ST2 may face each other in a first direction D1, and the third stepped sidewall ST3 and the fourth stepped sidewall ST4 may face each other in a second direction D2. The second stepped sidewall ST2 may be divided by a slit 300.

[0035] The first trapezoidal sidewall ST1 and the second trapezoidal sidewall ST2 may have asymmetrical slopes. The steps of the first trapezoidal sidewall ST1 may descend at a steeper slope than the steps of the second trapezoidal sidewall ST2. The steps of the second trapezoidal sidewall ST2 may descend at a gentler slope than the steps of the first trapezoidal sidewall ST1. The area occupied by the second trapezoidal sidewall ST2 may be larger than the area occupied by the first trapezoidal sidewall ST1.

[0036] The third trapezoidal sidewall ST3 and the fourth trapezoidal sidewall ST4 may have asymmetrical slopes. The steps of the third trapezoidal sidewall ST3 and the fourth trapezoidal sidewall ST4 may descend with a steeper slope. The first trapezoidal sidewall ST1, the third trapezoidal sidewall ST3, and the fourth trapezoidal sidewall ST4 may have the same slope. The steps of the second trapezoidal sidewall ST2 may have a larger surface area than the steps of the first trapezoidal sidewall ST1, the third trapezoidal sidewall ST3, and the fourth trapezoidal sidewall ST4.

[0037] The first trapezoidal sidewall ST1, the second trapezoidal sidewall ST2, the third trapezoidal sidewall ST3, and the fourth trapezoidal sidewall ST4 can be connected to each other to form a curved trapezoidal sidewall. The connecting portion of the first trapezoidal sidewall ST1, the second trapezoidal sidewall ST2, the third trapezoidal sidewall ST3, and the fourth trapezoidal sidewall ST4 can be bent to have an angle.

[0038] A stack of bent-step BS1 to BS4 can be obtained by stacking gate pads 201P on third-direction D3 with bent-step sidewalls.

[0039] The stepped trench TA may include four inclined sidewalls AC1, AC2, AC3, and AC4. For example, as... Figure 2BAs shown, the inclined sidewall AC3 of the stepped groove TA may include multiple inclined corner portions CR1, CR2, CR3, and CR4. Like the inclined sidewall AC3, each of the remaining inclined sidewalls AC1, AC2, and AC4 may also include inclined corner portions CR1, CR2, CR3, and CR4. The inclined corner portions CR1, CR2, CR3, and CR4 may include inclined corners, but they may have non-curved shapes. The inclined corner portions CR1, CR2, CR3, and CR4 may not be right angles.

[0040] The first trench T1 may include a first inclined corner portion CR1, and the second trench T2 may include a second inclined corner portion CR2. The third trench T3 may include a third inclined corner portion CR3, and the fourth trench T4 may include a fourth inclined corner portion CR4. The inclined corner portions CR1, CR2, CR3, and CR4 may not overlap each other in the depth direction of the stepped trench TA.

[0041] Trenches T1, T2, T3, and T4 may have inclined corner portions CR1, CR2, CR3, and CR4 of different sizes. For example, inclined corner portions CR1, CR2, CR3, and CR4 may have different lengths, but the length may gradually decrease from the uppermost fourth trench T4 (inclined corner portion CR4) to the lowermost first trench T1 (inclined corner portion CR1). Since the uppermost inclined corner portion CR4 has a larger length, seam formation can be further prevented in the interlayer dielectric layer 400. Each of the inclined corner portions CR1, CR2, CR3, and CR4 may have an obtuse angle or an acute angle. According to an embodiment of the invention, inclined corner portions CR1, CR2, CR3, and CR4 may have an obtuse angle.

[0042] The following section will describe the inclined corner section CR1 in detail, taking the first groove T1 as an example.

[0043] Figure 2C This is a plan view showing the inclined corner portion of the trench, and the inclined corner portion CR1 of the first trench T1 is used as an example for description.

[0044] Reference Figure 2C The first trench T1 may include multiple inclined corner portions CR1, and the interior of the first trench T1 may be filled with an interlayer dielectric layer 400. The inclined corner portions CR1 may be provided by multiple edges S1 to S5. The first edge S1 and the second edge S2 may contact at a first angle α1, the second edge S2 and the third edge S3 may contact at a second angle α2, the third edge S3 and the fourth edge S4 may contact at a third angle α3, and the fourth edge S4 and the fifth edge S5 may contact at a fourth angle α4. All of the first angles α1 to the fourth angle α4 may be obtuse angles, and they may be the same angle. According to another embodiment of the invention, the first angles α1 to the fourth angle α4 may be different obtuse angles.

[0045] A first inclined angle P1 with a first angle α1 can be formed between the first side S1 and the second side S2, and a second inclined angle P2 with a second angle α2 can be formed between the second side S2 and the third side S3. A third inclined angle P3 with a third angle α1 can be formed between the third side S3 and the fourth side S4, and a fourth inclined angle P4 with a fourth angle α4 can be formed between the fourth side S4 and the fifth side S5.

[0046] As described above, the inclined corner portion CR1 of the first groove T1 may include a plurality of inclined corners P1 to P4 with obtuse angles.

[0047] Figure 3A This is a plan view showing the lowermost gate electrode and gate pad, and the lowermost gate electrode 201 may include a gate pad 201P. The size of the gate pad 201P may be defined by the distance between the first trench T1 and the second trench T2. The gate pad 201P may correspond to... Figure 2A The curved staircase BS1 is shown.

[0048] The sidewalls of the gate pad 201P may include multiple edges S11 to S15 of the interlayer dielectric layer 400. The first edge S11 and the second edge S12 may contact at a first angle α11, the second edge S12 and the third edge S13 may contact at a second angle α12, the third edge S13 and the fourth edge S14 may contact at a third angle α13, and the fourth edge S14 and the fifth edge S15 may contact at a fourth angle α14. All angles α11 to α14 may be obtuse angles, and they may be the same angle. According to another embodiment of the invention, the first angle α11 to α14 may be different obtuse angles.

[0049] A first inclined angle P11 with a first angle α11 can be formed between the first side S11 and the second side S12, and a second inclined angle P12 with a second angle α12 can be formed between the second side S12 and the third side S13. A third inclined angle P13 with a third angle α11 can be formed between the third side S13 and the fourth side S14, and a fourth inclined angle P14 with a fourth angle α14 can be formed between the fourth side S14 and the fifth side S15.

[0050] As described above, the sidewall of the gate pad 201P may include inclined corners P11 to P14 with multiple obtuse angles. The inclined corners P11 to P14 of the gate pad 201P may be defined by the inclined corners P1 to P4 of the first trench T1. (Return to Reference) Figure 2C and Figure 3AThe first angle α1 to the fourth angle α4 of the tilting corners P1 to P4 of the first trench T1 can be the same as the first angle α11 to the fourth angle α14 of the tilting corners P11 to P14 of the gate pad 201P.

[0051] Figure 3B This is a partial perspective view showing the stack of layers for the gate pads. (Refer to...) Figure 3B Each gate pad 201P may be a curved step, and the sidewall of the gate pad 201P may include inclined corner portions CR1 to CR4. The inclined corner portions CR1 to CR4 may have different lengths. For example, the length may gradually decrease from the uppermost gate pad 201P (inclined corner portion CR4) to the lowermost gate pad 201P (inclined corner portion CR1).

[0052] As described above, in this embodiment, the inclined sidewalls AC1, AC2, AC3, and AC4 of the stepped trench TA defining the stepped region SA can be formed as inclined. Therefore, each of the inclined sidewalls AC1, AC2, AC3, and AC4 of the stepped trench TA can have inclined corner portions CR1, CR2, CR3, and CR4. The inclined corner portions CR1, CR2, CR3, and CR4 can be obtained by changing the shape of the openings of the photoresist pattern during the thinning process. The openings of the photoresist pattern will be discussed later. Figures 5A to 5D describe.

[0053] When the interlayer dielectric layer 400 is deposited through the inclined corners CR1, CR2, CR3 and CR4 of the stepped trench TA, the formation of seams can be suppressed. In addition, since the size gradually decreases from the uppermost inclined corner portion CR4 to the lowermost inclined corner portion CR1, the formation of seams in the interlayer dielectric layer 400 can be further suppressed.

[0054] Figures 4A to 4M This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor memory device according to an embodiment of the present invention. Figures 5A to 5D It is a planar diagram of the photoresist pattern used in thinning and etching processes. Figures 4A to 4M By presenting along Figure 1A The manufacturing method is illustrated by the cross-section taken by line A-A'.

[0055] like Figure 4A As shown, a buffer layer 102 can be formed above the substrate 101, and an alternating layer 110 can be formed above the buffer layer 102.

[0056] Substrate 101 may include a central region CA, a stepped region SA, and a dummy region DA. Substrate 101 may have a material suitable for semiconductor processing. Substrate 101 may include a semiconductor substrate. For example, substrate 101 may include a silicon substrate, a monocrystalline silicon substrate, a polycrystalline silicon substrate, an amorphous silicon substrate, a silicon-germanium substrate, a monocrystalline silicon-germanium substrate, a polycrystalline silicon-germanium substrate, a carbon-doped silicon substrate, a combination thereof, or a multilayer thereof. Substrate 101 may also include another semiconductor material such as germanium. Substrate 101 may include a group III / V semiconductor substrate, such as a compound semiconductor substrate such as GaAs. Substrate 101 may include a silicon-on-insulator (SOI) substrate. Although not shown, peripheral circuitry may be formed between substrate 101 and alternating layers 110. Peripheral circuitry may be formed using known methods, such as those for forming semiconductor circuits. After the peripheral circuitry is formed, alternating layers 110 may be formed. Buffer layer 102 may include a dielectric material or an etch-stop material. Buffer layer 102 may include silicon oxide.

[0057] The alternating laminate 110 can be a laminate, and a first material layer and a second material layer can be stacked alternately. The first material layer may include a first material, and the second material layer may include a second material. The first material and the second material may be different materials. The first material layer may include sacrificial layers NL1 to NL4, and the second material layer may include dielectric layers OL1 to OL4. The dielectric layers OL1 to OL4 may include a dielectric material, and the sacrificial layers NL1 to NL4 may include a sacrificial material. Here, "sacrificial material" may refer to a material that is removed in a subsequent process. In the alternating laminate 110, the sacrificial layers NL1 to NL4 and the dielectric layers OL1 to OL4 can be stacked alternately.

[0058] The dielectric layers OL1 to OL4 may include at least one dielectric material selected from silicon oxide, silicon nitride, silicon oxynitride, spin-on dielectric material (SOD), dielectric metal oxide, silicate, and dielectric metal oxynitride.

[0059] The sacrificial layers NL1 to NL4 may include sacrificial materials that can be selectively removed. The ratio of the removal rate of the sacrificial layers NL1 to NL4 to the removal rate of the dielectric layers OL1 to OL4 may be referred to as the selectivity of the removal process of the sacrificial layers NL1 to NL4 relative to the dielectric layers OL1 to OL4.

[0060] Sacrificial layers NL1 to NL14 may include a sacrificial material. Sacrificial layers NL1 to NL4 may be replaced with a conductive material in subsequent processes. For example, they may be replaced with the gate electrode of a vertical NAND device. Sacrificial layers NL1 to NL4 may include silicon nitride, amorphous silicon, or polycrystalline silicon. According to some embodiments of the invention, sacrificial layers NL1 to NL4 may include silicon nitride.

[0061] According to embodiments of the present invention, dielectric layers OL1 to OL4 may comprise silicon oxide, and sacrificial layers NL1 to NL4 may comprise silicon nitride. In the alternating stack 110, the stack of silicon nitride and silicon oxide (i.e., the NO stack) may be repeatedly stacked multiple times. When the buffer layer 102 comprises silicon oxide, the buffer layer 102 and the alternating stack 110 may be referred to as the ON stack.

[0062] In the alternating stack 110, the number of times the sacrificial layers NL1 to NL4 and the dielectric layers OL1 to OL4 are alternately stacked can be determined according to the number of memory cells. For example, when there are 48 vertically stacked memory cells, the sacrificial layers NL1 to NL4 and the dielectric layers OL1 to OL4 can be stacked individually 48 times. The sacrificial layers NL1 to NL4 and the dielectric layers OL1 to OL4 can be repeatedly stacked in a direction perpendicular to the surface of the substrate 101.

[0063] The dielectric layers OL1 to OL4 can be deposited using either chemical vapor deposition (CVD) or atomic layer deposition (ALD). The sacrificial layers NL1 to NL4 can also be deposited using either CVD or ALD.

[0064] Dielectric layers OL1 to OL4 and sacrificial layers NL1 to NL4 may have the same thickness. The top dielectric layer OL4 may be thicker than the other dielectric layers OL1 to OL3. The top dielectric layer OL4 may be referred to as the dielectric capping layer.

[0065] Reference Figure 4B and Figure 5A A photoresist pattern 130A can be formed above the uppermost dielectric layer OL4. The photoresist pattern 130A may have a first opening 131. The photoresist pattern 130A can be used to etch the uppermost dielectric layer OL4 and the sacrificial layer NL4. As a result, the first opening 131 of the photoresist pattern 130A is replicated into a first trench T1. The dielectric layer OL3 below the first trench T1 can be exposed. Figure 5A From the angle of the planar view, the corners of the first opening 131 and the first trench T1 of the photoresist pattern 130A may have an inclined shape CR1. The inclined corners of the first opening 131 and the first trench T1 may be abbreviated as the first inclined corner portion CR1. The first inclined corner portion CR1 may include a plurality of inclined corners with obtuse angles.

[0066] Reference Figure 4C and Figure 5BPhotoresist pattern 130B can be formed by thinning photoresist pattern 130A. Oxygen plasma can be used to thin photoresist pattern 130A. Photoresist pattern 130B may have a second opening 132. The uppermost dielectric layer OL4 and sacrificial layer NL4 can be exposed again through photoresist pattern 130B. In this case, for example, the amount of thinning of photoresist pattern 130B may be the same as the width of one of the steps in the steps to be formed later. Figure 5B The second opening 132 of the photoresist pattern 130B may include a second inclined corner portion CR2, depending on the angle of the plan view.

[0067] Reference Figure 4D and Figure 5B The uppermost dielectric layer OL4 and the sacrificial layer NL4 can be etched using a photoresist pattern 130B. As a result, a second opening 132 of the photoresist pattern 130B can be replicated into a second trench T2.

[0068] When etching the top dielectric layer OL4 and the sacrificial layer NL4, the dielectric layer OL3 and the sacrificial layer NL3 can be etched. Therefore, Figure 4C The first trench T1 shown can be replicated to the dielectric layer OL3 and the sacrificial layer NL3.

[0069] The corners of the second opening 132 of the photoresist pattern 130B and the second trench T2 may include an inclined corner portion CR2. The corner of the first trench T1 may include a first inclined corner portion CR1.

[0070] Reference Figure 4E and Figure 5C Photoresist pattern 130C can be formed by thinning photoresist pattern 130B. Oxygen plasma can be used to thin photoresist pattern 130C. Photoresist pattern 130C may have a third opening 133. The uppermost dielectric layer OL4 and sacrificial layer NL4 can be exposed again through photoresist pattern 130C. In this case, for example, the amount of thinning of photoresist pattern 130C may be the same as the width of one of the steps in the subsequently formed staircase. Figure 5C The angle of the plan view, the third opening 133 of the photoresist pattern 130C may include an inclined corner portion CR3.

[0071] Reference Figure 4F and Figure 5C The uppermost dielectric layer OL4 and the sacrificial layer NL4 can be etched through the photoresist pattern 130C. As a result, the third opening 133 of the photoresist pattern 130C can be replicated into the third trench T3.

[0072] When etching the topmost dielectric layer OL4 and the sacrificial layer NL4, the dielectric layer OL3 and the sacrificial layer NL3 can also be etched. Therefore, Figure 4DThe second trench T2 shown can be replicated to the dielectric layer OL3 and the sacrificial layer NL3.

[0073] When etching the topmost dielectric layer OL4 and the sacrificial layer NL4, the dielectric layer OL2 and the sacrificial layer NL2 can also be etched. Therefore, Figure 4D The first trench T1 shown can be replicated to the dielectric layer OL2 and the sacrificial layer NL2.

[0074] The corners of the third opening 133 of the photoresist pattern 130C and the corners of the third trench T3 may include an inclined corner portion CR3. The corners of the first trench T1 may include an inclined corner portion CR1, and the corners of the second trench T2 may include an inclined corner portion CR2.

[0075] Reference Figure 4G and Figure 5D Photoresist pattern 130D can be formed by thinning photoresist pattern 130C. Oxygen plasma can be used to thin photoresist pattern 130D. Photoresist pattern 130D may have a fourth opening 134. The uppermost dielectric layer OL4 and sacrificial layer NL4 can be exposed again through photoresist pattern 130D. In this case, for example, the amount of thinning of photoresist pattern 130D is the same as the width of any step in the subsequently formed stepped portion. Figure 5D The angle of the plan view, the fourth opening 134 of the photoresist pattern 130D may include a slanted corner portion CR4.

[0076] Reference Figure 4H and Figure 5D The uppermost dielectric layer OL4 and the sacrificial layer NL4 can be etched using a photoresist pattern 130D. As a result, the fourth opening 134 of the photoresist pattern 130D is replicated into the fourth trench T4.

[0077] When etching the top dielectric layer OL4 and the sacrificial layer NL4, the dielectric layer OL3 and the sacrificial layer NL3 can also be etched. Therefore, Figure 4F The third trench T3 shown can be replicated to the dielectric layer OL3 and the sacrificial layer NL3.

[0078] When etching the top dielectric layer OL4 and the sacrificial layer NL4, the dielectric layer OL2 and the sacrificial layer NL2 can also be etched. Therefore, Figure 4F The second trench T2 shown can be replicated to the dielectric layer OL2 and the sacrificial layer NL2.

[0079] When etching the topmost dielectric layer OL4 and the sacrificial layer NL4, the dielectric layer OL1 and the sacrificial layer NL1 can also be etched. Therefore, Figure 4F The first trench T1 shown can be replicated to the dielectric layer OL1 and the sacrificial layer NL1.

[0080] The corners of the fourth opening 134 and the fourth trench T4 of the photoresist pattern 130D may include inclined corner portions CR4. The corners of the first trench T1, the second trench T2, and the third trench T3 may respectively include inclined corner portions CR1, CR2, and CR3.

[0081] As shown above (refer to the reference) Figures 4B to 4H As described, stepped trenches TA can be formed by repeatedly performing thinning and etching processes. The stepped trenches TA can penetrate alternating layers 110. The stepped trenches TA may include a first stepped sidewall ST1 and a second stepped sidewall ST2 formed by multiple steps, and the first stepped sidewall ST1 and the second stepped sidewall ST2 may include multiple steps descending toward the substrate 10. Figure 2A As shown, the stepped groove TA may also include a third sidewall and a fourth sidewall.

[0082] A stepped groove TA can be formed in a stepped region SA, and the stepped region SA and the dummy region DA can be separated by the stepped groove TA. The slopes of the first stepped sidewall ST1 and the second stepped sidewall ST2 can be asymmetrical. The first stepped sidewall ST1 and the second stepped sidewall ST2 can have facing shapes and can have different stepped slopes. The steps of the first stepped sidewall ST1 can descend at a steeper slope than the steps of the second stepped sidewall ST2. The steps of the second stepped sidewall ST2 can descend at a gentler slope than the steps of the first stepped sidewall ST1. The area occupied by the second stepped sidewall ST2 can be larger than the area occupied by the first stepped sidewall ST1.

[0083] The first stepped sidewall ST1 and the second stepped sidewall ST2 can be connected to each other to form an integrated curved stepped sidewall. The integrated curved stepped sidewall can be provided by multiple curved steps BS1 to BS4.

[0084] The stepped groove TA may include multiple grooves T1, T2, T3, and T4, and grooves T1, T2, T3, and T4 may each include inclined corner portions CR1 to CR4. Grooves T1, T2, T3, and T4 may include a first groove T1, a second groove T2, a third groove T3, and a fourth groove T4. The second groove T2 may be located at a higher height than the first groove T1, the third groove T3 may be located at a higher height than the second groove T2, and the fourth groove T4 may be located at a higher height than the third groove T3. The width may gradually increase as one moves from the first groove T1 to the fourth groove T4. The first groove T1 may have a minimum width, and the fourth groove T4 may have a maximum width. The first groove T1 may define a first curved step BS1, the second groove T2 may define a second curved step BS2, the third groove T3 may define a third curved step BS3, and the fourth groove T4 may define a fourth curved step BS4. The inclined corner portions CR1 to CR4 of grooves T1, T2, T3 and T4 can be referred to as the inclined corner portions CR1 to CR4 of curved steps BS1 to BS4.

[0085] From a plan view perspective, the corners of trenches T1 to T4 may have angled corners CR1 to CR4. The angled corner portions CR1 to CR4 of trenches T1 to T4 can be formed by replicating the angled corner portions CR1 to CR4 of photoresist patterns 130A to 130D. The angled corner portions CR1 to CR4 of trenches T1 to T4 may include multiple obtuse angles.

[0086] The dimension of the inclined corner portion CR1 of the first groove T1 can be smaller than the dimension of the inclined corner portion CR2 of the second groove T2. The dimension of the inclined corner portion CR4 of the fourth groove T4 can be larger than the dimension of the inclined corner portion CR3 of the third groove T3. The dimension of the inclined corner portion CR3 of the third groove T3 can be larger than the dimension of the inclined corner portion CR2 of the second groove T2. Thus, the dimensions of the inclined corner portions CR1 to CR4 of grooves T1 to T4 can gradually increase along the stacking direction (i.e., the vertical direction) of the alternating laminate 110. Here, the dimensions of the inclined corner portions CR1 to CR4 can refer to their length. The length of the inclined corner portion CR4 of the fourth groove T4 can be greater than the length of the inclined corner portion CR3 of the third groove T3. The length of the inclined corner portion CR3 of the third groove T3 can be greater than the length of the inclined corner portion CR2 of the second groove T2. The length of the inclined corner portion CR2 of the second groove T2 can be greater than the length of the inclined corner portion CR1 of the first groove T1.

[0087] Reference Figure 4IAfter removing the photoresist pattern 130D, an interlayer dielectric layer 140 filling the stepped trench TA can be formed. The interlayer dielectric layer 140 may include silicon oxide. The formation of seams can be suppressed while forming the interlayer dielectric layer 140 through the inclined corner portions CR1 to CR4 of the trenches T1 to T4. Due to the inclined corner portions CR1 to CR4 of the trenches T1 to T4, the interlayer dielectric layer 140 may be seam-free.

[0088] As a comparative example, when the openings 131 to 134 of the photoresist patterns 130A to 130D and the corners of the trenches T1 to T4 have right angles or curved shapes, seams can be formed during the formation of the interlayer dielectric layer 140.

[0089] Reference Figure 4J The interlayer dielectric layer 140 can be planarized using a planarization process such as chemical mechanical polishing (CMP). The upper surface of the planarized interlayer dielectric layer 400 can be located at the same height as the upper surface of the uppermost dielectric layer OL4.

[0090] Reference Figure 4K Multiple vertical channel structures 203 can be formed penetrating the alternating laminates 110. The vertical channel structures 203 can extend vertically from the surface of the substrate 101. The vertical channel structures 203 can penetrate dielectric layers OL1 to OL4 and sacrificial layers NL1 to NL4, and can extend in the stacking direction of the dielectric layers OL1 to OL4 and the sacrificial layers NL1 to NL4. For a detailed description of the vertical channel structures 203, please refer to... Figures 1A to 1C The vertical channel structure 203 shown.

[0091] Subsequently, referring to Figure 4L and Figure 4M It can perform a process that replaces the sacrificial layers NL1 to NL4 with the gate electrode 201.

[0092] Reference Figure 4L Lateral recesses 150 can be formed by selectively removing some sacrificial layers NL1 to NL4 in the central region CA of the alternating stack 110. Lateral recesses 150 can be formed in the central region CA and the stepped region SA of the alternating stack 110. Lateral recesses 150 can extend laterally from the central region CA to the stepped region SA. Lateral recesses 150 can partially expose the sidewalls of the vertical trench structure 203. Although not shown, to form lateral recesses 150, a portion of the alternating stack 110 can be etched to form a vertical trench (not shown), and some sacrificial layers NL1 to NL4 can be removed through the vertical trench. Here, a vertical trench can refer to the trench to be formed. Figure 1A The space of the slit 300. In order to form the slit 300, a gate electrode 201 can be formed, and then a vertical trench can be filled with a dielectric material.

[0093] Reference Figure 4M A gate electrode 201 can be formed to fill the lateral recess 150. To form the gate electrode 201, a deposition can fill the lateral recess (see...). Figure 4L The conductive material (150) is then selectively etched. The gate electrode 201 may include polysilicon, metal, metal nitride, metal silicide, or a combination thereof. The gate electrode 201 may include titanium nitride, tungsten, or a stack of titanium nitride and tungsten.

[0094] The gate electrode 201 can extend from the central region CA to the stepped region SA. The edge of the gate electrode 201 located in the stepped region SA can serve as a gate pad (see [reference]). Figure 1A (201P in the middle).

[0095] An alternating stack of gate electrode 201 and dielectric layers OL1 to OL4 can be formed in the central region CA. Additionally, an alternating stack of residual sacrificial layers NL1 to NL4 and dielectric layers OL1 to OL4 can be formed in the dummy region DA.

[0096] According to another embodiment of the present invention, an alternating stack of gate electrode 201 and dielectric layers OL1 to OL4 may also be formed in the dummy region DA. In this case, Figure 4L The lateral recess 150 can also be formed in the dummy region DA, and the lateral recess 150 formed in the dummy region DA can be filled by the gate electrode 201. The gate electrode 201 formed in the dummy region DA can be referred to as the dummy gate electrode.

[0097] Subsequently, as Figure 1A and Figure 1B As shown, contact plugs 500 can be formed to be connected to the gate pads 201P of the gate electrode 201, respectively. The contact plugs 500 can penetrate the interlayer dielectric layer 400 and dielectric layers OL1 to OL4 to be connected to the gate pads 201P of the gate electrode 201, respectively.

[0098] Figure 6 A stepped groove according to another embodiment of the invention is shown in the plan view. Figure 6 The stepped groove TA' is Figure 4H and Figure 5D The example shown is a modified version of the stepped groove TA.

[0099] Reference Figure 6The stepped groove TA' penetrating the alternating layers 110 may include multiple grooves T1', T2', T3', and T4', and each of the grooves T1', T2', T3', and T4' may include concave corner portions CR1' to CR4'. The grooves T1', T2', T3', and T4' may include a first groove T1', a second groove T2', a third groove T3', and a fourth groove T4'. The second groove T2' may be located at a higher height than the first groove T1', the third groove T3' may be located at a higher height than the second groove T2', and the fourth groove T4' may be located at a higher height than the third groove T3'. The first groove T1' may have a minimum width, and the fourth groove T4' may have a maximum width.

[0100] The concave corner portions CR1' to CR4' can refer to acute corners. The size of the inclined corner portion CR1' of the first groove T1' can be smaller than the size of the inclined corner portion CR2' of the second groove T2'. The size of the inclined corner portion CR4' of the fourth groove T4' can be larger than the size of the inclined corner portion CR3' of the third groove T3'. The size of the inclined corner portion CR3' of the third groove T3' can be larger than the size of the inclined corner portion CR2' of the second groove T2'.

[0101] As described above, the dimensions of the inclined corner portions CR1' to CR4' of trenches T1' to T4' can gradually increase along the stacking direction of the alternating laminates 110. The radius of curvature of the inclined corner portion CR4' of the fourth trench T4' can be greater than the radius of curvature of the inclined corner portion CR3' of the third trench T3'. The radius of curvature of the inclined corner portion CR3' of the third trench T3' can be greater than the radius of curvature of the inclined corner portion CR2' of the second trench T2'. The radius of curvature of the inclined corner portion CR2' of the second trench T2' can be greater than the radius of curvature of the inclined corner portion CR1' of the first trench T1'. The acute corner portions CR1' to CR4' may include a recess and cusps defined at both ends of the recess. The acute corner portions CR1' to CR4' may differ from a curved shape, and there may be limitations on suppressing the formation of seams in the interlayer dielectric layer by bending the corners.

[0102] To form the inclined corner portions CR1' to CR4' of the trenches T1' to T4', as follows Figures 5A to 5D The openings 131 to 134 of the photoresist patterns 130A to 130D can be formed to have concave corner portions.

[0103] As described above, the inclined corner portions CR1' to CR4' of grooves T1' to T4' can suppress [the following conditions]. Figure 4I The formation of seams during the deposition process of the interlayer dielectric layer 140 shown.

[0104] According to the above embodiment, since the stepped trenches TA and TA' are formed with inclined corner portions CR1 to CR4 and CR1' to CR4', the formation of seams in the interlayer dielectric layer 140 can be suppressed. Since the interlayer dielectric layer 140 is formed without any seams, the stepped trenches TA and TA' can prevent cracks in the inclined corner portions CR1 to CR4 and CR1' to CR4'.

[0105] The sloping corner portions CR1 to CR4 and CR1' and CR4' of the stepped trenches TA and TA' can be applied to three-dimensional (3D) NAND. Despite the increased number of layers in the memory cell, cracks that could be caused by seams in the interlayer dielectric layer are prevented at the corners of the stepped region.

[0106] Figure 7 This is a plan view illustrating a semiconductor memory device 100M according to another embodiment of the present invention.

[0107] Reference Figure 7 The semiconductor memory device 100M may include a first gate electrode stack MB1 and a second gate electrode stack MB2. The first gate electrode stack MB1 and the second gate electrode stack MB2 may be spaced apart from each other by a slit SL. Each of the first gate electrode stack MB1 and the second gate electrode stack MB2 may include a first cell region MC1, a second cell region MC2, and a stepped region SA between the first cell region MC1 and the second cell region MC2. According to an embodiment of the invention, a case with one stepped region SA is shown. However, according to another embodiment of the invention, the stepped region SA may be divided into two or more regions arranged in a row along a first direction D1. The first gate electrode stack MB1 may be formed in a first memory block, and the second gate electrode stack MB2 may be formed in a second memory block. The first gate electrode stack MB1 and the second gate electrode stack MB2 may face each other in a second direction D2 and have a slit SL between them.

[0108] Each of the first gate electrode stack MB1 and the second gate electrode stack MB2 can correspond to Figure 1A The alternating stacks 200. Therefore, each of the first gate electrode stack MB1 and the second gate electrode stack MB2 may include a stack of gate electrode 201. The vertical channel structure 203 can penetrate the first gate electrode stack MB1 and the second gate electrode stack MB2.

[0109] Each of the first gate electrode stack MB1 and the second gate electrode stack MB2 may include vertically stacked gate pads 201P. The gate pads 201P of the first gate electrode stack MB1 and the second gate electrode stack MB2 may have the same size. The gate pads 201P may be located in a stepped region SA, and the gate pads 201P may be formed to have a stepped structure via stepped trenches TA. The gate pads 201P may have a "∩" shaped planar structure, and each gate pad 201P may include a sloped sidewall AC. The sloped sidewall AC may include an obtuse angle corner. According to another embodiment of the invention, the sloped sidewall AC may include an acute angle corner.

[0110] Contact plugs 500 can be connected to gate pads 201P respectively.

[0111] According to an embodiment of the present invention, seams in the interlayer dielectric layer filling the stepped trench can be prevented by forming the stepped trench with inclined corners.

[0112] According to an embodiment of the present invention, since the gate pad includes an inclined corner, a seamless interlayer dielectric layer can be formed.

[0113] According to an embodiment of the present invention, the reliability of vertical NAND can be improved.

[0114] Although the invention has been described with respect to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.

[0115] Cross-references to related applications

[0116] This application claims priority to Korean Patent Application No. 10-2021-0016744, filed on February 5, 2021, the entirety of which is incorporated herein by reference.

Claims

1. A semiconductor memory device, the semiconductor memory device comprising: A gate electrode stack, which is vertically stacked above a substrate and has a bent gate pad, the bent gate pad having a stepped structure; An interlayer dielectric layer covering the bent gate pad; and Multiple contact plugs are connected to the curved gate pads by penetrating the interlayer dielectric layer. In the plan view, the curved gate pad includes inclined corner portions of different sizes; in the cross-sectional view, the size of the inclined corner portions gradually varies based on the depth of the curved gate pad. Each of the inclined corner portions includes multiple inclined corners, each with an obtuse angle, or Each of the inclined corner portions includes multiple inclined corners, each with an acute angle, and In particular, due to the inclined corner portion, the interlayer dielectric layer is seamless.

2. The semiconductor memory device according to claim 1, wherein, The inclined corner portions of the bent gate pads have different lengths, and The length of the inclined corner portion gradually decreases from the uppermost curved gate pad to the lowermost curved gate pad.

3. The semiconductor memory device according to claim 1, wherein, The inclined corner portions of the curved gate pad do not overlap with each other in the stacking direction of the curved gate pad.

4. The semiconductor memory device according to claim 1, further comprising: Multiple vertical channel structures penetrate the gate electrode stack.

5. A semiconductor memory device, the semiconductor memory device comprising: substrate; A laminate in which multiple dielectric layers and multiple conductive layers are alternately stacked in a direction perpendicular to the surface of the substrate; A stepped trench penetrating the laminate, the stepped trench including a plurality of trenches extending perpendicularly toward the substrate; as well as An interlayer dielectric layer that fills the stepped trenches. In the plan view, the plurality of trenches include inclined corner sections of different sizes; in the cross-sectional view, the dimensions of the inclined corner sections vary progressively based on the depth of the plurality of trenches. Each of the inclined corner portions includes multiple inclined corners, each with an obtuse angle, or Each of the inclined corner portions includes multiple inclined corners, each with an acute angle, and In particular, due to the inclined corner portion, the interlayer dielectric layer is seamless.

6. The semiconductor memory device according to claim 5, wherein, The inclined corner portions of the trench have different lengths, and The length of the inclined corner portion gradually decreases from the uppermost groove to the lowermost groove.

7. The semiconductor memory device according to claim 5, wherein, The inclined corner portions of the trench do not overlap with each other in the depth direction of the trench.

8. The semiconductor memory device according to claim 5, wherein, Each of the conductive layers includes a curved step exposed through the stepped trench, and In the plan view, the curved steps have inclined corners that correspond to the inclined corner portions of the stepped grooves.

9. The semiconductor memory device of claim 8, further comprising: Multiple vertical channel structures, wherein the multiple vertical channel structures penetrate the conductive layer; as well as Multiple contact plugs are connected to the curved step by penetrating the interlayer dielectric layer.

10. A method for manufacturing a semiconductor memory device, the method comprising the following steps: A stack of multiple sacrificial layers and multiple dielectric layers is formed alternately on top of a substrate; A stepped groove is formed that penetrates the stacked material. The stepped groove includes multiple grooves. In a plan view, the multiple grooves have inclined corner portions of different sizes. In a cross-sectional view, the size of the inclined corner portions varies progressively based on the depth of the multiple grooves. An interlayer dielectric layer is formed to fill the stepped trenches; as well as Replace the sacrificial layer with a conductive layer. Each of the inclined corner portions includes multiple inclined corners, each with an obtuse angle, or Each of the aforementioned inclined corner portions includes multiple inclined corners, each with an acute angle. In particular, due to the inclined corner portion, the interlayer dielectric layer is seamless.

11. The method according to claim 10, wherein, The steps for forming the stepped groove include the following steps: A photoresist pattern including openings with angled corner portions is formed over the laminate; and The etching process of the laminated material that reuses the photoresist pattern and the thinning process of the photoresist pattern.

12. The method according to claim 11, wherein, The oblique corner portion of the opening in the photoresist pattern has the obtuse angle or the acute angle.

13. The method according to claim 10, wherein, The inclined corner portions of the trench have different lengths, and The length of the inclined corner portion gradually decreases from the uppermost groove to the lowermost groove.

14. The method of claim 10, wherein, The inclined corner portions of the trench do not overlap with each other in the depth direction of the trench.

15. The method according to claim 10, wherein, The step of replacing the sacrificial layer with the conductive layer includes the following steps: Lateral recesses are formed between the dielectric layers by selectively removing the sacrificial layer; and A gate electrode is formed to fill the lateral recess. Each of the gate electrodes includes a gate pad having an inclined corner portion corresponding to the inclined corner portion of the stepped trench.

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