Germanium-based sensor with junction gate field effect transistor and method of manufacturing the same

Abstract

Disclosed herein are germanium-based sensors having junction gate field effect transistors and methods of manufacturing the same. Disclosed herein are germanium-based sensors. An exemplary germanium-based sensor includes a germanium photodiode and a junction field effect transistor (JFET) formed from a germanium layer, which in some embodiments is disposed in a silicon substrate or in some embodiments is disposed on a silicon substrate. A doped silicon layer is disposed between the germanium layer and the silicon substrate, which can be formed by in-situ doping of epitaxially grown silicon. In embodiments where the germanium layer is on a silicon substrate, the doped silicon layer is disposed between the germanium layer and an oxide layer. The JFET has a doped polysilicon gate, and in some embodiments a gate diffusion region is disposed in the germanium layer and under the doped polysilicon gate.

Description

Technical Field

[0001] This disclosure relates to the semiconductor field, and more specifically, to a germanium-based sensor having a junction-gate field-effect transistor and a method for manufacturing the same. Background Technology

[0002] The electronics industry's demand for smaller, faster electronic devices that can simultaneously support a greater number of increasingly complex and sophisticated functions is constantly growing. Therefore, in the semiconductor industry, manufacturing low-cost, high-performance, and low-power integrated circuits (ICs) is an ongoing trend. To date, these goals have been largely achieved by shrinking the size of semiconductor ICs (e.g., minimizing feature size), thereby increasing production efficiency and reducing associated costs. However, this scaling also increases the complexity of semiconductor manufacturing processes, so continued advancements in ICs require similar progress in semiconductor manufacturing processes and technologies.

[0003] As an example, semiconductor sensors are widely used in a variety of applications to measure physical, chemical, biological, and / or environmental parameters. Some specific types of semiconductor sensors include gas sensors, pressure sensors, temperature sensors, and optical image sensors. For optical image sensors, dark current is a major concern for performance and reliability. Dark current is the current flowing in the absence of light and can be more generally described as leakage current present in optical image sensors. In at least some cases, poor interface quality between the various semiconductor layers used in optical image sensors and / or poor surface quality between the various semiconductor layers can lead to significant dark current. Another major concern for the performance and / or reliability of optical image sensors is the optical fill factor, which typically indicates the ratio of the photosensitive area of ​​a pixel (e.g., the area of ​​a photodiode) to the total area of ​​the pixel. While existing optical image sensors and their manufacturing methods are generally sufficient to meet their intended purpose, they are not entirely satisfactory in all aspects. Summary of the Invention

[0004] According to a first aspect of this disclosure, a photosensitive device is provided, comprising: a silicon substrate; a germanium layer disposed on the silicon substrate; a doped silicon layer disposed between the silicon substrate and the germanium layer; a first doped region, a second doped region, and a third doped region disposed in the germanium layer, wherein the first doped region is disposed between the second doped region and the third doped region, the first doped region comprising a first type dopant, and the second doped region and the third doped region comprising a second type dopant; a fourth doped region, a fifth doped region, and a sixth doped region disposed in the germanium layer, wherein the fourth doped region overlaps with a first interface between the first doped region and the second doped region, the fifth doped region overlaps with a second interface between the first doped region and the third doped region, the sixth doped region is disposed on the first doped region and between the fourth doped region and the fifth doped region, the fourth doped region and the fifth doped region comprising a first type dopant, and the sixth doped region comprising a second type dopant. A polysilicon gate is disposed above the sixth doped region, wherein the polysilicon gate includes the second type dopant; and a seventh doped region is disposed in the germanium layer and below the polysilicon gate, wherein the seventh doped region includes the second type dopant.

[0005] According to a second aspect of this disclosure, a photosensitive device is provided, comprising: a silicon substrate; a germanium-based photodiode having: a germanium layer disposed on the silicon substrate; two first doped regions having a first conductivity type and disposed in the germanium layer; two second doped regions having the first conductivity type and respectively disposed in the germanium layer and on the two first doped regions; a third doped region having a second conductivity type and disposed in the germanium layer and on the two first doped regions and between the two second doped regions; and a fourth doped region having the first conductivity type and disposed in the germanium layer and on the third doped region; a doped silicon layer disposed between the silicon substrate and the germanium layer of the germanium-based photodiode, and spaced between the silicon substrate and the germanium layer of the germanium-based photodiode; and two doped polysilicon gates disposed on the third doped region, wherein the fourth doped region is disposed between the two doped polysilicon gates.

[0006] According to a third aspect of this disclosure, a method for forming a photosensitive device is provided, the method comprising: forming a sensor cavity on a silicon substrate; forming an in-situ doped silicon layer, the in-situ doped silicon layer partially filling and lining the sensor cavity; forming a germanium layer on the in-situ doped silicon layer, the germanium layer filling the remaining portion of the sensor cavity; and forming a photodiode and a junction field-effect transistor including the germanium layer, wherein the junction field-effect transistor has a polysilicon gate. Attached Figure Description

[0007] This disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industry practice, the various structures are not drawn to scale and are drawn for illustrative purposes only. In fact, for clarity of discussion, the dimensions of the various structures may be arbitrarily enlarged or reduced.

[0008] Figure 1A-1J This is a schematic cross-sectional view of a portion or the whole of a photosensitive device (e.g., a germanium-based sensor with a junction gate field-effect transistor) at various stages of manufacturing according to various aspects of this disclosure.

[0009] Figure 2 Photosensitive devices (e.g., based on various aspects of this disclosure) Figure 1A-1J A schematic top view and schematic cross-sectional view of a part or the whole of a photosensitive device.

[0010] Figure 3A-3J This is a schematic cross-sectional view of a portion or the whole of a photosensitive device (e.g., a germanium-based sensor with a junction gate field-effect transistor) at various stages of manufacturing according to various aspects of this disclosure.

[0011] Figure 4 Photosensitive devices (e.g., based on various aspects of this disclosure) Figure 3A-3J A schematic top view and schematic cross-sectional view of a part or the whole of a photosensitive device.

[0012] Figure 5 This is a schematic cross-sectional view of a portion or the whole of a photosensitive device (e.g., a germanium-based sensor having a junction gate field-effect transistor) according to various aspects of this disclosure.

[0013] Figure 6 This is a schematic cross-sectional view of a portion or the whole of a photosensitive device (e.g., a germanium-based sensor having a junction gate field-effect transistor) according to various aspects of this disclosure.

[0014] Figure 7 It is based on various aspects of this disclosure for manufacturing photosensitive devices (e.g., Figure 1A-1J , Figure 2 , Figure 3A-3J , Figure 4 , Figure 5 and Figure 6 A flowchart of a method for a part or the whole of a photosensitive device (described in the document). Detailed Implementation

[0015] This disclosure relates generally to photosensitive devices, and more specifically to germanium-based photosensitive devices and methods for manufacturing the same.

[0016] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, forming a first feature on or over a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, spatially related terms such as “lower,” “higher,” “horizontal,” “vertical,” “above,” “above,” “below,” “under,” “up,” “bottom,” etc., and their derivatives (e.g., “horizontally,” “downward,” “upward,” etc.) are used to readily describe the relationship of one feature of this disclosure relative to another feature. Spatially related terms are intended to cover different orientations of the device including the feature. Additionally, when numbers or ranges of numbers are described using terms such as “about” or “approximately,” the term is intended to cover numbers within a reasonable range that takes into account variations inherent to occur during manufacturing, as understood by those skilled in the art. For example, based on known manufacturing tolerances associated with features having characteristics associated with numbers, the number or range of numbers covers a reasonable range including the quantity, such as within + / - 10% of the quantity. For example, a material layer having a thickness of “about 5 nm” can include a size range of 4.5 nm to 5.5 nm, where manufacturing tolerances associated with the deposited material layer are known to those skilled in the art to be + / - 10%. Furthermore, reference numerals and / or letters may be repeated in various examples within this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0017] This disclosure provides a germanium-based photosensitive device and a method for manufacturing the same. The disclosed germanium-based photosensitive device can reduce leakage current and / or dark current from a germanium photodiode, improve the optical fill factor, improve conversion gain, and / or reduce noise. Exemplary germanium-based sensors include a germanium photodiode and a junction field-effect transistor (JFET) formed from a germanium layer disposed in a silicon substrate in some embodiments or on a silicon substrate in others. A doped silicon layer is disposed between the germanium layer and the silicon substrate, which can be formed by in-situ doping of epitaxially grown silicon. In embodiments where the germanium layer is on the silicon substrate, the doped silicon layer is disposed between the germanium layer and an oxide layer. The JFET has a doped polysilicon gate, and in some embodiments, a gate diffusion region is disposed in the germanium layer and below the doped polysilicon gate. In some embodiments, a passivation layer for the pinned photodiode is disposed in the germanium layer. In some embodiments, a pair of doped regions in the germanium layer is configured as an electronic lens for the germanium-based sensor. The disclosed germanium-based photosensitive device can be implemented in indirect time-of-flight (iTOF) applications. For example, an exemplary germanium-based sensor could be a TOF sensor used in TOF applications. Details of embodiments of this disclosure are described below.

[0018] Figure 1A-1J This is a schematic cross-sectional view of a portion or the entire photosensitive device 100 at various manufacturing stages according to various aspects of this disclosure. For clarity, simplified diagrams have been provided. Figure 1A-1J To better understand the inventive concept of this disclosure. Additional features may be added to the photosensitive device 100, and some of the described features may be replaced, modified, or eliminated in other embodiments of the photosensitive device 100.

[0019] Go to Figure 1AFabrication begins with forming a silicon cavity in a silicon substrate within a device region of the photosensitive device. For example, photosensitive device 100 has device regions 102A and 102B, and fabrication may begin with receiving a silicon substrate (wafer) 105, forming a patterned oxide layer 110 on the silicon substrate 105, and using the patterned oxide layer 110 as an etching mask to form cavities 115 (also referred to as trenches or recesses) in the silicon substrate 105 within device regions 102A and 102B. In some embodiments, the patterned oxide layer 110 is formed by depositing an oxide layer on the silicon substrate 105, performing a photolithography process to form a patterned resist layer on the oxide layer, and performing an etching process to transfer the pattern formed in the patterned resist layer to the oxide layer. The patterned oxide layer 110 has oxide layer portions 110A, 110B, and 110C, wherein an opening 112A of the exposed silicon substrate 105 is formed by oxide layer portions 110A and 110B, and an opening 112B of the exposed silicon substrate 105 is formed by oxide layer portions 110B and 110C. The patterned oxide layer 110 has a thickness t1. In some embodiments, the thickness t1 is about 50 nm to about 90 nm. The photolithography process may include forming a resist layer on the oxide layer (e.g., by spin coating), performing a pre-exposure baking process, performing an exposure process using a mask, performing a post-exposure baking process, and performing a development process. During the exposure process, the resist layer is exposed to radiant energy (e.g., ultraviolet (UV), deep ultraviolet (DUV), or extreme ultraviolet (EUV) light), wherein the mask, depending on the mask pattern and / or mask type (e.g., binary mask, phase-shift mask, or EUV mask), blocks, transmits, and / or reflects the radiation to the resist layer, such that an image is projected onto the resist layer corresponding to the mask pattern. Because the resist layer is sensitive to radiant energy, depending on the characteristics of the resist layer and the characteristics of the developer used in the development process, the exposed portions of the resist layer undergo chemical changes during the development process, and the exposed (or unexposed) portions of the resist layer dissolve. After development, the patterned resist layer comprises a resist pattern corresponding to the mask. The etching process uses the patterned resist layer as an etching mask to remove the exposed portions of the oxide layer, thereby forming openings 112A and 112B extending through the oxide layer and exposing the silicon substrate 105. The etching process may include dry etching, wet etching, other suitable etching processes, or combinations thereof. Following the etching process, the patterned resist layer may be removed, for example, by a resist stripping process. In some embodiments, the patterned resist layer is completely or partially removed during etching of the oxide layer and / or during etching of the silicon substrate 105. In some embodiments, the exposure process may implement maskless lithography, electron beam writing, and / or ion beam writing.

[0020] Then, an etching process is performed using the patterned oxide layer 110 as an etching mask to form a cavity 115 in the silicon substrate 105. For example, the etching process removes portions of the silicon substrate 105 exposed by openings 112A and 112B of the patterned oxide layer 110, thereby forming the cavity 115, which has a bottom and sidewalls formed by the silicon substrate 105. The cavity 115 has a depth D and a width W. In some embodiments, the depth D is about 900 nm to about 1500 nm. In some embodiments, the width W is about 2000 nm to about 10000 nm. In some embodiments, the etching process is configured to selectively remove the silicon substrate 105 (relative to the patterned oxide layer 110). In other words, the etching process substantially removes the silicon substrate 105 but does not remove or substantially does not remove the patterned oxide layer 110. For example, an etchant is selected for the etching process that etches silicon (i.e., silicon substrate 105) at a higher rate than that used for etching silicon oxide (i.e., patterned oxide layer 110) (i.e., the etchant has high etch selectivity for silicon). The etching process is a dry etching process, a wet etching process, other suitable etching processes, or a combination of the foregoing.

[0021] Go to Figure 1B A doped silicon layer is formed in a silicon cavity, and the doped silicon layer partially fills the silicon cavity. For example, a doped silicon layer 120 is formed in cavity 115, and the doped silicon layer 120 partially fills cavity 115. The doped silicon layer 120 includes an n-type dopant (e.g., phosphorus, arsenic, other n-type dopant, or combinations thereof), a p-type dopant (e.g., boron, indium, other p-type dopant, or combinations thereof), or combinations thereof. The dopant concentration of the doped silicon layer 120 is greater than the dopant concentration of the silicon substrate 105. In some embodiments, the dopant concentration of the doped silicon layer 120 is about 5 × 10⁻⁶. 16 atoms / cm 3 (cm -3 ) to approximately 5×10 18 cm -3 In some embodiments, the dopant concentration of the silicon substrate 105 is less than about 1 × 10⁻⁶. 15 cm -3In some embodiments, the doped silicon layer 120 comprises an n-type dopant (e.g., phosphorus) and may be referred to as an n-doped silicon layer (e.g., a Si:P layer or a Si:C:P layer). In some embodiments, the doped silicon layer 120 comprises a p-type dopant (e.g., boron) and may be referred to as a p-doped silicon layer (e.g., a Si:B layer). The doped silicon layer 120 is disposed along and covers the bottom and sidewalls of the cavity 115. The thickness t2 of the doped silicon layer 120 along the bottom of the cavity 115 is less than the depth D of the cavity 115, and the total thickness of the doped silicon layer 120 along the sidewalls of the cavity 115 (i.e., the sum of the thickness t3 along the first sidewall of the respective silicon cavity 115 and the thickness t4 along the second sidewall of the respective silicon cavity) is less than the width W of the cavity 115. In some embodiments, the thicknesses t2, t3, and t4 are substantially the same, such that the doped silicon layer 120 is a conformal layer (i.e., a layer having a substantially uniform thickness on each surface). In some embodiments, thickness t2 differs from thickness t3 and / or thickness t4. In some embodiments, thickness t3 is substantially the same as thickness t4. In some embodiments, thickness t3 differs from thickness t4. In some embodiments, thickness t2, thickness t3, and / or thickness t4 is from about 10 nm to about 100 nm. In the depicted embodiments, the doped silicon layer 120 is substantially U-shaped. The doped silicon layer 120 may have different shapes depending on the contour of cavity 115.

[0022] In some embodiments, the doped silicon layer 120 is formed by a deposition process that selectively grows silicon on the silicon substrate 105 without growing silicon on the patterned oxide layer 110. For example, the doped silicon layer 120 is formed by epitaxially growing silicon from the silicon substrate 105. The epitaxial process used to form the doped silicon layer 120 may implement chemical vapor deposition (CVD) techniques (e.g., vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), low-pressure CVD (LPCVD), and / or plasma-enhanced CVD (PECVD)), molecular beam epitaxy, other suitable selective epitaxial growth (SEG) processes, or combinations thereof. Epitaxial processes can use gaseous and / or liquid precursors, including silicon-containing precursors (e.g., silane (SiH4), disilane (Si2H6), propane (Si3H8), dichlorosilane (DCS) (Si2H2Cl2), other suitable silicon-containing precursors, or combinations thereof) and support precursors (e.g., hydrogen precursors (e.g., H2), argon precursors (e.g., Ar), helium precursors (e.g., He), nitrogen precursors (e.g., N2), xenon precursors, other suitable inert precursors, or combinations thereof). In the depicted embodiments, the epitaxial process further uses dopant precursors, such as phosphine (PH3), arsine (AsH3), diborane (B2H6), other suitable dopant precursors, or combinations thereof. Thus, the epitaxially grown silicon is doped during deposition (i.e., in-situ doping). In some embodiments, the epitaxially grown silicon is doped after deposition, for example by ion implantation and / or diffusion processes. In some embodiments, a cleaning process and / or surface treatment process (collectively, a cleaning process) is performed prior to the formation of the doped silicon layer 120 to remove defects from the silicon substrate 105 and / or the patterned oxide layer 110, such as any native oxides, contaminants, and / or other defects on the silicon substrate 105 and / or the patterned oxide layer 110. In some embodiments, the cleaning process is a baking process performed in an environment including an etchant, wherein defects are removed (etched) from the silicon substrate 105 and / or the patterned oxide layer 110 during the baking process. For example, a chlorine-based baking process (e.g., an HCl baking process) is performed, which can remove (clean) surface nucleation sites on the patterned oxide layer 110.

[0023] Go to Figure 1CA germanium layer is formed in the remaining portion of the silicon cavity, and the germanium layer fills the remaining portion of the silicon cavity. For example, a germanium layer 130 is formed in the remaining portion of cavity 115, and the germanium layer 130 fills the remaining portion of cavity 115. Each germanium layer 130 has a first portion enclosed by a corresponding doped silicon layer 120, and a second portion configured to be higher than the doped silicon layer 120 and located between corresponding oxide layer portions of patterned oxide layer 110. For example, the doped silicon layer 120 is disposed along the bottom and sidewalls of the first portion of germanium layer 130, while the second portion of germanium layer 130 covers the top surface of the sidewall portion of the doped silicon layer 120 and contacts oxide layer portions 110A, 110B, and / or 110C. The thickness t5 of the first portion is less than the depth D (e.g., thickness t5 = depth D - thickness t2), the thickness width of the first portion is less than the width W (e.g., width of the first portion = width W - (thickness t3 + thickness t4)), and the second portion has a thickness t6 and a width approximately the same as the width W. In some embodiments, the thickness t5 is from about 900 nm to about 1500 nm. The thickness t6 is less than the thickness t1 of the patterned oxide layer 110, such that the germanium layer 130 partially fills the openings 112A and 112B of the patterned oxide layer 110, and the distance between the top surface of the germanium layer 130 and the top surface of the patterned oxide layer 110 is d1. In some embodiments, the thickness t6 is from about 0 nm to about 10 nm.

[0024] In some embodiments, the distance d1 is from about 0 nm to about 10 nm. In the depicted embodiments, the germanium layer 130 is a pure germanium layer. In some embodiments, the germanium layer 130 is undoped (or unintentionally doped (UID)) (i.e., the germanium layer 130 is substantially free of dopant). In some embodiments, the germanium layer 130 has a dopant concentration that is considered undoped. In some embodiments, the germanium layer 130 is doped with an n-type dopant (e.g., phosphorus), a p-type dopant (e.g., boron), or a combination thereof.

[0025] In some embodiments, the germanium layer 130 is formed by a deposition process that selectively grows germanium on the doped silicon layer 120 without growing germanium on the patterned oxide layer 110. For example, the germanium layer 130 is formed by epitaxially growing germanium from the doped silicon layer 120. The epitaxial process used to form the germanium layer 130 can implement CVD deposition techniques (e.g., VPE, UHV-CVD, LPCVD, and / or PECVD), molecular beam epitaxy, other suitable SEG processes, or combinations thereof. The epitaxial process can use gaseous and / or liquid precursors. For example, the epitaxial process uses germanium-containing precursors (e.g., germanane (GeH4), desgerane (Ge2H6), germanium tetrachloride (GeCl4), germanium dichloride (GeCl2), other suitable germanium-containing precursors, or combinations thereof) and support precursors (e.g., hydrogen precursors (e.g., H2), argon precursors (e.g., Ar), helium precursors (e.g., He), nitrogen precursors (e.g., N2), xenon precursors, other suitable inert precursors, or combinations thereof). An epitaxial process is performed until the epitaxially grown germanium extends between the respective oxide layer portions of the patterned oxide layer 110 and covers the top surface of the sidewall portion of the doped silicon layer 120. In some embodiments, the epitaxial process is performed until the epitaxially grown germanium fills openings 112A and 112B, and in some embodiments, the epitaxially grown germanium extends above the top surface of the patterned oxide layer 110 by a distance. A planarization process (e.g., chemical mechanical polishing (CMP)) may be performed to remove portions of the epitaxially grown germanium that extend above and / or above the top surface of the patterned oxide layer 110, wherein the patterned oxide layer 110 may serve as a planarization stop (i.e., the planarization process stops upon reaching the patterned oxide layer 110). In some embodiments, the top surfaces of the patterned oxide layer 110 and the germanium layer 130 are substantially planar after the planarization process. An etch-back process can be performed on the germanium layer 130 to recess the top surface of the germanium layer 130 relative to the top surface of the patterned oxide layer 110 by a distance d1. In some embodiments, a planarization process recesses the epitaxially grown germanium relative to the top surface of the patterned oxide layer 110, such that after the planarization process, the top surface of the germanium layer 130 is below the top surface of the patterned oxide layer 110 by a distance d1. In such embodiments, an additional etch-back process may be unnecessary. In embodiments where the germanium layer 130 is doped, the epitaxial process can use a dopant precursor (such as those described herein) to dope the epitaxially grown germanium in situ. In some embodiments, the epitaxially grown germanium is doped after deposition, for example, by an ion implantation process and / or a diffusion process.In some embodiments, a cleaning process is performed prior to the formation of the germanium layer 130 to remove defects from the doped silicon layer 120 and / or the patterned oxide layer 110, such as any native oxides, contaminants, and / or other defects on the doped silicon layer 120 and / or the patterned oxide layer 110. In some embodiments, the cleaning process is a baking process (e.g., the baking process described herein).

[0026] Go to Figure 1DAn undoped (or UID) capping layer is formed over a germanium layer. For example, a capping layer 135 is formed over a germanium layer 130. In the depicted embodiment, the capping layer 135 is an undoped silicon layer (i.e., a silicon layer substantially free of dopants, such as an n-type dopant (e.g., phosphorus) or a p-type dopant (e.g., boron)). In some embodiments, the capping layer 135 has a dopant concentration considered undoped. The capping layer 135 fills the remaining portion of the openings (e.g., openings 112A and 112B) in the patterned oxide layer 110. In the depicted embodiment, a first capping layer 135 is disposed between oxide layer portions 110A and 110B, and a second capping layer 135 is disposed between oxide layer portions 110B and 110C. The capping layer 135 has a thickness t7 less than the thickness t1 of the patterned oxide layer 110, and a width approximately the same as the width W. In some embodiments, the thickness t7 is from about 10 μm to about 50 μm. In some embodiments, the thickness t7 is substantially equal to the distance d1. In some embodiments, the capping layer 135 is formed by a deposition process that selectively grows silicon on the germanium layer 130 instead of on the patterned oxide layer 110. For example, the capping layer 135 is formed by epitaxially growing silicon from the germanium layer 130. The epitaxial process for forming the capping layer 135 may implement CVD deposition techniques (e.g., VPE, UHV-CVD, LPCVD, and / or PECVD), molecular beam epitaxy, other suitable SEG processes, or combinations thereof. The epitaxial process may use gaseous and / or liquid precursors, such as silicon-containing precursors and carrier precursors (e.g., those described herein). The epitaxial process is performed until the epitaxially grown silicon fills the openings 212A and 212B of the patterned oxide layer 110. In some embodiments, the epitaxially grown silicon may overfill the openings 212A and 212B such that the epitaxially grown silicon extends above the top surface of the patterned oxide layer 110. In such embodiments, a planarization process such as CMP can be performed to remove portions of the epitaxially grown silicon that extend above and / or over the top surface of the patterned oxide layer 110, wherein the patterned oxide layer 110 can serve as a planarization stop. In some embodiments, the top surfaces of the patterned oxide layer 110 and the cap layer 135 are substantially planar after the planarization process. In some embodiments, the cap layer 135 is formed by depositing an undoped semiconductor layer on the patterned oxide layer 110, the doped silicon layer 120, and the germanium layer 130, wherein the undoped semiconductor layer fills the remaining portions of openings 112A and 112B; and then performing a planarization process to remove the undoped semiconductor layer formed over the top surface of the patterned oxide layer 110.In some embodiments, a cleaning process is performed prior to the formation of the cap layer 135 to remove defects from the germanium layer 130 and / or the patterned oxide layer 110, such as any native oxides, contaminants, and / or other defects on the germanium layer 130 and / or the patterned oxide layer 110. In some embodiments, the cleaning process is a baking process (such as those described herein).

[0027] Go to Figure 1E An oxide layer is formed over a photosensitive device. For example, an oxide layer 140 is formed over photosensitive device 100 such that the oxide layer 140 covers device regions 102A and 102B. In the depicted embodiment, the oxide layer 140 covers a patterned oxide layer 110 and a cap layer 135. The oxide layer 140 includes oxygen and, in some embodiments, includes another suitable component. For example, the oxide layer 140 may include silicon and oxygen (e.g., SiO2) and is referred to as a silicon oxide layer. The oxide layer 140 has a thickness t8. In some embodiments, the thickness t8 is about 10 nm to about 20 nm. Any suitable deposition process can be performed to form the oxide layer 140, such as CVD, physical vapor deposition (PVD), atomic layer deposition (ALD), high-density plasma CVD (HDPCVD), metal-organic CVD (MOCVD), remote plasma CVD (RPCVD), rapid thermal CVD (RTCVD), PECVD, plasma-enhanced ALD (PEALD), LPCVD, atomic layer CVD (ALCVD), atmospheric pressure CVD (APCVD), other suitable methods, or combinations thereof. In the depicted embodiment, the oxide layer 140 is formed on the photosensitive device 100 by CVD.

[0028] Go to Figure 1FVarious doped regions are formed in the undoped cap layer and / or germanium layer of the device region of the photosensitive device. For example, a pair of first-type doped regions 145, a pair of first-type doped regions 150, a second-type doped region 155, and a first-type doped region 160 are formed in the corresponding cap layer 135 and / or the corresponding germanium layer 130 of device regions 102A and 102B. In the depicted embodiment, the first-type doped regions 145 and 160 are formed in the cap layer and the germanium layer 130, while the first-type doped regions 150 and 155 are formed in the germanium layer 130. The first-type doped regions 145, 150, and 160 include a first-type dopant. The second-type doped region 155 includes a second-type dopant different from the first-type dopant. Therefore, the first type doped region 145 includes a first type doped silicon portion (i.e., some portions of the capping layer 135) and a first type doped germanium portion (i.e., some portions of the germanium layer 130), the first type doped region 150 includes a first type doped germanium portion (i.e., some portions of the germanium layer 130), the second type doped region 155 includes a second type doped germanium portion (i.e., some portions of the germanium layer 130), and the first type doped region 160 includes a first type doped silicon portion (i.e., some portions of the capping layer 135) and a first type doped germanium portion (i.e., some portions of the germanium layer 130). In some embodiments, the first type dopant is an n-type dopant (e.g., phosphorus), and the second type dopant is a p-type dopant (e.g., boron). In such an embodiment, the first type doped region 145, the first type doped region 150, and the first type doped region 160 are n-doped regions, and the second type doped region 155 is a p-doped region. In a further embodiment of this invention, the first type-doped region 145 may be referred to as a germanium n-well (GNW), and the first type-doped region 150 may be referred to as a deep germanium n-well (DGNW). In some embodiments, the first type-doper is a p-type doper, and the second type-doper is an n-type doper. In such embodiments, the first type-doped regions 145, 150, and 160 are p-doped regions, and the second type-doped region 155 is an n-doped region. In a further embodiment of this invention, the first type-doped region 145 may be referred to as a germanium p-well (GPW), and the first type-doped region 150 may be referred to as a deep germanium p-well (DGPW). The dopant concentration of the first type-doped region 150 is greater than that of the first type-doped region 145 and less than that of the first type-doped region 160. The dopant concentration of the second type-doped region 155 is less than that of the first type-doped region 160, greater than that of the first type-doped region 145, and greater than that of the first type-doped region 150. The dopant concentration in the first type doped region 145 is less than the dopant concentration in the first type doped region 160.In some embodiments, the first type doped region 145 has approximately 1 × 10. 14 cm -3 Approximately 9×10 15 cm -3 The dopant concentration. In some embodiments, the first-type doped region 150 has approximately 1 × 10⁻⁶ dopant concentrations. 17 cm -3 Approximately 9×10 18 cm -3 The dopant concentration. In some embodiments, the second-type doped region 155 has approximately 1 × 10⁻⁶ dopant concentrations. 17 cm -3 Approximately 9×10 18 cm -3 The dopant concentration. In some embodiments, the first-type doped region 160 has approximately 1 × 10⁻⁶ dopant concentrations. 19 cm -3 Approximately 9×10 20 cm -3 The dopant concentration.

[0029] A first-type doped region 145 extends from the top surface of the cap layer 135 to a depth D1 in the germanium layer 130. A first-type doped region 150 is disposed at a depth D2 in the germanium layer 130 and extends from depth D2 to depth D1 (greater than D2). A second-type doped region 155 is disposed at a depth D3 in the germanium layer 130 and extends from depth D3 to depth D2 (greater than depth D3). A first-type doped region 160 extends from the top surface of the cap layer 135 to depth D3 in the germanium layer 130. Depths D1, D2, and D3 are measured from the top surface of the germanium layer 130. In some embodiments, depth D1 is about 100 nm to about 200 nm. In some embodiments, depth D2 is about 60 nm to about 90 nm. In some embodiments, depth D3 is about 10 nm to about 20 nm. A first type-doped region 160 is disposed above a second type-doped region 155, wherein a pn junction is formed by the interface between the first type-doped region 160 and the second type-doped region 155. Further, a second type-doped region 155 is disposed between first type-doped regions 145, wherein a pn junction is formed by the interface between the second type-doped region 155 and the first type-doped region 145. A first type-doped region 160 is also disposed between first type-doped regions 145, wherein an interface is located between the first type-doped regions 160 and the first type-doped regions 145. A first type-doped region 150 extends below the second type-doped region 155, wherein a pn junction is formed by the interface between the first type-doped region 150 and the second type-doped region 155. A first type-doped region 145 is disposed along the doped silicon layer 120 and overlaps the entire width of the first type-doped region 150. In some embodiments, the first type-doped region 145 extends into the germanium layer 130 to a depth less than depth D1, such that the first type-doped region 145 partially overlaps the first type-doped region 150 along its width. The first type doped region 145 has a thickness t9 and a width W1, the first type doped region 150 has a thickness t10 and a width W2, the second type doped region 155 has a thickness t11 and a width W3, and the second type doped region 160 has a thickness t12 and a width W3. The first type doped regions 145 disposed in the respective germanium layers 130 are separated by a spacing S1 (in the depicted embodiment, the spacing S1 is substantially equal to the width W3), and the first type doped regions 150 disposed in the respective germanium layers 130 are separated by a spacing S2 (in the depicted embodiment, the spacing S2 is less than the width W3). In some embodiments, the thickness t9 is about 85 nm to about 200 nm. In some embodiments, the thickness t10 is about 20 nm to about 30 nm. In some embodiments, the thickness t11 is about 60 nm to about 150 nm. In some embodiments, the thickness t12 is about 5 nm to about 20 nm. In some embodiments, the width W1 is about 400 nm to about 1500 nm.In some embodiments, the width W2 is from about 800 nm to about 2500 nm. In some embodiments, the width W3 is from about 3000 nm to about 5000 nm. In some embodiments, the thickness t9 is the sum of the thickness t7 and the depth D1, the thickness t10 is the difference between the depth D1 and the depth D2, the thickness t11 is the difference between the depth D2 and the depth D3, and / or the thickness t12 is the sum of the thickness t7 and the depth D3.

[0030] Various doped regions can be formed in the cap layer 135 and / or germanium layer 130 using photolithography processes (such as those described herein) and implantation processes. For example, forming various doped regions may include: performing a first photolithography process to form a first implantation mask exposing a first region of germanium layer 130, and using the first implantation mask to perform a first implantation process to introduce a type-1 dopant into the first region of germanium layer 130 to form a type-1 doped region 145; performing a second photolithography process to form a second implantation mask exposing a second region of germanium layer 130 (which may partially overlap with the first region), and using the second implantation mask to perform a second implantation process to introduce a type-1 dopant into the second region of germanium layer 130 to form a type-2 doped region 150; performing a third photolithography process... A third implantation mask is formed to expose a third region of germanium layer 130 (which may partially overlap with the second region and span between the first regions) using a photolithography process, and a third implantation process is performed using the third implantation mask to introduce a type-2 dopant into the third region of germanium layer 130 to form a type-2 doped region 155; and a fourth photolithography process is performed to form a fourth implantation mask to expose a fourth region of germanium layer 130 (which may overlap with the entire third region), and a fourth implantation process is performed using the fourth implantation mask to introduce a type-1 dopant into the fourth region of germanium layer 130 to form a type-1 doped region 160. In some embodiments, the type-2 doped region 155 and the type-1 doped region 160 are formed using a single photolithography process instead of two. For example, the fourth photolithography process may be omitted, and both the third and fourth implantation processes may use the third implantation mask to form the type-2 doped region 155 and the type-1 doped region, respectively. In such embodiments, implantation process parameters (e.g., implantation energy, implantation dopant type, implantation dose, implantation angle, and / or other suitable implantation parameters) can be adjusted to provide a second-type doped region 155 and a first-type doped region 160 in the germanium layer 130. This disclosure contemplates performing the first, second, third, and fourth lithography / implantation processes in any order. In some embodiments, parameters of the first, second, third, and / or fourth implantation processes (e.g., implantation energy, implantation dopant type, implantation dose, implantation angle, and / or other suitable implantation parameters) are adjusted to achieve desired depths, desired dopant concentrations, desired dimensions (e.g., thickness and / or width), and / or configurations of the first-type doped region 145, the first-type doped region 150, the second-type doped region 155, and / or the first-type doped region 160.

[0031] Go to Figure 1G-1J A doped polysilicon gate is formed on top of the germanium layer, and a type-1 doped region is formed in the germanium layer and below the doped polysilicon gate through self-diffusion. Figure 1GIn this process, fabrication may include forming a patterned mask layer 170 over an oxide layer 140, wherein the patterned mask layer 170 has gate openings 178A and 178B in device regions 102A and 102B that expose the oxide layer 140. Gate openings 178A and 178B are located over a second-type doped region 155 and a first-type doped region 160 formed in a germanium layer 130. In the depicted embodiment, the patterned mask layer 170 has a patterned dielectric layer 172 and a patterned oxide layer 175 disposed over the patterned dielectric layer 172. The patterned dielectric layer 172 includes a dielectric material suitable for subsequently formed gate spacers, such as silicon, oxygen, carbon, nitrogen, other suitable components, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbonoxynitride, and / or silicon carbonoxynitride). The patterned oxide layer 175 comprises an oxygen-containing dielectric material, and in some embodiments, the patterned oxide layer 175 comprises a dielectric material containing another suitable composition. In the depicted embodiments, the patterned dielectric layer 172 comprises silicon and nitrogen and may be referred to as a silicon nitride layer, and the patterned dielectric layer 175 comprises silicon and oxygen and may be referred to as a silicon oxide layer. The thickness of the patterned dielectric layer 172 is t13 (which corresponds to the thickness of the subsequently formed gate sidewall), and the thickness of the patterned oxide layer 175 is t14. In some embodiments, the thickness t13 is about 30 nm to about 50 nm. In some embodiments, the thickness t14 is about 20 nm to about 40 nm.

[0032] In some embodiments, the patterned mask layer 170 is formed by: depositing a dielectric layer over an oxide layer 140, depositing an oxide layer over the dielectric layer, performing a photolithography process to form a patterned resist layer over the oxide layer, and performing an etching process to transfer the resist pattern formed in the patterned resist layer to the oxide layer and the dielectric layer, thereby forming a patterned mask layer 170 having a patterned dielectric layer 172 and a patterned oxide layer 175. The dielectric layer and oxide layer are deposited by CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, RTCVD, PECVD, PEALD, LPCVD, ALCVD, APCVD, other suitable methods, or combinations thereof. The photolithography process may include forming a resist layer on the oxide layer (e.g., by spin coating), performing a pre-exposure baking process, performing an exposure process using a mask, performing a post-exposure baking process, and performing a development process (as described herein). The etching process uses a patterned resist layer as an etching mask to remove exposed portions of the oxide and dielectric layers to form gate openings 178A and 178B, which correspond to the locations of subsequently formed gates of the photosensitive device 100. The etching process includes dry etching, wet etching, other suitable etching processes, or combinations thereof. In some embodiments, a patterned resist layer is used as an etching mask to remove portions of the oxide layer to form a patterned oxide layer 175, and a patterned resist layer and / or patterned oxide 175 is used as an etching mask to remove portions of the dielectric layer to form a patterned dielectric layer 172. In some embodiments, the etching process includes multiple steps, such as a first etching step selectively etching the oxide layer and a second etching step selectively etching the dielectric layer (e.g., the first and second etching steps use different etchants). In some embodiments, the same etchant is used to remove both the oxide and dielectric layers. In some embodiments, the etching process stops upon reaching the oxide layer 140. In the depicted embodiments, the etching process intentionally or unintentionally etches the exposed portions of the oxide layer 140 and recesses the exposed portions of the oxide layer 140 by a distance d2, providing an oxide layer 140 with a varying thickness. For example, the unexposed portions of the oxide layer 140 have a thickness t1, and the exposed portions of the oxide layer 140 have a thickness less than thickness t1 (e.g., the thickness of the exposed portions of the oxide layer 140 = thickness t1 - distance d2). In some embodiments, the distance d2 is from about 0 nm to about 5 nm. After the etching process, the patterned resist layer can be removed, for example, by a resist stripping process. In some embodiments, the patterned resist layer is completely or partially removed during the etching of the oxide layer and / or the dielectric layer.

[0033] exist Figure 1HIn this process, fabrication can proceed to the removal of the patterned oxide layer 175 from the photosensitive device 100 and the formation of a doped polysilicon layer 180 over the patterned dielectric layer 172, wherein the doped polysilicon layer 180 fills gate openings 178A and 178B. In some embodiments, the patterned oxide layer 175 is removed by an etching process, such as a dry etching process, a wet etching process, other suitable etching processes, or a combination thereof. The etching process is configured to selectively remove the patterned oxide layer 175 (relative to the patterned dielectric layer 172). In other words, the etching process substantially removes the patterned oxide layer 175 but does not remove or substantially does not remove the patterned dielectric layer 172. For example, an etchant is selected for the etching process that etches silicon oxide (i.e., the patterned dielectric layer 175) at a higher rate than etching silicon nitride (i.e., the patterned dielectric layer 172) (i.e., the etchant has high etching selectivity for the oxide). In the depicted embodiments, the selective wet etching process uses a diluted hydrofluoric acid (DHF) solution to remove the patterned oxide layer 175. In some embodiments, the selective wet etching process uses a buffered oxide etch (BOE) solution to remove the patterned oxide layer 175.

[0034] A doped polysilicon layer 180 is formed by depositing polysilicon material over a patterned dielectric layer 172 using methods such as CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, RTCVD, PECVD, PEALD, LPCVD, ALCVD, APCVD, other suitable methods, or combinations thereof. In the depicted embodiments, a dopant is introduced into the polysilicon material during deposition (i.e., in situ). In some embodiments, the dopant is introduced into the polysilicon material after deposition (e.g., via an implantation process). In some embodiments, the doped polysilicon layer 180 comprises an n-type dopant (e.g., phosphorus) and may be referred to as an n-doped polysilicon layer. In some embodiments, the doped polysilicon layer 180 comprises a p-type dopant (e.g., boron) and may be referred to as a p-doped polysilicon layer. In some embodiments, the dopant concentration of the doped polysilicon layer 180 is approximately 1 × 10⁻⁶. 19 cm -3 To approximately 1×10 21 cm -3A doped polysilicon layer 180 covers the top surface of the patterned dielectric layer 172, fills gate openings 178A and 178B, and substantially contacts the oxide layer 140. The portion of the doped polysilicon layer 180 above the top surface of the patterned dielectric layer 172 has a thickness t15. In some embodiments, the thickness t15 is about 80 nm to about 120 nm. The thickness of the portion of the doped polysilicon layer 180 filling the gate openings 178A and 178B is less than the sum of the thickness t13 of the patterned dielectric layer 172 and the thickness t1 of the oxide layer 140 (e.g., thickness = thickness t13 + distance d2).

[0035] exist Figure 1I In this process, a patterning process is performed on a doped polysilicon layer 180 and a patterned dielectric layer 172 to form polysilicon gates 180A and 180B from the doped polysilicon layer 180, and gate spacers 184 from the patterned dielectric layer 172. The polysilicon gates 180A and 180B have a first portion disposed between the respective gate spacers 184 and a second portion disposed over and covering the top surface of the respective gate spacers 184. The first portion has a thickness t16 and a width W4, and the second portion has a thickness t17 and a width W5 greater than the width W4. In some embodiments, the width W4 is about 200 nm to about 600 nm. In some embodiments, the width W5 is about 30 nm to about 50 nm. In some embodiments, the thickness t16 is approximately equal to the thickness t13 of the patterned dielectric layer 172. In some embodiments, the thickness t17 is approximately equal to the thickness t15. In some embodiments, the thickness t17 is less than the thickness t15. Gate spacer 184 is disposed along the sidewall of the first portion of polysilicon gate 180A and the sidewall of the first portion of polysilicon gate 180B. Gate spacer 184 has a height approximately equal to the thickness t16 and a width W6 approximately equal to the difference between width W5 and width W4 (e.g., width W6 = width W5 - width W4).

[0036] In some embodiments, the patterning process includes: performing a photolithography process to form a patterned resist layer over a doped polysilicon layer 180; and performing an etching process to transfer the resist pattern formed in the patterned resist layer to the doped polysilicon layer 180, thereby forming polysilicon gates 180A and 180B. The photolithography process may include: forming a resist layer on the doped polysilicon layer 180 (e.g., by spin coating); performing a pre-exposure baking process; performing an exposure process using a mask; performing a post-exposure baking process; and performing a development process. The etching process uses the patterned resist layer as an etching mask to remove exposed portions of the doped polysilicon layer 180, such that unexposed, covered portions of the doped polysilicon layer 180 are retained to provide polysilicon gates 180A and 180B over the oxide layer 140. The etching process includes dry etching, wet etching, other suitable etching processes, or combinations thereof. In some embodiments, a patterned resist layer is used as an etching mask to remove portions of the doped polysilicon layer 180 to form polysilicon gates 180A and 180B, and a patterned resist layer and / or polysilicon gates 180A and 180B are used as etching masks to remove portions of the patterned dielectric layer 172 to form gate spacers 184. In embodiments where polysilicon gates 180A and 180B are used as etching masks for etching the patterned dielectric layer 172, the etching process may intentionally or unintentionally etch a second portion of the polysilicon gates 180A and 180B such that thickness t17 is less than thickness t15. In some embodiments, the etching process includes multiple steps, such as a first etching step selectively etching the doped polysilicon layer 180 and a second etching step selectively etching the patterned dielectric layer 172 (e.g., the first and second etching steps use different etchants). The etching process is configured to selectively remove the doped polysilicon layer 180 and / or the patterned dielectric layer 172 relative to the oxide layer 140. In other words, the etching process substantially removes the doped polysilicon layer 180 and / or the patterned dielectric layer 172, but does not remove or substantially does not remove the oxide layer 140. For example, an etchant is selected for the etching process, and the etcher etches the doped polysilicon (i.e., the doped polysilicon layer 180) and / or the silicon nitride (i.e., the patterned dielectric layer 172) at a higher rate than etching silicon oxide (i.e., the oxide layer 140) (i.e., the etchant has high etch selectivity relative to the doped polysilicon and / or silicon nitride). In some embodiments, a mask layer is formed over the doped polysilicon layer 180, and a patterned resist layer is formed over the mask layer. In such an embodiment, the first etching process may remove some portions of the mask layer to form a patterned mask layer, and the second etching process uses the patterned mask layer as an etching mask to remove some portions of the doped polysilicon layer 180 and / or some portions of the patterned dielectric layer 172.After the etching process, the patterned resist layer can be removed, for example, by a resist stripping process. In some embodiments, the patterned resist layer is completely or partially removed during etching of the doped polysilicon layer 180 and / or the patterned dielectric layer 172.

[0037] After forming polysilicon gates 180A and 180B, fabrication may include performing a diffusion process to diffuse dopant from polysilicon gates 180A and 180B into germanium layer 130, thereby forming a first type-doped region 185 that connects polysilicon gates 180A and 180B to a first type-doped region 160 in germanium layer 130. The first type-doped region 185 extends from polysilicon gates 180A and 180B to a depth D4 in germanium layer 130, such that the first type-doped region 185 overlaps with the first type-doped region 160. Depth D4 is measured from the top surface of germanium layer 130, and in the depicted embodiment, depth D4 is less than depth D3. Therefore, the first type-doped region 185 includes a first type-doped silicon portion (i.e., some portions of capping layer 135) and a first type-doped germanium portion (i.e., some portions of germanium layer 130). In some embodiments, the depth D4 is approximately 5 nm to approximately 10 nm. The dopant concentration of the first type doped region 185 is greater than that of the first type doped region 160. In some embodiments, the first type doped region 185 has approximately 1 × 10⁻⁶ nm. 19 cm -3 Approximately 9×10 20 cm -3The dopant concentration. In some embodiments, the first type doped region 185 includes an n-type dopant (e.g., phosphorus) and may be referred to as an n-type doped germanium region (Ge N+). In some embodiments, the first type doped region 185 includes a p-type dopant (e.g., boron) and may be referred to as a p-type doped germanium region (Ge P+). In the depicted embodiments, the width of the first type doped region 185 is approximately equal to the width W4. In some embodiments, the width of the first type doped region 185 is greater than or less than the width W4. The first type doped region 185 has a thickness t18. In some embodiments, the thickness t18 is from about 30 nm to about 60 nm. In some embodiments, the diffusion process is an annealing process that drives the dopant from polysilicon gates 180A and 180B into the germanium layer 130 to form the first type doped region 185. In some embodiments, the annealing process exposes the polysilicon gates 180A and 180B to heat at a temperature of about 700°C to about 850°C. In some embodiments, the annealing process is performed for approximately 30 minutes to approximately 120 minutes. Forming the first type-doped region 185 via self-diffusion prevents damage to the photosensitive device 100 that might occur during the formation of the first type-doped region 185 via the implantation process, such as damage to the doped regions in the germanium layer 130 (i.e., first type-doped region 145, first type-doped region 150, second type-doped region 155, and / or first type-doped region 160), and / or damage to the pn junction in the germanium layer formed by the interfaces between the doped regions. Since the first type-doped region 185 is formed via self-diffusion of the gate, the first type-doped region 185 can also be referred to as the gate diffusion region and / or diffusion region.

[0038] Go to Figure 1JAdditional doped regions are formed in the germanium layer. For example, a second type doped region 190 is formed in the germanium layer 130. The second type doped region 190 extends to a depth D5 in the germanium layer 130, such that the second type doped region 190 overlaps with the first type doped region 145, the second type doped region 155, and the first type doped region 160. The second type doped region 190 overlaps with the interfaces between the first type doped regions 145 and 160, and with the interfaces between the first type doped regions 145 and 155 (these interfaces form a pn junction). The second type doped region 190 is spaced apart from the first type doped region 180. The depth D5 is measured from the top surface of the germanium layer 130, and in the depicted embodiment, the depth D5 is greater than the depth D3 and less than the depth D2. Therefore, the second type doped region 190 includes a second type doped silicon portion (i.e., some portions of the cap layer 135) and a second type doped germanium portion (i.e., some portions of the germanium layer 130). In some embodiments, the depth D5 is from about 20 nm to about 40 nm. In some embodiments, such as those depicted, the second type doped region 190 extends into the oxide layer 140 and has a second type doped oxide portion. The second type doped region 190 also has a width W6 and a thickness t19. In some embodiments, the width W6 is from about 30 nm to about 50 nm. In some embodiments, the thickness t19 is from about 300 nm to about 1500 nm. The dopant concentration of the second type doped region 190 is greater than the dopant concentration of the first type doped region 145, the second type doped region 155, and / or the first type doped region 160. In some embodiments, the second type doped region 190 has about 1 × 10⁻⁶ nm. 17 cm -3 Approximately 9×10 18 cm -3 The dopant concentration. In some embodiments, the second type doped region 190 includes a p-type dopant (e.g., boron) and may be referred to as a p-type doped germanium region (Ge P+). In some embodiments, the second type doped region 190 includes an n-type dopant (e.g., phosphorus) and may be referred to as an n-type doped germanium region (Ge N+).

[0039] A first-type doped region 195 is also formed in the germanium layer 130. The first-type doped region 195 extends to a depth D6 in the germanium layer 130, such that the first-type doped region 195 overlaps with the first-type doped region 160. The first-type doped region 195 is located between and spaced apart from the respective first-type doped regions 185 by a certain distance. In some embodiments, this distance is approximately equal to the width W6 of the gate spacer 184. The depth D6 is measured from the top surface of the germanium layer 130, and in the depicted embodiment, the depth D4 is less than the depth D3. Therefore, the first-type doped region 195 includes a first-type doped silicon portion (i.e., some portions of the cap layer 135) and a first-type doped germanium portion (i.e., some portions of the germanium layer 130). In some embodiments, the depth D6 is approximately 5 nm to approximately 10 nm. The first-type doped region 195 also has a width W8 and a thickness t20. In some embodiments, the width W8 is approximately equal to the spacing between the polysilicon gate 180A and the polysilicon gate 180B. In some embodiments, the width W8 is from about 2000 nm to about 5000 nm. In some embodiments, the thickness t20 is from about 10 nm to about 20 nm. The dopant concentration of the first type doped region 195 is greater than that of the first type doped region 160. In some embodiments, the first type doped region 195 has about 1 × 10⁻⁶ nm. 18 cm -3 To approximately 1×10 20 cm -3 The dopant concentration. In some embodiments, the first type doped region 195 includes an n-type dopant (e.g., phosphorus) and may be referred to as an n-doped germanium region. In some embodiments, the first type doped region 195 includes a p-type dopant (e.g., boron) and may be referred to as a p-doped germanium region.

[0040] In some embodiments, the second type-doped region 190 is formed by: performing a photolithography process to form an implantation mask that exposes a region of the germanium layer 130 that overlaps with the interfaces between the first type-doped regions 145 and 160 and / or the interfaces between the first type-doped regions 145 and 155; and using the implantation mask to perform an implantation process to introduce a second type-doped agent into the exposed region of the germanium layer 130. In some embodiments, the first type-doped region 195 is formed by: performing a photolithography process to form an implantation mask that exposes a region of the germanium layer 130 located between polysilicon gates 180A and 180B; and using the implantation mask to perform an implantation process to introduce a first type-doped agent into the exposed region of the germanium layer 130. In some embodiments, the first type-doped region 195 is formed after the formation of the second type-doped region 190. In some embodiments, the first type-doped region 195 is formed before the formation of the second type-doped region 190. In some embodiments, an annealing process is performed after the formation of the first type-doped region 195 and / or the second type-doped region 190, for example, to activate the dopants therein and / or in other doped regions of the photosensitive device 100 (e.g., first type-doped region 145, first type-doped region 150, second type-doped region 155, first type-doped region 160, and / or first type-doped region 185). In some embodiments, the annealing process is rapid thermal annealing (RTA). In some embodiments, the annealing process exposes the photosensitive device 100 to heat at a temperature of about 700°C to about 900°C. In some embodiments, the annealing process is performed for a duration of about 10 seconds to about 30 seconds.

[0041] Figure 2 Provided in accordance with the aspects of this disclosure in experience and Figure 1A-1J A schematic top view and schematic cross-sectional view along line AA of a device region (e.g., device region 102A) of a photosensitive device 100 after associated manufacturing (and in some embodiments, additional manufacturing). For ease of understanding, Figure 2The oxide layer 140 and cap layer 135 are omitted in the top view. Device region 102A includes a germanium-based sensor with a germanium photodiode that can convert photons (e.g., electromagnetic radiation, such as light) into charge carriers (e.g., electrons and / or holes), which can be measured as current and / or voltage. The germanium photodiode is located in a silicon substrate 105. For example, a germanium layer 130 is enclosed by the silicon substrate 105 (e.g., the silicon substrate 105 is disposed along the sidewalls and bottom of the germanium layer 130), and the germanium layer 130 has a laterally diffused photodiode (LD-PD) formed therein through a pn junction between a second-type doped region 155 and a first-type doped region 145, for example, pn junction A (which may be referred to as the left pn junction) and pn junction B (which may be referred to as the right pn junction). The first, left floating voltage node (FN_L) and the second, right floating voltage node (FN_R) are connected to their respective type II diffusion regions 190, such that pn junction A and pn junction B are electrically connected to the first, left, and second, right floating voltage nodes through their respective type II diffusion regions 190. Leakage current (also known as dark current) from the germanium photodiode is reduced by inserting a doped silicon layer 120 between the germanium layer 130 and the silicon substrate 105. In some embodiments, the leakage current may be reduced by up to 1000% compared to conventional germanium-based sensors that do not have a doped silicon layer between the germanium photodiode and the silicon substrate. The germanium-based sensor in device region 102A also features a dual-gate junction field-effect transistor (JFET), which improves control of the germanium photodiode. For example, the gate of a dual-gate JFET is provided by a polysilicon gate 180A (and the underlying first-type doped region 185) and a polysilicon gate 180B (and the underlying first-type doped region 185), the channel of a dual-gate JFET is provided by a second-type doped region 155 (P-channel or N-channel (also referred to as channel layer and / or JFET channel)), and the source / drain region of a dual-gate JFET is provided by a second-type doped region 190 (P+ region or N+ region (also referred to as source / drain region)). The first and left gate voltage nodes (JFETG_L) and the second and right gate voltage nodes (JFETG_R) are respectively connected... Polysilicon gates 180A and 180B are connected. In the germanium-based sensor, a first-type doped region 160 serves as a passivation layer for the LD-PD, reducing leakage current at the surface of the germanium photodiode, and a first-type doped region 195 provides additional passivation for the pinned photodiode (PPD) (e.g., n-type PPD (NPPD) or p-type (PPPD)), which further reduces leakage current at the surface of the germanium photodiode. Furthermore, the first-type doped region 150 serves as an electronic lens in the germanium-based sensor, increasing the optical fill factor (FF) of the germanium-based sensor.For example, the first-type doped region 150 (i.e., the electron lens) can effectively guide or direct light to the ld-pd and the metal light-guiding structure, thereby eliminating the need for a back-side metal light-guiding structure (i.e., a metal mesh on the back surface of the silicon substrate 105 for guiding light to the ld-pd) in germanium-based sensors. This provides germanium-based sensors with a larger area on which light can be guided to the ld-pd (and thus a larger photosensitive area) compared to conventional sensors, thereby improving the optical fill factor. By reducing the leakage current of the germanium photodiode, increasing the optical fill factor of the germanium photodiode, and / or improving the control of the germanium photodiode with a dual-gate JFET, the germanium-based sensor with JFET exhibits better sensitivity, better conversion gain, and / or less noise than conventional germanium-based sensors. In some embodiments, the germanium-based sensor with JFET is a hole-sensing sensor. In such an embodiment, first-type doped regions 145, 150, 160, 185, and 195 are n-doped regions, while second-type doped regions 155 and 190 are p-doped regions. In a further embodiment, polysilicon gates 180A and 180B are n-doped polysilicon gates. In some embodiments, the germanium-based sensor with a JFET is an electronic sensing sensor. In such an embodiment, first-type doped regions 145, 150, 160, 185, and 195 are p-doped regions, while second-type doped regions 155 and 190 are n-doped regions. In a further embodiment, polysilicon gates 180A and 180B are p-doped polysilicon gates. Different embodiments may have different advantages, and no particular embodiment requires a specific advantage. For clarity, simplification has been provided. Figure 2 To better understand the inventive concept of this disclosure, additional features may be added to the device region 102A of the photosensitive device 100, and some features described below may be replaced, modified, or eliminated in other embodiments of the device region 102A of the photosensitive device 100.

[0042] Figure 3A-3J This is a schematic cross-sectional view of a portion or the entirety of a photosensitive device 200 (e.g., a germanium-based sensor with a junction-gate field-effect transistor) at various manufacturing stages according to various aspects of this disclosure. For clarity and simplicity, Figure 1A-1J The photosensitive device 100 and Figure 3A-3J Similar features of the photosensitive device 200 in the image are identified by the same reference numerals. Figure 3A-3J The fabrication of the photosensitive device 200 is similar in many ways to Figure 1A-1J The fabrication of the photosensitive device 100 differs in that the germanium photodiode of the photosensitive device 200 is fabricated and placed on the silicon substrate 105, rather than within the silicon substrate 105. For example, turning Figure 3A Fabrication begins with receiving a silicon substrate 105, depositing an oxide layer 205 on the silicon substrate 105, and forming a cavity 215 within the oxide layer 205. The oxide layer 205 comprises oxygen and, in some embodiments, includes another suitable component. For example, the oxide layer 205 may comprise silicon and oxygen (e.g., SiO2) and is referred to as a silicon oxide layer. The oxide layer 205 has a thickness t21, which, in some embodiments, is substantially the same as the desired depth (e.g., depth D) of the cavity 215. In some embodiments, the thickness t21 is about 900 nm to about 1500 nm. Any suitable deposition process (e.g., those described herein) is performed to form the oxide layer 205. Any suitable photolithography and etching processes (e.g., those described herein) are performed to pattern the oxide layer 205 to form the cavity 215. In contrast to the cavity 115, the cavity 215 extends through the oxide layer 205 and exposes the silicon substrate 205, such that the cavity 215 has sidewalls formed by the oxide layer 205 and a bottom formed by the silicon substrate 105. Figure 3B-3J Then, photosensitive device 300 is fabricated using photosensitive device 200, for example, by forming a doped silicon layer 120 that partially fills cavity 215. Figure 3B The remaining portion of the germanium layer 130 that forms the filling cavity 215 is formed on top of the doped silicon layer 120. Figure 3C A capping layer 135 is formed on top of the germanium layer 130. Figure 3D An oxide layer 140 is formed on the photosensitive device 300. Figure 3E Various doped regions (e.g., type I doped region 145, type I doped region 150, type II doped region 155, and type I doped region 160) are formed in the germanium layer 130. Figure 3F Polysilicon gates 180A and 180B are formed on the germanium layer 130. Figure 3G-3I A type I doped region 185 is formed in the germanium layer 130. Figure 3I ), and a second-type doped region 190 and a first-type doped region 195 are formed in the germanium layer 130. Figure 3J In some embodiments, the deposition process performed to form the doped silicon layer 120 in cavity 215 is a non-selective deposition process, for example, which can grow epitaxial silicon from both silicon substrate 105 and oxide layer 205. For clarity, simplified... Figure 3A-3JTo better understand the inventive concept of this disclosure. Additional features may be added to the photosensitive device 200, and some of the features described below may be replaced, modified, or eliminated in other embodiments of the photosensitive device 200.

[0043] Figure 4 Provided in accordance with the aspects of this disclosure in experience and Figure 3A-3J A schematic top view and schematic cross-sectional view along line AA of a device region (e.g., device region 102A) of a photosensitive device 200 after associated fabrication (and in some embodiments, additional fabrication). For ease of understanding, Figure 4 In the top view of the photosensitive device 200, the oxide layer 140 and the cap layer 135 are partially omitted. Figure 4 The device region 102A of the photosensitive device 200 is similar in many respects to Figure 2 The device region 102A of the photosensitive device 100 is shown. For example, device region 102 includes a germanium-based sensor configured to reduce leakage current of its germanium photodiode, increase the optical fill factor of its germanium photodiode, and / or improve control of its germanium photodiode with a dual-gate JFET, such that the germanium-based sensor exhibits better sensitivity than conventional germanium-based sensors. Furthermore, in the photosensitive device 200, leakage current from the germanium photodiode is further reduced by isolating the sidewalls of the germanium photodiode with an oxide layer 205. Different embodiments may have different advantages, and no particular advantage is required in any embodiment. For clarity, simplification has been implemented. Figure 4 To better understand the inventive concept of this disclosure, additional features may be added to the device region 102A of the photosensitive device 200, and some features described below may be replaced, modified, or eliminated in other embodiments of the device region 102A of the photosensitive device 200.

[0044] Figure 5 This is a schematic cross-sectional view of a portion or the entirety of the photosensitive device 300 according to various aspects of this disclosure. For clarity and simplicity, Figure 1A-1J The photosensitive device 100 and Figure 5 Similar features of the photosensitive device 300 are identified by the same reference numerals. The photosensitive device 300 is similar to the photosensitive device 100 in many respects, except that the first-type doped region 145 does not overlap with the first-type doped region 150. For example, the first-type doped region 145 extends to a depth D2 in the germanium layer 130, rather than a depth D3, such that the first-type doped region 145 and the first-type doped region 150 have an interface at a depth D2 in the germanium layer 130. For clarity, simplified diagrams have been provided. Figure 5To better understand the inventive concept of this disclosure. Additional features may be added to the photosensitive device 300, and some of the features described below may be replaced, modified, or eliminated in other embodiments of the photosensitive device 300.

[0045] Figure 6 This is a schematic cross-sectional view of a portion or the entirety of a photosensitive device 400 according to various aspects of this disclosure. For clarity and simplicity, Figure 3A-3J The photosensitive device 200 and Figure 6 Similar features of the photosensitive device 400 are identified by the same reference numerals. The photosensitive device 400 is similar to the photosensitive device 200 in many respects, the difference being that the first type doped region 145 does not overlap with the first type doped region 150. For example, the first type doped region 145 extends to a depth D2 in the germanium layer 130, rather than a depth D3, such that the first doped region 145 and the first type doped region 150 have an interface at a depth D2 in the germanium layer 130. For clarity, simplified diagrams have been provided. Figure 6 To better understand the inventive concept of this disclosure. Additional features may be added to the photosensitive device 400, and some of the features described below may be replaced, modified, or eliminated in other embodiments of the photosensitive device 400.

[0046] Figure 5 It is based on various aspects of this disclosure for manufacturing photosensitive devices (e.g., Figure 1A-1J , Figure 2 , Figure 3A-3J and Figure 4 A flowchart of a portion or all of method 500 (those depicted herein). Method 500 begins by forming a sensor cavity on a silicon substrate at block 505. Method 500 proceeds to forming an in-situ doped silicon layer that partially fills and linees the sensor cavity at block 510, forming a germanium layer that fills the remaining portion of the sensor cavity on top of the doped silicon layer at block 515, forming a photodiode and a junction field-effect transistor including a germanium layer at block 520 (wherein the junction field-effect transistor has a polysilicon gate), and forming a pinned photodiode passivation layer in the germanium layer at block 525. In some embodiments, self-diffusion is used to form a diffusion region under the polysilicon gate. For example, method 500 includes performing an annealing process on the polysilicon gate. For clarity, simplified diagrams have been provided. Figure 5 To better understand the inventive concept of this disclosure. Additional steps may be provided before, during, and after method 500, and for additional embodiments of method 500, some of the described steps may be moved, replaced, or eliminated.

[0047] The various doped regions described herein (e.g., first type doped region 145, first type doped region 150, second type doped region 155, first type doped region 160, first type doped region 185, second type doped region 190, and first type doped region 195) may include first type dopant and second type dopant, wherein a doped region is considered a first type doped region if the concentration of the first type dopant in the doped region is greater than the concentration of the second type dopant in the second type dopant (thus providing a doped region with first conductivity), and a doped region is considered a second type doped region if the concentration of the first type dopant in the doped region is less than the concentration of the second type dopant in the second type dopant (thus providing a doped region with second conductivity).

[0048] This disclosure provides numerous different embodiments, including hole-sensing photosensitive devices and electron-sensing photosensitive devices, such as those described herein. The disclosed photosensitive devices have dual-gate junction field-effect transistors for improved control and various doped regions for improved performance, such as electron lenses for increasing the optical fill factor, and / or channel layers and / or passivation layers for reducing leakage current, thereby improving performance.

[0049] An exemplary photosensitive device includes a silicon substrate, a germanium layer disposed on the silicon substrate, and a doped silicon layer disposed between the silicon substrate and the germanium layer. The photosensitive element further includes a first doped region, a second doped region, and a third doped region disposed in the germanium layer. The first doped region is disposed between the second and third doped regions. The first doped region includes a first type dopant. The second and third doped regions include a second type dopant. The photosensitive element further includes a fourth, fifth, and sixth doped region disposed in the germanium layer. The fourth doped region overlaps with a first interface between the first and second doped regions. The fifth doped region overlaps with a second interface between the first and third doped regions. The sixth doped region is disposed above the first doped region and between the fourth and fifth doped regions. The fourth and fifth doped regions include a first type dopant, and the sixth doped region includes a second type dopant. The photosensitive device further includes a polysilicon gate disposed above the sixth doped region. The polysilicon gate includes a second type dopant. The photosensitive element further includes a seventh doped region disposed in the germanium layer and below the polysilicon gate. The seventh doped region includes a second type dopant.

[0050] In some embodiments, the first type dopant is an n-type dopant and the second type dopant is a p-type dopant. In some embodiments, the first type dopant is a p-type dopant and the second type dopant is an n-type dopant. In some embodiments, a doped silicon layer is disposed between the sidewalls of the silicon substrate and the germanium layer and between the bottom of the silicon substrate and the germanium layer. In some embodiments, the doped silicon layer is further disposed between the oxide layer and the germanium layer. In some embodiments, the doped silicon layer is disposed between the sidewalls of the oxide layer and the germanium layer and between the bottom of the silicon substrate and the germanium layer.

[0051] In some embodiments, the photosensitive device further includes an eighth doped region and a ninth doped region disposed in the germanium layer. A second doped region is disposed above the eighth doped region. A third doped region is disposed above the ninth doped region. A first doped region is disposed above the eighth and ninth doped regions. The eighth and ninth doped regions include a type II dopant. In some embodiments, the second and third doped regions overlap with the eighth and ninth doped regions, respectively. In some embodiments, the polysilicon gate is a first polysilicon gate, and the photosensitive device further includes a second polysilicon gate disposed above the sixth doped region and an eighth doped region disposed in the germanium layer and below the second polysilicon gate. The first and second polysilicon gates are disposed between the fourth and fifth doped regions. The second polysilicon gate includes a type II dopant. A seventh doped region includes a type II dopant. In such embodiments, the photosensitive device may further include a ninth doped region disposed in the germanium layer and between the first and second polysilicon gates. The ninth doped region includes a type II dopant.

[0052] Another exemplary photosensitive device includes a silicon substrate and a germanium-based photodiode having a germanium layer disposed on the silicon substrate. The germanium-based photodiode further comprises: two first doped regions having a first conductivity type and disposed in the germanium layer; two second doped regions having a first conductivity type and disposed in the germanium layer and respectively on the two first doped regions; a third doped region having a second conductivity type and disposed in the germanium layer and between the two first doped regions and the two second doped regions; and a fourth doped region having a first conductivity type and disposed in the germanium layer and on the third doped region. A doped silicon layer is disposed between the silicon substrate and the germanium layer of the germanium-based photodiode, separating the silicon substrate from the germanium layer of the germanium-based photodiode. The photosensitive device also includes two doped polysilicon gates disposed on the third doped region. The fourth doped region is disposed between the two doped polysilicon gates. In some embodiments, the first conductivity type is n-type and the second conductivity type is p-type. In some embodiments, the first conductivity type is p-type and the second conductivity type is n-type. In some embodiments, the photosensitive device further includes a silicon cap layer disposed on the germanium layer. In such embodiments, two second doped regions and a fourth doped region are also disposed within the silicon capping layer. In some embodiments, the photosensitive device further includes two fifth doped regions having a first conductivity type and disposed within the germanium layer, respectively below the two doped polysilicon gates. In some embodiments, the photosensitive device further includes an oxide layer disposed on the silicon substrate. In such embodiments, the doped silicon layer is also disposed between the oxide layer and the germanium layer, separating the oxide layer and the germanium layer.

[0053] An exemplary method for forming a photosensitive device includes: forming a sensor cavity on a silicon substrate; forming an in-situ doped silicon layer that partially fills and linees the sensor cavity; forming a germanium layer on the in-situ doped silicon layer, the germanium layer filling the remaining portion of the sensor cavity; and forming a photodiode including the germanium layer and a junction field-effect transistor including the germanium layer. The junction field-effect transistor has a polysilicon gate. In some embodiments, forming the junction field-effect transistor includes performing a diffusion process to diffuse a dopant from the polysilicon gate into the germanium layer. In some embodiments, forming the sensor cavity includes etching the silicon substrate. In some embodiments, the method includes forming an oxide layer on the silicon substrate, wherein forming the sensor cavity includes etching the oxide layer to expose the silicon substrate.

[0054] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should appreciate that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

[0055] Example

[0056] Example 1. A photosensitive device, comprising: a silicon substrate; a germanium layer disposed on the silicon substrate; a doped silicon layer disposed between the silicon substrate and the germanium layer; a first doped region, a second doped region, and a third doped region disposed in the germanium layer, wherein the first doped region is disposed between the second doped region and the third doped region, the first doped region comprising a first type dopant, and the second doped region and the third doped region comprising a second type dopant; a fourth doped region, a fifth doped region, and a sixth doped region disposed in the germanium layer, wherein the fourth doped region overlaps with a first interface between the first doped region and the second doped region, the fifth doped region overlaps with a second interface between the first doped region and the third doped region, the sixth doped region is disposed on the first doped region and between the fourth doped region and the fifth doped region, the fourth doped region and the fifth doped region comprising a first type dopant, and the sixth doped region comprising a second type dopant. A polysilicon gate is disposed above the sixth doped region, wherein the polysilicon gate includes the second type dopant; and a seventh doped region is disposed in the germanium layer and below the polysilicon gate, wherein the seventh doped region includes the second type dopant.

[0057] Example 2. The photosensitive device according to Example 1 further includes an eighth doped region and a ninth doped region disposed in the germanium layer, wherein a second doped region is disposed above the eighth doped region, a third doped region is disposed above the ninth doped region, a first doped region is disposed above the eighth doped region and the ninth doped region, and the eighth doped region and the ninth doped region include a second type dopant.

[0058] Example 3. The photosensitive device according to Example 2, wherein the second doped region and the third doped region overlap with the eighth doped region and the ninth doped region, respectively.

[0059] Example 4. The photosensitive device according to Example 1, wherein the polysilicon gate is a first polysilicon gate, and the photosensitive device further includes a second polysilicon gate disposed above the sixth doped region and an eighth doped region disposed in the germanium layer below the second polysilicon gate, wherein the first polysilicon gate and the second polysilicon gate are disposed between the fourth doped region and the fifth doped region, the second polysilicon gate includes a second type dopant, and the seventh doped region includes a second type dopant.

[0060] Example 5. The photosensitive device according to Example 4 further includes a ninth doped region disposed in the germanium layer and between the first polysilicon gate and the second polysilicon gate, wherein the ninth doped region includes a second type dopant.

[0061] Example 6. The photosensitive device according to Example 1, wherein the doped silicon layer is disposed between the sidewalls of the silicon substrate and the germanium layer and between the bottom of the silicon substrate and the germanium layer.

[0062] Example 7. The photosensitive device according to Example 1, wherein the doped silicon layer is further disposed between the oxide layer and the germanium layer.

[0063] Example 8. The photosensitive device according to Example 7, wherein the doped silicon layer is disposed between the sidewalls of the oxide layer and the germanium layer and between the silicon substrate and the bottom of the germanium layer.

[0064] Example 9. The photosensitive device according to Example 1, wherein the first type dopant is an n-type dopant and the second type dopant is a p-type dopant.

[0065] Example 10. The photosensitive device according to Example 1, wherein the first type dopant is a p-type dopant and the second type dopant is an n-type dopant.

[0066] Example 11. A photosensitive device, comprising: a silicon substrate; a germanium-based photodiode having: a germanium layer disposed on the silicon substrate; two first doped regions having a first conductivity type and disposed in the germanium layer; two second doped regions having the first conductivity type and respectively disposed in the germanium layer and on the two first doped regions; a third doped region having a second conductivity type and disposed in the germanium layer and on the two first doped regions and between the two second doped regions; and a fourth doped region having the first conductivity type and disposed in the germanium layer and on the third doped region; a doped silicon layer disposed between the silicon substrate and the germanium layer of the germanium-based photodiode, and spacing the silicon substrate and the germanium layer of the germanium-based photodiode; and two doped polysilicon gates disposed on the third doped region, wherein the fourth doped region is disposed between the two doped polysilicon gates.

[0067] Example 12. The photosensitive device according to Example 11, wherein the first conductivity type is n-type and the second conductivity type is p-type.

[0068] Example 13. The photosensitive device according to Example 11, wherein the first conductivity type is p-type and the second conductivity type is n-type.

[0069] Example 14. The photosensitive device according to Example 11 further includes a silicon cap layer disposed on the germanium layer, wherein the two second doped regions and the fourth doped region are also disposed in the silicon cap layer.

[0070] Example 15. The photosensitive device according to Example 11 further includes two fifth doped regions having the first conductivity type and respectively disposed in the germanium layer and below the two doped polysilicon gates.

[0071] Example 16. The photosensitive device according to Example 11 further includes an oxide layer disposed on the silicon substrate, wherein the doped silicon layer is further disposed between the oxide layer and the germanium layer of the germanium-based photodiode, and separates the oxide layer from the germanium layer of the germanium-based photodiode.

[0072] Example 17. A method for forming a photosensitive device, the method comprising: forming a sensor cavity on a silicon substrate; forming an in-situ doped silicon layer, the in-situ doped silicon layer partially filling and lining the sensor cavity; forming a germanium layer on the in-situ doped silicon layer, the germanium layer filling the remaining portion of the sensor cavity; and forming a photodiode and a junction field-effect transistor including the germanium layer, wherein the junction field-effect transistor has a polysilicon gate.

[0073] Example 18. The method according to Example 17, wherein forming the junction field-effect transistor includes performing a diffusion process to diffuse a dopant from the polysilicon gate into the germanium layer.

[0074] Example 19. The method of Example 17 further includes forming an oxide layer on the silicon substrate, wherein forming the sensor cavity includes etching the oxide layer to expose the silicon substrate.

[0075] Example 20. The method according to Example 17, wherein forming the sensor cavity includes etching the silicon substrate.

Claims

1. A photosensitive device, comprising: silicon substrate; A germanium layer is disposed on the silicon substrate; A doped silicon layer is disposed between the silicon substrate and the germanium layer; A first doped region, a second doped region, and a third doped region are disposed in the germanium layer, wherein the first doped region is disposed between the second doped region and the third doped region, the first doped region includes a first type dopant, and the second doped region and the third doped region include a second type dopant. A fourth doped region, a fifth doped region, and a sixth doped region are disposed in the germanium layer, wherein the fourth doped region overlaps with a first interface between the first doped region and the second doped region, the fifth doped region overlaps with a second interface between the first doped region and the third doped region, and the sixth doped region is disposed above the first doped region and between the fourth doped region and the fifth doped region. The fourth doped region and the fifth doped region include a first type of dopant, and the sixth doped region includes a second type of dopant. A polysilicon gate is disposed above the sixth doped region, wherein the polysilicon gate includes the second type of dopant; and A seventh doped region is disposed in the germanium layer and below the polysilicon gate, wherein the seventh doped region includes the second type of dopant.

2. The photosensitive device according to claim 1 further includes an eighth doped region and a ninth doped region, wherein the eighth doped region and the ninth doped region are disposed in the germanium layer, wherein, The second doped region is disposed above the eighth doped region, the third doped region is disposed above the ninth doped region, the first doped region is disposed above the eighth and ninth doped regions, and the eighth and ninth doped regions include the second type of dopant.

3. The photosensitive device according to claim 2, wherein, The second doped region and the third doped region overlap with the eighth doped region and the ninth doped region, respectively.

4. The photosensitive device according to claim 1, wherein, The polysilicon gate is a first polysilicon gate, and the photosensitive device further includes a second polysilicon gate disposed above the sixth doped region and an eighth doped region disposed in the germanium layer below the second polysilicon gate, wherein the first polysilicon gate and the second polysilicon gate are disposed between the fourth doped region and the fifth doped region, the second polysilicon gate includes a second type dopant, and the seventh doped region includes a second type dopant.

5. The photosensitive device according to claim 4, further comprising a ninth doped region, the ninth doped region being disposed in the germanium layer and between the first polysilicon gate and the second polysilicon gate, wherein, The ninth doped region includes the second type of dopant.

6. The photosensitive device according to claim 1, wherein, The doped silicon layer is disposed between the sidewalls of the silicon substrate and the germanium layer and between the bottom of the silicon substrate and the germanium layer.

7. The photosensitive device according to claim 1, wherein, The doped silicon layer is also disposed between the oxide layer and the germanium layer.

8. The photosensitive device according to claim 7, wherein, The doped silicon layer is disposed between the sidewalls of the oxide layer and the germanium layer, and between the silicon substrate and the bottom of the germanium layer.

9. The photosensitive device according to claim 1, wherein, The first type of dopant is an n-type dopant, and the second type of dopant is a p-type dopant.

10. The photosensitive device according to claim 1, wherein, The first type of dopant is a p-type dopant, and the second type of dopant is an n-type dopant.

11. A photosensitive device, comprising: silicon substrate; A germanium-based photodiode, wherein the germanium-based photodiode has: A germanium layer is disposed on the silicon substrate. Two first doped regions, each having a first conductivity type, are disposed within the germanium layer. Two second doped regions, having the first conductivity type, are respectively disposed in the germanium layer and above the two first doped regions. A third doped region, having a second conductivity type, is disposed within the germanium layer and above the two first doped regions and between the two second doped regions. A fourth doped region having the first conductivity type is disposed in the germanium layer and above the third doped region; A doped silicon layer is disposed between the silicon substrate and the germanium layer of the germanium-based photodiode, and spaced apart from the silicon substrate and the germanium layer of the germanium-based photodiode; as well as Two doped polysilicon gates are disposed above the third doped region, wherein the fourth doped region is disposed between the two doped polysilicon gates.

12. The photosensitive device according to claim 11, wherein, The first conductivity type is n-type, and the second conductivity type is p-type.

13. The photosensitive device according to claim 11, wherein, The first conductivity type is p-type, and the second conductivity type is n-type.

14. The photosensitive device according to claim 11, further comprising a silicon cap layer disposed on the germanium layer, wherein, The two second doped regions and the fourth doped region are also disposed in the silicon capping layer.

15. The photosensitive device of claim 11 further comprises two fifth doped regions having the first conductivity type and respectively disposed in the germanium layer and below the two doped polysilicon gates.

16. The photosensitive device according to claim 11, further comprising an oxide layer disposed on the silicon substrate, wherein, The doped silicon layer is also disposed between the oxide layer and the germanium layer of the germanium-based photodiode, and separates the oxide layer from the germanium layer of the germanium-based photodiode.

17. A method for forming a photosensitive device, the method comprising: A sensor cavity is formed on a silicon substrate; An in-situ doped silicon layer is formed, which partially fills and liner the sensor cavity; A germanium layer is formed on top of the in-situ doped silicon layer, and the germanium layer fills the remaining portion of the sensor cavity; Two first doped regions, two second doped regions, a third doped region, and a fourth doped region are formed in the germanium layer. The two first doped regions have a first conductivity type; the two second doped regions have the first conductivity type and are disposed above the two first doped regions; the third doped region has a second conductivity type and is disposed above the two first doped regions and between the two second doped regions; and the fourth doped region has the first conductivity type and is disposed above the third doped region. A photodiode and a junction field-effect transistor comprising the germanium layer are formed, wherein the junction field-effect transistor has a polysilicon gate.

18. The method according to claim 17, wherein, Forming the junction field-effect transistor includes performing a diffusion process to diffuse a dopant from the polysilicon gate into the germanium layer.

19. The method of claim 17, further comprising forming an oxide layer on the silicon substrate, wherein, Forming the sensor cavity includes etching the oxide layer to expose the silicon substrate.

20. The method of claim 17, wherein, Forming the sensor cavity includes etching the silicon substrate.

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