Display panel and manufacturing method thereof, and display terminal

Abstract

The present invention provides a display panel and a preparation method thereof, and a display terminal. The display panel comprises a substrate layer, a first metal layer, an active layer and a second metal layer; the first metal layer comprises a first electrode plate of a storage capacitor; the active layer comprises a second electrode plate of the storage capacitor; the second metal layer comprises a third electrode plate of the storage capacitor, and the third electrode plate is electrically connected to the first electrode plate; wherein a barrier layer is arranged on a surface of the active layer facing the second metal layer, the barrier layer comprises a first barrier portion, and the first barrier portion is located on the second electrode plate; the present invention arranges a barrier layer on a surface of the active layer facing the second metal layer, the first barrier portion of the barrier layer can block the deconductivity of the second electrode plate, thereby preparing a three-layer sandwich capacitor structure under the premise of ensuring the flatness of the pixel light-emitting area, so that the capacitance value of the storage capacitor meets the display driving requirements of the display panel, so as to improve the display performance of the display panel.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a manufacturing method thereof, and a display terminal. Background Art

[0002] The pixel driving circuit of the existing organic light emitting diode (OLED) display panel generally includes a switch thin film transistor (Switch TFT), a driving thin film transistor (Driving TFT) and a storage capacitor (Cst). Its array substrate process traditionally uses a top-gate thin film transistor (Top-gate TFT) and a light-emitting material evaporation (Evaporation) process. In order to improve the mass production characteristics of OLED display panels and reduce the cost of the array substrate process, one of the current development directions is to use a gate-source-drain onelayer (GSD) process that can reduce the yellow light process. At the same time, combined with inkjet printing (IJP) technology, the mass production feasibility of OLED display panels can be further improved.

[0003] The current bottom emission OLED display panel needs to set up a light-emitting area independent of the circuit area, which is not conducive to improving the aperture ratio; the top emission OLED display panel does not need to set up an independent light-emitting area, which can achieve a higher aperture ratio and improve the display performance of the OLED display panel. The top emission GSD process OLED display panel adopts the design of setting the storage capacitor under the light-emitting device to improve the pixel resolution.

[0004] Since the IJP technology has very high requirements for the flatness of the pixel light-emitting area, the current GSD process OLED display panel usually adopts the upper and lower plate capacitor structure of the light-shielding layer (LS) / active layer (IGZO) to ensure the driving performance of the OLED display panel, so that there is no need to punch holes in the flattening layer, so that the flatness of the pixel light-emitting area can be guaranteed. However, as the resolution increases, the capacitance value of the upper and lower plate capacitor structure cannot meet the display driving requirements of the OLED display panel, which in turn affects the display performance of the OLED display panel. If a three-layer sandwich capacitor structure with an additional layer of plate between the active layer and the flattening layer is used to increase the capacitance value, the active layer will be deconductive and unable to conduct electricity. Therefore, it is necessary to improve this defect. Summary of the invention

[0005] The embodiment of the present invention provides a display panel for solving the technical problem that a capacitor plate is added between an active layer and a planarization layer in the display panel of the prior art, which causes the active layer to be deconductive and unable to conduct electricity.

[0006] An embodiment of the present invention provides a display panel, including a substrate layer, a first metal layer, an active layer and a second metal layer; the first metal layer is located on the substrate layer, and the first metal layer includes a first electrode plate of a storage capacitor; the active layer is located on the first metal layer, and the active layer includes a second electrode plate of the storage capacitor; the second metal layer is located on the active layer, and the second metal layer includes a third electrode plate of the storage capacitor, and the third electrode plate is electrically connected to the first electrode plate; wherein a barrier layer is provided on a surface of the active layer facing the second metal layer, and the barrier layer includes a first barrier portion, and the first barrier portion is located on the second electrode plate.

[0007] In the display panel provided by the embodiment of the present invention, in a direction perpendicular to the light emitting side of the display panel, the width of the first blocking portion and the width of the second electrode plate are both greater than the width of the first electrode plate.

[0008] In the display panel provided by the embodiment of the present invention, the second electrode plate includes a conductor portion and semiconductor portions located on both sides of the conductor portion, and the orthographic projection of the first electrode plate on the second electrode plate is located on the conductor portion.

[0009] In the display panel provided by the embodiment of the present invention, the first blocking portion covers a surface of the second electrode plate that is away from the first electrode plate and a side surface of the second electrode plate.

[0010] In the display panel provided by an embodiment of the present invention, the active layer includes an active pattern, the active pattern includes a channel portion and a source contact portion and a drain contact portion located on both sides of the channel portion; the second metal layer includes a gate, a source and a drain, the orthographic projection of the gate on the active pattern is located on the channel portion, the source is electrically connected to the source contact portion, and the drain is electrically connected to the drain contact portion.

[0011] In the display panel provided by the embodiment of the present invention, the blocking layer includes a second blocking portion and a third blocking portion, the second blocking portion is located on the source contact portion, and the third blocking portion is located on the drain contact portion.

[0012] An embodiment of the present invention provides a method for preparing a display panel, comprising: forming a first metal layer on a substrate layer; patterning the first metal layer to form a first electrode plate of a storage capacitor; forming an active layer on the first metal layer; forming a blocking material layer on a surface of the active layer away from the first metal layer; patterning the active layer to form a second electrode plate of the storage capacitor, and patterning the blocking material layer to form a first blocking portion, the first blocking portion being located on the second electrode plate; forming a second metal layer on the first blocking portion, patterning the second metal layer to form a third electrode plate of the storage capacitor, the third electrode plate being electrically connected to the first electrode plate.

[0013] In the method for preparing a display panel provided in an embodiment of the present invention, the active layer is patterned to form a second electrode plate of the storage capacitor, and the blocking material layer is patterned to form a first blocking portion, including: the active layer is patterned to form a conductor structure and the second electrode plate of the storage capacitor, and the blocking material layer is patterned and annealed to form a first blocking portion.

[0014] In the method for preparing a display panel provided in an embodiment of the present invention, the method further includes: forming a gate insulating layer on a surface of the first blocking portion on a side away from the active layer and on a surface of the active layer on a side away from the first metal layer; annealing the gate insulating layer, deconducting the area where the conductor structure contacts the gate insulating layer to form a semiconductor structure, and deconducting the area where the second electrode contacts the gate insulating layer to form a semiconductor portion; forming a first contact hole and a second contact hole on the gate insulating layer to expose the semiconductor structure; and conducting the semiconductor structure in the first contact hole and the second contact hole to form a source contact portion and a drain contact portion.

[0015] An embodiment of the present invention further provides a display terminal, comprising a terminal body and the above-mentioned display panel, wherein the terminal body and the display panel are combined into one body.

[0016] Beneficial effects: A display panel provided by an embodiment of the present invention comprises a substrate layer, a first metal layer, an active layer and a second metal layer; the first metal layer is located on the substrate layer, and the first metal layer comprises a first electrode plate of a storage capacitor; the active layer is located on the first metal layer, and the active layer comprises a second electrode plate of the storage capacitor; the second metal layer is located on the active layer, and the second metal layer comprises a third electrode plate of the storage capacitor, and the third electrode plate is electrically connected to the first electrode plate; wherein a barrier layer is arranged on a surface of the active layer facing the second metal layer, and the barrier layer comprises a first barrier portion, and the first barrier portion is arranged on the second electrode plate; the present invention arranges a barrier layer on a surface of the active layer facing the second metal layer, and the first barrier portion of the barrier layer can block the deconductivity of the second electrode plate, thereby preparing a three-layer sandwich capacitor structure under the premise of ensuring the flatness of the pixel light-emitting area, so that the capacitance value of the storage capacitor meets the display driving requirements of the OLED display panel, so as to improve the display performance of the OLED display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for describing the embodiments are briefly introduced below.

[0018] Figure 1 It is a basic structural diagram of a display panel in the prior art.

[0019] Figure 2 It is a basic structural diagram of another display panel in the prior art.

[0020] Figure 3 It is a schematic diagram of the basic structure of a display panel provided by an embodiment of the present invention.

[0021] Figure 4 It is a basic structural schematic diagram of another display panel provided by an embodiment of the present invention.

[0022] Figure 5 It is a flow chart of a method for manufacturing a display panel provided in an embodiment of the present invention.

[0023] Figure 6a to Figure 6g It is a basic structural schematic diagram of each component in the manufacturing process flow of the display panel provided by an embodiment of the present invention.

[0024] Figure 7a to Figure 7e Is Figure 6a to Figure 6b Schematic diagram of the basic structure of each component in the process flow.

[0025] Figure 8a to Figure 8c Is Figure 6b to Figure 6c Schematic diagram of the basic structure of each component in the process flow. DETAILED DESCRIPTION

[0026] The following will be combined with the accompanying drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. In the drawings, for the sake of clarity and ease of understanding and description, the sizes and thicknesses of the components shown in the drawings are not in proportion.

[0027] like Figure 1 As shown in FIG. 1 , a basic structural diagram of a display panel of the prior art is shown. The display panel of the prior art usually uses a light shielding layer (LS) and an active layer (IGZO) as the upper and lower plates of C1, so that there is no need to drill holes in the flattening layer, so that the flatness of the pixel light-emitting area can be guaranteed. However, as the resolution increases, the capacitance value of C1 cannot meet the display driving requirements of the display panel, thereby affecting the display performance of the display panel.

[0028] like Figure 2 As shown, it is a basic structural schematic diagram of another display panel in the prior art. Another display panel in the prior art usually uses a light shielding layer (LS), an active layer (IGZO) and an anode layer (Anode) as a three-layer electrode plate of C2. However, the inkjet printing technology has very high requirements on the flatness of the pixel light-emitting area. If the structure of C2 is adopted, in order to increase the capacitance value of C2, it is inevitable to open a hole in the flattening layer in the pixel opening area, which will cause the flatness to deteriorate and affect the yield of the display panel. If a three-layer sandwich capacitor structure with an additional electrode plate between the active layer and the flattening layer is used to increase the capacitance value, the active layer will be deconductive and thus unable to conduct electricity. The embodiment of the present invention can solve the above defects.

[0029] like Figure 3 As shown, it is a schematic diagram of the basic structure of a display panel provided in an embodiment of the present invention, wherein the display panel comprises a substrate layer 10, a first metal layer 20, an active layer 40 and a second metal layer 70; the first metal layer 20 is located on the substrate layer 10, and the first metal layer 20 comprises a first electrode 201 of a storage capacitor; the active layer 40 is located on the first metal layer 20, and the active layer 40 comprises a second electrode 401 of the storage capacitor; the second metal layer 70 is located on the active layer 40, and the second metal layer 70 comprises a third electrode 701 of the storage capacitor, and the third electrode 701 is electrically connected to the first electrode 201; wherein a barrier layer 50 is provided on a surface of the active layer 40 facing the second metal layer 70, and the barrier layer 50 comprises a first barrier portion 501, and the first barrier portion 501 is located on the second electrode 401.

[0030] It should be noted that the embodiment of the present invention increases the capacitance value of the storage capacitor by electrically connecting the third electrode plate 701 to the first electrode plate 201 to form a parallel capacitor structure (the capacitor formed by the first electrode plate 201 and the second electrode plate 401 is connected in parallel with the capacitor formed by the second electrode plate 401 and the third electrode plate 701). Among them, only the film layer structure is shown in the drawings of the specification, and the wiring connection is not shown.

[0031] It can be understood that the present invention sets a blocking layer 50 on the surface of the active layer 40 facing the second metal layer 70. The first blocking portion 501 of the blocking layer 50 can block the deconductivity of the second electrode 401, thereby preparing a three-layer sandwich capacitor structure while ensuring the flatness of the pixel light-emitting area, so that the capacitance value of the storage capacitor meets the display driving requirements of the display panel, so as to improve the display performance of the display panel.

[0032] It should be noted that the barrier layer 50 can block H and O elements, and can keep the active layer 40 thereunder conductive. The material of the barrier layer 50 is, for example, dense aluminum oxide. The material of the active layer 40 is metal oxide, such as indium gallium zinc oxide (IGZO).

[0033] In one embodiment, in a direction perpendicular to the light-emitting side of the display panel, the width of the first blocking portion 501 and the width of the second electrode plate 401 are both greater than the width of the first electrode plate 201 .

[0034] It can be understood that, in this embodiment, by setting the width of the first blocking portion 501 and the width of the second electrode plate 401 to be greater than the width of the first electrode plate 201, the facing area between the first electrode plate 201 and the second electrode plate 401 can be increased, and the capacitance value of the capacitor formed by the first electrode plate 201 and the second electrode plate 401 can be increased.

[0035] In one embodiment, the second electrode plate 401 includes a conductor portion 4011 and semiconductor portions 4012 located on both sides of the conductor portion 4011 , and the orthographic projection of the first electrode plate 201 on the second electrode plate 401 is located on the conductor portion 4011 .

[0036] It can be understood that since the first blocking portion 501 is located on the second electrode plate 401, the first blocking portion 501 does not cover the side of the second electrode plate 401. Therefore, the area where the side of the second electrode plate 401 contacts the gate insulating layer 60 will be degenerated and conductive to form a semiconductor portion 4012, and the semiconductor portion 4012 cannot conduct electricity. In this embodiment, by setting the orthographic projection of the first electrode plate 201 on the second electrode plate 401 on the conductor portion 4011, the facing area of ​​the first electrode plate 201 and the conductor portion 4011 of the second electrode plate 401 can be maximized, so as to increase the capacitance value of the capacitor formed by the first electrode plate 201 and the second electrode plate 401.

[0037] In one embodiment, the active layer 40 includes an active pattern 402, the active pattern 402 includes a channel portion 4021 and a source contact portion 4022 and a drain contact portion 4023 located on both sides of the channel portion 4021; the second metal layer 70 includes a gate 702, a source 703 and a drain 704, the orthographic projection of the gate 702 on the active pattern 402 is located on the channel portion 4021, the source 703 is electrically connected to the source contact portion 4022, and the drain 704 is electrically connected to the drain contact portion 4023.

[0038] It is understandable that the second plate 401 of the storage capacitor and the active pattern 402 can be formed in one photomask process, and the third plate 701 of the storage capacitor and the gate 702, source 703 and drain 704 can be formed in one photomask process. Therefore, the display panel provided by the embodiment of the present invention does not add any additional photomask process, and does not cause cost increase. Moreover, the third plate 701 of the storage capacitor and the gate 702, source 703 and drain 704 are arranged in the same layer, and there is no need to punch holes in the flattening layer 90, which can ensure the flatness of the pixel light-emitting area and improve the yield of inkjet printing.

[0039] In one embodiment, the blocking layer 50 includes a second blocking portion 502 and a third blocking portion 503 , wherein the second blocking portion 502 is located on the source contact portion 4022 , and the third blocking portion 503 is located on the drain contact portion 4023 .

[0040] It can be understood that in this embodiment, by setting the second blocking portion 502 and the third blocking portion 503 on the upper surface of the active pattern 402, the second blocking portion 502 and the third blocking portion 503 can block the deconductive polarization of the active pattern 402 below, thereby increasing the lateral area of ​​the source contact portion 4022 and the drain contact portion 4023, improving the conductive effect between the source 703 and the source contact portion 4022, and improving the conductive effect between the drain 704 and the drain contact portion 4023.

[0041] In one embodiment, the display panel further includes a buffer layer 30, a passivation layer 80, an anode layer 12, a pixel definition layer 13, an organic light emitting layer 14, and a cathode layer 15. The first metal layer 20 further includes a light shielding layer 202, and the orthographic projection of the channel portion 4021 on the first metal layer 20 is located on the light shielding layer 202. The buffer layer 30 is located between the first metal layer 20 and the active layer 40. The active pattern 402 also includes a semiconductor structure 42 located at one end of the source contact portion 4022 away from the channel portion 4021 and one end of the drain contact portion 4023 away from the channel portion 4021. The source 703 overlaps the source contact portion 4022 through the first contact hole 601, and the drain 704 overlaps the drain contact portion 4023 through the second contact hole 602. The passivation layer 80 is located between the second metal layer 70 and the planarization layer 90. The anode layer 12 is located on the planarization layer 90, and the anode layer 12 is electrically connected to the source electrode 703 through the fourth contact hole 11. The pixel definition layer 13 is located on the planarization layer 90 and the anode layer 12, and the pixel definition layer 13 includes a plurality of pixel openings. The organic light emitting layer 14 is located on the anode layer 12 in the pixel opening. The cathode layer 15 is located on the organic light emitting layer 14 and the pixel definition layer 13.

[0042] Next, see Figure 4 , is a basic structural diagram of another display panel provided by an embodiment of the present invention, and Figure 3 The difference is that, in this embodiment, the first blocking portion 501 covers a surface of the second electrode plate 401 that is away from the first electrode plate 201 and a side surface of the second electrode plate 401 .

[0043] It can be understood that in this embodiment, by making the first blocking portion 501 cover the upper surface and the side surface of the second electrode plate 401, it is possible to prevent the second electrode plate 401 from forming a semiconductor portion 4012 (such as Figure 3 ), thereby reducing the width of the second electrode plate 401 in a direction perpendicular to the light-emitting side of the display panel to improve the resolution of the display panel.

[0044] In one embodiment, the second blocking portion 502 covers a side surface of the source contact portion 4022 away from the first metal layer 20 and a side surface of the source contact portion 4022 away from one end of the channel portion 4021, and the third blocking portion 503 covers a side surface of the drain contact portion 4023 away from the first metal layer 20 and a side surface of the drain contact portion 4023 away from one end of the channel portion 4021, so as to prevent the semiconductor structure 42 (such as Figure 3 ) to further increase the lateral area of ​​the source contact portion 4022 and the drain contact portion 4023, improve the conductive effect between the source 703 and the source contact portion 4022, and improve the conductive effect between the drain 704 and the drain contact portion 4023.

[0045] Next, see Figure 5 , is a flow chart of a method for manufacturing a display panel provided in an embodiment of the present invention, the manufacturing method comprising:

[0046] S1, forming a first metal layer on the substrate layer;

[0047] S2, the first metal layer is patterned to form a first electrode plate of a storage capacitor;

[0048] S3, forming an active layer on the first metal layer;

[0049] S4, forming a barrier material layer on a surface of the active layer away from the first metal layer;

[0050] S5, the active layer is patterned to form a second electrode plate of the storage capacitor, and the barrier material layer is patterned to form a first barrier portion, wherein the first barrier portion is located on the second electrode plate;

[0051] S6. Form a second metal layer on the first blocking portion, wherein the second metal layer is patterned to form a third electrode plate of the storage capacitor, and the third electrode plate is electrically connected to the first electrode plate.

[0052] It can be understood that the present invention forms a blocking material layer on the surface of the active layer away from the first metal layer. The first blocking portion formed by patterning the blocking material layer can block the deconductive polarization of the second electrode, thereby preparing a three-layer sandwich capacitor structure while ensuring the flatness of the pixel light-emitting area, so that the capacitance value of the storage capacitor meets the display driving requirements of the display panel, so as to improve the display performance of the display panel.

[0053] It should be noted that the first blocking portion can block H and O elements, and can keep the conductive properties of the second electrode below it. The material of the first blocking portion is, for example, dense aluminum oxide. The material of the active layer is a metal oxide, such as indium gallium zinc oxide (IGZO). The blocking material layer is, for example, aluminum. In the process of forming an aluminum film on IGZO, the aluminum film captures oxygen in the IGZO to form oxygen vacancies to achieve the first conductorization of IGZO. After completing the patterning process in step S5, the aluminum film is annealed to form dense aluminum oxide (i.e., the first blocking portion).

[0054] In one embodiment, the step S5 includes: patterning the active layer to form a conductor structure and a second electrode plate of the storage capacitor, and patterning and annealing the barrier material layer to form a first barrier portion.

[0055] It can be understood that after step S5, the active layer is conductorized to form a conductor structure and a second electrode, and the barrier material layer is patterned and annealed to form a first barrier, which can block the deconductivity of the second electrode thereunder.

[0056] In one embodiment, the step S5 and the step S6 also include: forming a gate insulating layer on a surface of the first blocking portion away from the active layer and a surface of the active layer away from the first metal layer; annealing the gate insulating layer, deconducting the area where the conductor structure contacts the gate insulating layer to form a semiconductor structure, and deconducting the area where the second electrode contacts the gate insulating layer to form a semiconductor portion; forming a first contact hole and a second contact hole on the gate insulating layer to expose the semiconductor structure; and conducting the semiconductor structure in the first contact hole and the second contact hole to form a source contact portion and a drain contact portion.

[0057] It can be understood that since a gate insulating layer needs to be formed on the active layer and the first blocking portion, the oxygen in the gate insulating layer will diffuse into the active layer during the annealing process, so that the area where the conductor structure contacts the gate insulating layer is deconducted to form a semiconductor structure, and the area where the second electrode contacts the gate insulating layer is deconducted to form a semiconductor portion. Subsequently, a first contact hole and a second contact hole are formed on the gate insulating layer on the semiconductor structure, and the semiconductor structure in the first contact hole and the second contact hole is conductorized (second conductorization) to form a source contact portion and a drain contact portion. The semiconductor structure not exposed between the first contact hole and the second contact hole is the channel portion, and thus the active pattern is prepared.

[0058] For details, please refer to Figure 6a to Figure 6g , which is a basic structural diagram of each component in the manufacturing process of the display panel provided by the embodiment of the present invention, firstly, Figure 6a As shown, a first metal layer 20 is formed on the substrate layer 10, and the first metal layer 20 is patterned to form a light shielding layer 202 and a first electrode 201 of the storage capacitor. The first metal layer 20 is divided into three layers, the lower layer contains one or more alloys of Mo, Ti, and Ni, the middle layer is Cu or Cu alloy, and the upper layer contains one or more alloys of Mo, Ti, and Ni. The thickness of the lower layer ranges from 50 to 500 angstroms, the thickness of the middle layer ranges from 2000 to 10000 angstroms, and the thickness of the upper layer ranges from 50 to 500 angstroms.

[0059] Next, if Figure 6bAs shown, a buffer layer 30 is formed on the first metal layer 20, and the buffer layer 30 is one or a combination of silicon nitride and silicon oxide, and the thickness of the buffer layer 30 ranges from 2000 to 10000 angstroms; then an active layer 40 and a barrier material layer 51 are sequentially formed on the buffer layer 30, and a conductor structure 41 and a second plate 401 of a storage capacitor are formed by a half-tone mask, and a first barrier 501 located on the second plate 401, a second barrier 502 and a third barrier 503 located on the conductor structure 41 are formed, and the first barrier 501, the second barrier 502 and the third barrier 503 are collectively referred to as a barrier layer 50. Among them, the thickness of the active layer 40 ranges from 100 to 1000 angstroms, and the thickness of the barrier layer 50 ranges from 100 to 500 angstroms. Among them, in the direction perpendicular to the light-emitting side of the display panel, the difference between the width of the first blocking portion 501 / the second electrode 401 and the width of the first electrode 201 is greater than 5 times the thickness of the active layer 40 in the direction from the first metal layer 20 to the active layer 40.

[0060] Next, if Figure 6c As shown, a gate insulating layer 60 is formed on the active layer 40 and the barrier layer 50. The material of the gate insulating layer 60 is silicon oxide. Through annealing, the region where the gate insulating layer 60 directly contacts the active layer 40 forms a semiconductor region (i.e., a semiconductor structure 42 and a semiconductor portion 4012) due to oxygen diffusion. Then, a photomask is used to form a first contact hole 601, a second contact hole 602, and a third contact hole 603. Then, the semiconductor structure 42 in the first contact hole 601 and the second contact hole 602 is subjected to plasma (He Plasma) treatment to form a source contact portion 4022 and a drain contact portion 4023. The semiconductor structure 42 not exposed between the first contact hole 601 and the second contact hole 602 is the channel portion 4021. Thus, the active pattern 402 is prepared. The thickness of the gate insulating layer 60 is in the range of 1000 to 3000 angstroms.

[0061] Next, if Figure 6dAs shown, a second metal layer 70 is formed on the gate insulating layer 60, and the second metal layer 70 is patterned to form a gate 702, a source 703, a drain 704 and a third plate 701 of the storage capacitor. The third plate 701 is electrically connected to the first plate 201 (not shown), the source 703 is electrically connected to the source contact portion 4022 through the first contact hole 601, the source 703 is electrically connected to the light shielding layer 202 through the third contact hole 603, and the drain 704 is electrically connected to the drain contact portion 4023 through the second contact hole 602. The second metal layer 70 is divided into three layers, the lower layer contains one or more alloys of Mo, Ti, and Ni, the middle layer is Cu or a Cu alloy, and the upper layer contains one or more alloys of Mo, Ti, and Ni. The thickness of the lower layer ranges from 50 to 500 angstroms, the thickness of the middle layer ranges from 2000 to 10000 angstroms, and the thickness of the upper layer ranges from 50 to 500 angstroms.

[0062] Next, if Figure 6e As shown, a passivation layer 80 and a planarization layer 90 are sequentially formed on the second metal layer 70, wherein the material of the passivation layer 80 is silicon oxide and the planarization layer 90 is an organic layer; and then a half-tone mask is used to form a fourth contact hole 11 on the passivation layer 80 and the planarization layer 90. The thickness of the passivation layer 80 ranges from 1000 to 5000 angstroms.

[0063] Next, if Figure 6f As shown, an anode layer 12 of a top-emitting OLED device is formed on the planarization layer 90, and the anode layer 12 is electrically connected to the source electrode 703 through the fourth contact hole 11. The anode layer 12 is a stacked structure of ITO / Ag / ITO.

[0064] Next, if Figure 6g As shown, a pixel definition layer 13 is formed on the planarization layer 90 and the anode layer 12, a plurality of pixel openings are formed on the pixel definition layer 13, an organic light emitting layer 14 is formed in the pixel openings using an IJP process, and finally a cathode layer 15 is formed on the pixel definition layer 13 and the organic light emitting layer 14, thereby obtaining a display panel. The pixel definition layer 13 is an organic photoresist material.

[0065] Next, see Figure 7a to Figure 7e , for Figure 6a to Figure 6b The basic structural diagram of each component in the process flow is as follows: Figure 7a As shown, an active layer 40 (IGZO) and a barrier material layer 51 (Al) are sequentially formed on the buffer layer 30. Specifically, an Al film is prepared by sputtering on the IGZO. During the preparation process, the Al film takes away oxygen in the IGZO to form oxygen vacancies, thereby realizing the first conductorization of the IGZO. In particular, an aluminum oxide film is formed on the side of the Al film close to the IGZO.

[0066] Next, if Figure 7b As shown, a corresponding photoresist (PR) pattern 52 is formed on the blocking material layer 51 using a halftone mask, wherein A1 represents a fully exposed area (transparent), A2 represents a partially exposed area (semi-transparent), and A3 represents a non-exposed area (shielded).

[0067] Next, if Figure 7c As shown, the first acid solution wet etching is performed by optimizing the parameters to remove the blocking material layer 51 and the active layer 40 in the area not covered by the photoresist pattern 52 (i.e., A1) at the same time, and the active layer 40 forms a conductor structure 41 and a first electrode 201 of the storage capacitor; then, through a one-step ash treatment, the photoresist pattern 52 in the partially exposed area (i.e., A2) is removed to expose the blocking material layer 51 that needs to be opened.

[0068] Next, if Figure 7d As shown, the second alkaline solution wet etching is performed by optimizing the parameters to remove the barrier material layer 51 in the A2 area, exposing the underlying conductor structure 41. The alkaline solution contains KOH, NaOH, TMAH, etc., such as an alkaline developer, which will not react with IGZO, thereby avoiding damage to the IGZO surface.

[0069] Next, if Figure 7e As shown, after removing the photoresist pattern 52 , an annealing process is used to transform the barrier material layer 51 (Al film) into a barrier layer 50 (dense aluminum oxide), and the barrier layer 50 includes a first barrier portion 501 , a second barrier portion 502 and a third barrier portion 503 .

[0070] Next, see Figure 8a to Figure 8c , for Figure 6b to Figure 6c The basic structural diagram of each component in the process flow is as follows: Figure 8a As shown, a gate insulating layer 60 is formed on the barrier layer 50 and the active layer 40. The gate insulating layer 60 is annealed so that oxygen diffuses into the active layer 40 in the area where the gate insulating layer 60 is in direct contact with the active layer 40, and the area where the active layer 40 is in contact with the gate insulating layer 60 is degenerated into a conductor to form a semiconductor structure 42 and a semiconductor portion 4012. The barrier layer 50 has the function of blocking H elements and O elements, and the area protected by the barrier layer 50 still maintains the conductor characteristics, forming a conductor structure 41 and a conductor portion 4011.

[0071] Next, if Figure 8b As shown, a first contact hole 601 , a second contact hole 602 , and a third contact hole 603 are formed on the gate insulating layer 60 using a photomask.

[0072] Next, if Figure 8cAs shown, the semiconductor structure 42 in the first contact hole 601 and the second contact hole 602 is subjected to plasma (He Plasma) treatment (second conductorization) to form a source contact portion 4022 and a drain contact portion 4023. The semiconductor structure 42 not exposed between the first contact hole 601 and the second contact hole 602 is the channel portion 4021. Thus, the active pattern 402 is prepared.

[0073] The embodiment of the present invention further provides a display terminal, comprising a terminal body and the above-mentioned display panel, wherein the terminal body and the display panel are integrated into one body. The structure and preparation method of the display panel are described in detail in Figures 3 to 8c The display terminal provided by the embodiment of the present invention may be a product or component with a display function, such as a mobile phone, a tablet computer, a notebook computer, a television, a digital camera, and a navigator.

[0074] In summary, an embodiment of the present invention provides a display panel, including a substrate layer, a first metal layer, an active layer and a second metal layer; the first metal layer is located on the substrate layer, and the first metal layer includes a first electrode plate of a storage capacitor; the active layer is located on the first metal layer, and the active layer includes a second electrode plate of the storage capacitor; the second metal layer is located on the active layer, and the second metal layer includes a third electrode plate of the storage capacitor, and the third electrode plate is electrically connected to the first electrode plate; wherein a barrier layer is provided on a side surface of the active layer facing the second metal layer, and the barrier layer includes a first barrier portion, and the first barrier portion is located on the second electrode plate; the present invention provides a barrier layer on a side surface of the active layer facing the second metal layer, and the first barrier portion of the barrier layer can block the deconductivity of the second electrode plate, thereby preparing a three-layer sandwich capacitor structure under the premise of ensuring the flatness of the pixel light-emitting area, so that the capacitance value of the storage capacitor meets the display driving requirements of the OLED display panel, so as to improve the display performance of the OLED display panel, and solves the technical problem that the display panel of the prior art adds a capacitor electrode plate between the active layer and the planarization layer, resulting in the deconductivity of the active layer and the inability to conduct electricity.

[0075] The above describes in detail a display panel and a manufacturing method thereof and a display terminal provided by an embodiment of the present invention. It should be understood that the exemplary embodiments described herein should only be considered as descriptive, used to help understand the method and core concept of the present invention, and are not used to limit the present invention.

Claims

1. A display panel, characterized in that: include: substrate layer; A first metal layer, located on the substrate layer, wherein the first metal layer includes a first electrode plate of a storage capacitor; An active layer, located on the first metal layer, the active layer comprising a second electrode plate of the storage capacitor; A gate insulating layer, located on the active layer, and the gate insulating layer covers the active layer; A second metal layer, located on the gate insulating layer, the second metal layer includes a third electrode plate of the storage capacitor, and the third electrode plate is electrically connected to the first electrode plate; A barrier layer is provided between the active layer and the gate insulating layer, the barrier layer comprises a first barrier portion, the first barrier portion is located on the second electrode plate, and the gate insulating layer covers the first barrier portion and the second electrode plate.

2. The display panel according to claim 1, wherein: In a direction perpendicular to the light-emitting side of the display panel, a width of the first blocking portion and a width of the second electrode plate are both greater than a width of the first electrode plate.

3. The display panel according to claim 2, wherein: The second electrode plate includes a conductor portion and semiconductor portions located at both sides of the conductor portion, and the orthographic projection of the first electrode plate on the second electrode plate is located on the conductor portion.

4. The display panel according to claim 2, wherein: The first blocking portion covers a surface of the second electrode plate that is away from the first electrode plate and a side surface of the second electrode plate.

5. The display panel according to claim 1, wherein: The active layer includes an active pattern, wherein the active pattern includes a channel portion and a source contact portion and a drain contact portion located at two sides of the channel portion; The second metal layer includes a gate, a source and a drain. The orthographic projection of the gate on the active pattern is located on the channel portion. The source is electrically connected to the source contact portion, and the drain is electrically connected to the drain contact portion.

6. The display panel according to claim 5, wherein: The barrier layer includes a second barrier portion and a third barrier portion, the second barrier portion is located on the source contact portion, and the third barrier portion is located on the drain contact portion.

7. A method for preparing a display panel, characterized in that: include: forming a first metal layer on the substrate layer; The first metal layer is patterned to form a first electrode plate of a storage capacitor; forming an active layer on the first metal layer; forming a barrier material layer on a surface of the active layer away from the first metal layer; The active layer is patterned to form a second electrode plate of the storage capacitor, and the barrier material layer is patterned to form a first barrier portion, wherein the first barrier portion is located on the second electrode plate; forming a gate insulating layer on a surface of the first barrier away from the active layer and a surface of the active layer away from the first metal layer, wherein the gate insulating layer covers the active layer, the first barrier and the second electrode plate; A second metal layer is formed on the gate insulating layer. The second metal layer is patterned to form a third electrode plate of the storage capacitor. The third electrode plate is arranged corresponding to the first blocking portion and is electrically connected to the first electrode plate.

8. The method for preparing a display panel according to claim 7, wherein: The active layer is patterned to form a second electrode plate of the storage capacitor, and the barrier material layer is patterned to form a first barrier portion, comprising: The active layer is patterned to form a conductor structure and a second electrode plate of the storage capacitor, and the barrier material layer is patterned and annealed to form a first barrier.

9. The method for preparing a display panel according to claim 8, wherein: The preparation method further comprises: Annealing the gate insulating layer, deconducting the region where the conductor structure contacts the gate insulating layer to form a semiconductor structure, and deconducting the region where the second electrode contacts the gate insulating layer to form a semiconductor portion; forming a first contact hole and a second contact hole on the gate insulating layer to expose the semiconductor structure; Conductivity treatment is performed on the semiconductor structure in the first contact hole and the second contact hole to form a source contact portion and a drain contact portion.

10. A display terminal, characterized in that: The invention comprises a terminal body and a display panel according to any one of claims 1 to 6, wherein the terminal body and the display panel are integrated into one body.

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