Analog signal source system and analog signal generation method

Abstract

The application provides an analog signal source system and an analog signal generation method, and the analog signal source system comprises an FPGA control board card and a digital-to-analog converter source board card; based on the overall structure design of the FPGA control board card and the digital-to-analog converter source board card, the FPGA control board card and the digital-to-analog converter source board card are both board card structures based on circuit boards, support plug and play, do not need to be connected with bulky equipment and instruments, the structure of the whole analog signal source system is small in size and low in cost; in the digital-to-analog converter source board card, through the combination of digital-to-analog converters, two low-resolution digital-to-analog converters are combined into a high-resolution digital-to-analog converter module, while effectively realizing a high-purity and high-resolution analog signal source, the cost is further reduced; the output of the generated analog signal and the data acquisition of the subsequent to-be-tested digital-to-analog converter can be directly time sequence controlled based on the FPGA control board card, without the communication interaction of the program control instrument mode, and the test efficiency of the to-be-tested digital-to-analog converter is improved.

Description

Technical Field

[0001] This invention relates to the field of circuit testing technology, and in particular to an analog signal source system and an analog signal generation method. Background Technology

[0002] With the rapid development of computer, communication and multimedia technologies, the degree of digitalization in high-tech fields around the world is constantly deepening. Analog-to-digital converters (ADCs) are widely used in various fields such as digital signal processing, data acquisition systems, automatic testing, industrial control, digital communication and measurement. Among them, the performance indicators of ADCs have become very important. At the same time, the performance requirements of various industries for ADCs are also constantly increasing, which makes the requirements for ADCs in terms of speed, power consumption and accuracy constantly increasing.

[0003] In recent years, various types of ADCs have been widely developed and applied. For example, foreign companies have launched 24-bit resolution Msps-level sampling rate SAR structures and 32-bit resolution hundreds of Ksps-level sampling rate Σ-Δ ADC structures, with analog input frequencies ranging from several kHz to hundreds of kHz. The testing of high-resolution ADCs has reached new heights, requiring not only the selection of appropriate test methods but also a strong dependence on high-resolution analog signal sources within specific frequency ranges. However, most currently available precision signal source instruments are no longer capable of testing such high-resolution analog converters, and the high performance specifications of high-resolution ADCs cannot be addressed using precision signal source instruments. While differential nonlinearity (DNL) or integral nonlinearity (INL) techniques can address the performance requirements of many research lab-level solutions both domestically and internationally, these measurement methods involving programmable instruments add extra communication time and test instability, significantly reducing testing and delivery efficiency.

[0004] Therefore, there is an urgent need for a high-purity, high-resolution analog signal source technology solution to meet the increasingly demanding testing requirements of ADC products. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a high-resolution analog signal source solution to upgrade the performance of domestic and foreign ADC products, realize the testing of high-resolution ADCs, and solve the technical problem of low testing efficiency of high-resolution ADCs.

[0006] To achieve the above and other related objectives, the technical solution provided by this invention is as follows.

[0007] An analog signal source system, comprising:

[0008] An FPGA control board includes a first circuit board and an FPGA chip, wherein the FPGA chip is disposed on the first circuit board.

[0009] A digital-to-analog converter (DAC) source board includes a second circuit board, a DAC source module, a signal conditioning module, an amplitude adjustment module, and an output driver module. The DAC source module, the signal conditioning module, the amplitude adjustment module, and the output driver module are respectively disposed on the second circuit board and are connected sequentially. The DAC source module is connected to an FPGA chip. The FPGA chip controls the DAC source module to generate a plurality of consecutive first analog signals. The signal conditioning module filters and conditions the plurality of first analog signals to obtain and output a second analog signal. The amplitude adjustment module biases and adjusts the amplitude of the second analog signal to obtain and output a third analog signal. The output driver module follows the third analog signal and drives the subsequent load to obtain and output a fourth analog signal to the subsequent load.

[0010] The first analog signal, the second analog signal, the third analog signal, and the fourth analog signal each include two signals, one positive and one negative.

[0011] Optionally, the FPGA control board further includes a USB chip and a first ribbon cable. The USB chip and the first ribbon cable are respectively disposed on the first circuit board. The USB chip and the first ribbon cable are respectively connected to the FPGA chip, and the USB chip leads out a USB interface.

[0012] Optionally, the FPGA chip is connected to a host computer via the USB chip and an external USB data cable, and the host computer sends control commands to the FPGA chip.

[0013] Optionally, the digital-to-analog conversion source module includes a first digital-to-analog conversion source unit and a second digital-to-analog conversion source unit. The first digital-to-analog conversion source unit generates a plurality of consecutive first analog positive signals under the control of the FPGA chip, and the second digital-to-analog conversion source unit generates a plurality of consecutive first analog negative signals under the control of the FPGA chip. The first digital-to-analog conversion source unit and the second digital-to-analog conversion source unit each include an N+M bit resolution digital-to-analog converter. The N+M bit resolution digital-to-analog converter is composed of two N-bit resolution digital-to-analog converters, where M and N are integers greater than or equal to 2 and N is greater than or equal to M.

[0014] Optionally, the first digital-to-analog converter source unit includes a first digital-to-analog converter, a second digital-to-analog converter, a first operational amplifier, a second operational amplifier, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, and a sixth resistor. The first digital-to-analog converter and the second digital-to-analog converter are respectively connected to the FPGA chip. The output terminal of the first digital-to-analog converter is grounded after passing through the first resistor and the second resistor connected in series. The non-inverting input terminal of the first operational amplifier is connected to the common terminal of the first resistor and the second resistor. The inverting input terminal of the first operational amplifier is connected to the output terminal of the first operational amplifier. The output terminal of the first operational amplifier is connected to the inverting input terminal of the second operational amplifier after passing through the third resistor connected in series. The output terminal of the second digital-to-analog converter is connected to the inverting input terminal of the second operational amplifier after passing through the fourth resistor connected in series. The inverting input terminal of the second operational amplifier is also connected to the output terminal of the second operational amplifier after passing through the fifth resistor connected in series. The non-inverting input terminal of the second operational amplifier is grounded after passing through the sixth resistor connected in series. The output terminal of the second operational amplifier outputs the first analog positive signal.

[0015] Optionally, the second digital-to-analog converter source unit includes a third digital-to-analog converter, a fourth digital-to-analog converter, a third operational amplifier, a fourth operational amplifier, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, and a twelfth resistor. The third digital-to-analog converter and the fourth digital-to-analog converter are respectively connected to the FPGA chip. The output terminal of the third digital-to-analog converter is grounded after passing through the seventh resistor and the eighth resistor connected in series. The non-inverting input terminal of the third operational amplifier is connected to the common terminal of the seventh resistor and the eighth resistor. The inverting input terminal of the third operational amplifier is connected to the output terminal of the third operational amplifier. The output terminal of the third operational amplifier is connected to the inverting input terminal of the fourth operational amplifier after passing through the ninth resistor connected in series. The output terminal of the fourth digital-to-analog converter is connected to the inverting input terminal of the fourth operational amplifier after passing through the tenth resistor connected in series. The inverting input terminal of the fourth operational amplifier is also connected to the output terminal of the fourth operational amplifier after passing through the eleventh resistor connected in series. The non-inverting input terminal of the fourth operational amplifier is grounded after passing through the twelfth resistor connected in series. The output terminal of the fourth operational amplifier outputs the first analog negative signal.

[0016] Optionally, the first digital-to-analog converter (DAC) and the second DAC are respectively the N-bit resolution DACs, and the high M bits of the second DAC are extracted under the control of the FPGA chip; the ratio of the resistance value of the first resistor to the resistance value of the second resistor is 2. M-1, the resistance values ​​of the third, fourth, and fifth resistors are equal, and the ratio of the resistance value of the sixth resistor to the resistance value of the third resistor is one-third; the third and fourth digital-to-analog converters are respectively the N-bit resolution digital-to-analog converters, and the high M bits of the fourth digital-to-analog converter are taken under the control of the FPGA chip; the ratio of the resistance value of the seventh resistor to the resistance value of the eighth resistor is 2. M -1, the resistance values ​​of the ninth resistor, the tenth resistor, and the eleventh resistor are equal, and the ratio of the resistance value of the twelfth resistor to the resistance value of the ninth resistor is one-third.

[0017] Optionally, the signal conditioning module includes a first signal conditioning unit and a second signal conditioning unit. The first signal conditioning unit filters and conditions the first analog positive signal to obtain and output a second analog positive signal. The second signal conditioning unit filters and conditions the first analog negative signal to obtain and output a second analog negative signal.

[0018] Optionally, the first signal conditioning unit includes a first three-way switch, a second three-way switch, a pass-through branch, a low-pass filter branch, and a band-pass filter branch. The control terminals of the first three-way switch and the second three-way switch are respectively connected to the FPGA chip. The input terminal of the first three-way switch is connected to the first analog positive signal. The three output terminals of the first three-way switch are connected one-to-one with the input terminals of the pass-through branch, the low-pass filter branch, and the band-pass filter branch. The output terminals of the pass-through branch, the low-pass filter branch, and the band-pass filter branch are connected one-to-one with the three input terminals of the second three-way switch. The output terminal of the second three-way switch outputs the second analog positive signal.

[0019] Optionally, the amplitude adjustment module includes a first amplitude adjustment unit and a second amplitude adjustment unit, which are respectively connected to the FPGA chip; under the control of the FPGA chip, the first amplitude adjustment unit biases and adjusts the amplitude of the second analog positive signal to obtain and output a third analog positive signal, and the second amplitude adjustment unit biases and adjusts the amplitude of the second analog negative signal to obtain and output a third analog negative signal.

[0020] Optionally, the output driving module includes a first output driving unit and a second output driving unit, which are respectively connected to the FPGA chip. Under the control of the FPGA chip, the first output driving unit follows the third analog positive signal and drives the subsequent load to obtain and output a fourth analog positive signal to the subsequent load. The second output driving unit follows the third analog negative signal and drives the subsequent load to obtain and output a fourth analog negative signal to the subsequent load.

[0021] Optionally, the first output driving unit includes a fifth operational amplifier, a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, and a third three-to-one switch. The non-inverting input of the fifth operational amplifier is connected to the third analog positive signal, and the inverting input of the fifth operational amplifier is connected to its output. The output of the fifth operational amplifier is connected to one end of the thirteenth resistor, one end of the fourteenth resistor, and one end of the fifteenth resistor. The other ends of the thirteenth resistor, the fourteenth resistor, and the fifteenth resistor are connected one-to-one to the three inputs of the third three-to-one switch. The output of the third three-to-one switch outputs the fourth analog positive signal. The second output driving unit includes a sixth operational amplifier, a sixteenth resistor, a seventeenth resistor, an eighteenth resistor, and a fourth three-to-one switch. The non-inverting input of the sixth operational amplifier is connected to the third analog negative signal, and the inverting input of the sixth operational amplifier is connected to the output of the sixth operational amplifier. The output of the sixth operational amplifier is connected to one end of the sixteenth resistor, one end of the seventeenth resistor, and one end of the eighteenth resistor. The other ends of the sixteenth resistor, the seventeenth resistor, and the eighteenth resistor are connected to the three inputs of the fourth three-to-one switch in a corresponding manner. The output of the fourth three-to-one switch outputs the fourth analog negative signal.

[0022] Optionally, the digital-to-analog converter source board further includes a reference module and an offset compensation module. The reference module and the offset compensation module are respectively disposed on the second circuit board. The reference module is connected to the digital-to-analog converter source module and the offset compensation module respectively. The offset compensation module is also connected to the FPGA chip and the output driver module. The reference module generates a reference voltage, and the offset compensation module generates an offset compensation voltage under the control of the FPGA chip. The offset compensation voltage is used to compensate and adjust the fourth analog signal.

[0023] Optionally, the digital-to-analog converter source board further includes a first ribbon cable slot and a first SMA connector. The first ribbon cable slot and the first SMA connector are respectively disposed on the second circuit board. The first ribbon cable slot is connected to the digital-to-analog converter source module, the signal conditioning module, the amplitude adjustment module, the output driver module, and the bias compensation module. The first ribbon cable slot is matched with the first ribbon cable, and the first SMA connector is connected to the output driver module. The first SMA connector is used to output the fourth analog signal.

[0024] A method for generating an analog signal, comprising the steps of:

[0025] Generate the first analog signal;

[0026] The first analog signal is filtered and conditioned to obtain and output the second analog signal;

[0027] The second analog signal is biased and its amplitude is adjusted to obtain and output the third analog signal;

[0028] The third analog signal is followed and output to obtain and output the fourth analog signal;

[0029] The first analog signal, the second analog signal, the third analog signal, and the fourth analog signal each include two signals, one positive and one negative.

[0030] Optionally, the step of generating the first analog signal includes:

[0031] Provides two N-bit resolution digital-to-analog converters;

[0032] Step-down of the output of one of the N-bit resolution digital-to-analog converters The first signal is obtained by multiplying the signal by 100%.

[0033] The high M bits of the output of another N-bit resolution digital-to-analog converter are taken to obtain the second signal;

[0034] The first signal and the second signal are superimposed and output to obtain the first analog signal;

[0035] The magnitude of the first analog signal is adjusted by the code control of the FPGA chip to generate multiple consecutive first analog signals;

[0036] Where M and N are integers greater than or equal to 2, and N is greater than or equal to M.

[0037] As described above, the analog signal source system and analog signal generation method provided by the present invention have at least the following beneficial effects:

[0038] The entire analog signal source system is based on an architecture of "FPGA control board + digital-to-analog converter source board". Both the FPGA control board and the digital-to-analog converter source board are circuit board-based structures, supporting plug-and-play functionality and eliminating the need for bulky equipment. This results in a relatively small system size. Furthermore, since both the FPGA control board and the digital-to-analog converter source board are built with integrated circuits, they do not require high-precision instruments, leading to lower costs. In addition, the signal output of the analog signal source system and the subsequent data acquisition by the analog-to-digital converter can be directly time-controlled via the FPGA control board, eliminating the need for communication interaction via programmable instruments and effectively improving the testing efficiency of the analog-to-digital converter under test. Attached Figure Description

[0039] Figure 1 The diagram shown is a structural block diagram of the analog signal source system in this invention.

[0040] Figure 2 Displayed as Figure 1 Circuit diagram of the digital-to-analog converter source module.

[0041] Figure 3 Displayed as Figure 1 Circuit diagram of the first signal conditioning unit.

[0042] Figure 4 Displayed as Figure 1 Circuit diagram of the output driver module.

[0043] Figure 5 The diagram shows the steps of the analog signal generation method in this invention. Detailed Implementation

[0044] As mentioned in the background section, regarding the performance testing of high-resolution analog-to-digital converters (ADCs), the inventors discovered that: Testing high-resolution ADCs not only requires selecting appropriate testing methods but also has a strong dependence on high-resolution analog signal sources within specific frequency ranges. Firstly, most currently available precision signal source instruments are no longer capable of testing such high-resolution analog converters. For example, the maximum analog output frequency of the AP2712 audio signal source is 192kHz. Testing ADCs with analog input frequencies exceeding 192kHz is difficult; for instance, a certain high-resolution ADC requires testing its dynamic performance at an input frequency of 400kHz. Secondly, high-resolution ADCs have high performance specifications; for example, typical signal-to-noise ratio (SNR) values ​​are in the range of 110dB to 135dB, and typical harmonic distortion (THD) values ​​are in the range of -113dB to -142dB. These are also issues that cannot be addressed using current precision signal source instruments. Domestic research lab-level solutions have been proposed for high-resolution ADC testing, such as those using Fluke... The 5730 DC source outputs a high-resolution DC signal. After sampling by the analog converter, the data is transmitted back to the PC for direct point-to-point linearity calculation. Alternatively, the required analog signal waveform can be obtained via programmable control (IEEE-488, Ethernet, USB, RS-232) to achieve ADC testing. For Σ-Δ structure ADCs launched domestically and internationally, only integral nonlinearity (INL) technical specifications are listed, not differential nonlinearity (DNL). This solution can address this, but the testing efficiency will be significantly reduced due to the back-and-forth interaction of the programmable instrument. Furthermore, most high-resolution SAR structure ADCs launched domestically and internationally list differential nonlinearity (DNL) technical specifications. This means that the amount of data sampled by the ADC will be greatly increased. For example, a SAR structure ADC with a resolution of 24 bits and a sampling rate of 1 MSPS requires a sampling data volume of 536,870,912 to reflect the ADC's most accurate performance indicators. In other words, the testing method involving programmable instruments significantly increases the interaction communication time and the instability of the test, greatly reducing testing efficiency and supply efficiency.

[0045] Based on this, the present invention proposes a high-resolution analog signal source technology solution: combining an "FPGA control board + digital-to-analog converter source board" structure to generate analog signals. The overall structure is a board-based structure based on a circuit board, which supports plug-and-play, thereby reducing the size of the device and enhancing its flexibility of use, while also reducing testing and production costs. The output of the generated analog signal and the subsequent data acquisition of the analog-to-digital converter can be directly time-controlled based on the FPGA control board, without the need for communication interaction through programmable instruments, thereby improving the testing efficiency of the analog-to-digital converter under test.

[0046] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0047] Please see Figures 1 to 5 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show components relevant to the present invention and are not drawn according to the actual number, shape, and size of the components in implementation. In actual implementation, the form, quantity, and proportion of each component can be arbitrarily changed, and the component layout may be more complex. The structures, proportions, sizes, etc., depicted in the accompanying drawings are only for illustrative purposes to aid those skilled in the art and are not intended to limit the implementation conditions of the present invention. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effects and objectives of the present invention, should still fall within the scope of the technical content disclosed in the present invention.

[0048] like Figure 1 As shown, the present invention provides an analog signal source system, which includes:

[0049] An FPGA control board includes a first circuit board (not shown in the figure) and an FPGA chip, wherein the FPGA chip is mounted on the first circuit board.

[0050] The digital-to-analog converter (DAC) source board includes a second circuit board (not shown in the figure), a DAC source module, a signal conditioning module, an amplitude adjustment module, and an output driver module. The DAC source module, signal conditioning module, amplitude adjustment module, and output driver module are respectively mounted on the second circuit board and are connected in sequence. The DAC source module is connected to an FPGA chip. The FPGA chip controls the DAC source module to generate multiple consecutive first analog signals. The signal conditioning module filters and conditions the multiple first analog signals to obtain and output a second analog signal. The amplitude adjustment module biases and adjusts the amplitude of the second analog signal to obtain and output a third analog signal. The output driver module follows the third analog signal and drives the subsequent load to obtain and output a fourth analog signal to the subsequent load.

[0051] The first analog signal, the second analog signal, the third analog signal, and the fourth analog signal each include two signals, one positive and one negative. Specifically, the first analog signal includes the first analog positive signal Vp1 and the first analog negative signal Vn1, the second analog signal includes the second analog positive signal Vp2 and the second analog negative signal Vn2, the third analog signal includes the third analog positive signal Vp3 and the third analog negative signal Vn3, and the fourth analog signal includes the fourth analog positive signal Vp4 and the fourth analog negative signal Vn4.

[0052] In detail, the FPGA control board also includes a USB chip (not shown in the figure) and a first ribbon cable (not shown in the figure). The USB chip and the first ribbon cable are respectively mounted on the first circuit board and are respectively connected to the FPGA chip. The USB chip has a USB interface. The FPGA chip is connected to the host computer through the USB chip and an external USB data cable. The host computer sends control commands to the FPGA chip.

[0053] In detail, such as Figure 1 and Figure 2 As shown, the digital-to-analog converter (DAC) source module includes a first DAC source unit and a second DAC source unit. The first DAC source unit generates multiple consecutive first analog positive signals Vp1 under the control of the FPGA chip, and the second DAC source unit generates multiple consecutive first analog negative signals Vn1 under the control of the FPGA chip. The first DAC source unit and the second DAC source unit each include an N+M bit resolution DAC. The N+M bit resolution DAC is composed of two N-bit resolution DACs, where M and N are integers greater than or equal to 2 and N is greater than or equal to M.

[0054] In an optional embodiment of the present invention, such as Figure 2As shown, the first digital-to-analog converter (DAC) source unit includes a first DAC1, a second DAC2, a first operational amplifier U1, a second operational amplifier U2, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6. The first DAC1 and the second DAC2 are respectively connected to an FPGA chip. The output of the first DAC1 is grounded after passing through the first resistor R1 and the second resistor R2 connected in series. The non-inverting input of the first operational amplifier U1 is connected to the common terminal of the first resistor R1 and the second resistor R2. The inverting input of operational amplifier U1 is connected to the output of the first operational amplifier U1. The output of the first operational amplifier U1 is connected to the inverting input of the second operational amplifier U2 via a third resistor R3 connected in series. The output of the second digital-to-analog converter DAC2 is connected to the inverting input of the second operational amplifier U2 via a fourth resistor R4 connected in series. The inverting input of the second operational amplifier U2 is also connected to the output of the second operational amplifier U2 via a fifth resistor R5 connected in series. The non-inverting input of the second operational amplifier U2 is grounded via a sixth resistor R6 connected in series. The output of the second operational amplifier U2 outputs the first analog positive signal Vp1.

[0055] In an optional embodiment of the present invention, such as Figure 2 As shown, the second digital-to-analog converter source unit includes a third digital-to-analog converter (DAC3), a fourth digital-to-analog converter (DAC4), a third operational amplifier (U3), a fourth operational amplifier (U4), a seventh resistor (R7), an eighth resistor (R8), a ninth resistor (R9), a tenth resistor (R10), an eleventh resistor (R11), and a twelfth resistor (R12). The third and fourth digital-to-analog converters (DAC3 and DAC4) are connected to the FPGA chip. The output of the third DAC3 is grounded after passing through the seventh resistor (R7) and the eighth resistor (R8) connected in series. The non-inverting input of the third operational amplifier (U3) is connected to the common terminal of the seventh resistor (R7) and the eighth resistor (R8). The inverting input of operational amplifier U3 is connected to the output of the third operational amplifier U3. The output of the third operational amplifier U3 is connected to the inverting input of the fourth operational amplifier U4 via the ninth resistor R9 connected in series. The output of the fourth digital-to-analog converter DAC4 is connected to the inverting input of the fourth operational amplifier U4 via the tenth resistor R10 connected in series. The inverting input of the fourth operational amplifier U4 is also connected to the output of the fourth operational amplifier U4 via the eleventh resistor R11 connected in series. The non-inverting input of the fourth operational amplifier U4 is grounded via the twelfth resistor R12 connected in series. The output of the fourth operational amplifier U4 outputs the first analog negative signal Vn1.

[0056] Among them, the first digital-to-analog converter (DAC1) and the second digital-to-analog converter (DAC2) are both N-bit resolution digital-to-analog converters. Under the control of the FPGA chip, the high M bits of the second digital-to-analog converter (DAC2) are extracted; the ratio of the resistance value of the first resistor R1 to the resistance value of the second resistor R2 is 2. M -1, the resistance values ​​of the third resistor R3, the fourth resistor R4, and the fifth resistor R5 are equal; the ratio of the resistance value of the sixth resistor R6 to the resistance value of the third resistor R3 is one-third; the third digital-to-analog converter DAC3 and the fourth digital-to-analog converter DAC4 are both N-bit resolution digital-to-analog converters, and the high M bits of the fourth digital-to-analog converter DAC4 are extracted under the control of the FPGA chip; the ratio of the resistance value of the seventh resistor R7 to the resistance value of the eighth resistor R8 is 2. M -1, the resistance values ​​of the ninth resistor R9, the tenth resistor R10, and the eleventh resistor R11 are equal, and the ratio of the resistance value of the twelfth resistor R12 to the resistance value of the ninth resistor R9 is one-third.

[0057] More specifically, the first and second digital-to-analog converter source units are N+M bit resolution digital-to-analog converters, which are composed of two N-bit resolution digital-to-analog converters. The specific implementation method of the N+M bit resolution digital-to-analog converter is as follows:

[0058] Given:

[0059] N-bit resolution DAC1 output:

[0060]

[0061] The output of an (N+M) bit resolution DAC is:

[0062]

[0063] From equation (2), we can obtain:

[0064]

[0065] From equation (3), V DAC Can be written as:

[0066]

[0067] As shown in equation (4), an (N+M) bit resolution DAC can be composed of an N-bit resolution DAC and an M-bit resolution DAC. The N-bit resolution DAC needs to be stepped down. The M-bit resolution DAC is obtained by taking the high M bits from the N-bit resolution DAC.

[0068] More in detail, such as Figure 2As shown, in the first digital-to-analog converter (DAC) source unit, both the first DAC1 and the second DAC2 are N-bit resolution DACs. Under the control of the FPGA chip, when the output bits of the first DAC1 are fully processed, the ratio of the resistance of the first resistor R1 to the resistance of the second resistor R2 is 2. M -1, after voltage division by the voltage divider network formed by the resistance of the first resistor R1 and the second resistor R2, and following the output of the first operational amplifier U1, the output voltage of the first digital-to-analog converter DAC1 is reduced. Under the control of the FPGA chip, the output of the second digital-to-analog converter DAC2 is taken as the high M bits; the output of the first digital-to-analog converter DA1 is stepped down. The voltage superimposed on the second digital-to-analog converter (DAC2) is then connected to the inverting input of the second operational amplifier (U2) via the third resistor R3. The output of DAC2 is then connected to the inverting input of DAC2 via the fourth resistor R4. DAC2 inverts the voltage superimposed on its inverting input and outputs the first analog positive signal Vp1. Thus, two low-resolution N-bit DACs are combined to form a high-resolution N+M-bit DAC. The resistance of the sixth resistor R6 matches the equivalent parallel resistance of the third resistor R3, the fourth resistor R4, and the fifth resistor R5. The specific principle of the second DAC source unit is similar and will not be elaborated further here.

[0069] In detail, such as Figure 1 As shown, the signal conditioning module includes a first signal conditioning unit and a second signal conditioning unit. The first signal conditioning unit filters and conditions the first analog positive signal Vp1 to obtain and output the second analog positive signal Vp2. The second signal conditioning unit filters and conditions the first analog negative signal Vn1 to obtain and output the second analog negative signal Vn2.

[0070] In an optional embodiment of the present invention, such as Figure 3As shown, the first signal conditioning unit includes a first three-way switch A1, a second three-way switch A2, a pass-through branch, a low-pass filter branch, and a band-pass filter branch. The control terminals of the first three-way switch A1 and the second three-way switch A2 are respectively connected to the FPGA chip. The input terminal of the first three-way switch A1 is connected to the first analog positive signal Vp1. The three output terminals of the first three-way switch A1 are connected one-to-one with the input terminals of the pass-through branch, the low-pass filter branch, and the band-pass filter branch. The output terminals of the pass-through branch, the low-pass filter branch, and the band-pass filter branch are connected one-to-one with the three input terminals of the second three-way switch A2. The output terminal of the second three-way switch A2 outputs the second analog positive signal Vp2. Under the control of the FPGA chip, one of the following branches—the pass-through branch, the low-pass filter branch, and the band-pass filter branch—is selected through the first three-way switch A1 and the second three-way switch A2. The first analog positive signal Vp1 is then processed by pass-through, low-pass filtering, or band-pass filtering, and finally the second analog positive signal Vp2 is output.

[0071] It is understood that the first signal conditioning unit may include more branches, such as multiple different low-pass filter branches or multiple different band-pass filter branches, and the corresponding switches may be four-to-one switches, five-to-one switches, etc., which are not limited here; the structure of the second signal conditioning unit is similar to that of the first signal conditioning unit, and will not be described in detail here.

[0072] In detail, such as Figure 1 As shown, the amplitude adjustment module includes a first amplitude adjustment unit and a second amplitude adjustment unit, both connected to an FPGA chip. Under the control of the FPGA chip, the first amplitude adjustment unit biases and adjusts the amplitude of the second analog positive signal Vp2 to obtain and output a third analog positive signal Vp3. The second amplitude adjustment unit biases and adjusts the amplitude of the second analog negative signal Vn2 to obtain and output a third analog negative signal Vn3. The first amplitude adjustment unit (and the second amplitude adjustment unit) adjusts the amplitude by using the code operation (output digital code) of the FPGA chip.

[0073] In detail, such as Figure 1 As shown, the output driving module includes a first output driving unit and a second output driving unit, which are respectively connected to the FPGA chip. Under the control of the FPGA chip, the first output driving unit follows the third analog positive signal Vp3 and drives the subsequent load, thereby obtaining and outputting a fourth analog positive signal Vp4 to the subsequent load. The second output driving unit follows the third analog negative signal Vn3 and drives the subsequent load, thereby obtaining and outputting a fourth analog negative signal Vn4 to the subsequent load.

[0074] In an optional embodiment of the present invention, such as Figure 4 As shown, the first output drive unit includes a fifth operational amplifier U5, a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, and a third three-to-one switch A3. The non-inverting input of the fifth operational amplifier U5 is connected to the third analog positive signal Vp3, and the inverting input of the fifth operational amplifier U5 is connected to its output. The output of the fifth operational amplifier U5 is connected to one end of the thirteenth resistor R13, one end of the fourteenth resistor R14, and one end of the fifteenth resistor R15. The other ends of the thirteenth resistor R13, the fourteenth resistor R14, and the fifteenth resistor R15 are connected to the three inputs of the third three-to-one switch A3. The output of the third three-to-one switch A3 outputs the fourth analog positive signal Vp3. 4; The second output drive unit includes a sixth operational amplifier U6, a sixteenth resistor R16, a seventeenth resistor R17, an eighteenth resistor R18, and a fourth three-to-one switch A4. The non-inverting input of the sixth operational amplifier U6 is connected to the third analog negative signal Vn3, and the inverting input of the sixth operational amplifier U6 is connected to the output of the sixth operational amplifier U6. The output of the sixth operational amplifier U6 is connected to one end of the sixteenth resistor R16, one end of the seventeenth resistor R17, and one end of the eighteenth resistor R18, respectively. The other ends of the sixteenth resistor R16, the seventeenth resistor R17, and the eighteenth resistor R18 are connected to the three inputs of the fourth three-to-one switch A4 in a corresponding manner. The output of the fourth three-to-one switch A4 outputs the fourth analog negative signal Vn4. The control terminals of the third three-way selector switch A3 and the fourth three-way selector switch A4 are connected to the FPGA chip. Under the control of the FPGA chip, one branch (each branch has a different resistance value) will follow the output. The third three-way selector switch A3 outputs the fourth analog positive signal Vp4 to the downstream load (the analog-to-digital converter under test), and the fourth three-way selector switch A4 outputs the fourth analog negative signal Vn4 to the downstream load.

[0075] In detail, such as Figure 1 As shown, the digital-to-analog converter source board also includes a reference module and a bias compensation module. The reference module and the bias compensation module are respectively mounted on the second circuit board. The reference module is connected to both the digital-to-analog converter source module and the bias compensation module. The bias compensation module is also connected to the FPGA chip and the output driver module. The reference module generates a reference voltage. The bias compensation module includes a digital-to-analog converter, which receives the reference voltage and the control code from the FPGA chip. Under the control of the FPGA chip, the digital-to-analog converter generates a bias compensation voltage, which is used to compensate and adjust the fourth analog signal (fourth analog positive signal Vp4 and fourth analog negative signal Vn4) of the output driver module. At the same time, the reference voltage is also connected to the digital-to-analog converter in the digital-to-analog converter source module, which will not be described in detail here.

[0076] In an optional embodiment of the present invention, the digital-to-analog converter source board further includes a first ribbon cable slot and a first SMA connector. The first ribbon cable slot and the first SMA connector are respectively disposed on the second circuit board. The first ribbon cable slot is connected to the digital-to-analog converter source module, the signal conditioning module, the amplitude adjustment module, the output driving module and the bias compensation module respectively. The first ribbon cable slot is matched with the first ribbon cable. The first SMA connector is connected to the output driving module. The first SMA connector is used to output a fourth analog signal.

[0077] Correspondingly, the analog-to-digital converter (ADC) under test (DUT) is also a board structure, forming an ADC test board. This test board includes a third circuit board, the ADC under test, a second SMA connector, and a second ribbon cable slot. The ADC under test, the second SMA connector, and the second ribbon cable slot are respectively mounted on the third circuit board, and are connected to the ADC. The second SMA connector can be connected to the first SMA connector via an external coaxial cable, and the second ribbon cable slot is matched with the second ribbon cable. During testing, the ADC source board connects to the FPGA chip through the first ribbon cable slot and the first ribbon cable; the ADC under test connects to the FPGA chip through the second ribbon cable slot and the second ribbon cable; and the ADC under test connects to the ADC source board through the second SMA connector, the external coaxial cable, and the first SMA connector.

[0078] More in detail, such as Figure 1As shown, both the FPGA control board and the digital-to-analog converter (DAC) source board are circuit board-based structures, supporting plug-and-play functionality and eliminating the need for bulky equipment. The overall analog signal source system has a relatively small size. Both the FPGA control board and the DAC source board are built with integrated circuits, requiring no high-precision instruments, thus reducing the overall cost of the analog signal source system. In the DAC source board, under the control of the FPGA chip, the DAC source module generates multiple consecutive first analog signals. The signal conditioning module filters and conditions these first analog signals to obtain and output a second analog signal. The amplitude adjustment module biases and adjusts the amplitude of the second analog signal to obtain and output a third analog signal. The output driver module follows the third analog signal to obtain and output a fourth analog signal, which is the final output analog signal. Multiple consecutive fourth analog signals can be generated through code control of the FPGA chip. The digital-to-analog converter source module is composed of two lower N-bit resolution digital-to-analog converters combined into a higher N+M-bit resolution digital-to-analog converter. The corresponding principle and structure are simple, effectively realizing a high-purity, high-resolution analog signal source while further reducing costs. The output of the generated analog signal and the subsequent data acquisition of the analog-to-digital converter under test can be directly time-controlled based on the FPGA control board, without the need for communication interaction through programmable instruments, thus improving the testing efficiency of the analog-to-digital converter under test.

[0079] In an optional embodiment of the present invention, the FPGA control board drives the digital-to-analog converter source module, causing its output signal to pass through the signal conditioning module, amplitude adjustment module, and output driving module to output a continuous analog signal with 22-bit resolution. The FPGA control board drives the analog-to-digital converter under test (ADC) to acquire the continuous analog signal output by the ADC source board, and transmits the acquired data back to the PC for analysis, thereby realizing the testing of the ADC under test.

[0080] In this invention, by combining two low-resolution digital-to-analog converters into a high-resolution digital-to-analog converter module, the testing of the high-resolution analog-to-digital converter is realized, and the test time for its static index INL is less than 15 seconds; while the test time using a programmable precision instrument is approximately in the minute range. This invention greatly shortens the test time.

[0081] This invention, through the research of high-resolution analog signal source systems and the implementation method of digital-to-analog converter source modules, has carried out different high-resolution analog signal source systems for analog-to-digital converters with different sampling rates, different input frequencies, and different resolutions. It has been applied to the testing of SAR structure analog-to-digital converters with 18-bit resolution and above, as well as Σ-Δ structure analog-to-digital converters with 24-bit resolution and above.

[0082] Among them, the FPGA chip, high-precision digital-to-analog converter and the analog-to-digital converter under test involved in data acquisition during the test must meet certain test matching requirements.

[0083] In an optional embodiment of the present invention, a 20-bit SAR-type analog-to-digital converter (ADC) under test has an analog power supply voltage of ±1.80V, receives a true bipolar (±5V) analog input signal, i.e., a resolution of up to 9.54μV, a maximum data output rate of 1.8MSPS, a DNL of ±1ppm, an NNL of ±3.1ppm, and under an analog input frequency Fin = 100kHz, dynamic performance indicators SNR = 99.5dBFS and THD = -100dB; under an analog input frequency Fin = 400kHz, dynamic performance indicators SNR = 93dBFS and THD = -94dB. For these performance indicators, the ADC source module selects two 18-bit ADCs combined. The maximum output amplitude of this 18-bit ADC is ±10V, the output data rate is >20MSPS, and the typical values ​​of INL and DNL are both ±0.4LSB. Figure 2 The implementation method of the digital-to-analog converter (DAC) source module shown enables the DAC source module to output analog signals with a 22-bit resolution, i.e., a resolution of 2.38μV. The DAC clock signal is 100MHz, and the FPGA control board uses a certain FPGA chip with a maximum I / O port output frequency of 710MHz and a clock jitter of time_jitter ≤ 3ps. Based on the relationship between signal-to-noise ratio (SNR), analog frequency, and clock jitter, an SNR ≥ 102.45dB can be obtained. Therefore, the FPGA chip also meets the test requirements.

[0084] In addition, such as Figure 5 As shown, based on the design concept of the above-mentioned analog signal source system, the present invention also provides an analog signal generation method, which includes the following steps:

[0085] S1. Generate the first analog signal;

[0086] S2. Filter and condition the first analog signal to obtain and output the second analog signal;

[0087] S3. The second analog signal is biased and its amplitude is adjusted to obtain and output the third analog signal;

[0088] S4. Follow the third analog signal to obtain and output the fourth analog signal;

[0089] The first analog signal, the second analog signal, the third analog signal, and the fourth analog signal each include two signals, one positive and one negative.

[0090] In detail, step S1, which generates the first analog signal, further includes:

[0091] S11 provides two N-bit resolution digital-to-analog converters;

[0092] S12, Stepping down the output of an N-bit resolution digital-to-analog converter. The first signal is obtained by multiplying the signal by a factor of 1.

[0093] S13. Take the high M bits of the output of another N-bit resolution digital-to-analog converter to obtain the second signal;

[0094] S14. Superimpose the first signal and the second signal to obtain the first analog signal;

[0095] S15. By controlling the code of the FPGA chip, the magnitude of the first signal and the magnitude of the second signal are adjusted, thereby adjusting the magnitude of the first analog signal and generating multiple consecutive first analog signals of different magnitudes.

[0096] Where M and N are integers greater than or equal to 2, and N is greater than or equal to M.

[0097] In summary, the analog signal source system and analog signal generation method of the present invention are based on an overall structural design of "FPGA control board + digital-to-analog converter source board". Both the FPGA control board and the digital-to-analog converter source board are circuit board-based structures, supporting plug-and-play functionality and eliminating the need for bulky equipment. The overall structure of the analog signal source system is relatively small. Both the FPGA control board and the digital-to-analog converter source board are built with integrated circuits, requiring no high-precision instruments, thus reducing the overall cost of the analog signal source system. In the digital-to-analog converter source board, by combining two low-resolution digital-to-analog converters into a high-resolution digital-to-analog converter module, a high-purity, high-resolution analog signal source is effectively achieved while further reducing costs. The output of the generated analog signal and the subsequent data acquisition of the analog-to-digital converter under test can be directly time-controlled based on the FPGA control board, eliminating the need for communication interaction via programmable instruments and improving the testing efficiency of the analog-to-digital converter under test.

[0098] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. An analog signal source system, characterized in that, include: An FPGA control board includes a first circuit board and an FPGA chip, wherein the FPGA chip is disposed on the first circuit board. A digital-to-analog converter (DAC) source board includes a second circuit board, a DAC source module, a signal conditioning module, an amplitude adjustment module, and an output driver module. The DAC source module, the signal conditioning module, the amplitude adjustment module, and the output driver module are respectively disposed on the second circuit board and are connected sequentially. The DAC source module is connected to an FPGA chip. The FPGA chip controls the DAC source module to generate a plurality of consecutive first analog signals. The signal conditioning module filters and conditions the plurality of first analog signals to obtain and output a second analog signal. The amplitude adjustment module biases and adjusts the amplitude of the second analog signal to obtain and output a third analog signal. The output driver module follows the third analog signal and drives the subsequent load to obtain and output a fourth analog signal to the subsequent load. Wherein, the first analog signal, the second analog signal, the third analog signal and the fourth analog signal each include two signals, positive and negative; The digital-to-analog converter (DAC) source module includes a first DAC source unit and a second DAC source unit. The first DAC source unit generates a series of first analog positive signals under the control of the FPGA chip, and the second DAC source unit generates a series of first analog negative signals under the control of the FPGA chip. The first DAC source unit and the second DAC source unit each include an N+M bit resolution DAC. The N+M bit resolution DAC is composed of two N-bit resolution DACs, where M and N are integers greater than or equal to 2 and N is greater than or equal to M.

2. The analog signal source system according to claim 1, characterized in that, The FPGA control board also includes a USB chip and a first ribbon cable. The USB chip and the first ribbon cable are respectively disposed on the first circuit board. The USB chip and the first ribbon cable are respectively connected to the FPGA chip, and the USB chip leads out a USB interface.

3. The analog signal source system according to claim 2, characterized in that, The FPGA chip is connected to the host computer via the USB chip and an external USB data cable, and the host computer sends control commands to the FPGA chip.

4. The analog signal source system according to claim 1, characterized in that, The first digital-to-analog converter (DAC) source unit includes a first DAC, a second DAC, a first operational amplifier, a second operational amplifier, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, and a sixth resistor. The first DAC and the second DAC are respectively connected to the FPGA chip. The output terminal of the first DAC is grounded after passing through the first resistor and the second resistor connected in series. The non-inverting input terminal of the first operational amplifier is connected to the common terminal of the first resistor and the second resistor. The inverting input terminal of the first operational amplifier is connected to the output terminal of the first operational amplifier. The output terminal of the first operational amplifier is connected to the inverting input terminal of the second operational amplifier after passing through the third resistor connected in series. The output terminal of the second DAC is connected to the inverting input terminal of the second operational amplifier after passing through the fourth resistor connected in series. The inverting input terminal of the second operational amplifier is also connected to the output terminal of the second operational amplifier after passing through the fifth resistor connected in series. The non-inverting input terminal of the second operational amplifier is grounded after passing through the sixth resistor connected in series. The output terminal of the second operational amplifier outputs the first analog positive signal.

5. The analog signal source system according to claim 4, characterized in that, The second digital-to-analog converter (DAC) source unit includes a third DAC, a fourth DAC, a third operational amplifier, a fourth operational amplifier, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, and a twelfth resistor. The third DAC and the fourth DAC are respectively connected to the FPGA chip. The output terminal of the third DAC is grounded after passing through the seventh and eighth resistors connected in series. The non-inverting input terminal of the third operational amplifier is connected to the common terminal of the seventh and eighth resistors. The inverting input terminal of the third operational amplifier is connected to the output terminal of the third operational amplifier. The output terminal of the third operational amplifier is connected to the inverting input terminal of the fourth operational amplifier after passing through the ninth resistor connected in series. The output terminal of the fourth DAC is connected to the inverting input terminal of the fourth operational amplifier after passing through the tenth resistor connected in series. The inverting input terminal of the fourth operational amplifier is also connected to the output terminal of the fourth operational amplifier after passing through the eleventh resistor connected in series. The non-inverting input terminal of the fourth operational amplifier is grounded after passing through the twelfth resistor connected in series. The output terminal of the fourth operational amplifier outputs the first analog negative signal.

6. The analog signal source system according to claim 5, characterized in that, The first and second digital-to-analog converters are respectively the N-bit resolution digital-to-analog converters, and the high M bits of the second digital-to-analog converter are taken under the control of the FPGA chip; the resistance value of the first resistor is 2M-1 to the resistance value of the second resistor, the resistance values ​​of the third, fourth, and fifth resistors are equal, and the resistance value of the sixth resistor is one-third of the resistance value of the third resistor; the third and fourth digital-to-analog converters are respectively the N-bit resolution digital-to-analog converters, and the high M bits of the fourth digital-to-analog converter are taken under the control of the FPGA chip; the resistance value of the seventh resistor is 2M-1 to the resistance value of the eighth resistor, the resistance values ​​of the ninth, tenth, and eleventh resistors are equal, and the resistance value of the twelfth resistor is one-third of the resistance value of the ninth resistor.

7. The analog signal source system according to claim 6, characterized in that, The signal conditioning module includes a first signal conditioning unit and a second signal conditioning unit. The first signal conditioning unit filters and conditions the first analog positive signal to obtain and output a second analog positive signal. The second signal conditioning unit filters and conditions the first analog negative signal to obtain and output a second analog negative signal.

8. The analog signal source system according to claim 7, characterized in that, The first signal conditioning unit includes a first three-way selector switch, a second three-way selector switch, a pass-through branch, a low-pass filter branch, and a band-pass filter branch. The control terminals of the first three-way selector switch and the second three-way selector switch are respectively connected to the FPGA chip. The input terminal of the first three-way selector switch is connected to the first analog positive signal. The three output terminals of the first three-way selector switch are connected one-to-one with the input terminals of the pass-through branch, the low-pass filter branch, and the band-pass filter branch. The output terminals of the pass-through branch, the low-pass filter branch, and the band-pass filter branch are connected one-to-one with the three input terminals of the second three-way selector switch. The output terminal of the second three-way selector switch outputs the second analog positive signal.

9. The analog signal source system according to claim 7, characterized in that, The amplitude adjustment module includes a first amplitude adjustment unit and a second amplitude adjustment unit, which are respectively connected to the FPGA chip. Under the control of the FPGA chip, the first amplitude adjustment unit biases and adjusts the amplitude of the second analog positive signal to obtain and output a third analog positive signal, and the second amplitude adjustment unit biases and adjusts the amplitude of the second analog negative signal to obtain and output a third analog negative signal.

10. The analog signal source system according to claim 9, characterized in that, The output driving module includes a first output driving unit and a second output driving unit, which are respectively connected to the FPGA chip. Under the control of the FPGA chip, the first output driving unit follows the third analog positive signal and drives the subsequent load to obtain and output a fourth analog positive signal to the subsequent load. The second output driving unit follows the third analog negative signal and drives the subsequent load to obtain and output a fourth analog negative signal to the subsequent load.

11. The analog signal source system according to claim 10, characterized in that, The first output driving unit includes a fifth operational amplifier, a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, and a third three-to-one switch. The non-inverting input of the fifth operational amplifier is connected to the third analog positive signal, and the inverting input of the fifth operational amplifier is connected to the output of the fifth operational amplifier. The output of the fifth operational amplifier is connected to one end of the thirteenth resistor, one end of the fourteenth resistor, and one end of the fifteenth resistor, respectively. The other ends of the thirteenth resistor, the fourteenth resistor, and the fifteenth resistor are connected to the three inputs of the third three-to-one switch in a one-to-one correspondence. The output of the third three-to-one switch outputs the fourth analog positive signal. The second output driving unit includes a sixth operational amplifier, a sixteenth resistor, a seventeenth resistor, an eighteenth resistor, and a fourth three-to-one switch. The non-inverting input of the sixth operational amplifier is connected to the third analog negative signal, and the inverting input of the sixth operational amplifier is connected to the output of the sixth operational amplifier. The output of the sixth operational amplifier is connected to one end of the sixteenth resistor, one end of the seventeenth resistor, and one end of the eighteenth resistor, respectively. The other ends of the sixteenth resistor, the seventeenth resistor, and the eighteenth resistor are connected to the three inputs of the fourth three-to-one switch in a corresponding manner. The output of the fourth three-to-one switch outputs the fourth analog negative signal.

12. The analog signal source system according to claim 2, characterized in that, The digital-to-analog converter source board also includes a reference module and an offset compensation module. The reference module and the offset compensation module are respectively disposed on the second circuit board. The reference module is connected to the digital-to-analog converter source module and the offset compensation module respectively. The offset compensation module is also connected to the FPGA chip and the output driver module. The reference module generates a reference voltage, and the offset compensation module generates an offset compensation voltage under the control of the FPGA chip. The offset compensation voltage is used to compensate and adjust the fourth analog signal.

13. The analog signal source system according to claim 12, characterized in that, The digital-to-analog converter source board also includes a first ribbon cable slot and a first SMA connector. The first ribbon cable slot and the first SMA connector are respectively disposed on the second circuit board. The first ribbon cable slot is connected to the digital-to-analog converter source module, the signal conditioning module, the amplitude adjustment module, the output driver module, and the bias compensation module. The first ribbon cable slot is matched with the first ribbon cable, and the first SMA connector is connected to the output driver module. The first SMA connector is used to output the fourth analog signal.

14. A method for generating an analog signal applied to an analog signal source system as described in any one of claims 1 to 13, characterized in that, Including the following steps: Generate the first analog signal; The first analog signal is filtered and conditioned to obtain and output the second analog signal; The second analog signal is biased and its amplitude is adjusted to obtain and output the third analog signal; The third analog signal is followed and output to obtain and output the fourth analog signal; The first analog signal, the second analog signal, the third analog signal, and the fourth analog signal each include two signals, one positive and one negative.

15. The analog signal generation method according to claim 14, characterized in that, The step of generating the first analog signal includes: Provides two N-bit resolution digital-to-analog converters; Step-down of the output of one of the N-bit resolution digital-to-analog converters The first signal is obtained by multiplying the signal by a factor of 1. The high M bits of the output of another N-bit resolution digital-to-analog converter are taken to obtain the second signal; The first signal and the second signal are superimposed and output to obtain the first analog signal; The magnitude of the first analog signal is adjusted by the code control of the FPGA chip to generate multiple consecutive first analog signals; Where M and N are integers greater than or equal to 2, and N is greater than or equal to M.

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