frequency division multiplexing

Abstract

Embodiments of the present application relate to methods and systems for frequency division multiplexing. A method is provided. In some examples, the method includes generating (410), by processing circuitry, a chip spread representing input bits. Additionally, the method includes converting (420), by the processing circuitry, the chip spread into a plurality of symbols comprising a pair of symbols. The method also includes mapping (430), by the processing circuitry, the pair of symbols to a single carrier signal, and generating, by the processing circuitry, a radio frequency (RF) signal based on the single carrier signal. The method further includes transmitting (450), by the processing circuitry, the RF signal via an antenna.

Description

[0001] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 146,375, filed February 5, 2021, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to methods and systems for frequency division multiplexing. Background Technology

[0003] In frequency division multiplexing (FDM), a transmitter can encode data across multiple frequency bands and transmit a radio frequency (RF) signal that combines signals from those bands. The RF signal is a combination of multiple subcarrier signals, each of which encodes information. Because unique information can be encoded in each frequency band, FDM systems typically have higher data throughput compared to other systems that use only a single carrier frequency.

[0004] In an orthogonal FDM (OFDM) system, each frequency band is orthogonal to its neighboring bands. In other words, the center frequency of the first band is aligned with the zero frequency of each neighboring band. This orthogonality reduces interference between cross-carrier signals. Furthermore, orthogonality allows OFDM receivers to more easily extract information from each band of the combined RF signal. Summary of the Invention

[0005] In some instances, a method includes generating a chip spread representing input bits by a processing circuitry system. Additionally, the method includes converting the chip spread into a plurality of symbols comprising a pair of symbols by the processing circuitry system. The method further includes mapping the pair of symbols to a single-carrier signal by the processing circuitry system, and generating a radio frequency (RF) signal based on the single-carrier signal by the processing circuitry system. The method further includes transmitting the RF signal via an antenna by the processing circuitry system.

[0006] In a further example, a computing system includes a processing circuitry and a non-transitory computer-readable medium coupled to the processing circuitry and storing instructions that, when executed by the processing circuitry, cause the processing circuitry to generate a chip spread representing input bits. Additionally, the non-transitory computer-readable medium stores instructions that cause the processing circuitry to convert the chip spread into a plurality of symbols comprising a pair of symbols and to map the pair of symbols to a single-carrier signal. The non-transitory computer-readable medium also stores instructions that cause the processing circuitry to generate a radio frequency (RF) signal based on the single-carrier signal comprising the pair of mapped symbols and to transmit the RF signal via an antenna.

[0007] In a further example, a system includes an antenna and a processing circuitry configured to generate chip diffusion representing input bits. The processing circuitry is further configured to convert the chip diffusion into a plurality of symbols comprising a pair of symbols, and to map the pair of symbols to a single-carrier signal. The processing circuitry is also configured to generate a radio frequency (RF) signal based on the single-carrier signal comprising the mapped pairs of symbols. The processing circuitry is further configured to transmit the RF signal via the antenna. Attached Figure Description

[0008] The features of the present invention can be understood from the following detailed description and accompanying drawings. In this respect:

[0009] Figure 1 This is a conceptual block diagram of a transmitter based on some aspects of this disclosure.

[0010] Figure 2 Four tables illustrate example conversions of bit-to-chip spread using direct sequence spread spectrum, according to some aspects of this disclosure.

[0011] Figure 3 A grid of forty symbols encoded across sixteen carrier frequencies is shown, according to some aspects of this disclosure.

[0012] Figure 4 This is a flowchart of a method for modulating an input bit onto a radio frequency (RF) signal according to some aspects of this disclosure.

[0013] Figure 5 This is a conceptual block diagram of a receiver based on some aspects of this disclosure.

[0014] Figure 6 This is a flowchart of a method for demodulating RF signals according to some aspects of this disclosure. Detailed Implementation

[0015] Specific examples are described in detail below with reference to the accompanying drawings. It should be understood that these examples are not intended to be limiting, and unless otherwise stated, no particular example requires any feature. Furthermore, in the following description, the formation of a first feature on or over a second feature may include instances in which the first feature and the second feature are in direct contact, and instances in which an additional feature is formed between the first feature and the second feature such that the first and second features are not in direct contact.

[0016] Generally, frequency division multiplexing (FDM) transmitters encode information across multiple frequency bands and combine signals from these bands for transmission. Compared to some other communication systems, FDM systems offer high throughput. However, FDM transmitters can consume significant power under peak conditions, resulting in a high peak-to-average power ratio (PAPR).

[0017] The transmitter of this disclosure can be configured to encode information only in a frequency band at a time, which can result in a PAPR closer to 1. Therefore, by using direct sequence spread spectrum (DSSS) and / or single-carrier frequency division multiple access (SC-FDMA) to spread information across time and / or multiple frequency bands, the transmitter of this disclosure can be more resistant to interference and noise. The lower PAPR and increased resilience can be useful for long-distance transmission. Of course, these advantages are merely examples, and no particular embodiment requires these advantages.

[0018] Refer to the diagram below for an example of frequency division multiplexing. In this regard, Figure 1 This is a conceptual block diagram of a transmitter 100 based on some aspects of this disclosure. Figure 1 In the example shown, transmitter 100 includes processing circuitry 102, forward error correction circuitry 110, interleaver circuitry 120, DSSS circuitry 130, bit-to-symbol circuitry 140, single-subcarrier mapping circuitry 150, inverse transformation circuitry 160, cyclic prefix circuitry 170, and antenna 180.

[0019] In some instances, transmitter 100 may contain more or fewer components. For example, transmitter 100 may include a digital-to-analog converter, a mixer, a combiner circuit (e.g., connected in parallel to a series circuit), and / or a splitter circuit (e.g., connected in series to a parallel circuit). Additionally or alternatively, Figure 1 Some of the components shown may be located outside of transmitter 100 and / or outside of processing circuitry system 102. For example, transmitter 100 may include an output node configured to couple to an external antenna.

[0020] Despite Figure 1 While shown as individual components, some or all of the forward error correction circuitry 110, interleaver circuitry 120, DSSS circuitry 130, bit-to-symbol circuitry 140, single subcarrier mapping circuitry 150, inverse transform circuitry 160, and cyclic prefix circuitry 170 may be implemented as hardware blocks within the processing circuitry system 102. Additionally or alternatively, Figure 1 Some or all of the elements shown may be implemented in instructions stored in non-transitory memory, wherein the processing circuitry system 102 may be configured to read instructions from memory and execute instructions.

[0021] Forward error correction circuit 110 can be configured to perform convolutional coding of the input bit stream and then send the bit stream to interleaver circuit 120. Examples of forward error correction include convolutional coding, channel coding, and polarity coding. In some instances, forward error correction circuit 110 uses concatenated codes that include Reed-Solomon block codes and inner half-rate convolutional codes. Additional details of examples of forward error correction can be found in the IEEE low-rate wireless network standard IEEE Std 802.15.4-2020, the entire contents of which are incorporated herein by reference. Interleaver circuit 120 can be configured to interleave bits received from forward error correction circuit 110 across time and / or frequency. To increase the robustness of the encoded information, interleaver circuit 120 can separate the payload bits output by forward error correction circuit 110.

[0022] Generally, there are two types of interference or noise experienced by transmitter 100: vertical interference and horizontal interference. In an example of vertical interference, transmitter 100 experiences short bursts of interference that affect all frequencies used by transmitter 100. By separating and spreading the payload bits across time, interleaver circuit 120 makes the payload bits more robust to short bursts of interference. In an example of horizontal interference, transmitter 100 experiences narrowband interference that affects some, but not all, of the frequency band in which transmitter 100 operates. By separating and spreading the payload bits across time (and therefore across frequency channels), interleaver circuit 120 makes the payload bits more robust to narrowband interference.

[0023] The bit stream output by interleaver circuit 120 contains payload bits that will be transmitted from transmitter 100 to remote receiver. DSSS circuit 130 can be configured to generate chip spread based on each input bit received from interleaver circuit 120. In instances where DSSS circuit 130 is configured to generate two, four, eight, twelve, or sixteen chips for each input bit received from interleaver circuit 120, the chip stream output by DSSS circuit 130 will be longer than the input bit stream received by DSSS circuit 130 from interleaver circuit 120. As an alternative to 1:X spread techniques, DSSS circuit 130 can use spread techniques that convert two or more bits into sequences of four or more chips (e.g., 2:X, 4:X, or 8:X spread techniques). Other spread spectrum techniques can be used as a complement to or alternative to DSSS. Additional details of instances of DSSS in communication systems can be found in U.S. Patent No. 9,935,681, entitled "Preamble Sequence Detection of Direct Sequence Spread Spectrum (DSSS) Signals," published April 3, 2018, and U.S. Patent No. 9,831,909, entitled "DSSS Inverted Spreading for Smart Utility Networks," published November 28, 2017, the entire contents of which are incorporated herein by reference.

[0024] In some instances, the chip stream output by the DSSS circuit 130 is more robust to interference because the receiver can still identify the payload bit in the transmitted signal even if one of the chips associated with the payload bit is corrupted by interference. Short interference bursts may damage the chips, but the receiver can evaluate neighboring chips to identify the value of the payload bit.

[0025] Bit-to-symbol circuit 140 can be configured to convert each chip received from DSSS circuit 130 into a corresponding symbol. Each symbol can be represented as a complex number with real and imaginary values. Each complex number can ultimately be mapped onto a carrier signal as a phase shift, amplitude variation, and / or frequency variation. Bit-to-symbol circuit 140 can use modulation processes such as quadrature amplitude modulation (QAM) (e.g., 16-QAM) or phase shift keying (PSK) (e.g., binary PSK or quadrature PSK). The chip ratio representing the payload bits to symbols can be 1:1, 1:2, 2:1, 4:1, or any other ratio. In an example where processing circuitry system 102 implements binary PSK, bit-to-symbol circuit 140 can be configured to convert each chip from DSSS circuit 130 into a corresponding symbol. Additional details on examples of PSK and QAM can be found in U.S. Patent No. 9,001,948, entitled “Pulse Shaping in a Communication System,” published April 7, 2015, the entire contents of which are incorporated herein by reference.

[0026] Single-subcarrier mapping circuit 150 can be configured to map each symbol to a single-subcarrier signal of inverse transform circuit 160. Single-subcarrier mapping circuit 150 can also be configured to map each symbol to a single input of inverse transform circuit 160, thereby setting all other inputs of inverse transform circuit 160 to zero. Therefore, for each time slot, circuits 150 and 160 can map a single symbol to a single subcarrier by at least modulating a sine wave or a cosine wave, or switching between sine and cosine waves. The total bandwidth of transmitter 100 can be divided into multiple frequency bands, and transmitter 100 can be configured to transmit on one of the frequency bands at a time. Processing circuitry system 102 can reuse the same carrier for the second symbol of a pair, such that differentially coded symbols share the same subcarrier.

[0027] Inverse transform circuit 160 can be configured to compute inverse Fast Fourier Transform (FFT) on the symbols output by single subcarrier mapping circuit 150. The output of inverse transform circuit 160 may contain samples of the symbols. Cyclic prefix circuit 170 may repeat all or part of each symbol before and / or after the symbol. Cyclic prefix circuit 170 can be configured to add a guard interval between the transmission of adjacent symbols. The guard interval reduces inter-symbol interference between adjacent symbols, which is an important consideration in multipath environments. Additional instance details of cyclic prefixes and guard intervals can be found in the IEEE low-rate wireless network standard IEEE Std 802.15.4-2020, the entire contents of which are incorporated herein by reference.

[0028] Figure 2Four tables, 210, 220, 230, and 240, illustrate example conversions of bit-to-chip diffusion using DSSS according to some aspects of this disclosure. Each of tables 210, 220, 230, and 240 illustrates the conversion from an input bit of 1 or 0 to a DSSS sequence, also known as chip diffusion. Tables 210, 220, 230, and 240 respectively illustrate diffusions of input bits into two, four, eight, and twelve chips. As used herein, a “DSSS value” refers to the number of chips used to represent each payload bit. Thus, table 210 depicts DSSS value 2, table 220 depicts DSSS value 4, and so on. The DSSS value may be a predetermined value built into the communication device. Alternatively, the user may be able to set the DSSS value such that the communication device selects a DSSS value based on user input.

[0029] Tables 210, 220, 230, and 240 illustrate implementations for converting a single bit value into two, four, eight, or twelve chips. A single bit value can be converted into other numbers of chips, such as sixteen, twenty, thirty-two, or sixty-four chips. In some instances, the transmitter can be configured to convert multiple bits, rather than a single bit, into sequences of chips. For example, two to eight DSSS can convert two bits into a sequence of eight chips. In this example, each pair of two bits can have four possible values, each of which is associated with at least one unique sequence of eight chips. This disclosure considers examples of two to sixteen DSSS and four to sixteen DSSS for communication apparatuses implementing DSSS.

[0030] Each input bit shown in Tables 210, 220, 230, and 240 corresponds to a payload bit of the information. By spreading each payload bit across the chips shown in Tables 210, 220, 230, and 240, the transmitter can increase the redundancy and flexibility of the transmitted data. For example, the spreads of 0011 and 1100 in Table 220 represent payload bits with logic 1, and the spreads of 0110 and 1001 represent payload bits with logic 0.

[0031] For each diffusion shown in Tables 210, 220, 230, and 240, two consecutive matching or identical chips (e.g., 11 or 00) at the beginning of the diffusion represent a logic value of 1 for the payload bit. Similarly, two consecutive non-matching or different chips (e.g., 10 or 01) at the beginning of the diffusion represent a logic value of 0 for the payload bit. For each symbol pair, a positive symbol is followed by a logic value of 1, a positive symbol is followed by a negative symbol indicating a logic value of 0, a negative symbol is followed by a positive symbol indicating a logic value of 0, and a negative symbol is followed by a negative symbol indicating a logic value of 1. The DSSS patterns shown in Tables 210, 220, 230, and 240 provide differential coding for the payload bits. The receiver can identify the value of the payload bit by determining whether the first two chips or symbols in the sequence are the same or different. For DSSS values ​​greater than 2, the receiver can evaluate multiple pairs of symbols to determine the value of each payload bit.

[0032] To avoid repetition of the same sequence, the transmitter can switch between even and odd spreads, using different codes for odd and even information. The transmitter can switch between even and odd spreads after each input bit or after a specific number of input bits. By switching between even and odd spreads, the transmitter avoids reusing the same spread. As an example of switching between even and odd spreads, the transmitter can generate a first even spread representing the first input bit, and then a second odd spread representing the next input bit. If three consecutive input bits have a logic value of 1, the transmitter can generate an even spread 00 representing the first input bit, an odd spread 11 representing the second input bit, and an even spread 00 representing the third input bit. Therefore, even if the three consecutive input bits in this example have the same logic value, the logic value of the chip representing the first input bit is opposite to the logic value of the chip representing the second input bit. The logic value of the chip representing the first input bit is the same as the logic value of the chip representing the third input bit.

[0033] Transmitting multiple chips or symbols for each payload bit improves robustness and redundancy. If the receiver has low sensitivity and / or the signal encounters interference, transmitting a single chip or symbol for each payload bit may result in information loss. Conversely, transmitting multiple chips for each payload bit spreads the information across time and, possibly, across frequencies. In an instance where one chip is damaged, a receiver with low sensitivity can still extract the value of the payload bit by evaluating the remaining chips in the sequence representing the payload bit.

[0034] Figure 3 A grid 300 of forty symbols encoded across sixteen carrier frequencies is shown, according to some aspects of this disclosure. Figure 3The symbols are shown after mapping to the carrier signal and after applying the inverse transform. Therefore, grid 300 and... Figure 1 The possible outputs of the inverse converter circuit 160 shown in the diagram correspond to the symbols 310 to 348, which are represented as two horizontally adjacent boxes in grid 300. Figure 3 The horizontal axis in the diagram represents the forty time slots used to transmit data. Figure 3 The vertical axis in the diagram represents 16 frequency bands, where data can be encoded for transmission. Grid 300 contains 16 frequency bands, but the transmitter of this disclosure may contain more or fewer transmission channels.

[0035] A transmitter implementing grid 300 can use a single subcarrier signal for each time slot. This technique results in lower throughput compared to another transmitter that encodes data across all 16 frequency bands during each time slot. Therefore, a transmitter implementing a single subcarrier signal for each time slot grid 300 will have a lower PAPR and produce an RF signal that is easier for the receiver to demodulate.

[0036] According to grid 300, only one subcarrier frequency is used for each time slot. A transmitter implementing grid 300 can select a new subcarrier frequency after every two time slots, such that symbols in each pair share the same frequency band. The transmitter can use FDM to divide the total bandwidth into channels, which can be selected by the transmitter for each pair of time slots. Alternatively, the transmitter of this disclosure can be configured to implement other forms of multiplexing for modulating RF signals, such as time division multiplexing or code division multiplexing.

[0037] Grid 300 shows the new channel assignments after every two time slots. For example, the transmitter assigns a pair of symbols 310 to band nine, a pair of symbols 312 to band six, and so on. Figure 3 In the example shown, the transmitter assigns each pair of symbols to a new, randomly selected frequency band. Although in Figure 3 Not shown in the diagram, but other implementations are possible, such as assigning three or more symbols to each channel, resulting in less frequent channel switching than in the example shown in grid 300. Additionally, the assignment of new channels can be random, pseudo-random, quasi-random, or deterministic.

[0038] The receiver can be configured to determine the payload bit represented by each pair of symbols by comparing the two symbol values ​​in each pair. In some instances, a logic value of 1 is represented by two identical symbol values, and a logic value of 0 is represented by two different symbol values. Therefore, the receiver can compare the second symbol value in the pair with the previous symbol value to determine the value of the payload bit represented by the pair of symbols. The receiver can demodulate RF signals using local information without any additional information, thereby reducing interference caused by frequency drift over time and multipath environments.

[0039] For a DSSS value of 2, the transmitter can be configured to convert each payload bit into a sequence of two chips and map each chip to a symbol. Therefore, each payload bit will be mapped to a pair of symbols. For a DSSS value of 2, each chip will occupy a distinct time slot, such that the two time slots will represent a single payload bit. Therefore, for a DSSS value of 2, each payload bit will be mapped to two time slots, such that pair 310 represents the first payload bit, pair 312 represents the second payload bit, and so on.

[0040] For DSSS values ​​higher than 2, each payload bit will be mapped to more than one pair of symbols. For example, at a DSSS value of 4, each payload bit will be converted into four chips, and each chip will be mapped to a symbol. Therefore, the payload bit will be represented by four symbols (e.g., across four time slots in grid 300), such that 310 and 312 represent the first payload bit, 314 and 316 represent the second payload bit, and so on. For a DSSS value of 4, each chip will occupy a different time slot, such that four time slots will represent a single payload bit. For a DSSS value of 8, 310, 312, 314, and 316 represent the first payload bit, 318, 320, 322, and 324 represent the second payload bit, and so on. For a DSSS value of 8, there will be eight time slots representing one payload bit, making the communication system more robust to interference than communication with a DSSS value of 1. The receiver will have eight chances to identify the value represented by the DSSS sequence, which increases the likelihood that the receiver will correctly identify the payload bit value.

[0041] A transmitter implementing the technology of this disclosure can be configured to perform random channel assignment. For example, the transmitter can assign each pair of symbols to a carrier signal based on a random number generator. An example represented in grid 300 includes a pair of symbols 312 encoded in a first carrier signal in the ninth frequency band of the sixteen frequency bands in grid 300. Symbol pair 314 is encoded in a second carrier signal in the sixth frequency band, symbol pair 316 is encoded in a third carrier signal in the twelfth frequency band, symbol pair 318 is encoded in a fourth carrier signal in the seventh frequency band, and symbol pair 320 is encoded in a fifth carrier signal in the fifth frequency band.

[0042] Consecutive symbol pairs are typically assigned to different carrier signals. However, depending on the generation of random numbers, some consecutive symbol pairs may be assigned to the same carrier signal, such that four or more consecutive symbols are assigned to the same carrier signal. As two examples, symbol pairs 320 and 322 are encoded in the carrier signal of the fifteenth frequency band, and symbol pairs 332 and 334 are encoded in the carrier signal of the fifth frequency band. Furthermore, due to random channel assignment, in Figure 3Five of the sixteen frequency bands shown in grid 300 are not used during the time slot period depicted.

[0043] Figure 4 This is a flowchart of a method for modulating an input bit onto an RF signal according to some aspects of this disclosure. Some procedures of method 400 may be performed in a different order than described, and many procedures may be performed concurrently in parallel. Furthermore, in some instances of this disclosure, procedures of method 400 may be omitted or substituted. Reference to method 400 Figure 1 The transmitter 100 shown in the figure is used to describe the technology, although other components may exemplify similar techniques.

[0044] In reference block 410, the DSSS circuit 130 generates chip spreads based on the input bits. Each spread may contain two or more chips representing a single payload bit received by the DSSS circuit 130 from the interleaver circuit 120. The chips may spread across time and / or frequency to encode information in the payload bit to prevent interference. In reference block 420, the bit-to-symbol circuit 140 converts the chip spreads into multiple symbols containing a pair of symbols. Each symbol may be represented as a complex number with real and imaginary values. Each complex number may be mapped onto the carrier signal as a phase shift, frequency modulation, and / or amplitude modulation based on the value of the complex number. In an instance where the DSSS value 2 is used by the processing circuitry system 102, the multiple symbols will contain only a pair of symbols. However, for higher DSSS numbers, the multiple symbols will contain multiple pairs of symbols, which can lead to greater robustness against narrowband interference.

[0045] Reference block 430, single subcarrier mapping circuit 150 maps the symbol pair to a single carrier signal. Processing circuitry system 102 can be configured to randomly assign frequency channels to each symbol pair. Processing circuitry system 102 can map each symbol to the assigned carrier signal by modulating the phase, frequency, and / or amplitude of the carrier signal using PSK, QAM, and / or any other suitable modulation technique. Reference block 440, inverse transform circuitry 160 performs an inverse FFT on the output of single subcarrier mapping circuitry circuit 150 to generate an RF signal. Processing circuitry system 102 can be configured to insert cyclic prefixes and / or guard intervals between adjacent symbols. Reference block 450, transmitter 100 transmits RF signals via antenna 180.

[0046] Figure 5 This is a conceptual block diagram of a receiver 500 based on some aspects of this disclosure. Figure 5In the example shown, receiver 500 includes processing circuitry 502, deinterleaver circuitry 520, symbol-to-bit circuitry 540, carrier extraction circuitry 550, conversion circuitry 560, and antenna 580. In some examples, receiver 500 may include more or fewer components. For example, receiver 500 may include an analog-to-digital converter, a mixer, inverse error correction, cyclic prefix removal, combiner circuitry, and / or splitter circuitry. Additionally or alternatively, Figure 5 Some of the components shown may be located outside the receiver 500 and / or outside the processing circuitry system 502. For example, the receiver 500 may include an output node configured to couple to an external antenna.

[0047] Despite Figure 5 While shown as separate components, some or all of the deinterleaver circuit 520, symbol bit-to-bit circuit 540, carrier extraction circuit 550, and conversion circuit 560 may be implemented as hardware blocks within the processing circuit system 502. Alternatively, Figure 5 Some or all of the elements shown may be implemented in instructions stored in non-transitory memory, wherein the processing circuitry system 502 may be configured to read instructions from memory and execute instructions.

[0048] The transformation circuit 560 can be configured to perform an FFT on the RF signal received by the antenna 580. The output of the transformation circuit 560 may contain samples of the RF signal. The carrier extraction circuit 550 can be configured to extract one or more symbols from the output of the transformation circuit 560. The carrier extraction circuit 550 can be configured to determine the carrier frequency and output symbols based on the phase, frequency, and / or amplitude modulation detected by the receiver 500 on the carrier signal.

[0049] For example, the symbol bit-to-bit circuit 540 can be configured to convert each pair of symbols into the value of the corresponding payload bit by comparing two consecutive symbols output from the carrier extraction circuit 550. The symbol bit-to-bit circuit 540 can use demodulation processes such as PSK and / or QAM. The number of symbols corresponding to each payload bit depends on the DSSS ratio used by the transmitter. The deinterleaving circuit 520 can be configured to deinterleave the bits received from the symbol bit-to-bit circuit 540.

[0050] Figure 6 This is a flowchart of a method for demodulating RF signals according to some aspects of this disclosure. Some procedures of method 600 may be performed in a different order than described, and many procedures may be performed concurrently in parallel. Furthermore, in some instances of this disclosure, procedures of method 600 may be omitted or substituted. Method 600 Reference Figure 5 The transmitter 500 shown in the figure is used to describe this, although other components may exemplify similar technologies.

[0051] Reference block 610, antenna 580 receives RF signals. The RF signals may contain information mapped to a single carrier signal for each time slot. Reference block 620, transformation circuit 560 performs a transformation on the RF signals to generate samples of the RF signals. The samples contain information about the symbols mapped to the carrier signal in each time slot. Reference block 630, carrier extraction circuit 550 extracts a pair of symbols from the samples.

[0052] Reference block 640, symbol bit-to-bit circuit 540 converts the pair of symbols into the pair of chips. Processing circuitry system 502 can be configured to use demodulation processes such as PSK and / or QAM to convert symbols into chips. Symbols can be represented as complex numbers with real and imaginary values. Each complex number can be mapped as an amplitude, phase, or frequency variation to a carrier signal mapped onto each carrier signal. Reference block 650, symbol bit-to-bit circuit 540 determines the payload bit value based on the pair of chips. The number of chips representing each payload bit depends on the DSSS implemented by the transmitter.

[0053] Generally, OFDM communication has the ability to deliver more information per hertz than many other communication types. Furthermore, OFDM communication systems can combat multipath conditions with longer symbol durations and the addition of cyclic prefixes. However, OFDM modulation typically suffers from significant PAPR in the range of 6 to 12 dB. The PAPR of an OFDM transmitter depends on the number of subcarriers used by the OFDM transmitter. High PAPR means higher power consumption for the same transmission power level, which is particularly important for battery-powered devices and vehicle-based devices. Therefore, OFDM transmitters are generally not used for communication over longer distances.

[0054] This disclosure describes a transmitter employing a single subcarrier per time slot, similar to SC-FDMA. Therefore, the transmitter can have a very low PAPR, approaching the theoretical limit of zero dB. Compared to an OFDM transmitter with the same average power consumption, the transmitter can be designed with fewer and / or smaller power amplifiers due to the lower PAPR. Additionally, the transmitter can be configured to create redundancy for each payload bit using DSSS. This redundancy can be particularly useful under low signal-to-noise ratio conditions (e.g., more noise energy or lower signal energy). By combining zero-dB PAPR with DSSS diffusion, the overall link budget of the communication system can be extended by up to 20 dB.

[0055] This disclosure also describes encoding binary information in pairs into symbols. The transmitter can be configured to spread each bit into multiple chips, convert each chip into a symbol, and map two consecutive symbols onto a single subcarrier signal. The transmitter can use differential coding of DSSS to differentially map incoming symbols onto the same subcarrier signal, allowing the symbols to effectively share a common phase reference. In contrast, transmitters using multiple simultaneous subcarrier signals may struggle to achieve a common phase reference without precise channel equalization.

[0056] In some instances, the transmitters disclosed herein can support long-distance communication due to their low PAPR and flexibility. Furthermore, in accordance with Federal Communications Commission Regulation 47C.FR §15.247(a)(2), the transmitters may have a bandwidth of 6 dB, potentially greater than 500 kHz.

[0057] The following numbered aspects represent one or more aspects of this disclosure.

[0058] Aspect 1. A method includes generating a chip spread representing input bits by a processing circuitry system. Additionally, the method includes converting the chip spread into a plurality of symbols comprising a pair of symbols by the processing circuitry system. The method further includes mapping the pair of symbols to a single-carrier signal by the processing circuitry system, and generating an RF signal based on the single-carrier signal by the processing circuitry system. The method further includes transmitting the RF signal via an antenna by the processing circuitry system.

[0059] Aspect 2. The method according to the foregoing aspect, wherein generating the chip diffusion comprises generating two consecutive chips representing the input bits.

[0060] Aspect 3. The method according to the foregoing aspect, wherein the matching value of the two consecutive chips represents the first value of the input bit.

[0061] Aspect 4. The method according to either of the foregoing aspects or any combination thereof, wherein the non-matching values ​​of the two consecutive chips represent a second value of the input bit that is different from the first value.

[0062] Aspect 5. The method according to the foregoing aspects or any combination thereof, wherein the input bit is a first input bit, the chip diffusion is a first chip diffusion, and the method further comprises generating a second chip diffusion representing a second input bit after generating the first chip diffusion.

[0063] Aspect 6. The method according to the foregoing aspect, wherein the logic value of the second input bit is the same as the logic value of the first input bit, and the logic value of the second chip diffusion is opposite to the logic value of the first chip diffusion.

[0064] Aspect 7. The method according to any of the foregoing aspects or any combination thereof, further comprising generating a third chip diffusion representing a third input bit after generating the second chip diffusion.

[0065] Aspect 8. The method according to the foregoing aspect, wherein the logic value of the third input bit is the same as the logic value of the second input bit, the logic value of the third chip diffusion is opposite to the logic value of the second chip diffusion, and the logic value of the third chip diffusion is the same as the logic value of the first chip diffusion.

[0066] Aspect 9. The method according to the foregoing aspects or any combination thereof, wherein the pair of symbols is a first pair of symbols, the single carrier signal is a first carrier signal, the plurality of symbols further includes a second pair of symbols, and the method further includes mapping the second pair of symbols to a second carrier signal different from the first carrier signal.

[0067] Aspect 10. The method according to the foregoing aspect, wherein the first pair of symbols encodes the value of the input bit, and the second pair of symbols encodes the value of the input bit.

[0068] Aspect 11. The method according to any of the foregoing aspects or any combination thereof, wherein transmitting the RF signal comprises transmitting a first RF signal at a first time, and the method further comprises generating a second RF signal based on a second carrier signal comprising the second pair of symbols.

[0069] Aspect 12. The method according to the foregoing aspect further includes transmitting the second RF signal at a second time after the first time.

[0070] Aspect 13. The method according to the four foregoing aspects or any combination thereof, wherein the first frequency band of the first carrier signal is orthogonal to the second frequency band of the second carrier signal.

[0071] Aspect 14. The method according to the foregoing aspects or any combination thereof, wherein the plurality of symbols comprises a first pair of symbols representing the input bit and a second pair of symbols representing the input bit.

[0072] Aspect 15. The method according to the foregoing aspects or any combination thereof, wherein the plurality of symbols comprises a first pair of symbols representing the input bit and a second pair of symbols representing the input bit, the single carrier signal is a first carrier signal, the second pair of symbols is different from the first pair of symbols, and the method further comprises selecting a first channel centered on a first frequency. The method further comprises mapping the first pair of symbols to the first carrier signal in the first channel, generating a first RF signal based on the first carrier signal, and transmitting the first RF signal at a first time. The method further comprises selecting a second channel centered on a second frequency different from the first frequency, mapping the second pair of symbols to a second carrier signal in the second channel, generating a second RF signal based on the second carrier signal, and transmitting the second RF signal at a second time after the first time.

[0073] Aspect 16. The method according to the foregoing aspects or any combination thereof, wherein converting the chip spread into the plurality of symbols comprises performing binary phase shift keying on the chip spread.

[0074] Aspect 17. The method according to the foregoing aspects or any combination thereof further includes adding a cyclic prefix and a guard interval between the pairs of symbols.

[0075] Aspect 18. The method according to the foregoing aspects or any combination thereof, wherein generating the RF signal comprises performing an inverse transformation on the single-carrier signal containing the pair of mapped symbols to generate the RF signal.

[0076] Aspect 19. A computing system includes a processing circuitry system and a non-transitory computer-readable medium coupled to the processing circuitry system and storing instructions that, when executed by the processing circuitry system, cause the processing circuitry system to generate a chip spread representing input bits. Additionally, the non-transitory computer-readable medium stores instructions that cause the processing circuitry system to convert the chip spread into a plurality of symbols comprising a pair of symbols and to map the pair of symbols to a single-carrier signal. The non-transitory computer-readable medium also stores instructions that cause the processing circuitry system to generate a radio frequency (RF) signal based on the single-carrier signal comprising the pair of mapped symbols and to transmit the RF signal via an antenna.

[0077] Aspect 20. The computing system according to the preceding aspect, wherein the non-transitory computer-readable medium storage instructions cause the processing circuitry system to perform the methods or any combination thereof described in aspects 1 to 18.

[0078] Aspect 21. A system includes an antenna and a processing circuitry configured to generate chip diffusion representing input bits. The processing circuitry is further configured to convert the chip diffusion into a plurality of symbols comprising a pair of symbols, and to map the pair of symbols to a single-carrier signal. The processing circuitry is also configured to generate a radio frequency (RF) signal based on the single-carrier signal comprising the pair of mapped symbols. The processing circuitry is further configured to transmit the RF signal via the antenna.

[0079] Aspect 22. The computing system according to the foregoing aspect, wherein the processing circuitry is configured to perform the methods or any combination thereof described in aspects 1 to 18.

[0080] Aspect 23. A system comprising components for performing the methods described in aspects 1 to 18 or any combination thereof.

[0081] This disclosure attributes functionality to transmitter 100, processing circuit systems 102 and 502, circuits 110, 120, 130, 140, 150, 160, 170, 520, 540, 550 and 560, and antennas 180 and 580. Transmitter 100, processing circuit systems 102 and 502, circuits 110, 120, 130, 140, 150, 160, 170, 520, 540, 550 and 560, and antennas 180 and 580 may include one or more processors. Transmitter 100, processing circuit systems 102 and 502, circuits 110, 120, 130, 140, 150, 160, 170, 520, 540, 550 and 560, and antennas 180 and 580 may include integrated circuit systems, discrete logic circuit systems, analog circuit systems, such as one or more microprocessors, microcontrollers, DSPs, application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), FPGAs, and / or any combination of any other processing resources.

[0082] In some instances, transmitter 100, processing circuit systems 102 and 502, circuits 110, 120, 130, 140, 150, 160, 170, 520, 540, 550 and 560, and antennas 180 and 580 may include multiple components, such as any combination of the processing resources listed above, as well as other discrete or integrated logic circuit systems and / or analog circuit systems.

[0083] The techniques described in this disclosure may also be embodied or encoded in articles of art that include non-transitory computer-readable storage media. Examples of non-transitory computer-readable storage media include random access memory (RAM), read-only memory (ROM), programmable ROM, erasable programmable ROM, electronically erasable programmable ROM, flash memory, drives, hard disks, magnetic media, optical media, or any other computer-readable storage device or tangible computer-readable medium. The term "non-transitory" may indicate that the storage medium is not embodied in a carrier wave or propagating signal. In some instances, non-transitory storage media may store data that may change over time (e.g., in RAM or cache).

[0084] In this description, the term "coupled" may encompass a connection, communication, or signaling path that achieves a functional relationship consistent with this description. For example, if device A generates a signal to control device B to perform an action: (a) in a first instance, device A is coupled to device B via a direct connection; or (b) in a second instance, if the intervening component C does not alter the functional relationship between device A and device B, then device A is coupled to device B via the intervening component C such that device B is controlled by device A via a control signal generated by device A.

[0085] It should be understood that this disclosure provides several exemplary embodiments, and modifications are possible for these embodiments. Such modifications are explicitly within the scope of this disclosure. Furthermore, applying these teachings to other environments, applications, and / or purposes is consistent with and conceived by this disclosure.

Claims

1. A method for modulating a radio frequency (RF) signal, comprising: The processing circuit system generates chip diffusion representing the input bits; The processing circuit system diffuses the chip into multiple symbols, each consisting of a pair of symbols; The processing circuitry system maps the pair of symbols to a single-carrier signal; The RF signal is generated by the processing circuit system based on the single-carrier signal; and The RF signal is transmitted by the processing circuit system via an antenna. The generation of the chip diffusion includes generating two consecutive chips representing the input bits. The matching value of the two consecutive chips represents the first value of the input bit, and The non-matching values ​​of the two consecutive chips represent a second value of the input bit that is different from the first value.

2. The method according to claim 1, The pair of symbols mentioned above is the first pair of symbols. The single-carrier signal mentioned above is the first carrier signal, and The plurality of symbols further includes a second pair of symbols. The method further includes mapping the second pair of symbols to a second carrier signal that is different from the first carrier signal.

3. The method according to claim 2, The first pair of symbols encodes the value of the input bit, and The second pair of symbols encodes the value of the input bit.

4. The method of claim 2, wherein transmitting the RF signal includes transmitting a first RF signal at a first time, the method further comprising: A second RF signal is generated based on the second carrier signal containing the second pair of symbols; and The second RF signal is transmitted at a second time after the first time.

5. The method according to claim 2, wherein the first frequency band of the first carrier signal is orthogonal to the second frequency band of the second carrier signal.

6. The method of claim 1, wherein converting the chip spread into the plurality of symbols comprises performing binary phase shift keying on the chip spread.

7. The method of claim 1, further comprising adding a cyclic prefix and a guard interval between the pair of symbols.

8. The method of claim 1, wherein generating the RF signal comprises performing an inverse transform on the single-carrier signal containing the mapped pair of symbols to generate the RF signal.

9. A method for modulating a radio frequency (RF) signal, comprising: The processing circuit system generates chip diffusion representing the input bits; The processing circuit system diffuses the chip into multiple symbols, each consisting of a pair of symbols; The processing circuitry system maps the pair of symbols to a single-carrier signal; The RF signal is generated by the processing circuit system based on the single-carrier signal; and The RF signal is transmitted by the processing circuit system via an antenna. The input bit mentioned above is the first input bit. The chip diffusion mentioned above is the first chip diffusion. The method further includes generating a second chip spread representing the second input bit after generating the first chip spread. The logic value of the second input bit is the same as the logic value of the first input bit, and The logic value of the second chip diffusion is the opposite of the logic value of the first chip diffusion.

10. The method of claim 9, further comprising generating a third chip diffusion representing a third input bit after generating the second chip diffusion. The logic value of the third input bit is the same as the logic value of the second input bit. The logic value of the third chip diffusion is opposite to the logic value of the second chip diffusion, and The logic value of the third chip diffusion is the same as the logic value of the first chip diffusion.

11. A method for modulating a radio frequency (RF) signal, comprising: The processing circuit system generates chip diffusion representing the input bits; The processing circuit system diffuses the chip into multiple symbols, each consisting of a pair of symbols; The processing circuitry system maps the pair of symbols to a single-carrier signal; The RF signal is generated by the processing circuit system based on the single-carrier signal; and The RF signal is transmitted by the processing circuit system via an antenna. The plurality of symbols includes a first pair of symbols representing the input bit and a second pair of symbols representing the input bit. The single-carrier signal mentioned above is the first carrier signal. The second pair of symbols is different from the first pair of symbols, and The method further includes: Select the first channel centered on the first frequency; In the first channel, the first pair of symbols is mapped to the first carrier signal; A first RF signal is generated based on the first carrier signal; The first RF signal is transmitted at the first moment; Select a second channel centered at a second frequency different from the first frequency; In the second channel, the second pair of symbols is mapped to the second carrier signal; A second RF signal is generated based on the second carrier signal; and The second RF signal is transmitted at a second time after the first time.

12. A computing system comprising: Processing circuit system; A non-transitory computer-readable medium coupled to the processing circuitry and storing instructions that, when executed by the processing circuitry, cause the processing circuitry to: Generate chip diffusion representing the input bits; The chip is diffused into multiple symbols, each consisting of a pair of symbols; Map the pair of symbols to a single-carrier signal; A radio frequency (RF) signal is generated based on the single-carrier signal containing the mapped pair of symbols; and The RF signal is transmitted via an antenna. The instructions for generating the chip diffusion include instructions for generating two consecutive chips representing the input bits. The matching value of the two consecutive chips represents the first value of the input bit, and The non-matching values ​​of the two consecutive chips represent a second value of the input bit that is different from the first value.

13. The computing system according to claim 12, The pair of symbols mentioned above is the first pair of symbols. The single-carrier signal mentioned above is the first carrier signal. The plurality of symbols further includes a second pair of symbols, and The non-transitory computer-readable medium further stores instructions that cause the processing circuitry to map the second pair of symbols to a second carrier signal that is different from the first carrier signal.

14. The computing system according to claim 13, The first pair of symbols encodes the value of the input bit, and The second pair of symbols encodes the value of the input bit.

15. The computing system according to claim 13, The RF signal mentioned above is the first RF signal transmitted at the first moment, and The non-transitory computer-readable medium further stores instructions that cause the processing circuitry to: A second RF signal is generated based on the second carrier signal; and The second RF signal is transmitted at a second time after the first time.

16. A computing system comprising: Processing circuit system; A non-transitory computer-readable medium coupled to the processing circuitry and storing instructions that, when executed by the processing circuitry, cause the processing circuitry to: Generate chip diffusion representing the input bits; The chip is diffused into multiple symbols, each consisting of a pair of symbols; Map the pair of symbols to a single-carrier signal; A radio frequency (RF) signal is generated based on the single-carrier signal containing the mapped pair of symbols; and The RF signal is transmitted via an antenna. The input bit mentioned above is the first input bit. The chip diffusion mentioned above is the first chip diffusion. The non-transitory computer-readable medium further stores instructions that cause the processing circuitry system to generate a second chip spread representing a second input bit after generating the first chip spread. The logic value of the second input bit is the same as the logic value of the first input bit, and The logic value of the second chip diffusion is the opposite of the logic value of the first chip diffusion.

17. A computing system comprising: Processing circuit system; A non-transitory computer-readable medium coupled to the processing circuitry and storing instructions that, when executed by the processing circuitry, cause the processing circuitry to: Generate chip diffusion representing the input bits; The chip is diffused into multiple symbols, each consisting of a pair of symbols; Map the pair of symbols to a single-carrier signal; A radio frequency (RF) signal is generated based on the single-carrier signal containing the mapped pair of symbols; and The RF signal is transmitted via an antenna. The plurality of symbols includes a first pair of symbols representing the input bit and a second pair of symbols representing the input bit. The second pair of symbols is different from the first pair of symbols, and The non-transitory computer-readable medium further stores instructions that cause the processing circuitry to: Select the first channel centered on the first frequency; In the first channel, the first pair of symbols is mapped to the first carrier signal; A first RF signal is generated based on the first carrier signal; The first RF signal is transmitted at the first moment; Select a second channel centered at a second frequency different from the first frequency; In the second channel, the second pair of symbols is mapped to the second carrier signal; A second RF signal is generated based on the second carrier signal; and The second RF signal is transmitted at a second time after the first time.

18. A system for modulating radio frequency (RF) signals, comprising: antenna; and The processing circuit system is configured to: Generate chip diffusion representing the input bits; The chip is diffused into multiple symbols, each consisting of a pair of symbols; Map the pair of symbols to a single-carrier signal; The RF signal is generated based on the single-carrier signal containing the mapped pair of symbols; and The RF signal is transmitted via the antenna. The generation of the chip diffusion includes generating two consecutive chips representing the input bits. The matching value of the two consecutive chips represents the first value of the input bit, and The non-matching values ​​of the two consecutive chips represent a second value of the input bit that is different from the first value.

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