Three-dimensional memory and methods of making the same, memory systems

Abstract

The application provides a three-dimensional memory, a preparation method thereof, and a storage system. The three-dimensional memory comprises: a stack structure comprising at least one stack layer formed by a gate layer and an insulating layer stacked along a first direction; a plurality of channel structures, each channel structure penetrating through the stack structure along the first direction; and a plurality of local conductive contact structures corresponding to the channel structures one by one and electrically connected to the channel structures on the stack structure. At least one channel structure is electrically connected to the local conductive contact structure through a channel connecting part. The lateral size of the channel connecting part in a direction perpendicular to the first direction is greater than the lateral size of the channel structure in contact with the channel connecting part. By arranging the channel connecting part corresponding to the channel structure and having a larger feature size than the channel structure, and by realizing the electrical connection between the channel structure and the local conductive contact structure, good electrical conduction between the channel structure and the bit line or the source line can be realized, and the reliability of the three-dimensional memory is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor design and manufacturing, and more specifically, to a structure of a three-dimensional memory, a method for fabricating a three-dimensional external memory, and a memory system. Background Technology

[0002] With the rise and development of artificial intelligence, big data, the Internet of Things, mobile communications, mobile devices, and cloud storage, the demand for storage density in memory (such as 3D memory) is increasing. However, due to limitations in technology, equipment, materials, and other factors, further increasing the storage density of memory is quite difficult. Summary of the Invention

[0003] This application provides a three-dimensional memory and a method for its fabrication that can at least partially solve the aforementioned problems existing in related technologies.

[0004] This application provides a three-dimensional memory, the memory comprising: a stacked structure including at least one stacked layer formed by a gate layer and an insulating layer stacked along a first direction; a plurality of channel structures, each of the channel structures penetrating the stacked structure along the first direction; and a plurality of local conductive contact structures located on the stacked structure, corresponding one-to-one with and electrically connected to the channel structures, wherein at least one of the channel structures is electrically connected to the local conductive contact structure through a channel connection portion, and in a direction perpendicular to the first direction, the lateral dimension of the channel connection portion is greater than the lateral dimension of the channel structure in contact with the channel connection portion.

[0005] In one embodiment, the plurality of channel structures include a plurality of first channel structures, the first channel structures being electrically connected to the local conductive contact structure via the channel connection portion, wherein the channel structure includes a channel layer and a channel plug, the channel layer penetrating the stacked structure along the first direction, the channel plug being disposed at one end of the channel structure and electrically connected to the channel layer; and the memory further includes at least one top select gate cutout structure, the top select gate cutout structure sequentially passing through the channel connection portion and a portion of the channel plug and a portion of the channel layer of the plurality of first channel structures along the first direction.

[0006] In one embodiment, the orthographic projection of the first channel structure in a plane perpendicular to the first direction and the orthographic projection of the top selection gate cutout structure in the same plane form an overlapping area, the maximum area of ​​the overlapping area being half the area of ​​the orthographic projection of the first channel structure.

[0007] In one embodiment, a plurality of first channel structures are arranged in a plane perpendicular to the first direction as a plurality of rows of first channel structures extending along a second direction perpendicular to the first direction; and the top selection gate cutout structure extends along the second direction and passes through the channel plug and a portion of the channel layer of each first channel structure in the corresponding row of first channel structures along the first direction.

[0008] In one embodiment, there are multiple channel connection portions, each corresponding to one of the multiple channel structures, and the channel structures are electrically connected to the local conductive contact structure through the corresponding channel connection portions.

[0009] In one embodiment, in a direction perpendicular to the first direction, the lateral dimension of the channel connection portion is greater than the lateral dimension of the portion of the local conductive contact structure that contacts the channel connection portion.

[0010] In one embodiment, the center of the orthographic projection of the first channel structure in contact with the top selection gate cutout structure in a plane perpendicular to the first direction does not overlap with the center of the orthographic projection of the corresponding channel connection portion in the same plane.

[0011] In one embodiment, in a plane perpendicular to the first direction, the locally conductive contact structure electrically connected to the first channel structure is spaced apart from the top select gate cutout structure.

[0012] In one embodiment, the top selected gate cutout structure passes through at least the first stacked layer among the plurality of stacked layers that is closest to the local conductive contact structure.

[0013] In one embodiment, the channel structure includes a channel layer that extends through the stacked structure along the first direction and includes a first region and a second region. The first region is adjacent to the local conductive contact structure, and the second region is located on the side of the first region away from the local conductive contact structure. The conductive impurity doping concentration of the first region is greater than that of the second region.

[0014] In one embodiment, the memory further includes a substrate located on the side of the stacked structure away from the local conductive contact structure and including a first substrate semiconductor layer; the channel structure includes a channel layer extending through the stacked structure along the first direction and reaching the first substrate semiconductor layer, and being connected to the first substrate semiconductor layer.

[0015] In one embodiment, the channel includes a third region and a fourth region along the first direction. The third region includes a portion of the channel layer extending into and adjacent to the first substrate semiconductor layer. The fourth region is located on the side of the third region away from the first substrate semiconductor layer. The conductive impurity doping concentration of the third region is greater than that of the fourth region.

[0016] In one embodiment, the memory further includes a substrate located on the side of the stacked structure away from the local conductive contact structure and including a second substrate semiconductor layer; the channel structure includes a channel layer extending through the stacked structure along the first direction and extending through the second substrate semiconductor layer; and the second substrate semiconductor layer is connected to a side portion of the channel layer.

[0017] In one embodiment, the channel structure includes: a channel hole penetrating the stacked structure along the first direction, an epitaxial layer located at the bottom of the channel hole, a functional layer located on the inner wall of the channel hole and on the epitaxial layer, and a channel layer located on the surface of the functional layer and penetrating the functional layer and connecting the epitaxial layer.

[0018] In one embodiment, the stacked structure includes multiple storage areas and multiple step areas, the channel structure is located within the storage areas, each storage area corresponds to at least one step area, the at least one step area is located in the middle of the corresponding storage area to divide the corresponding storage area into at least two sub-storage areas; or the at least one step area is located on the side of the corresponding storage area.

[0019] This application, in another aspect, provides a method for fabricating a three-dimensional memory. The method includes: forming an initial stacked structure, the initial stacked structure including at least one initial stacked layer formed by alternating gate sacrificial layers and insulating layers stacked along a first direction; forming a plurality of channel structures penetrating the initial stacked structure along the first direction; forming a channel connection portion on at least one of the channel structures, wherein in a direction perpendicular to the first direction, the lateral dimension of the channel connection portion is larger than the lateral dimension of the channel structure in contact with the channel connection portion; and forming an insulating isolation layer covering the channel connection portion on the top surface of the initial stacked structure, and forming local conductive contact structures that correspond one-to-one with and are electrically connected to the channel structures in the insulating isolation layer, wherein at least one of the local conductive contact structures is formed on the channel connection portion.

[0020] In one embodiment, the plurality of channel structures include a plurality of first channel structures, the first channel structures being electrically connected to the local conductive contact structure via the channel connection portion, the channel structure including a channel layer and a channel plug, the channel layer penetrating the initial stacked structure along the first direction, the channel plug being disposed at one end of the channel structure and electrically connected to the channel layer, the method further comprising: forming a top selection gate cutout structure that sequentially passes through the channel connection portion, a portion of the plurality of first channel structures, and a portion of the channel layer along the first direction.

[0021] In one embodiment, the maximum area of ​​the overlapping region formed by the orthographic projection of the first channel structure and the orthographic projection of the top selection gate cutout structure is set to half the area of ​​the orthographic projection of the first channel structure, wherein the orthographic projection of the first channel structure is the orthographic projection of the first channel structure in a plane perpendicular to the first direction, and the orthographic projection of the top selection gate cutout structure is the orthographic projection of the top selection gate cutout structure in the plane.

[0022] In one embodiment, forming a channel connection on at least one of the channel structures includes forming a plurality of channel connections corresponding one-to-one with the plurality of channel structures, wherein the channel structures are electrically connected to the local conductive contact structure through the corresponding channel connections.

[0023] In one embodiment, the method further includes setting the lateral dimension of the channel connection portion to be larger than the lateral dimension of the portion of the local conductive contact structure that contacts the channel connection portion in a direction perpendicular to the first direction.

[0024] In one embodiment, the method further includes setting the center of the orthographic projection of the first channel structure in contact with the top selection gate cutout structure in a plane perpendicular to the first direction to not overlap with the center of the orthographic projection of the corresponding channel connection portion in the plane.

[0025] In one embodiment, after forming the top selection gate cutout structure, the method further includes: forming a first contact hole offset from the top selection gate cutout structure in a plane perpendicular to the first direction; and filling the first contact hole with a conductive material filling layer to form the local conductive contact structure electrically connected to the first channel structure.

[0026] In one embodiment, forming the top select gate cutout structure includes: setting the top select gate cutout structure to pass through at least the first initial stacked layer among the plurality of initial stacked layers that is closest to the local conductive contact structure.

[0027] In one embodiment, before forming a channel connection on at least one of the channel structures, the method further includes doping a first region of the channel layer adjacent to the channel plug.

[0028] In one embodiment, forming a channel connection on at least one of the channel structures includes: forming an initial channel connection layer covering the channel structure on the top surface of the initial stacked structure; removing the portion of the initial channel connection layer located between the channel structures; and removing the portion of the initial channel connection layer located on a second channel structure to form a plurality of the channel connections, wherein the second channel structure is a channel structure directly electrically connected to the local conductive contact structure.

[0029] In one embodiment, forming a plurality of channel structures penetrating the initial stacked structure along the first direction includes: forming a plurality of channel vias penetrating the initial stacked structure along the first direction and extending into an initial substrate; sequentially forming a functional layer and a channel layer on the inner wall of the channel vias; removing the initial substrate and exposing the functional layer extending into the initial substrate; removing the exposed functional layer to expose the channel layer corresponding to the removed functional layer; and forming a first substrate semiconductor layer that covers the exposed channel layer.

[0030] In one embodiment, after exposing and removing the channel layer corresponding to the functional layer, the method further includes doping the exposed channel layer.

[0031] In one embodiment, forming the initial stacked structure on an initial substrate, the initial substrate including a substrate sacrificial layer, and forming a plurality of channel structures penetrating the initial stacked structure along a first direction includes: forming a plurality of channel holes penetrating the initial stacked structure along the first direction and extending through the substrate sacrificial layer; sequentially forming a functional layer and a channel layer on the inner wall of the channel holes; removing the substrate sacrificial layer to form a substrate void, and removing a portion of the sidewall of the functional layer exposed in the substrate void through the substrate void to expose the channel layer corresponding to the removed functional layer; and filling the substrate void to form a second substrate semiconductor layer extending through the exposed channel layer.

[0032] In one embodiment, forming a plurality of channel structures penetrating the initial stacked structure along the first direction includes: forming a plurality of channel holes penetrating the initial stacked structure along the first direction; forming the epitaxial layer at the bottom of the channel holes; forming an initial functional layer on the inner wall of the channel holes and on the surface of the epitaxial layer; removing a portion of the initial functional layer located on the surface of the epitaxial layer to form a functional layer and expose a portion of the epitaxial layer; and forming the channel layer connected to the epitaxial layer on the surface of the functional layer and on the exposed surface of the epitaxial layer.

[0033] In one embodiment, the initial stacked structure includes multiple storage areas and multiple step areas, the channel structure is formed within the storage areas, each storage area corresponds to at least one step area, and the method further includes: setting the at least one step area in the middle of the corresponding storage area to divide the corresponding storage area into at least two sub-storage areas; or setting the at least one step area on the side of the corresponding storage area.

[0034] This application provides another aspect of a storage system, the storage system comprising: a controller and a memory as described in any one of the claims of this application, the controller being coupled to the memory and used to control the memory to store data.

[0035] In one embodiment, the memory includes at least one of a three-dimensional NAND memory and a three-dimensional NOR memory.

[0036] According to at least one embodiment of the three-dimensional memory, fabrication method, and storage system provided in this application, by providing a channel connection portion corresponding to the channel structure and having a larger feature size than the channel structure, and electrically connecting the channel structure and the local conductive contact structure through the channel connection portion, the feature size of the contact window for the electrical connection between the channel structure and the local conductive contact structure can be increased, achieving good electrical conduction between the channel structure and the bit line or source line, thereby improving the reliability and electrical characteristics of the three-dimensional memory. Furthermore, for the channel structure near the top select gate notch structure, the spacing between the two rows of channel structures on both sides of the top select gate notch structure can be avoided due to the influence of the top select gate notch structure, and / or the channel structure near the top select gate notch structure can only serve as a virtual channel structure due to the influence of the top select gate notch structure. Therefore, at least one embodiment of this application can increase the arrangement density of the channel structure and reduce the setting of virtual channel structures, thereby facilitating the improvement of storage density per unit of three-dimensional memory.

[0037] Furthermore, by setting a channel connection portion that corresponds to the channel structure and has a larger feature size than the channel structure, and electrically connecting the channel structure and the local conductive contact structure through the channel connection portion, the feature size of the contact window for the electrical connection between the channel structure and the local conductive contact structure can be increased. Based on this, the top select gate cutout structure can obtain a larger lateral dimension in the direction perpendicular to its extension direction; and to a certain extent, it can avoid the risk of leakage or short circuits caused by damage to the channel structure due to its proximity to the top select gate opening structure during the formation of the top select gate opening structure, further improving the reliability and electrical characteristics of the three-dimensional memory. The aforementioned lateral dimension can be understood as the lateral feature size of the top select gate cutout structure. Attached Figure Description

[0038] Other features, objects, and beneficial effects of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. In the drawings:

[0039] Figure 1A This is a top view of a three-dimensional memory device;

[0040] Figure 1B This is a top view of another type of three-dimensional memory.

[0041] Figure 2 This is a top view schematic diagram of a three-dimensional memory according to one embodiment of this application;

[0042] Figure 3A It is along Figure 2 A schematic diagram of a partial cross-section taken by line M-M' in the diagram;

[0043] Figure 3B This is a cross-sectional view of a three-dimensional memory according to one embodiment of this application;

[0044] Figure 4 This is a top view schematic diagram of a three-dimensional memory according to another embodiment of this application;

[0045] Figure 5A It is along Figure 4 A schematic diagram of a partial cross-section taken by line N-N' in the diagram;

[0046] Figure 5B This is a cross-sectional view of a three-dimensional memory according to another embodiment of this application;

[0047] Figure 6 According to one embodiment of this application, Figure 3B or Figure 5B The diagram shows a partial cross-sectional view of region S in the three-dimensional memory.

[0048] Figure 7According to another embodiment of this application, Figure 3B or Figure 5B The diagram shows a partial cross-sectional view of region S in the three-dimensional memory.

[0049] Figure 8 According to yet another embodiment of this application, Figure 3B or Figure 5B The diagram shows a partial cross-sectional view of region S in the three-dimensional memory.

[0050] Figure 9 This is a top view schematic diagram of a stacked structure according to one embodiment of this application;

[0051] Figure 10 This is a top view schematic diagram of a stacked structure according to another embodiment of this application;

[0052] Figure 11 This is a flowchart of a method for fabricating a three-dimensional memory according to one embodiment of this application;

[0053] Figures 12A to 12E These are schematic diagrams illustrating the fabrication method of a three-dimensional memory according to one embodiment of this application.

[0054] Figures 13A to 13E These are schematic diagrams illustrating the fabrication method of a three-dimensional memory according to yet another embodiment of this application; and

[0055] Figure 14 This is a schematic diagram of a storage system structure according to one embodiment of this application.

[0056] Specific methods

[0057] The present application will now be described in detail with reference to the accompanying drawings. The exemplary embodiments mentioned herein are for illustrative purposes only and are not intended to limit the scope of the application. Throughout the specification, the same reference numerals refer to the same elements.

[0058] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. As used herein, the terms “approximately,” “about,” and similar terms are used to indicate approximation rather than degree and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0059] It should also be understood that the expression "and / or" includes any and all combinations of one or more of the associated listed items. Expressions such as "comprising," "including," "having," "having," and / or "having have" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence or addition of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. When describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to an example or illustration.

[0060] In addition, when terms such as “connection,” “covering,” and / or “formed on” are used in this application, they may indicate that the corresponding components are in direct or indirect contact, unless there are other explicit limitations or can be inferred from the context.

[0061] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. Furthermore, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and shall not be interpreted in an idealized or overly formalized sense.

[0062] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps in the methods described in this application are not limited to the order in which they are described, but can be performed in any order or in parallel. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0063] Figure 1A This is a top view schematic diagram of a three-dimensional memory 10. Figure 1B This is a top view of another type of three-dimensional memory 10'.

[0064] like Figure 1A and Figure 1B As shown, in a three-dimensional memory 10 or 10', the channel structures 20 are arranged in an interleaved manner and can be divided into multiple channel structure rows, such as channel structure rows 21 and 22. The top select gate cutout structure 30 can extend in the y-direction and has a lateral dimension CD3 in the x-direction, where the x-direction is perpendicular to the y-direction. The top select gate cutout structure 30 can divide the channel structure rows on both sides of the top select gate cutout structure 30 into multiple operating areas, thereby facilitating the control of the divided operating areas for programming, erasing, and other operations.

[0065] However, when forming the cut in the top selection grid cut structure, the cut location is adjacent to the aforementioned channel structure row, which can easily damage the channel structure in the adjacent channel structure row, leading to risks such as leakage or short circuits. To mitigate these risks to some extent, it is possible to... Figure 1A This can be achieved by increasing the row spacing between the two rows of channel structures 21 and 22 on both sides of the top selection gate cutout structure 30, as shown. Alternatively, it can be achieved through methods such as... Figure 1B The channel structure row 23 shown, which is covered by the top selected gate cutout structure 30, is used as a virtual channel structure row without storage function. However, all of the above arrangements limit the improvement of unit storage density in three-dimensional memory.

[0066] Figure 2 This is a top view schematic diagram of a three-dimensional memory 1000 according to one embodiment of this application. Figure 3A It is along Figure 2 A schematic diagram of a partial cross-section taken by line M-M' in the diagram. Figure 3B This is a cross-sectional view of a three-dimensional memory 1000 according to one embodiment of this application. Figure 4 This is a top view of a three-dimensional memory 1000 according to another embodiment of this application. Figure 5A It is along Figure 4 A schematic diagram of a partial cross-section taken by line N-N' in the diagram. Figure 5B This is a cross-sectional view of a three-dimensional memory 1000 according to another embodiment of this application.

[0067] like Figures 2 to 5BAs shown, the three-dimensional memory 1000 provided in at least one manner according to this application may include: a stacked structure 200', a plurality of channel structures (not shown), a plurality of local conductive contact structures (not shown), and a channel connection portion (not shown). The stacked structure 200' includes at least one stacked layer 201 formed by alternatingly stacked gate layers 230 and insulating layers 210 along a first direction (z direction). The plurality of channel structures may include: two first channel structures 300-1 and 300-3, and a second channel structure 300-2. Each channel structure may extend through the stacked structure 200' along the first direction. The plurality of local conductive contact structures are located on the stacked structure 200' and correspond one-to-one with and are electrically connected to the channel structures. The local conductive contact structures may include a first local conductive contact structure 800-1 and a second local conductive contact structure 800-2, and the channel connection portion may include a first channel connection portion 600-1 and a second channel connection portion 600-2. At least one channel structure is electrically connected to the local conductive contact structure through its corresponding channel connection portion. For example, a first channel structure 300-1 is electrically connected to a first local conductive contact structure 800-1 via a first channel connection portion 600-1; and another first channel structure 300-3 is electrically connected to the first local conductive contact structure 800-1 via a second channel connection portion 600-2.

[0068] like Figure 3A and 5A As shown, in a direction perpendicular to the first direction, such as the x-direction or y-direction, the lateral dimension of the channel connection portion is greater than the lateral dimension of the channel structure's contact portion with the channel connection portion. The lateral dimension of the channel connection portion can be understood as a characteristic dimension of the channel connection portion, and the lateral dimension of the channel structure's contact portion with the channel connection portion can be understood as a characteristic dimension of the channel structure. For example, the lateral dimension CD2-2 of the first channel connection portion 600-1 is greater than the lateral dimension CD1-2 of the contact portion of a first channel structure 300-1; the lateral dimension CD2-1 of the second channel connection portion 600-2 is greater than the lateral dimension CD1-1 of the contact portion of another first channel structure 300-3.

[0069] Alternatively, the channel structure can also be directly electrically connected to the local conductive contact structure. For example, the second channel structure 300-2 can be directly electrically connected to the second local conductive contact structure 800-2.

[0070] Locally conductive contact structures, typically bit line contacts or source line contacts in 3D memory, are used to achieve electrical connection between the channel structure and the bit line or source line. As the number of stacked layers increases and the storage density per unit area improves, the feature sizes of 3D memory are approaching their lower limits. During the process of achieving electrical connection between the channel structure and the locally conductive contact structure, the feature size of the contact window between the two is often too small, leading to risks such as poor contact or lack of electrical conduction. These risks ultimately affect the reliability of 3D memory, resulting in reliability degradation or low wafer testing yield.

[0071] The three-dimensional memory provided in at least one embodiment of this application, by setting a channel connection portion corresponding to the channel structure and having a larger feature size than the channel structure, and electrically connecting the channel structure and the local conductive contact structure through the channel connection portion, can increase the feature size of the contact window for the electrical connection between the channel structure and the local conductive contact structure, thereby achieving good electrical conduction between the channel structure and the bit line or source line, and improving the reliability and electrical characteristics of the three-dimensional memory.

[0072] Specifically, such as Figure 3A and 5A As shown, the stacked structure 200' may include at least one stacked layer 201 formed by alternatingly stacked insulating layers 210 and gate layers 230 along a first direction. Each stacked layer 201 may include an insulating layer 210 and a gate layer 230. The gate layer 230 may include a conductive material, such as any one or a combination of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), doped crystalline silicon, or silicides. The insulating layer 210 may be used as an isolation stacked layer, including but not limited to an insulating dielectric material layer such as a silicon oxide layer. Furthermore, the number of layers in the stacked structure 200' is not limited to the number shown in the figure, and may be additionally configured as needed, such as 32 layers, 64 layers, 128 layers, etc.

[0073] As the demand for storage capacity in three-dimensional memory continues to increase, the number of memory stack layers is gradually increasing. The stack structure 200' may include multiple sub-stack structures formed using techniques such as dual-stack or multi-stack. These multiple sub-stack structures may be stacked sequentially in a first direction to form the stack structure 200', wherein each sub-stack structure may include multiple alternately stacked insulating layers and gate layers. The number of layers in each sub-stack structure may be the same or different. The description of a single stack structure below is entirely or partially applicable to stack structures formed by multiple sub-stack structures; therefore, related or similar descriptions will not be repeated.

[0074] The stacked structure 200' may include a channel structure extending therethrough. The channel structure may be, for example, a first channel structure 300-1, another first channel structure 300-3, and a second channel structure 300-2. The channel structure may include a semiconductor layer and a composite dielectric layer filled in a channel hole (not shown), such as a functional layer (not shown) and a channel layer (not shown) sequentially formed on the inner wall of the channel hole, and a channel plug (not shown) connected to the channel layer, wherein the channel layer extends through the stacked structure 200' along a first direction, and the channel plug is disposed at one end of the channel structure and electrically connected to the channel layer.

[0075] The functional layer may include a barrier layer, a charge trapping layer, and a tunneling layer sequentially disposed on the inner wall of the channel via. Alternatively, the channel via may have a cylindrical or columnar shape extending through the stacked structure 200'. The channel layer may include silicon, such as amorphous silicon, polycrystalline silicon, or monocrystalline silicon. The material of the channel layer includes, but is not limited to, N-type doped polycrystalline silicon. Similar to the channel via, the functional layer and the channel layer may also have a cylindrical or columnar shape extending through the stacked structure 200'.

[0076] A first channel structure 300-1 includes a first channel layer 330-1 and a first channel plug 340-1; a second channel structure 300-2 includes a second channel layer 330-2 and a second channel plug 340-2; and another first channel structure 300-3 includes another first channel layer 330-3 and another channel plug 340-3.

[0077] A first channel layer 330-1, a second channel layer 330-2, and a second first channel layer 330-3 can all penetrate the stacked structure 200' along a first direction. A first channel plug 340-1, a second channel plug 340-2, and a second channel plug 340-3 are respectively disposed at one end of a first channel structure 300-1, a second channel structure 300-2, and a second first channel structure 300-3, for example, at one end of the channel structure near the local conductive contact structure, and are electrically connected to a first channel layer 330-1, a second channel layer 330-2, and a second first channel layer 330-3, respectively.

[0078] The first local conductive contact structure 800-1 and the second local conductive contact structure 800-2 are located on the stacked structure 200' and correspond one-to-one with the channel structures and are electrically connected. At least one channel structure is electrically connected to the local conductive contact structure through its corresponding channel connection portion. For example, a first channel structure 300-1 is electrically connected to the first local conductive contact structure 800-1 through a first channel connection portion 600-1; and another first channel structure 300-3 is electrically connected to the first local conductive contact structure 800-1 through a second channel connection portion 600-2.

[0079] In directions perpendicular to the first direction (e.g., the x and y directions), the lateral dimension of the channel connection is larger than the lateral dimension of the portion of the channel structure that contacts the channel connection. For example, the lateral dimension CD2-2 of the first channel connection 600-1 is larger than the lateral dimension CD1-2 of the portion of a first channel structure 300-1 that contacts the first channel connection 600-1; the lateral dimension CD2-1 of the second channel connection 600-2 is larger than the lateral dimension CD1-1 of the portion of another first channel structure 300-3 that contacts the second channel connection 600-2. Alternatively, the channel structure can also be directly electrically connected to a local conductive contact structure. For example, the second channel structure 300-2 can be directly electrically connected to a second local conductive contact structure 800-2.

[0080] Furthermore, in one embodiment of this application, in directions perpendicular to the first direction (e.g., the x and y directions), the lateral dimension of the channel connection portion is larger than the lateral dimension of the portion of the local conductive contact structure that contacts the channel connection portion. For example, the lateral dimension CD2-2 of the first channel connection portion 600-1 is larger than the lateral dimension CD3-1 of the portion of the first local conductive contact structure 800-1 that contacts the first channel connection portion 600-1; the lateral dimension CD2-1 of the second channel connection portion 600-2 is larger than the lateral dimension CD3-2 of the portion of the first local conductive contact structure 800-1 that contacts the second channel connection portion 600-2.

[0081] Therefore, the three-dimensional memory provided in at least one embodiment of this application, by providing a channel connection portion corresponding to the channel structure and having a larger feature size than the channel structure, and electrically connecting the channel structure and the local conductive contact structure through the channel connection portion, can increase the feature size of the contact window for the electrical connection between the channel structure and the local conductive contact structure, thereby achieving good electrical conduction between the channel structure and the bit line or source line, and improving the reliability and electrical characteristics of the three-dimensional memory.

[0082] In addition, refer to again Figures 2 to 5B The three-dimensional memory 1000 provided in at least one embodiment of this application further includes at least one top select gate cutout structure 700. The three-dimensional memory may include multiple memory blocks, and further, each memory block may be divided into multiple finger memory areas. By setting a top select gate cutout structure in the three-dimensional memory, more precise control over memory structures such as finger memory areas can be obtained, and the power consumption of the three-dimensional memory can be reduced, as well as its resistance-capacitance delay, etc.

[0083] The top selection gate cutout structure 700 passes sequentially along a first direction through the channel connection portion and the channel plug and a portion of the channel layer of a plurality of first channel structures. For example, the top selection gate cutout structure 700 passes sequentially along the first direction through a first channel plug 340-1 and a portion of a first channel layer 330-1 of a first channel structure 300-1.

[0084] In other words, the difference between one first channel structure 300-1 and another first channel structure 300-3 is that one first channel structure 300-1 contacts the top selection gate cutout structure 700, and a first channel plug 340-1 and a portion of a first channel layer 330-1 located on top of it are penetrated by the top selection gate cutout structure 700. Furthermore, the difference between the first channel connection portion 600-1 and the second channel connection portion 600-2 is that the first channel connection portion 600-1 contacts the top selection gate cutout structure 700, and is penetrated by the top selection gate cutout structure 700.

[0085] Therefore, according to at least one embodiment of the three-dimensional memory provided in this application, by providing a channel connection portion corresponding to the channel structure and having a larger feature size than the channel structure, and electrically connecting the channel structure and the local conductive contact structure through the channel connection portion, the feature size of the contact window for the electrical connection between the channel structure and the local conductive contact structure can be increased. Therefore, for the channel structure near the top selection gate cutout structure, the spacing between the two rows of channel structures on both sides of the top selection gate cutout structure can be avoided due to the influence of the top selection gate cutout structure, and / or the channel structure near the top selection gate cutout structure can be avoided from only serving as a virtual channel structure due to the influence of the top selection gate cutout structure. Therefore, at least one embodiment of this application can increase the arrangement density of the channel structure and reduce the setting of virtual channel structures, thereby facilitating the improvement of storage density in a three-dimensional memory unit.

[0086] Specifically, such as Figure 2 and Figure 4 As shown, multiple first channel structures 300-1 are arranged in a plane perpendicular to the first direction (which can be understood as the plane containing the x and y directions) as multiple rows of first channel structures extending along a second direction (y direction) perpendicular to the first direction, such as first channel structure rows 31 and 32.

[0087] Combination Figure 2 , Figure 4 and Figure 5AThe top selection gate cutout structure 700 extends along a second direction and passes through a portion of a first channel plug 340-1 and a first channel layer 330-1 of each first channel structure 300-1 in the corresponding rows of first channel structures 31 and 32. Furthermore, a first channel connection portion 600-1 is provided above a first channel structure 300-1, and the top selection gate cutout structure 700 extends along the second direction, similarly passing through a portion of the top of each first channel connection portion 600-1 in the corresponding row of first channel structures, wherein each first channel connection portion 600-1 corresponds to each first channel structure 300-1 in the row of first channel structures. The top selection gate cutout structure 700 has a lateral dimension CD4 in the x-direction perpendicular to the y-direction.

[0088] Alternatively, the orthographic projection of a first channel structure 300-1 in a plane perpendicular to a first direction overlaps with the orthographic projection of the top selected gate cutout structure 700 in the same plane, the maximum area of ​​which is half the area of ​​the orthographic projection of the first channel structure 300-1.

[0089] Combination Figure 1A , Figure 1B as well as Figures 2 to 4 In at least one embodiment of the three-dimensional memory provided in this application, the top selection gate cutout structure 700 passes through a portion of each of the first channel structures 300-1 in the corresponding first channel structure row along a first direction, so that the first channel structure 300-1 near the top selection gate cutout structure still has storage function. Based on this, the width of a storage area of ​​the three-dimensional memory tends to decrease in the third direction (x direction), for example, it can be reduced from width W1 / W2 to width W3 / W4.

[0090] For example, Figure 1B The illustrated three-dimensional memory includes nine rows of channel structures arranged in an interleaved manner along a third direction. The channel structure row 23, covered by the top selected gate cutout structure 30, is used as a virtual channel structure row without storage function, indicating a storage area with a width of W2 in the third direction. Figure 2In the illustrated three-dimensional memory, the top selection gate cutout structure 700 passes through a portion of each of the first channel structures 300-1 in the corresponding rows 31 and 32 of the first channel structure. Therefore, the first channel structure 300-1 that is passed through still retains its storage function. Thus, eight rows of first channel structures can be arranged in an interleaved manner in the third direction, indicating that the width of the storage area in the third direction can be reduced to W3. Therefore, the structural arrangement of the three-dimensional memory provided according to at least one embodiment of this application can increase the unit storage density in the three-dimensional memory, allowing more channel structures to be arranged in the same storage area. Furthermore, the number of channel structure rows is not limited to the number shown in the figure and can be set separately as needed.

[0091] In addition, such as Figure 3A and Figure 5A As shown, the top select gate cutout structure 700 can sequentially pass through a portion of the first channel connection 600-1, a first channel plug 340-1 of a first channel structure 300-1, and a first channel layer 330-1 along a first direction. In other words, the top select gate cutout structure 700 can extend along the first direction and pass through at least one of the plurality of stacked layers 201 included in the stacked structure 200', such as the first stacked layer closest to the local conductive contact structure. The first stacked layer can be the top select stacked layer of a three-dimensional memory, which can form the top select transistor controlling the string of memory cells in the three-dimensional memory. However, this application does not limit the extension length of the top select gate cutout structure 700 in the first direction.

[0092] Furthermore, in one embodiment of this application, in a plane perpendicular to the first direction (e.g., the plane containing the x and y directions), a first local conductive contact structure 800-1 electrically connected to a first channel structure 300-1 is spaced apart from the top select gate cutout structure 700. In other words, the first local conductive contact structure 800-1 is located above the first channel structure 300-1 and is offset from the first channel structure 300-1 in the first direction, so that the first local conductive contact structure 800-1 is spaced apart from the top select gate cutout structure 700 in a plane perpendicular to the first direction. By spaced apart the first local conductive contact structure 800-1 from the top select gate cutout structure 700, the risk of short circuits between, for example, bit line contacts and the top select gate cutout structure can be avoided to a certain extent, thereby improving the reliability of the 3D memory.

[0093] In addition, such as Figure 2 and 3AAs shown, in one embodiment of this application, the center (not shown) of the orthographic projection of a first channel structure 300-1 that contacts the top selection gate cutout structure 700 in a plane perpendicular to the first direction does not overlap with the center (not shown) of the orthographic projection of the corresponding first channel connection portion 600-1 in the plane. By setting the two centers to not overlap, the risk of damage to the first channel structure due to the proximity of the cutout position to the first channel structure during the formation of the top selection gate cutout structure can be avoided to a certain extent, thus preventing the risk of leakage or short circuit.

[0094] As an option, combine Figures 2 to 3B In one embodiment of this application, the channel structure 300 of the three-dimensional memory 1000 may include a first channel structure 300-1 and another first channel structure 300-3, wherein both the first channel structure 300-1 and the other first channel structure 300-3 are provided with channel connection portions. For example, the first channel structure 300-1 is provided with a first channel connection portion 600-1 and is electrically connected to the first local conductive contact structure 800-1 through the first channel connection portion 600-1; the other first channel structure 300-3 is provided with a second channel connection portion 600-2 and is electrically connected to the first local conductive contact structure 800-1 through the second channel connection portion 600-2.

[0095] As another option, combining Figures 4 to 5B In one embodiment of this application, the channel structure 300 of the three-dimensional memory 1000 may include a first channel structure 300-1 and a second channel structure 300-2. The first channel structure 300-1 is provided with a first channel connection portion 600-1 and is electrically connected to a first local conductive contact structure 800-1 through the first channel connection portion 600-1. The second channel structure 300-2 is not provided with a channel connection portion and is directly electrically connected to the second local conductive contact structure 800-2.

[0096] The first local conductive contact structure 800-1 and the second local conductive contact structure 800-2 have the same function and can be formed simultaneously, and their structures are also basically similar. The difference between the two is that, in the first direction, the first local conductive contact structure 800-1 has a relatively shorter extension length compared to the second local conductive contact structure 800-2, so that it can be electrically connected to a first channel structure 300-1 through the first channel connection portion 600-1.

[0097] In addition, such as Figure 3A and Figure 5AAs shown, in one embodiment of this application, the channel layer may include at least two regions with different doping concentrations along a first direction, such as a first region 331 and a second region 332. The first region 331 is adjacent to local conductive contact structures 800-1 and 800-2, and the second region 332 is located on the side of the first region 331 away from the local conductive contact structures 800-1 and 800-2. Compared to the second region, the doping concentration of conductive impurities in the first region 331 is greater than that in the second region 332. The specific fabrication process of the channel layer will be described below. Increasing the doping concentration of conductive impurities in the portion of the channel layer closer to the local conductive contact structures can achieve a good and stable electrical connection between the channel layer and the local conductive contact structures, thereby improving the electrical performance of the three-dimensional memory.

[0098] Figure 6 According to one embodiment of this application, Figure 3B or Figure 5B A partial cross-sectional schematic diagram of region S in the three-dimensional memory 1000 is shown. Figure 7 According to another embodiment of this application, Figure 3B or Figure 5B A partial cross-sectional schematic diagram of region S in the three-dimensional memory 1000 is shown. Figure 8 According to yet another embodiment of this application, Figure 3B or Figure 5B A partial cross-sectional schematic diagram of region S in the three-dimensional memory 1000 is shown.

[0099] Combination Figure 3B , Figure 5B as well as Figures 6 to 8 The three-dimensional memory 1000 provided in at least one embodiment of this application also includes a substrate 100, on which a stacked structure 200' may be located. However, those skilled in the art should understand that, without departing from the teachings of this application, the substrate 100 may include different layer structures depending on the three-dimensional memory architecture, and this application does not limit this. For example, the substrate 100 may include local structures connected to a channel layer, which are used to form circuit loops that enable the operation of memory cells.

[0100] As an option, combine Figure 3B , Figure 5B and Figure 6In one embodiment of this application, substrate 100 is located on the side of stacked structure 200' away from local conductive contact structures 800-1 and 800-2, and includes a first substrate semiconductor layer 110. The channel layer (not shown) may be, for example, a first channel layer 330-1 included in a first channel structure 300-1, a second channel layer 330-2 included in a second channel structure 300-2, and another first channel layer 330-3 included in another first channel structure 300-3. The channel layer may extend through stacked structure 200' in a first direction and reach the first substrate semiconductor layer 110, wherein the first substrate semiconductor layer 110 is at least connected to the bottom surface portion of the channel layer.

[0101] For example, the channel layer may extend through the stacked structure 200' along a first direction and into the first substrate semiconductor layer 110, wherein the first substrate semiconductor layer 110 may be connected to the bottom portion of the channel layer and to a portion of the side portion of the channel layer, the portion of which is the part of the side portion of the channel layer connected to the bottom portion.

[0102] The first substrate semiconductor layer 110 may be a highly doped semiconductor layer. For example, the first substrate semiconductor layer 110 may be doped with any suitable, such as N-type dopant (e.g., phosphorus (P), arsenic (Ar), or antimony (Sb)) to contribute free electrons and increase the conductivity of the intrinsic semiconductor.

[0103] Furthermore, in one embodiment of this application, in order to achieve a good and stable electrical connection between the channel layers, such as a first channel layer 330-1, a second channel layer 330-2, and another first channel layer 330-3, and the first substrate semiconductor layer 110, and to improve the electrical performance of the three-dimensional memory, the exposed channel layers may be highly doped before the step of forming the first substrate semiconductor layer 110. Specific steps will be described below.

[0104] The aforementioned channel layer may include at least two regions with different doping concentrations along a first direction. For example, a first channel layer 330-1 may have a third region 333 and a fourth region 334, wherein the third region 333 includes a portion of the first channel layer 330-1 extending into and adjacent to the first substrate semiconductor layer 110, and the fourth region 334 is located on the side of the third region 333 facing away from the first substrate semiconductor layer 110. Compared to the fourth region 334, the doping concentration of conductive impurities in the third region 333 is greater than that in the fourth region 334. This configuration can increase the doping concentration of conductive impurities in the portion of the channel layer closer to the first substrate semiconductor layer, achieving a good and stable electrical connection between the channel layer and the first substrate semiconductor layer, and improving the electrical performance of the three-dimensional memory.

[0105] In addition, the first substrate semiconductor layer 110 also includes a common source terminal 111, which may be directly opposite the channel structure, for example, the common source terminal 111 may be directly opposite a first channel structure 300-1, and this application does not limit this.

[0106] As another option, combining Figure 3B , Figure 5B and Figure 7 In one embodiment of this application, substrate 100 is located on the side of stacked structure 200' away from local conductive contact structures 800-1 and 800-2, and includes a second substrate semiconductor layer 130. A channel layer (not shown) may, for example, include a first channel layer 330-1 included in a first channel structure 300-1; a second channel layer 330-2 included in a second channel structure 300-2; and another first channel layer 330-3 included in another first channel structure 300-3. The channel layer may extend through stacked structure 200' in a first direction and through the second substrate semiconductor layer 130, wherein the second substrate semiconductor layer 130 may be connected to a side portion of the channel layer.

[0107] The second substrate semiconductor layer 130 may be a highly doped semiconductor layer. For example, the second substrate semiconductor layer 130 may be doped with any suitable, such as N-type dopant (e.g., phosphorus (P), arsenic (Ar), or antimony (Sb)) to contribute free electrons and increase the conductivity of the intrinsic semiconductor.

[0108] As another option, combining Figure 3B , Figure 5B and Figure 8In one embodiment of this application, the three-dimensional memory may also include a substrate 100, and the channel structure may include, for example, a first channel structure 300-1, a second channel structure 300-2, and another first channel structure 300-3. The channel structure may include a channel via 310, a functional layer (not shown), an epitaxial layer 120, and a channel layer (not shown), wherein the channel layer may be, for example, a first channel layer 330-1 included in a first channel structure 300-1; a second channel layer 330-2 included in a second channel structure 300-2; and another first channel layer 330-3 included in another first channel structure 300-3. Taking a first channel structure 300-1 as an example, the channel structure 300-1 includes: a channel hole 310 penetrating the stacked structure 200' along a first direction; an epitaxial layer 120 located at the bottom of the channel hole 310; a functional layer 320-1 located on the inner wall of the channel hole 310 and on the epitaxial layer 120; and a first channel layer 330-1 located on the surface of the functional layer 320-1 and penetrating the functional layer 320-1 to connect with the epitaxial layer 120. The epitaxial layer 120 may be at least one of epitaxial silicon, silicon germanium, germanium, III-V compound materials, II-VI compound materials, organic semiconductor materials, and other suitable semiconductor materials.

[0109] Figure 9 This is a top view schematic diagram of a stacked structure 200' according to one embodiment of this application. Figure 10 This is a top view schematic diagram of a stacked structure 200' according to another embodiment of this application.

[0110] In addition, such as Figure 3B , Figure 5B , Figure 9 and Figure 10 As shown, in the three-dimensional memory 1000 provided in at least one embodiment of this application, the stacked structure 200' may have multiple step regions 01 and multiple storage regions 02, each storage region 02 corresponding to at least one step region 01, wherein the step regions 01 can be used to form multiple stepped steps, and the storage regions 02 can be used to form a storage array composed of multiple channel structures arranged and distributed. Subsequently, the gate layers in the storage array can be connected and turned on one by one through word line contacts formed on each stepped step.

[0111] like Figure 9 As shown, according to some embodiments, at least one stepped area 01 may be provided on one or more edges of the storage area 02. For example... Figure 10 As shown, according to some embodiments, at least one step region 01 may be disposed in the middle of the storage region 02, and the storage region 02 may be divided into at least two sub-storage regions. This application does not limit the relative position and specific structure of the step region 01 and the storage region 02. In addition, the stacked structure 200' may also include a peripheral circuit region for forming peripheral circuits.

[0112] Therefore, the three-dimensional memory provided by at least one embodiment of this application has good scalability and compatibility, and can be adapted to different three-dimensional memory architectures, and is not limited by the number of stacked layers in the stacked structure. Furthermore, the above description of the local structure of the substrate, the distribution of the step region, and the storage region is merely an embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the technical solutions of this application regarding the distribution of the local structure of the substrate, the step region, and the storage region are not limited to the technical solutions formed by the selected combination of the above technical features.

[0113] According to at least one embodiment of the present application, a three-dimensional memory is provided by setting a channel connection portion that corresponds to the channel structure and has a larger feature size than the channel structure, and electrically connecting the channel structure and the local conductive contact structure through the channel connection portion. This can increase the feature size of the contact window for the electrical connection between the channel structure and the local conductive contact structure, achieve good electrical conduction between the channel structure and the bit line or source line, and improve the reliability and electrical characteristics of the three-dimensional memory.

[0114] In at least one embodiment of this application, by providing a channel connection portion that corresponds to the channel structure and has a larger feature size than the channel structure, and electrically connecting the channel structure and the local conductive contact structure through the channel connection portion, the feature size of the contact window for the electrical connection between the channel structure and the local conductive contact structure can be increased. Therefore, for the channel structure near the top selection gate cutout structure, the spacing between the two rows of channel structures on both sides of the top selection gate cutout structure can be avoided due to the influence of the top selection gate cutout structure, or / and the channel structure near the top selection gate cutout structure can be avoided as a virtual channel structure due to the influence of the top selection gate cutout structure. Therefore, at least one embodiment of this application can increase the arrangement density of the channel structure and reduce the setting of virtual channel structures, thereby facilitating the improvement of storage density in the three-dimensional memory unit.

[0115] Furthermore, by setting a channel connection portion that corresponds to the channel structure and has a larger feature size than the channel structure, and electrically connecting the channel structure and the local conductive contact structure through the channel connection portion, the feature size of the contact window for the electrical connection between the channel structure and the local conductive contact structure can be increased. This allows the top selection gate cutout structure to obtain a larger lateral dimension in the direction perpendicular to its extension direction. It can also, to a certain extent, avoid the risk of leakage or short circuit caused by damage to the channel structure due to its proximity to the top selection gate cutout structure during the formation of the top selection gate cutout structure, thereby further improving the reliability and electrical characteristics of the three-dimensional memory.

[0116] Figure 11This is a flowchart of a method for preparing a three-dimensional memory according to one embodiment of this application, 2000. Figures 12A to 12E These are schematic diagrams illustrating the fabrication method 2000 of a three-dimensional memory according to one embodiment of this application. Figures 13A to 13E These are schematic diagrams illustrating the fabrication method 2000 of a three-dimensional memory according to another embodiment of this application.

[0117] like Figure 11 As shown, the method for fabricating a three-dimensional memory 2000 may include:

[0118] S11, forming an initial stacked structure, the initial stacked structure including at least one initial stacked layer formed by alternating stacked gate sacrificial layers and insulating layers along a first direction.

[0119] S12, forming multiple channel structures that extend along the first direction and penetrate the initial stacked structure.

[0120] S13, a channel connection portion is formed on at least one channel structure, wherein in a direction perpendicular to the first direction, the lateral dimension of the channel connection portion is greater than the lateral dimension of the portion of the channel structure that contacts the channel connection portion.

[0121] S14, an insulating isolation layer covering the channel connection portion is formed on the top surface of the initial stacked structure, and a local conductive contact structure corresponding to and electrically connected to the channel structure is formed in the insulating isolation layer, wherein at least one local conductive contact structure is formed on the channel connection portion.

[0122] The following will combine Figures 12A to 12E The specific process of each step of the above preparation method 2000 in one embodiment of this application is described in detail.

[0123] Step S11

[0124] Figure 12A This is a cross-sectional schematic diagram of the structure formed after forming the channel layer structure 300 according to a preparation method of one embodiment of this application.

[0125] like Figure 12A As shown, step S11 forms an initial stacked structure, which includes at least one initial stacked layer formed by alternating stacked gate sacrificial layers and insulating layers along a first direction. This may include, for example, providing an initial substrate 100' and forming an initial stacked structure 200 on the initial substrate 100'.

[0126] Specifically, in one embodiment of this application, the material used to fabricate the initial substrate 100' can be any suitable semiconductor material, such as single-crystal silicon (Si), single-crystal germanium (Ge), silicon-germanium (GeSi), silicon carbide (SiC), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or gallium arsenide, etc., which are III-V compounds. Further, the initial substrate 100' can be selected as single-crystal silicon.

[0127] In one embodiment of this application, the initial substrate 100' may be, for example, a composite substrate for supporting a device structure thereon. Multiple layers made of different materials may be sequentially deposited using thin film deposition processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof to form the initial substrate 100'.

[0128] The initial substrate 100' may include a substrate sacrificial layer for subsequent formation of a semiconductor interconnect layer (e.g., forming a second substrate semiconductor layer in a subsequent step). The substrate sacrificial layer may include a single layer, multiple layers, or a suitable composite layer. For example, the substrate sacrificial layer may include any one or more of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. Alternatively, the substrate sacrificial layer may be a high-dielectric-constant dielectric layer. Alternatively, the substrate sacrificial layer may include a dielectric layer, a sacrificial layer, and a dielectric layer sequentially disposed, wherein the dielectric layer may be a silicon nitride layer, and the sacrificial layer may be a silicon oxide layer. Alternatively, the substrate sacrificial layer may include any one or more of a dielectric material, a semiconductor material, and a conductive material. For example, the sacrificial layer may be monocrystalline silicon or polycrystalline silicon. Specifically, in one embodiment of this application, an exemplary material for forming the sacrificial layer may be polycrystalline silicon.

[0129] A portion of the initial substrate 100' may also form a well region doped with an N-type or P-type dopant via ion implantation or diffusion processes. The dopant may include any one or a combination of phosphorus (P), arsenic (As), and antimony (Sb). In some embodiments of this application, the well regions may be prepared using the same or different dopants; furthermore, the doping concentration of the well regions may be the same or different, and this application does not limit this.

[0130] After the initial substrate 100' is formed, an initial stacked structure 200 can be formed on the initial substrate 100' by one or more thin film deposition processes. The thin film deposition processes may include, but are not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof, and this application does not limit them.

[0131] The initial stack-up structure 200 may include insulating layers 210 and gate sacrificial layers 220 stacked alternately on top of each other. For example, the initial stack-up structure 200 may include 64 pairs, 128 pairs, or more than 128 pairs of insulating layers 210 and gate sacrificial layers 220.

[0132] In other words, the initial stacked structure 200 may include at least one initial stacked layer 201' formed by alternating stacked gate insulating layer 210 and gate sacrificial layer 220 along a first direction (z direction).

[0133] In some embodiments, the insulating layer 210 and the gate sacrificial layer 220 may each comprise a first dielectric material and a second dielectric material different from the first dielectric material. Exemplary materials used to form the insulating layer 210 and the gate sacrificial layer 220 may each comprise silicon oxide and silicon nitride. The silicon oxide layer may be used as an isolation stack layer, while the silicon nitride layer may be used as a sacrificial stack layer. The sacrificial stack layer may then be etched away and replaced with a conductive layer comprising a conductive material to form the gate layer of the three-dimensional memory.

[0134] The fabrication method for a single initial stacked structure has been described above. In fact, with the increasing demand for 3D memory storage, the size of the memory stack is gradually increasing. To overcome the limitations of process technology, dual-stack or multi-stack techniques can also be used to form an initial stacked structure by sequentially stacking multiple sub-stacked structures in the thickness direction of the stacked structure. Each sub-stacked structure may include multiple alternately stacked insulating layers and gate sacrificial layers. The number of layers in each sub-stacked structure may be the same or different. Since the fabrication process of the single initial stacked structure described above is fully or partially applicable to the initial stacked structure formed by multiple sub-stacked structures described herein, related or similar content will not be repeated. However, those skilled in the art will understand that subsequent fabrication processes can be performed based on multi-stacked or single-stacked structures.

[0135] Step S12

[0136] Refer again Figure 12A Step S12, which forms a plurality of channel structures that extend along a first direction and penetrate the initial stacked structure, may include: forming a channel hole 310; sequentially forming a functional layer 320 and a channel layer 330 on the inner wall of the channel hole 310; and forming a channel plug 340.

[0137] The channel structure 300 may include a channel hole 310 filled with a semiconductor layer and a composite dielectric layer. A functional layer 320 and a channel layer 330 may be formed on the inner wall of the channel hole 310 by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0138] Specifically, the channel hole 310 can be formed by, for example, a dry etching process or a combination of dry and wet etching processes; other manufacturing processes can also be performed, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing. The channel hole 310 may have a cylindrical or columnar shape extending through the initial stacked structure 200. Alternatively, the channel hole 310 may extend into the initial substrate 100'.

[0139] The functional layer 320 may include a barrier layer formed on the inner wall of the channel hole 310 to prevent charge outflow, a charge trapping layer formed on the surface of the barrier layer to store charge during operation of the three-dimensional memory, and a tunneling layer formed on the surface of the charge trapping layer.

[0140] In some embodiments, functional layer 320 may include an oxide-nitride-oxide (ONO) structure. However, in other embodiments, functional layer 320 may have a structure different from that of an ONO configuration. Channel layer 330 is capable of transporting the required charge (electrons or holes).

[0141] However, those skilled in the art should understand that, without departing from the teachings of this application, the functional layer may be formed on the inner wall of the channel hole (which can be understood as the side wall and bottom surface of the channel hole) or on the inner wall of the channel hole (which can be understood as the side wall of the channel hole) depending on the different three-dimensional memory architectures, and this application does not limit this.

[0142] For example, as an option, combining Figure 6 , Figure 7 and Figure 12A According to one embodiment of this application, a functional layer 320 may be formed on the sidewalls and bottom surface of the channel hole 310, and a channel layer 330 may be formed on the surface of the tunneling layer of the functional layer 320 by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof.

[0143] As another option, combining Figure 8 and Figure 12AAccording to one embodiment of this application, an epitaxial layer 120 may first be formed at the bottom of the channel hole 310 by an epitaxial growth process. The manufacturing process for epitaxially growing the epitaxial layer 120 may include, but is not limited to, vapor phase epitaxy (VPE), liquid phase epitaxy (LPE), molecular beam epitaxy (MPE), or any combination thereof. The epitaxial layer 120 may be at least one of epitaxial silicon, silicon-germanium, germanium, III-V compound materials, II-VI compound materials, organic semiconductor materials, and other suitable semiconductor materials. After forming the epitaxial layer 120, an initial functional layer (not shown) may be formed on the inner wall of the channel hole 310 and the surface of the epitaxial layer 120 by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. After the initial functional layer is formed, the portion of the initial functional layer located on the surface of the epitaxial layer can be removed by, for example, a dry etching process or a combination of dry and wet etching processes; other manufacturing processes can also be performed, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing, to form the functional layer 320 and expose a portion of the surface of the epitaxial layer 120. It is understood that the functional layer 320 is formed only on the sidewalls of the channel via 310. After the functional layer 320 is formed, a channel layer 330 connected to the epitaxial layer 120 can be formed on the surface of the tunneling layer of the functional layer 320 and on the exposed surface of the epitaxial layer 120 by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0144] In some embodiments, the channel layer 330 may comprise silicon, such as polycrystalline silicon or monocrystalline silicon. The material of the channel layer 330 may include, but is not limited to, N-type doped polycrystalline silicon. Similar to the channel via 310, the channel layer 330 may also extend through the stacked structure 200 and have a cylindrical or columnar shape. Alternatively, the channel via 310 may also extend into the initial substrate 100'.

[0145] Furthermore, the channel structure 300 also includes a channel plug 340 formed at the end of the channel hole 310 away from the initial substrate 100' (which can be understood as the top of the channel structure 300). Specifically, the channel hole 310 can be filled with a filling dielectric layer. The filling dielectric layer may include an oxide dielectric layer, such as silicon oxide. Further, during the filling process, multiple insulating gaps can be formed in the filling dielectric layer to reduce structural stress by controlling the channel filling process. Then, the channel plug 340 is formed in the portion of the filling dielectric layer located at the top of the channel hole 310. The material of the channel plug 340 may be the same as that used for the channel layer 330, such as N-type doped polysilicon. The channel plug 340 is electrically connected to the channel layer 330.

[0146] Step S13

[0147] Figure 12B This is a cross-sectional schematic diagram of the structure formed after forming the initial channel connection layer 600' according to a preparation method of one embodiment of this application. Figure 12C This is a cross-sectional schematic diagram of the structure formed after forming the first channel connection portion 600-1 according to a preparation method of one embodiment of this application.

[0148] like Figure 12B and Figure 12C As shown, step S13 forms a channel connection portion on at least one channel structure, wherein in a direction perpendicular to the first direction, the lateral dimension of the channel connection portion is greater than the lateral dimension of the portion of the channel structure that contacts the channel connection portion. This may include, for example, forming an initial channel connection layer 600' on the surface of the initial stacked structure 200 away from the initial substrate 100'; and removing a portion of the initial channel connection layer 600' to form a first channel connection portion 600-1, such that the lateral dimension CD2 of the first channel connection portion 600-1 is greater than the lateral dimension CD1 of the portion of the first channel structure 300-1 that contacts the first channel connection portion 600-1.

[0149] Specifically, such as Figure 12B As shown, in one embodiment of this application, an initial channel connection layer 600' can be formed on the surface of the initial stacked structure 200 away from the initial substrate 100' by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. Alternatively, the initial channel connection layer 600' can be fabricated using a semiconductor material such as polysilicon. The material of the initial channel connection layer 600' can be the same as that used for the channel plug, such as N-type doped polysilicon, for example, the same material used for a first channel plug 340-1 of a first channel structure 300-1.

[0150] As an option, such as Figure 12B and Figure 12CAs shown, after forming the initial channel connection layer 600', a first channel connection portion 600-1 can be selectively formed on a selected channel structure, such as a first channel structure 300-1. The portion of the initial channel connection layer 600' located on the second channel structure 300-2, and the portion of the initial channel connection layer 600' located between the first channel structure 300-1 and the second channel structure 300-2, can be removed by, for example, a dry etching process or a combination of dry and wet etching processes; other manufacturing processes can also be performed, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing. Through this operation, the first portion of the initial channel connection layer 600' located on the first channel structure 300-1 can be retained, and the lateral dimension CD2 of this first portion is made larger than the lateral dimension CD1 of the contact portion between the first channel structure 300-1 and this first portion. The retained first portion of the initial channel connection layer 600' is formed as the first channel connection portion 600-1.

[0151] As mentioned above, the processes for forming the first channel structure 300-1 and the second channel structure 300-2 are the same (refer to the above and Figure 12A The process for forming the channel structure 300 shown is identical to that of the two. The difference between the first channel structure 300-1 and the second channel structure 300-2 lies in the fact that the top selection gate cutout structure formed in subsequent steps will be formed in... Figure 12C As indicated by the dashed line, the top selected grid cutout structure can pass through the first channel connection 600-1, as well as a first channel plug 340-1 and a portion of a first channel structure 300-1 located below the first channel connection 600-1, a first channel plug 340-1 and a first channel layer 330-1.

[0152] In other words, the channel structure for forming the channel connection portion thereon can be determined based on the position of the top selected gate cutout structure in the three-dimensional memory. For example, the position of a first channel structure 300-1 for forming the first channel connection portion 600-1 thereon in the three-dimensional memory can be determined based on the position of the top selected gate cutout structure in the three-dimensional memory.

[0153] In another embodiment of this application, forming a channel connection portion on at least one channel structure includes forming a plurality of channel connection portions corresponding one-to-one with the plurality of channel structures, wherein the channel structure is electrically connected to a subsequently formed local conductive contact structure through the corresponding channel connection portion.

[0154] Furthermore, this application does not limit the material and shape of the initial channel connection layer 600' or the first channel connection portion 600-1. Those skilled in the art should understand that, without departing from the teachings of this application, the initial channel connection layer 600' or the first channel connection portion 600-1 may have different materials or shapes depending on the three-dimensional memory architecture.

[0155] Furthermore, in one embodiment of this application, before forming the first channel connection portion 600-1, the method 2000 for fabricating a three-dimensional memory further includes: doping a first region 331 of the channel layer 300 adjacent to the channel plug 340. The exposed channel layer 330 can be doped, for example, by a process such as ion implantation (IMP), wherein the exposed channel layer 330 can be understood as the portion of the channel layer 330 in contact with the channel plug 340. The aforementioned N-type doping can include any suitable N-type dopant (e.g., phosphorus (P), arsenic (Ar), or antimony (Sb)) to contribute free electrons and increase the conductivity of the intrinsic semiconductor.

[0156] like Figure 12A As shown, after the exposed channel layer 330 is further heavily doped, the channel layer 330 may include a first region 331 formed by a secondary doping process. Compared to other regions of the adjacent channel layer 330 (e.g., the second region 332), the first region 331 is closer to the subsequent formation of local conductive contact structures, and the doping concentration of conductive impurities in the first region 331 is greater than that in the second region 332. Increasing the doping concentration of conductive impurities in the portion of the channel layer closer to the local conductive contact structures enables a good and stable electrical connection between the channel layer and the local conductive contact structures, thereby improving the electrical performance of the three-dimensional memory.

[0157] The method for fabricating a three-dimensional memory according to at least one embodiment of this application increases the feature size of the contact window for electrical connection between the channel structure and the local conductive contact structure by providing a channel connection portion that corresponds to the channel structure and has a larger feature size than the channel structure, and electrically connecting the channel structure and the local conductive contact structure through the channel connection portion. This achieves good electrical conduction between the channel structure and the bit line or source line, improving the reliability and electrical characteristics of the three-dimensional memory. Furthermore, the above-described configuration also provides a favorable process window, optimizing the fabrication process of the three-dimensional memory.

[0158] Step S14

[0159] Figure 12D This is a cross-sectional schematic diagram of the structure formed after forming the top selection gate cutout 710 according to a preparation method of one embodiment of this application. Figure 12EThis is a cross-sectional schematic diagram of the structure formed after forming the top selection gate cutout structure 700 according to a preparation method of one embodiment of this application.

[0160] like Figure 12D , Figure 12E and Figure 5A As shown, step S14 forms an insulating isolation layer covering the channel connection portion on the top surface of the initial stacked structure, and forms local conductive contact structures that correspond one-to-one with and are electrically connected to the channel structure in the insulating isolation layer. The formation of at least one local conductive contact structure on the channel connection portion may include, for example, forming an insulating isolation layer 202; forming a gate line gap 410; forming a gate layer 230; forming a gate line gap structure 400; forming a planarization stop layer 203; forming a top select gate cutout structure 700; and forming local conductive contact structures 800-1 and 800-2.

[0161] Specifically, such as Figure 12D As shown, after forming the first channel connection 600-1, one or more thin film deposition processes can be used to deposit the initial stacked structure 200 (e.g., ...). Figure 12C An insulating isolation layer 202 covering the first channel connection portion 600-1 is formed on the top surface of the material (as shown). The thin film deposition process may include, but is not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof, and this application does not limit the specific process. The material forming the insulating isolation layer 202 may include insulating dielectric materials such as silicon oxide, silicon nitride, and silicon oxynitride, and this application does not limit the specific materials used.

[0162] In addition, grid line gaps 410 with a spacing in the x direction from the channel structure (e.g., a first channel structure 300-1 and a second channel structure 300-2) can be formed in the initial stacked structure 200.

[0163] Specifically, the gate line slot 410 can be formed by, for example, a dry etching process or a combination of dry and wet etching processes. The gate line slot 410 can penetrate the initial stacked structure 200 along a first direction. Alternatively, the gate line slot 410 can penetrate the initial stacked structure 200 along the first direction and extend into the initial substrate 100'. When an insulating isolation layer 202 is provided above the initial stacked structure 200, the gate line slot 410 can penetrate the insulating isolation layer 202 and the initial stacked structure 200 along the first direction.

[0164] Furthermore, the gate gap 410 can be used as a pathway to provide etchant and chemical precursors, and processes such as wet etching can be used to remove all the gate sacrificial layer 220 in the initial stacked structure 200 (e.g., Figure 12C (as shown) to form a sacrificial gap (not shown).

[0165] In some embodiments of this application, the gate layer 230 may be formed in the sacrificial gap using thin film deposition processes such as CVD, PVD, ALD, or any combination thereof. The gate layer 230 may be made of a conductive material, such as any one or a combination of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), doped crystalline silicon, or silicides.

[0166] Furthermore, prior to forming the gate layer 230, the method 1000 for fabricating a three-dimensional memory according to one embodiment of this application further includes forming a dielectric layer (not shown) on the inner wall of the sacrificial gap and the inner sidewall of the gate line gap 410 using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. Alternatively, the dielectric layer may be a high-dielectric-constant dielectric layer. Further, an adhesive layer (e.g., a titanium nitride (TiN) layer, not shown) may be formed between the insulating layer 210 and the gate layer 230 or between the dielectric layer and the gate layer 230 using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof.

[0167] Furthermore, in some embodiments of this application, after forming the gate layer 230, a gate line gap structure 400 can be formed by filling the gate line gaps 410. Specifically, thin film deposition processes such as CVD, PVD, ALD, or any combination thereof can be used to fill the gate line gaps 410 with a dielectric filling layer 420 to form the gate line gap structure 400. The dielectric filling layer 420 can be made of insulating dielectric materials such as silicon oxide, silicon nitride, and silicon oxynitride, or it can be made of semiconductor materials such as polysilicon; this application does not limit the choice of dielectric material.

[0168] In the initial stacked structure 200 (e.g.) Figure 12C After the gate line gap structure 400 and the gate layer 230 are formed in the diagram, the initial stacked structure 200 is formed into a stacked structure 200'.

[0169] Alternatively, in some embodiments of this application, a planarization stop layer 203 may be formed on the surface of the insulating isolation layer 202 after the gate gap structure 400 is formed. The planarization stop layer 203 may be formed using thin film deposition processes such as CVD, PVD, ALD, or any combination thereof, and may be prepared using a dielectric material such as silicon nitride.

[0170] After forming the gate gap structure 400, a planarization process, such as a low-rate chemical mechanical polishing (Buffer CMP), can be performed on the surface of the three-dimensional memory intermediate approximately perpendicular to the first direction. The surface of the three-dimensional memory intermediate includes the surface of the insulating isolation layer 202 and the surface of the dielectric filling layer 420. Planarization makes it easier to obtain a smoother surface for the three-dimensional memory intermediate, which is beneficial for the subsequent formation of good electrical connectivity between the local conductive contact structure and the channel structure. A planarization stop layer 203 can serve as a stop layer for the planarization process.

[0171] like Figure 12E As shown, the top selection gate cutout structure 700 may include a top selection gate cutout 710 and a top selection gate cutout filling medium 720.

[0172] like Figure 12D As shown, the top select gate notch 710 can be formed by, for example, a dry etching process or a combination of dry and wet etching processes, and other manufacturing processes, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing, can also be performed. The top select gate notch 710 penetrates the planarization stop layer 203 and the insulating isolation layer 202 along a first direction, and passes through the first channel connection portion 600-1 and a portion of the channel plug 340-1 and the channel layer 330-1 of a first channel structure 300-1. In other words, the top select gate notch 710 can be configured to extend along the first direction through the first stacked layer of the stacked structure 200' that is closest to the local conductive contact structure to be subsequently formed.

[0173] like Figure 12E As shown, in forming the top select gate cutout 710, an insulating dielectric material such as silicon oxide, silicon nitride, and silicon oxynitride can be used as the top select gate cutout filling medium 720 to fill the top select gate cutout 710 to form the top select gate cutout structure 700.

[0174] In addition, combined Figure 4 , Figure 12A and Figure 12D In some embodiments of this application, the channel structure 300 is arranged as a storage array in a plane perpendicular to the first direction (e.g., the plane containing the x and y directions), wherein the storage array may be divided into a plurality of first channel structure rows extending along a second direction (y direction) perpendicular to the first direction, such as first channel structure rows 31 and 32.

[0175] The top selection gate cutout 710 can be configured to extend in a second direction and pass through each channel structure in the corresponding first channel structure rows 31 and 32, such as a portion of the top of a first channel structure 300-1, along a first direction. In other words, the subsequently formed top selection gate cutout structure 700 can be configured to extend in a second direction and pass through a portion of a first channel plug 340-1 and a first channel layer 330-1 of each first channel structure 300-1 in the corresponding first channel structure rows 31 and 32, along a first direction. The first channel structure 300-1 that is passed through still has a storage function. Furthermore, a first channel connection portion 600-1 is provided above a first channel structure 300-1. The top selection gate cutout structure 700 can extend in the second direction and similarly pass through a portion of the top of each first channel connection portion 600-1 in the corresponding first channel structure row, wherein each first channel connection portion 600-1 corresponds to each first channel structure 300-1 in the first channel structure row. like Figure 4 As shown, the top selection gate cutout structure 700 has a lateral dimension CD4 in a third direction perpendicular to the second direction. Furthermore, by setting the top selection gate cutout 710 in the above manner, the number of first channel structure rows in a single memory region of the three-dimensional memory can be reduced, the width in the third direction (x direction) can be decreased, the unit storage density in the three-dimensional memory can be increased, and more channel structures can be arranged in the same storage area.

[0176] According to at least one embodiment of the three-dimensional memory fabrication method provided in this application, by providing a channel connection portion corresponding to the channel structure and having a larger feature size than the channel structure, and electrically connecting the channel structure and the local conductive contact structure through the channel connection portion, the feature size of the contact window for the electrical connection between the channel structure and the local conductive contact structure can be increased. Therefore, for the channel structure near the top selection gate notch structure, the spacing between the two rows of channel structures on both sides of the top selection gate notch structure can be avoided due to the influence of the top selection gate notch structure, and / or the channel structure near the top selection gate notch structure can only serve as a virtual channel structure due to the influence of the top selection gate notch structure. Therefore, at least one embodiment of this application can increase the arrangement density of the channel structure and reduce the setting of virtual channel structures, thereby facilitating the improvement of storage density per unit of three-dimensional memory. Furthermore, the above-mentioned arrangement can also obtain a good process window, optimizing the fabrication process of the three-dimensional memory.

[0177] Furthermore, based on this, the top select gate cutout structure can achieve a larger lateral dimension in the direction perpendicular to its extension direction; and can to a certain extent avoid the risk of leakage or short circuit caused by damage to the channel structure due to its proximity to the top select gate opening structure during the formation of the top select gate opening structure, thereby further improving the reliability and electrical characteristics of the three-dimensional memory. The aforementioned lateral dimension can be understood as the lateral feature dimension of the top select gate cutout structure.

[0178] Alternatively, the maximum area of ​​the overlapping region formed by the orthographic projection of the first channel structure 300-1 and the orthographic projection of the top selection gate cutout structure 700 can be set to half the area of ​​the orthographic projection of the first channel structure 300-1, wherein the orthographic projection of the first channel structure 300-1 is the orthographic projection of the first channel structure 300-1 in a plane perpendicular to the first direction, and the orthographic projection of the top selection gate cutout structure 700 is the orthographic projection of the top selection gate cutout structure 700 in the aforementioned plane.

[0179] In another embodiment of this application, the center of the orthographic projection of a first channel structure 300-1 that contacts the top selection gate cutout structure 700 in a plane perpendicular to the first direction can be set to not overlap with the center of the orthographic projection of the corresponding first channel connection portion 600-1 in the same plane. By setting the two centers to not overlap, risks such as leakage or short circuits can be avoided to a certain extent, for example, when forming the cutout of the top selection gate cutout structure, because the cutout position is adjacent to a first channel structure.

[0180] like Figure 12D , Figure 12E and 5A As shown, after forming the top selective gate cutout structure 700, local conductive contact structures 800-1 and 800-2 can be formed in the insulating isolation layer 202.

[0181] Locally conductive contact structures can serve as bit line contacts or source line contacts in a three-dimensional memory, enabling electrical connection between the channel structure and the bit line or source line. Specifically, in one embodiment of this application, contact holes 801 and 803 of the locally conductive contact structure can be formed by, for example, a dry etching process or a combination of dry and wet etching processes, or by performing other manufacturing processes, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing. The first contact hole 801 faces a first channel structure 300-1 and is used to form a first locally conductive contact structure 800-1 electrically connected to the first channel structure 300-1 through a first channel connection portion 600-1; the second contact hole 803 faces a second channel structure 300-2 and is used to form a second locally conductive contact structure 800-2 directly electrically connected to the second channel structure 300-2. Therefore, in the first direction, the first contact hole 801 has a relatively shorter extension length compared to the second contact hole 803, so that the subsequently formed first local conductive contact structure 800-1 can be electrically connected to a first channel structure 300-1 through the first channel connection portion 600-1.

[0182] Furthermore, in one embodiment of this application, the first contact hole 801 and the top select gate cutout structure 700 can be spaced apart from each other in a plane perpendicular to the first direction (e.g., the plane containing the x and y directions). In other words, the first partial conductive contact structure 800-1, which is electrically connected to a first channel structure 300-1, can be spaced apart from the top select gate cutout structure 700. The first partial conductive contact structure 800-1 is located above the first channel structure 300-1 and is offset from the first channel structure 300-1 in the first direction, so that the first partial conductive contact structure 800-1 is spaced apart from the top select gate cutout structure 700 in a plane perpendicular to the first direction. By spaced apart the first partial conductive contact structure 800-1 from the top select gate cutout structure 700, the risk of short circuits between, for example, bit line contacts and the top select gate cutout structure can be avoided to a certain extent, thereby improving the reliability of the 3D memory.

[0183] After forming the first contact hole 801 and the second contact hole 803, the first contact hole 801 and the second contact hole 803 can be filled with conductive material layers (e.g., conductive material layers 802 and 804) by CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. The conductive material for forming the first local conductive contact structure 800-1 and the second local conductive contact structure 800-2 may include tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), or a combination of two or more of these materials. In some embodiments, when preparing the first local conductive contact structure 800-1 and the second local conductive contact structure 800-2, another conductive material layer (e.g., titanium nitride TiN) may be deposited as a contact layer before depositing the aforementioned conductive materials.

[0184] In the above embodiments of this application, the first contact hole and the second contact hole can be formed by the same preparation process, thus the preparation is less difficult and less expensive.

[0185] Furthermore, the method for fabricating a three-dimensional memory provided in at least one embodiment of this application, by setting a channel connection portion corresponding to the channel structure and having a larger feature size than the channel structure, and electrically connecting the channel structure and the local conductive contact structure through the channel connection portion, can increase the feature size of the contact window for the electrical connection between the channel structure and the local conductive contact structure, thereby achieving good electrical conduction between the channel structure and the bit line or source line, and improving the reliability and electrical characteristics of the three-dimensional memory.

[0186] Alternatively, in a direction perpendicular to the first direction, the lateral dimension of the channel connection portion can be set to be greater than the lateral dimension of the portion of the local conductive contact structure that contacts the channel connection portion.

[0187] Refer again Figure 3A , Figure 5A , Figures 6 to 8 as well as Figure 12A The method for fabricating a three-dimensional memory 2000 further includes forming a local structure connected to a channel layer. This local structure is used to form a circuit loop that enables the memory cell to operate. The following example illustrates the formation of a local structure connected to a first channel layer 330-1; the methods for forming local structures connected to other channel layers are the same and will not be described further. The following example illustrates the formation of a local structure connected to a first channel layer 320-1; the methods for forming local structures connected to other channel layers are the same and will not be described further.

[0188] As an option, combine Figure 3A , Figure 5A , Figure 6 and 12AIn one embodiment of this application, the method 2000 for fabricating a three-dimensional memory further includes: removing an initial substrate 100' and exposing a portion of a first functional layer 320-1 extending into the initial substrate 100'; removing the exposed first functional layer 320-1 to expose a portion of a first channel layer 330-1 corresponding to the removed first functional layer 320-1; and forming a first substrate semiconductor layer 110, the first substrate semiconductor layer 110 covering the exposed portion of the first channel layer 330-1.

[0189] Furthermore, after exposing and removing a portion of a first channel layer 330-1 corresponding to a first functional layer 32-10, the exposed first channel layer 330-1 can be subjected to, for example, N-type doping via processes such as ion implantation (IMP). The aforementioned N-type doping may include any suitable N-type dopant (e.g., phosphorus (P), arsenic (Ar), or antimony (Sb)) to contribute free electrons and increase the conductivity of the intrinsic semiconductor. Figure 6 As shown, after a second high-doping of an exposed first channel layer 330-1, the first channel layer 330-1 may include a third region 333 formed by a secondary doping process. Compared to other adjacent regions, such as a fourth region 334 located to one side of the third region 333 and far from the first substrate semiconductor layer 110, the doping concentration of conductive impurities in the third region 333 is greater than that in the fourth region 334. Increasing the doping concentration of conductive impurities in the portion of the channel layer closer to the first substrate semiconductor layer enables a good and stable electrical connection between the channel layer and the first substrate semiconductor layer, improving the electrical performance of the three-dimensional memory.

[0190] As another option, combining Figure 3A , Figure 5A , Figure 7 and 12A In one embodiment of this application, forming the channel structure 300 further includes: providing an initial substrate 100' including a substrate sacrificial layer (not shown); removing the substrate sacrificial layer in the initial substrate 100' to form a substrate void (not shown); the substrate void may expose a side portion of a first functional layer 320-1, removing a portion of the exposed side portion of the first functional layer 320-1 via the substrate void to expose a portion of a first channel layer 330-1 corresponding to the removed first functional layer 320-1; and filling the substrate void with a second substrate semiconductor layer 130, the second substrate semiconductor layer 130 being formed in the initial substrate 100' extending through the exposed portion of the first channel layer 330-1.

[0191] As another option, combining Figure 3A , Figure 5A , Figure 8 and 12A In one embodiment of this application, forming the channel structure 300 further includes: forming a plurality of channel holes 310 penetrating the initial stacked structure 200 along a first direction; forming an epitaxial layer 120 at the bottom of the channel holes 310; forming an initial functional layer (not shown) on the inner wall of the channel holes 310 and the surface of the epitaxial layer 120; removing a portion of the initial functional layer located on the surface of the epitaxial layer to form a first functional layer 320-1 and expose a portion of the epitaxial layer 120; and forming a first channel layer 330-1 connected to the epitaxial layer 120 on the surface of the first functional layer 320-1 and the exposed surface of the epitaxial layer 120.

[0192] In addition, such as Figure 9 and Figure 10 As shown, in the three-dimensional memory fabrication method 2000 provided in at least one embodiment of this application, the stacked structure 200' may have multiple step regions 01 and multiple storage regions 02, each storage region 02 corresponding to at least one step region 01, wherein the step regions 01 can be used to form multiple stepped steps, and the storage regions 02 can be used to form a storage array composed of multiple channel structures arranged and distributed. Subsequently, the gate layers in the storage array can be connected and turned on one by one through word line contacts formed on each stepped step.

[0193] like Figure 9 As shown, according to some embodiments, at least one stepped area 01 may be provided on one or more edges of the storage area 02. For example... Figure 10 As shown, according to some embodiments, at least one step region 01 can be disposed in the middle of the storage region 02, and the corresponding storage region 02 can be divided into at least two sub-storage regions. This application does not limit the relative position and specific structure of the step region 01 and the storage region 02. In addition, the stacked structure 200' may also include a peripheral circuit region for forming peripheral circuits.

[0194] Therefore, the method for fabricating a three-dimensional memory provided in at least one embodiment of this application has good scalability and compatibility, and can be adapted to different three-dimensional memory architectures, and is not limited by the number of stacked layers in the stacked structure. Furthermore, the above description of the local structure of the substrate formation, the distribution of the step regions and the memory regions is merely an embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the technical solutions of this application regarding the local structure of the substrate formation, the distribution of the step regions and the memory regions are not limited to the selected combinations of the above-described technical features.

[0195] The following will combine Figures 13A to 13E The specific process of each step of the above preparation method 2000 in another embodiment of this application is described in detail.

[0196] Since the fabrication process and structure of the three-dimensional memory fabrication method 2000 described above can be fully or partially applied to the three-dimensional memory fabrication method described herein, related or similar content will not be repeated. The fabrication process of the first channel connection portion 600-1 and the second channel connection portion 600-2 in another embodiment of this application will be described in detail below.

[0197] Step S11

[0198] Figure 13A This is a cross-sectional schematic diagram of the structure formed after forming the channel layer structure 300 according to another embodiment of the present application.

[0199] like Figure 13A As shown, step S11 forms an initial stacked structure, which includes at least one initial stacked layer formed by alternatingly stacked gate sacrificial layers and insulating layers along a first direction. This may include, for example, providing an initial substrate 100'; and forming an initial stacked structure 200 on the initial substrate 100', wherein the initial stacked structure 200' may include at least one stacked layer 201 formed by alternatingly stacked insulating layers 210 and gate layers 230 along the first direction. Each stacked layer 201 may include an insulating layer 210 and a gate layer 230.

[0200] Step S12

[0201] Refer again Figure 13A Step S12, which forms a plurality of channel structures that extend along a first direction and penetrate the initial stacked structure, may include: forming a channel hole 310; sequentially forming a functional layer 320 and a channel layer 330 on the inner wall of the channel hole 310; and forming a channel plug 340.

[0202] Alternatively, before forming the first channel connection 600-1, the first region 331 of the channel layer 300 adjacent to the channel plug 340 may be doped to give the first region 331 a higher concentration of conductive impurities compared to other regions of the adjacent channel layer 330.

[0203] Step S13

[0204] Figure 13B This is a cross-sectional schematic diagram of the structure formed after forming the initial channel connection layer 600' according to another embodiment of the preparation method of this application. Figure 13C This is a cross-sectional schematic diagram of the structure formed after forming the first channel connection portion 600-1 and the second channel connection portion 600-2 according to another embodiment of the preparation method of this application.

[0205] like Figure 13B and Figure 13C As shown, step S13 forms a channel connection portion on at least one channel structure, wherein in a direction perpendicular to the first direction, the lateral dimension of the channel connection portion is greater than the lateral dimension of the channel structure and the portion in contact with the channel connection portion. This may include, for example, forming an initial channel connection layer 600' on the surface of the initial stacked structure 200 away from the initial substrate 100'; and removing a portion of the initial channel connection layer 600' to form a corresponding channel connection portion on each channel structure 300, such as a first channel connection portion 600-1 and a second channel connection portion 600-2, and making the lateral dimension CD2 of the channel connection portion greater than the lateral dimension CD1 of the channel structure and the portion in contact with the channel connection portion.

[0206] As another option, such as Figure 13B and Figure 13C As shown, after forming the initial channel connection layer 600', a channel connection portion can optionally be formed above each channel structure 300. The portion of the initial channel connection layer 600' located between one first channel structure 300-1 and another first channel structure 300-3 can be removed by, for example, a dry etching process or a combination of dry and wet etching processes; other manufacturing processes can also be performed, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing. Through this operation, the portion of the initial channel connection layer 600' located on each channel structure 300 can be retained, and the lateral dimension CD2 of this portion is larger than the lateral dimension CD1 of the channel structure 300 that contacts this portion. In other words, the retained portion of the initial channel connection layer 600' is formed as a channel connection portion, which may include a first channel connection portion 600-1 and a second channel connection portion 600-2.

[0207] As mentioned earlier, the processes for forming one first channel structure 300-1 and another first channel structure 300-3 are the same, and both can refer to the process for forming channel structure 300 described above. The structures of both are also identical. The difference between one first channel structure 300-1 and another first channel structure 300-3 lies in the fact that the top selection gate cutout structure formed in subsequent steps will be formed in... Figure 13C As indicated by the dashed line, the top selected gate cutout structure can pass through the first channel connection 600-1, as well as a portion of the channel plug 340-1 and channel layer 330-1 of a first channel structure 300-1 located below the first channel connection 600-1.

[0208] In other words, the position of the channel structure for forming the channel connection portion thereon can be determined in the three-dimensional memory based on the position of the top selected gate cut-out structure in the three-dimensional memory. For example, the position of the first channel structure 300-1 for forming the first channel connection portion 600-1 thereon can be determined in the three-dimensional memory based on the position of the top selected gate cut-out structure in the three-dimensional memory.

[0209] Step S14

[0210] Figure 13D This is a cross-sectional schematic diagram of the structure formed after forming the top selection gate cutout 710 according to another embodiment of the present application. Figure 13E This is a cross-sectional schematic diagram of the structure formed after forming the top selection gate cutout structure 700 according to another embodiment of the present application.

[0211] like Figure 13D , Figure 13E and Figure 3A As shown, step S14 forms an insulating isolation layer covering the channel connection portion on the top surface of the initial stacked structure, and forms local conductive contact structures that correspond one-to-one with and are electrically connected to the channel structures in the insulating isolation layer. The formation of at least one local conductive contact structure on the channel connection portion may include, for example, forming an insulating isolation layer 202; forming a gate line gap 410; forming a gate layer 230; forming a gate line gap structure 400; forming a planarization stop layer 203; forming a top select gate cutout structure 700; and forming a local conductive contact structure, such as a first local conductive contact structure 800-1, above each first channel structure 300-1 and 300-3.

[0212] Specifically, in combination Figure 3A , Figure 13D and Figure 13E After forming the top selective gate cutout structure 700, a first local conductive contact structure 800-1 can be formed in the insulating isolation layer 202.

[0213] The first contact hole 801 of the local conductive contact structure can be formed by, for example, a dry etching process or a combination of dry and wet etching processes, or by other manufacturing processes, such as patterning processes including photolithography, cleaning and chemical mechanical polishing, to form the first local conductive contact structure 800-1 that is electrically connected to the channel structure through the channel connection portion.

[0214] Furthermore, in one embodiment of this application, the first contact hole 801 and the top select gate cutout structure 700 can be spaced apart from each other in a plane perpendicular to the first direction (e.g., the plane containing the x and y directions). In other words, the first partial conductive contact structure 800-1, which is electrically connected to a first channel structure 300-1, can be spaced apart from the top select gate cutout structure 700. The first partial conductive contact structure 800-1 is located above the first channel structure 300-1 and is offset from the first channel structure 300-1 in the first direction, so that the first partial conductive contact structure 800-1 is spaced apart from the top select gate cutout structure 700 in a plane perpendicular to the first direction. By spaced apart the first partial conductive contact structure 800-1 and the top select gate cutout structure 700, the risk of short circuits between bit line contacts and the top select gate cutout structure can be avoided to a certain extent, thereby improving the reliability of the three-dimensional memory.

[0215] After the first contact hole 801 is formed, the first contact hole 801 can be filled with a conductive material filling layer 802 by CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. The conductive material forming the first local conductive contact structure 800-1 may include tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), or a combination of two or more of these materials. In some embodiments, when preparing the first local conductive contact structure 800-1, another conductive material (e.g., titanium nitride TiN) layer may be deposited as a contact layer before depositing the aforementioned conductive material.

[0216] Therefore, the method for fabricating a three-dimensional memory provided in at least one embodiment of this application, by setting a channel connection portion corresponding to the channel structure and having a larger feature size than the channel structure, and electrically connecting the channel structure and the local conductive contact structure through the channel connection portion, can increase the feature size of the contact window for the electrical connection between the channel structure and the local conductive contact structure, thereby achieving good electrical conduction between the channel structure and the bit line or source line, and improving the reliability and electrical characteristics of the three-dimensional memory.

[0217] Furthermore, for the channel structure near the top selection gate cutout structure, the spacing between the two rows of channel structures on both sides of the top selection gate cutout structure can be avoided due to the influence of the top selection gate cutout structure, and / or the channel structure near the top selection gate cutout structure can be prevented from only serving as a virtual channel structure due to the influence of the top selection gate cutout structure. Therefore, at least one embodiment of this application can increase the arrangement density of channel structures and reduce the setting of virtual channel structures, thereby facilitating the improvement of storage density in a three-dimensional memory unit.

[0218] Furthermore, by setting a channel connection portion that corresponds to the channel structure and has a larger feature size than the channel structure, and electrically connecting the channel structure and the local conductive contact structure through the channel connection portion, the feature size of the contact window for the electrical connection between the channel structure and the local conductive contact structure can be increased. Based on this, the top select gate cutout structure can obtain a larger lateral dimension in the direction perpendicular to its extension direction; and to a certain extent, it can avoid the risk of leakage or short circuits caused by damage to the channel structure due to its proximity to the top select gate opening structure during the formation of the top select gate opening structure, further improving the reliability and electrical characteristics of the three-dimensional memory. The aforementioned lateral dimension can be understood as the lateral feature size of the top select gate cutout structure.

[0219] Although exemplary methods and structures for fabricating three-dimensional memories have been described herein, it is understood that one or more features may be omitted, substituted, or added to the structure of the three-dimensional memory. Furthermore, the materials of the layers described are merely exemplary.

[0220] Figure 14 This is a schematic diagram of the structure of a storage system 30000 according to one embodiment of this application.

[0221] like Figure 14 As shown, at least one embodiment of another aspect of this application also provides a storage system 30000. The storage system 30000 may include at least one three-dimensional memory 20000 and a controller 32000. The three-dimensional memory 20000 may be the same as the memory described in any of the embodiments above, and will not be described again in this application.

[0222] Alternatively, the 3D memory 20000 may include at least one of 3D NAND memory and 3D NOR memory.

[0223] Specifically, the controller 32000 can control the 3D memory 20000 via channel CH to control the 3D memory 20000 to store data. The 3D memory 20000 can receive commands CMD and addresses ADDR from the controller 32000 via channel CH and access the region selected from the memory cell array in response to the address. In other words, the 3D memory 20000 can perform internal operations corresponding to commands on the region selected by the address.

[0224] In some implementations, the storage system may be implemented as a Universal Flash Storage (UFS) device, a Solid State Drive (SSD), a multimedia card in the form of MMC, eMMC, RS-MMC, and Micro MMC, a Secure Digital Card in the form of SD, Mini SD, and Micro SD, a PCMCIA card type storage device, a Peripheral Component Interconnect (PCI) type storage device, a High Speed ​​PCI (PCI-E) type storage device, a Compact Flash (CF) card, a Smart Media Card, or a Memory Stick, etc. The storage system provided in this application, due to the inclusion of the three-dimensional memory provided in this application, has the same beneficial effects as the described three-dimensional memory, which will not be elaborated upon here.

[0225] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this application is not limited to the technical solutions formed by the selected combination of the above-described technical features, but should also cover other technical solutions formed by any combination of the above-described technical features or their equivalents without departing from the technical concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A three-dimensional memory, characterized in that, include: A stacked structure, comprising at least one stacked layer formed by a gate layer and an insulating layer stacked along a first direction; Multiple channel structures, each of the channel structures penetrating the stacked structure along the first direction; Multiple locally conductive contact structures are located on the stacked structure, corresponding one-to-one with and electrically connected to the channel structure. In this embodiment, at least one of the channel structures is electrically connected to the local conductive contact structure through a channel connection portion, and in a direction perpendicular to the first direction, the lateral dimension of the channel connection portion is greater than the lateral dimension of the portion of the channel structure that contacts the channel connection portion. The plurality of channel structures include a plurality of first channel structures, each first channel structure being electrically connected to the local conductive contact structure via a channel connection portion. Each channel structure includes a channel layer and a channel plug. The channel layer penetrates the stacked structure along the first direction. The channel plug is disposed at one end of the channel structure and is electrically connected to the channel layer. The memory further includes at least one top select gate cutout structure, which passes sequentially along the first direction through the channel connection portion and a portion of the channel plug and channel layer of a plurality of first channel structures. In a plane perpendicular to the first direction, the locally conductive contact structure electrically connected to the first channel structure is spaced apart from the top select gate cutout structure.

2. The memory according to claim 1, wherein, The orthographic projection of the first channel structure in a plane perpendicular to the first direction and the orthographic projection of the top selection gate cutout structure in the same plane form an overlapping area, the maximum area of ​​which is half the area of ​​the orthographic projection of the first channel structure.

3. The memory according to claim 1, wherein, The plurality of first channel structures are arranged in a plane perpendicular to the first direction as a row of multiple first channel structures extending along a second direction perpendicular to the first direction; The top selection gate cutout structure extends along the second direction and passes along the first direction through the channel plug and part of the channel layer of each first channel structure in the corresponding first channel structure row.

4. The memory according to claim 1, wherein, The number of the channel connection portions is multiple, and each of the multiple channel structures corresponds to one of them. The channel structure is electrically connected to the local conductive contact structure through the corresponding channel connection portion.

5. The memory according to claim 1, wherein, In a direction perpendicular to the first direction, the lateral dimension of the channel connection portion is greater than the lateral dimension of the portion of the local conductive contact structure that contacts the channel connection portion.

6. The memory according to claim 1, wherein, The center of the orthographic projection of the first channel structure that contacts the top selected grating cut structure in a plane perpendicular to the first direction does not overlap with the center of the orthographic projection of the corresponding channel connection portion in the same plane.

7. The memory according to claim 1, wherein, The channel structure includes a channel layer that penetrates the stacked structure along the first direction and includes a first region and a second region. The first region is adjacent to the local conductive contact structure, and the second region is located on the side of the first region opposite to the local conductive contact structure. The conductive impurity doping concentration in the first region is greater than that in the second region.

8. A method for fabricating a three-dimensional memory, characterized in that, The method includes: An initial stacked structure is formed, the initial stacked structure comprising at least one initial stacked layer formed by alternating stacked gate sacrificial layers and insulating layers along a first direction; Multiple channel structures are formed that penetrate the initial stacked structure along the first direction; A channel connection portion is formed on at least one of the channel structures, wherein in a direction perpendicular to the first direction, the lateral dimension of the channel connection portion is greater than the lateral dimension of the portion of the channel structure that contacts the channel connection portion; An insulating layer covering the channel connection portion is formed on the top surface of the initial stacked structure, and local conductive contact structures corresponding one-to-one with and electrically connected to the channel structure are formed in the insulating layer, wherein at least one of the local conductive contact structures is formed on the channel connection portion; and A channel plug is formed along the first direction, sequentially passing through the channel connection portion, a portion of the first channel structures, and a top selective gate cutout structure of a portion of the channel layer. The multiple channel structures include multiple first channel structures, each electrically connected to the local conductive contact structure via the channel connection portion. Each channel structure includes a channel layer and a channel plug. The channel layer penetrates the initial stacked structure along the first direction. The channel plug is disposed at one end of the channel structure and electrically connected to the channel layer. The method further includes, after forming the top selection gate cutout structure: A first contact hole is formed in a plane perpendicular to the first direction and offset from the top selection grille cutout structure; and The first contact hole is filled with a conductive material filling layer to form the local conductive contact structure that is electrically connected to the first channel structure.

9. The method according to claim 8, wherein, The method further includes: The maximum area of ​​the overlapping region formed by the orthographic projection of the first channel structure and the orthographic projection of the top selection gate cutout structure is set to half the area of ​​the orthographic projection of the first channel structure, wherein the orthographic projection of the first channel structure is the orthographic projection of the first channel structure in a plane perpendicular to the first direction, and the orthographic projection of the top selection gate cutout structure is the orthographic projection of the top selection gate cutout structure in the plane.

10. The method according to claim 8, wherein, Forming a channel connection portion on at least one of the channel structures includes: A plurality of channel connection portions are formed, each corresponding to one of the plurality of channel structures, wherein the channel structures are electrically connected to the local conductive contact structure through the corresponding channel connection portions.

11. The method according to claim 8, wherein, The method further includes: In a direction perpendicular to the first direction, the lateral dimension of the channel connection portion is set to be greater than the lateral dimension of the portion of the local conductive contact structure that contacts the channel connection portion.

12. The method according to claim 8, wherein, The method further includes: The center of the orthographic projection of the first channel structure that contacts the top selected gate cutout structure in a plane perpendicular to the first direction is set to not overlap with the center of the orthographic projection of the corresponding channel connection portion in the same plane.

13. The method according to claim 8, wherein, Before forming a channel connection on at least one of the channel structures, the method further includes: The first region of the channel layer adjacent to the channel plug is doped.

14. The method according to claim 8, wherein, Forming a channel connection portion on at least one of the channel structures includes: An initial channel connection layer covering the channel structure is formed on the top surface of the initial stacked structure; The portion of the initial channel connecting layer located between the channel structures is removed, and the portion of the initial channel connecting layer located on the second channel structure is also removed to form a plurality of the channel connecting portions. The second channel structure is the channel structure that is directly electrically connected to the local conductive contact structure.

15. A storage system, characterized in that, The storage system includes: a controller and a memory according to any one of claims 1 to 7, wherein the controller is coupled to the memory and is used to control the memory to store data.

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