Three-dimensional memory and methods of making the same

Abstract

Embodiments of the present application provide a three-dimensional memory and a preparation method thereof. The preparation method comprises: forming a silicon nitride layer on the inner wall of a channel hole penetrating through a stack structure; performing a first oxidation treatment on a first part of the silicon nitride layer away from the inner wall of the channel hole; and performing a second oxidation treatment on the silicon nitride layer. Through the above method, the process operation is simplified, the process cost is saved, and at the same time, the finally formed silicon oxide layer has good film uniformity and film quality.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a three-dimensional memory and a method for fabricating the same. Background Technology

[0002] In the fabrication process of 3D memory, it is typically necessary to form a silicon oxide layer as a charge-blocking layer on the inner wall of the vias penetrating the stacked structure. To accommodate the progressively increasing number of stacked layers, in some practical processes, the vias can be formed using, for example, a two-step etching process. However, for vias formed using the above process, forming a charge-blocking layer on their inner walls presents a technological challenge. Summary of the Invention

[0003] This application provides a method for fabricating three-dimensional storage, the method comprising: forming a silicon nitride layer on the inner wall of a channel hole penetrating a stacked structure; performing a first oxidation treatment on a first portion of the inner wall of the silicon nitride layer away from the channel hole; and performing a second oxidation treatment on the silicon nitride layer.

[0004] In some embodiments, the oxidation rate of the first oxidation treatment is lower than the oxidation rate of the second oxidation treatment.

[0005] In some embodiments, the temperature during the first oxidation treatment is lower than the temperature during the second oxidation treatment.

[0006] In some embodiments, the first oxidation treatment includes an isotropic thermal oxidation treatment.

[0007] In some embodiments, the isotropic thermal oxidation treatment includes performing an isotropic thermal oxidation treatment on the first part using oxygen and hydrogen as reaction gases.

[0008] In some embodiments, the isotropic thermal oxidation process includes performing an isotropic thermal oxidation process on the first portion using a machine for forming a silicon nitride layer.

[0009] In some implementations, the thickness of the first portion is greater than half the total thickness of the silicon nitride layer.

[0010] In some embodiments, the second oxidation treatment includes plasma oxidation treatment.

[0011] In some embodiments, forming a silicon nitride layer on the inner wall of a channel hole through the stacked structure includes forming the silicon nitride layer by an atomic layer deposition process.

[0012] In some embodiments, the channel hole includes a first channel hole and a second channel hole disposed along the stacking direction of the stacked structure and communicating with each other. At the connection between the first channel hole and the second channel hole, the cross-sectional dimension of the first channel hole in a plane perpendicular to the stacking direction is different from the cross-sectional dimension of the second channel hole in a plane perpendicular to the stacking direction.

[0013] This application also provides a three-dimensional memory comprising: at least one channel structure, the channel structure including an outer silicon oxide layer, and the silicon oxide layer being formed according to the preparation method described in any of the preceding embodiments.

[0014] According to at least one embodiment of this application, by forming a silicon nitride layer in one step and performing two oxidation processes on the silicon nitride layer, the process operation is simplified and the process cost is reduced. Simultaneously, the final silicon oxide layer can have better film uniformity and film quality, for example, good film coverage at the step surface where two sub-channel vias connect. Furthermore, provided the thickness of the final silicon oxide layer is met, forming the silicon nitride layer in one step helps reduce process control difficulty, improves the process window, and effectively reduces the risk of pinhole defects. Attached Figure Description

[0015] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. Wherein: Figure 1 This is a cross-sectional schematic diagram of a silicon oxide layer formed on the inner wall of a channel hole according to an embodiment of this application. Figure 2 This is a flowchart of a method for preparing a three-dimensional memory according to another embodiment of this application; Figure 3A It is based on Figure 2 A schematic cross-sectional view of the channel holes in the through-stacking structure of the fabrication method is shown. Figure 3B It is based on Figure 2 The diagram shows a cross-sectional view of the preparation method after a silicon nitride layer is formed on the inner wall of the channel hole. Figure 3C It is based on Figure 2 The diagram shows a cross-sectional view of the first portion of the silicon nitride layer after undergoing a first oxidation treatment according to the fabrication method shown; and Figure 3D It is based on Figure 2 A schematic cross-sectional view of the second portion of the silicon nitride layer after a second oxidation treatment is shown in the preparation method. Figure 3E It is based on Figure 2 The diagram shows a cross-sectional view of the channel structure formed by the fabrication method shown. Figure 4 This is a cross-sectional schematic diagram of a channel hole in a through-stacking structure according to another embodiment of this application. Detailed Implementation

[0016] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this application and are not intended to limit the scope of this application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0017] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features, especially not any order of precedence. Therefore, without departing from the teachings of this application, the first part discussed herein may also be referred to as the second part, and the first channel structure may also be referred to as the second structure, and vice versa.

[0018] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. As used herein, the terms “approximately,” “about,” and similar terms are used as expressions of approximation, not as expressions of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0019] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to examples or illustrations.

[0020] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0021] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this application are not limited to the order in which they are described, but can be performed in any order or in parallel. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0022] In the fabrication process of 3D memory, it is usually necessary to form a silicon oxide layer as a charge blocking layer on the inner wall of the channel hole that runs through the stacked structure. Figure 1 A cross-sectional schematic diagram illustrating a method of embodiment of this application after forming a silicon oxide layer 141 on the inner wall of a channel hole 120 is shown.

[0023] like Figure 1 As shown, the stacked structure 110 may include, for example, a plurality of alternately stacked dielectric layers (e.g., 111) and a plurality of dielectric sacrificial layers (e.g., 112). A via 120 may extend through the stacked structure 110 into, for example, a substrate 130. The via 120 may include a first via 121 and a second via 122, and the first via 121 and the second via 122 are disposed along the stacking direction (z-direction) of the stacked structure 110 and communicate with each other. For example, the first via 121 may be disposed close to and through a portion of the substrate 130, and the second via 122 may be disposed on the side of the first via 121 away from the substrate 130. In a plane perpendicular to the stacking direction (xy plane), the first via 121 and the second via 122 may have the same or different cross-sectional shapes, such as circular, elliptical, square, or other irregular shapes. Optionally, the cross-sectional shape of the first channel hole 121 or the second channel hole 122 can gradually decrease along the negative z-direction. For example, when the cross-sectional shape of the first channel hole 121 and the second channel hole 122 in the xy plane is circular, at the connection 123 of the first channel hole 121 and the second channel hole 122, the diameter D1 of the first channel hole 121 is larger than the diameter D2 of the second channel hole 122. In other words, at the connection 123 of the first channel hole 121 and the second channel hole 122, due to the difference in cross-sectional dimensions, the sidewalls of the first channel hole 121 and the second channel hole 122 will form a step-like surface.

[0024] A silicon oxide layer 141 is typically formed on the inner wall of the channel holes 120 (i.e., the first channel hole 121 and the second channel hole 122), and the silicon oxide layer 141 can serve as, for example, a charge blocking layer. However, the physical structure of the stepped surface at the junction 123 of the first channel hole 121 and the second channel hole 122 can affect the thin film coverage of the silicon oxide layer 141 at the junction 123.

[0025] This application provides a method for fabricating a three-dimensional memory. The method first forms a silicon nitride layer on the inner wall of a channel hole, and then transforms the silicon nitride layer into a silicon oxide layer, i.e., a charge blocking layer, by subjecting the silicon nitride layer to two oxidation processes. The silicon oxide film formed in this manner improves its film coverage at the junctions and ensures the film quality of the silicon oxide layer.

[0026] Figure 2 This is a flowchart of a method 200 for preparing a three-dimensional memory according to another embodiment of this application. Figures 3A to 3E It is based on Figure 2 The diagram shows a cross-sectional view of the preparation method 200 during the preparation process. The following will be combined with... Figures 3A to 3E Steps 210 to 230 are described further. It should be noted that, for clarity, [the following is an explanation of steps 210 to 230]. Figures 3A to 3E The spatial relationships of the layers are shown, with the interfaces between layers indicated by solid lines. However, in reality, layers of the same material may not have clearly defined interfaces.

[0027] In step 210, Figure 3A Examples are based on Figure 2 A schematic cross-sectional view of the channel holes in the through-stacking structure of fabrication method 200 is shown. (See diagram below.) Figure 3A As shown, in some examples, the stacked structure 310 may be formed on one side of the substrate 330. Exemplarily, the substrate 330 may include silicon (e.g., single-crystal silicon, polycrystalline silicon), silicon-germanium (SiGe), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), glass, III-V compound semiconductors, and any other suitable materials. The substrate 330 may be used to provide mechanical support for, for example, the stacked structure 310. Optionally, the substrate 330 may be removed during the fabrication process of the three-dimensional memory, and a semiconductor material layer (not shown) may be reformed at its approximate spatial location.

[0028] In some examples, the stacked structure 310 may include multiple dielectric layers (e.g., 311) and multiple dielectric sacrificial layers (e.g., 312) stacked alternately. The multiple dielectric sacrificial layers (e.g., 312) may be replaced by multiple conductive layers (e.g., ...). Figure 3E (As shown in 313). Exemplarily, in a process of removing multiple dielectric sacrificial layers (e.g., 312), the dielectric layer (e.g., 311) and the dielectric sacrificial layer (e.g., 312) may have different etching selectivity ratios. For example, the material of the dielectric layer 311 may include silicon oxide, and the material of the dielectric sacrificial layer 312 may include silicon nitride.

[0029] In some examples, each replaced conductive layer (e.g., Figure 3E The 313 shown can serve as a word line connecting multiple memory cells in a three-dimensional memory, for example, by applying a voltage to the word line to control the multiple memory cells connected thereto. For instance, the number of dielectric sacrificial layers (e.g., 312) in the stacked structure 310 can be positively correlated with the number of unit memory cells. In other words, the more pairs of dielectric layers (e.g., 311) and dielectric sacrificial layers (e.g., 312) in the stacked structure 310, the greater the unit storage density of the fabricated three-dimensional memory. Increasing the unit storage density by increasing the number of dielectric layer (e.g., 311) and dielectric sacrificial layer (e.g., 312) pairs in the stacked structure 310 is one of the development trends in three-dimensional memories and their fabrication processes.

[0030] like Figure 3A As shown, the via 320 may extend through the stacked structure 310 into, for example, a substrate 330. In some examples, the via 320 may include a first via 321 and a second via 322, and the first via 321 and the second via 322 are disposed along the stacking direction (z-direction) of the stacked structure 310 and communicate with each other. Optionally, the central axes of the first via 321 and the second via 322 may not coincide with each other, and the central axes of the first via 321 and the second via 322 may be offset. As mentioned above, because the cross-sectional dimensions of the junction 323 of the first via 321 and the second via 322 are different in the xy plane, the sidewalls of the first via 321 and the second via 322 will form a step-like surface.

[0031] In this step, Figure 3B Examples are based on Figure 2 The diagram shows a cross-sectional view after a silicon nitride layer has been formed on the inner wall of the channel hole. (See attached diagram.) Figure 3B As shown, a silicon nitride layer 342 can be formed on the inner wall of the channel hole 320 using, for example, a thin-film deposition process. For example, the inner wall of the channel hole 320 may include the sidewalls and bottom of the first channel hole 321 and the sidewalls of the second channel hole 322. Along the thickness direction of the silicon nitride layer 342, the silicon nitride layer 342 may include a second portion 3422 in contact with the channel hole 320 and an exposed first portion 3421. It should be noted that... Figure 3B The first portion 3421 and the second portion 3422 of the silicon nitride layer 342 shown do not have an interface (dashed line). The dashed line is used here to show the portion of the silicon nitride layer 342 where the first oxidation treatment is performed in the subsequent step 220.

[0032] In some examples, atomic layer deposition (ALD) can be used to form a silicon nitride layer 342 on the inner wall of the channel via 320. Exemplarily, atomic layer deposition is a process in which a gas-phase precursor is alternately pulsed into a reaction chamber and deposited onto a substrate surface to undergo a gas-solid phase chemisorption reaction to form a thin film. Forming the silicon nitride layer 342 using the ALD process is advantageous in meeting the film uniformity requirements of the silicon nitride layer 342. For example, it facilitates better coverage of the stepped surface at the junction 323 of the first and second channel vias 321 and 322 by the silicon nitride layer 342. Furthermore, it facilitates precise control of the film thickness of the silicon nitride layer 342, thereby improving the electrical performance of the transformed silicon oxide layer as a charge-blocking layer.

[0033] In some examples, the thickness t0 of the silicon nitride layer 342 can be greater than or equal to 1.6 nm. When the thickness t0 of the silicon nitride layer 342 is ≥ 1.6 nm, the silicon oxide layer 341 formed using the silicon nitride layer 342 can be satisfied (see...). Figure 3D The thickness requirement of the charge blocking layer can effectively avoid the pinhole defect caused by the excessively thin silicon nitride layer 342.

[0034] In step 220, an oxidation process can be used to perform a first oxidation treatment on the first portion 3421 of the silicon nitride layer 342 that is away from the channel hole 320. Figure 3C Examples are based on Figure 2 The diagram shows a cross-sectional view of the first portion of the silicon nitride layer after undergoing a first oxidation treatment. (See attached image.) Figure 3C As shown, after the first oxidation treatment, the first portion 3421 (reference) of the silicon nitride layer 342 Figure 3B The silicon nitride layer 342 is transformed into a first silicon oxide layer 3411, while the second portion 3422 of the silicon nitride layer 342 is not subjected to the first oxidation treatment. In other words, the portion of the silicon nitride layer 342 that has undergone the first oxidation treatment can be referred to as the first portion 3421, while the remaining portion of the silicon nitride layer 342 that has not undergone the first oxidation treatment can be referred to as the second portion 3422.

[0035] In some examples, the first oxidation process can be performed using a slower oxidation rate. For example, the oxidation rate of the first oxidation process can be lower than that of the second oxidation process. This ensures that during the first oxidation process, the reactant gas (e.g., oxygen) diffuses sufficiently to the top of the channel hole 320 away from the substrate 330 and to the bottom of the channel hole 330. This allows the reactant gas (e.g., oxygen) to uniformly contact the surface of the silicon nitride layer 342 away from the inner wall of the channel hole 320, thereby improving the uniformity of the first silicon oxide layer 3411 formed by reacting with the silicon nitride layer 342 and the silicon oxide layer 341 (see [link to documentation]). Figure 3DThe uniformity of oxidation. For example, the oxidation rate of the second oxidation treatment may be greater than or equal to 50 times the oxidation rate of the first oxidation treatment.

[0036] In some examples, the first oxidation process can be performed using a batch isotropic oxidation (BIO) process. Exemplarily, the isotropic oxidation process uses a temperature (e.g., a low temperature) to dissociate oxygen in the reaction gas into oxygen atoms and / or oxygen groups, such that oxygen reacts with silicon nitride in the form of oxygen atoms and / or oxygen groups during the first oxidation process. Due to the strong oxidizing properties of oxygen atoms and / or oxygen groups, the resulting first silicon oxide layer 3411 film has high density and few bulk defects. Exemplarily, in the first oxidation process using an isotropic oxidation process, firstly, oxygen atoms and / or oxygen groups react with silicon nitride layer 342 (see...). Figure 3B The silicon nitride on the surface of the silicon nitride layer 342 is consumed upon surface contact to form an initial silicon oxide layer. Then, oxygen atoms and / or oxygen groups diffuse through the initial silicon oxide layer into the internal silicon nitride of the silicon nitride layer 342, causing the interface between the initial silicon oxide layer and the silicon nitride layer to shift towards the internal silicon nitride. Exemplarily, in the first oxidation process, the reaction gas may also include hydrogen, which helps maintain equilibrium in the reversible reaction of oxygen dissociating into oxygen atoms and / or oxygen groups, thereby ensuring that oxygen exists in the form of oxygen atoms and / or oxygen groups.

[0037] In some examples, the first portion 3421 of the silicon nitride layer 342 subjected to the first oxidation treatment can be controlled by controlling process parameters such as reaction time (see [reference]). Figure 3B The thickness of the silicon nitride layer 342. For example, the thickness t1 of the first portion 3421 of the silicon nitride layer 342 is greater than half of the total thickness t0 of the silicon nitride layer 342. It should be noted that the thickness t1 of the first portion 3421 of the silicon nitride layer 342 can be different from the thickness t1' of the first silicon oxide layer 3411 transformed from the first portion 3421 after the first oxidation treatment. When the thickness t1 of the first portion 3421 of the silicon nitride layer 342 is greater than or equal to half of the total thickness t0 of the silicon nitride layer 342, the first oxidation treatment can play a dominant role in the two oxidation treatments, which is beneficial to ensuring the uniformity of the film of the first silicon oxide layer 3411 and the silicon oxide layer 341 (see Figure 3D ( ) film uniformity.

[0038] In some examples, the machine used for the first oxidation treatment in step 220 can be the same as the machine used to form the silicon nitride layer 342 in step 210. In other words, the first oxidation treatment of the first portion 3421 of the silicon nitride layer 342 can be performed using the same machine after step 210. For example, the first oxidation treatment can be performed using an isotropic thermal oxidation process, hence the name in-situ isotropic thermal oxidation (In-situ BIO) process. The In-situ BIO process can reduce the number of operations, improve production efficiency, and reduce production costs.

[0039] In step 230, another oxidation process can be used to perform a second oxidation treatment on the silicon nitride layer 342. Figure 3D Examples are based on Figure 2 The diagram shows a cross-sectional view of the silicon nitride layer 342 after the second oxidation treatment. Figure 3D As shown, after the second oxidation treatment, the second portion 3422 of the silicon nitride layer 342 (reference) Figure 3C The silicon oxide layer 3412 is transformed into the second silicon oxide layer 342, so that the silicon nitride layer 342 formed in step 210 (see...) Figure 3B The silicon oxide layer 341 is transformed into a silicon oxide layer 341. After the above process, along the thickness direction of the silicon oxide layer 341, the silicon oxide layer 341 may include a first silicon oxide layer 3411 obtained in step 220 and a second silicon oxide layer 3412 obtained in step 230. At the same time, the second oxidation process can adjust the film quality of the first silicon oxide layer 3411 obtained from the first oxidation process, so that the silicon oxide layer 341 has a higher overall film quality.

[0040] In some examples, the second oxidation process can be performed at high temperatures. For example, the temperature during the second oxidation process can be higher than the temperature during the first oxidation process. Since high-temperature reaction conditions are beneficial for improving the film quality of the formed silicon oxide layer during the oxidation process of the silicon nitride layer, by making the temperature during the second oxidation process higher than the temperature during the first oxidation process, it is possible to adjust the film quality of the first silicon oxide layer 3411 obtained from the first oxidation process while transforming the second portion 3422 of the silicon nitride layer 342 into the second silicon oxide layer 3412, so that the silicon oxide layer 341 has a higher overall film quality.

[0041] In some examples, the second oxidation process can be performed using plasma oxidation, such as remote plasma oxidation (RPO). Exemplarily, the plasma oxidation process utilizes glow discharge at high temperatures to dissociate oxygen into oxygen atoms and / or oxygen clusters, thereby allowing oxygen to react with silicon nitride in the form of oxygen atoms and / or oxygen clusters during the second oxidation process. Optionally, the RPO process refers to a process where, for the equipment performing the second oxidation process, the dissociation region where oxygen is dissociated into oxygen atoms and / or oxygen clusters is located far from the reaction region where oxygen atoms and / or oxygen clusters react with silicon nitride. This approach achieves better spatial uniformity, resulting in better plasma treatment performance.

[0042] In some exemplary embodiments, a silicon oxide layer that meets the thickness requirements can be formed by alternately depositing a partial silicon nitride layer and oxidizing the partial silicon nitride layer. However, this will result in the partial silicon nitride layer being too thin each time, which will easily lead to pinhole defects and increase the difficulty of process control in forming the partial silicon nitride layer.

[0043] Compared to the exemplary embodiment, the fabrication method of the three-dimensional memory provided by the embodiments of this application simplifies the process operation and saves process costs by forming a silicon nitride layer in one step and performing two oxidation processes on the silicon nitride layer. It also allows the final silicon oxide layer to have better film uniformity and film quality, such as good film coverage at the step surface at the connection of two sub-channel holes, and the thickness difference of the silicon oxide layer in the direction away from the substrate is within 0.5 nm, resulting in good thickness consistency of the silicon oxide layer. Furthermore, under the condition of satisfying the thickness of the final silicon oxide layer, forming the silicon nitride layer in one step helps to reduce the difficulty of process control, improve the process window, and effectively reduce the risk of pinhole defects.

[0044] Figure 3E Examples are based on Figure 2 The diagram shows a cross-sectional view of the channel structure formed by the fabrication method. Figure 3EAs shown, in some examples, after performing fabrication method 200, the following steps may be taken to form the channel structure 350. Exemplarily, a thin film deposition process such as physical vapor deposition (PVD), chemical vapor deposition (CVD), ALD, or any combination thereof may be used to sequentially form a charge trapping layer 343, a tunneling layer 344, and a channel layer 346 on the surface where the silicon oxide layer 341 is formed. Exemplarily, the materials of the charge trapping layer 343 and the tunneling layer 344 may be silicon nitride and silicon oxide, respectively. As mentioned above, the silicon oxide layer 341 may serve as a charge blocking layer, and the charge blocking layer (i.e., silicon oxide layer 341), the charge trapping layer 343, and the tunneling layer 344 may be referred to as the functional layer 345. The material of the channel layer 346 may include semiconductor materials such as monocrystalline silicon and (doped) polycrystalline silicon. Optionally, any suitable thin film deposition process may be used to fill the interior of the functional layer 345 and the channel layer 346 with one or more insulating materials, such as silicon oxide, silicon nitride, or silicon oxynitride. It should be noted that, Figure 3E The thicknesses of the charge blocking layer (i.e., silicon oxide layer 341), charge trapping layer 343, tunneling layer 344, and channel layer 346 shown are merely exemplary, and their thicknesses may vary. Figure 3E Examples.

[0045] In some examples, as described above, multiple conductive layers (e.g., 313) are separated by multiple dielectric sacrificial layers (e.g., Figure 3D The layer shown (312) is formed through a "gate replacement" process. Each conductive layer (e.g., 313) and the corresponding functional layer 345 and channel layer 346 together constitute the memory cell MC. For example, by applying a voltage to the conductive layer 313, charge (e.g., electrons) in the channel layer 346 can be injected into the charge trapping layer 343, or by cooperating with the conductive layer 313 and other control lines, charge in the charge trapping layer 343 can be returned to the channel layer 346.

[0046] Multiple memory cells (e.g., MCs) arranged in the z-direction share the channel layer 346; in other words, multiple memory cells (e.g., MCs) can be arranged in series in the z-direction (similar to NAND gates).

[0047] Figure 4 This is a cross-sectional schematic diagram of a channel hole in a through-stacking structure according to another embodiment of this application. For example... Figure 4 As shown, the positional relationship between the channel hole 420 and the stacked structure 410 is... Figure 3A The examples in [the document] are the same, and will not be repeated here. [And] Figure 3A Compared to the channel hole 320 shown, the channel hole 420 also includes a groove 424 located at the junction 423 of the first channel hole 421 and the second channel hole 422.

[0048] In this embodiment, the groove 424 is disposed around the top of the first channel hole 421 and communicates with the first channel hole 421. Since some processes for fabricating the channel hole 420 are performed in the order of the first channel hole 421, the groove 424, and the second channel hole 422, the groove 424 can, for example, provide a larger overlay window for fabricating the second channel hole 422. Thus, the junction 423 of the first channel hole 421 and the second channel hole 422, including the groove 424, can produce a more complex surface structure. For this purpose, a silicon oxide layer (not shown) can be formed within the channel hole 420 by the fabrication method 200 described in detail above, thereby enabling the formed silicon oxide layer to have better film uniformity and film quality, for example, better film coverage at the surface of the junction of the two sub-channel holes.

[0049] This application also provides a three-dimensional memory. (See again...) Figure 3E The three-dimensional memory includes at least one channel structure 350. Each channel structure 350 includes an outer silicon oxide layer 341. The silicon oxide layer 341 may serve as, for example, a charge blocking layer, and the silicon oxide layer 341 may be formed according to the fabrication method 200 described above.

[0050] Since the content and structure described in the preparation method 200 above are fully or partially applicable to the three-dimensional memory described herein, related or similar content will not be repeated.

[0051] The above description is merely an illustration of the embodiments of this application and the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the technical concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A method for fabricating a three-dimensional memory, characterized in that, include: A silicon nitride layer is formed on the inner wall of a channel hole penetrating the stacked structure. The channel hole includes a first channel hole and a second channel hole that are disposed along the stacking direction of the stacked structure and are interconnected with each other. At the connection between the first channel hole and the second channel hole, the cross-sectional dimension of the first channel hole in a plane perpendicular to the stacking direction is different from that of the second channel hole in a plane perpendicular to the stacking direction, thereby forming a stepped surface. A first oxidation treatment is performed on the first portion of the inner wall of the silicon nitride layer away from the channel hole to form a first silicon oxide layer; as well as The silicon nitride layer is subjected to a second oxidation treatment to transform a second portion of the silicon nitride layer, excluding the first portion, into a second silicon oxide layer. The silicon oxide layer, composed of the first silicon oxide layer and the second silicon oxide layer, covers the sidewalls of the first channel hole and the second channel hole, as well as the step surface. The first oxidation treatment includes isotropic thermal oxidation treatment, and the second oxidation treatment includes remote plasma oxidation treatment.

2. The preparation method according to claim 1, wherein, The oxidation rate of the first oxidation treatment is less than the oxidation rate of the second oxidation treatment.

3. The preparation method according to claim 1 or 2, wherein, The temperature during the first oxidation treatment is lower than the temperature during the second oxidation treatment.

4. The preparation method according to claim 1, wherein, The isotropic thermal oxidation treatment includes: The first part is subjected to isotropic thermal oxidation treatment using oxygen and hydrogen as reaction gases.

5. The preparation method according to claim 1, wherein, The isotropic thermal oxidation treatment includes: The first portion is subjected to the isotropic thermal oxidation treatment using a machine used to form the silicon nitride layer.

6. The preparation method according to claim 1, wherein, The thickness of the first portion is greater than half the total thickness of the silicon nitride layer.

7. The preparation method according to claim 1, wherein, Forming a silicon nitride layer on the inner wall of the channel vias penetrating the stacked structure includes: The silicon nitride layer is formed by atomic layer deposition.

8. A three-dimensional memory, characterized in that, include: At least one channel structure, the channel structure comprising an outer silicon oxide layer, the silicon oxide layer being formed according to the preparation method of any one of claims 1 to 7.

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