Active triggered PMOS circuit for ESD protection and control method

Abstract

The application relates to the field of electronic technology and discloses an active trigger PMOS circuit for ESD protection and a control method. In the application, the active trigger PMOS circuit for ESD protection comprises a flyback module and a PMOS device. In the application, when an ESD pulse signal exists in a power supply, the flyback module generates an induction signal to make the PMOS device enter a conduction state, and then the PMOS device discharges the ESD pulse signal in the power supply when in the conduction state. Compared with the prior art that actively identifies the rising edge of an ESD pulse waveform and then actively triggers an ESD clamping device through RC delay, the application can identify the ESD pulse signal through the flyback module to rapidly drive the PMOS device, can perform ESD protection through the PMOS device, and can reduce the chip area occupied by the circuit.

Description

Technical Field

[0001] This invention relates to the field of electronic technology, and in particular to an active triggering PMOS circuit and control method for ESD protection. Background Technology

[0002] ESD, or electrostatic discharge, is a ubiquitous phenomenon in nature. ESD is present throughout chip manufacturing, packaging, testing, and use. Accumulated static charge is released in nanoseconds to microseconds with currents ranging from several to tens of amperes, resulting in instantaneous power of tens or hundreds of watts, causing immense damage to chips within circuit systems. Statistics show that most chip failures are caused by ESD damage. Therefore, the design of electrostatic protection modules in chip or system design directly affects the functional stability and reliability of the circuit system, making it extremely important for electronic products. Traditional ESD detection circuits are a new type of ESD protection circuit that actively identifies the rising edge of the ESD pulse waveform and actively triggers the ESD clamping device through RC delay. This is commonly used in the power supply ESD protection of many chips. However, this solution can only drive N-type MOS devices and cannot drive PMOS devices, which have more reliable latch-up. Furthermore, the large integrated capacitors waste significant chip area. Therefore, how to achieve active triggering of PMOS devices for ESD protection has become a pressing technical problem.

[0003] The above content is only used to help understand the technical solution of the present invention and does not represent an admission that the above content is prior art. Summary of the Invention

[0004] The main objective of this invention is to propose an active triggering PMOS circuit and control method for ESD protection, aiming to solve the technical problem of how to achieve active triggering of PMOS devices for ESD protection.

[0005] To achieve the above objectives, the present invention proposes an active trigger PMOS circuit for ESD protection, wherein the active trigger PMOS circuit for ESD protection includes: a flyback module and a PMOS device;

[0006] One end of the flyback module is connected to the source of the PMOS device and the power supply, the other end of the flyback module is connected to the gate of the PMOS device, and the other end of the flyback module is grounded to the drain of the PMOS device.

[0007] The flyback module is used to generate an induction signal when an ESD pulse signal is present in the power supply, so as to cause the PMOS device to enter the conduction state.

[0008] The PMOS device is used to discharge ESD pulse signals in the power supply when it is in the on state.

[0009] Optionally, the flyback module is further configured to enter a breakdown state when an ESD pulse signal is present in the power supply, generate an induction signal, and transmit the induction signal to the gate of the PMOS device;

[0010] The PMOS device is also used to discharge the built-in gate-source parasitic capacitance when receiving the sensing signal, so as to reduce the gate voltage and enable the PMOS device to enter the conduction state.

[0011] Optionally, the active trigger PMOS circuit for ESD protection further includes: an anti-latch-up module;

[0012] One end of the anti-latch-up module is connected to the power supply, and the other end of the anti-latch-up module is connected to one end of the flyback module and the gate of the PMOS device, respectively.

[0013] The anti-latch-up module is used to reduce the operating current of the flyback module so that the flyback module can achieve anti-latch-up.

[0014] Optionally, the anti-latch-up module includes: a first resistor;

[0015] The first end of the first resistor is connected to the power supply, and the second end of the first resistor is connected to one end of the flyback module and the gate of the PMOS device.

[0016] Optionally, the resistance of the first resistor is greater than the ratio of the power supply voltage to the minimum holding current of the flyback module.

[0017] Optionally, the flyback module includes: a PNP transistor and an NPN transistor;

[0018] The emitter of the PNP transistor is connected to the other end of the anti-latch-up module and the gate of the PMOS device, respectively. The base of the PNP transistor is connected to the other end of the anti-latch-up module, the gate of the PMOS device, and the collector of the NPN transistor, respectively. The collector of the PNP transistor, the base of the NPN transistor, and the emitter of the NPN transistor are grounded.

[0019] Optionally, the flyback module further includes: a second resistor and a third resistor;

[0020] The first end of the second resistor is connected to the other end of the anti-latch-up module and the gate of the PMOS device, the second end of the second resistor is connected to the base of the PNP transistor and the collector of the NPN transistor, the first end of the third resistor is connected to the collector of the PNP transistor and the base of the NPN transistor, and the second end of the third resistor is grounded.

[0021] Optionally, the flyback module includes: a gate-grounded MOS transistor;

[0022] The drain of the gate-grounded MOS transistor is connected to the other end of the anti-latch-up module, and the source and gate of the gate-grounded MOS transistor are grounded.

[0023] To achieve the above objectives, the present invention also proposes an active triggering PMOS control method for ESD protection, wherein the active triggering PMOS control method for ESD protection is applied to the active triggering PMOS circuit for ESD protection as described above.

[0024] The active triggering PMOS control method for ESD protection includes:

[0025] When an ESD pulse signal is present in the power supply, the flyback module generates an induction signal to cause the PMOS device to enter the conduction state.

[0026] When the PMOS device is in the ON state, it discharges the ESD pulse signal in the power supply.

[0027] Optionally, the step of the flyback module generating an induction signal to cause the PMOS device to enter the conduction state when an ESD pulse signal exists in the power supply specifically includes:

[0028] When an ESD pulse signal is present in the power supply, the flyback module enters a breakdown state, generates an induction signal, and transmits the induction signal to the gate of the PMOS device.

[0029] When the PMOS device receives the sensing signal, it discharges its built-in gate-source parasitic capacitance to reduce the gate voltage and enable the PMOS device to enter the conduction state.

[0030] In this invention, the active triggering PMOS circuit for ESD protection includes a flyback module and a PMOS device. One end of the flyback module and the source of the PMOS device are connected to the power supply, the other end of the flyback module is connected to the gate of the PMOS device, and the other end of the flyback module and the drain of the PMOS device are grounded. This invention first generates an induction signal when an ESD pulse signal exists in the power supply through the flyback module, so as to make the PMOS device enter the conduction state. Then, when the PMOS device is in the conduction state, it discharges the ESD pulse signal in the power supply. Compared with the existing method of actively identifying the rising edge of the ESD pulse waveform and then actively triggering the ESD clamping device through RC delay, the above method of this invention can identify the ESD pulse signal through the flyback module to quickly drive the PMOS device, perform ESD protection through the PMOS device, and reduce the chip area occupied by the circuit. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0032] Figure 1 This is a functional block diagram of the first embodiment of the active trigger PMOS circuit for ESD protection of the present invention;

[0033] Figure 2 This is a functional block diagram of a second embodiment of the active trigger PMOS circuit for ESD protection according to the present invention;

[0034] Figure 3 This is a schematic diagram of the active trigger PMOS circuit for ESD protection according to the present invention.

[0035] Figure 4 This is a schematic diagram of the working principle of the active trigger PMOS circuit for ESD protection of the present invention.

[0036] Figure 5 This is another circuit structure diagram of the active trigger PMOS circuit for ESD protection according to the present invention.

[0037] Figure 6 This is a flowchart illustrating the first embodiment of the active triggering PMOS control method for ESD protection according to the present invention.

[0038] Explanation of icon numbers:

[0039] 10 Backflip module R1~R3 First resistor to third resistor P PMOS devices Q1 PNP pipe 20 Anti-latch-up module Q2 NPN transistor G Gate-grounded MOSFET Cgs Gate-source parasitic capacitance

[0040] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0041] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0042] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indication will also change accordingly.

[0043] Furthermore, the use of terms such as "first" and "second" in this invention is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of that feature. Additionally, the technical solutions of the various embodiments can be combined with each other, but only on the basis of being achievable by those skilled in the art. When the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed by this invention.

[0044] This invention proposes an active trigger PMOS circuit for ESD protection.

[0045] Reference Figure 1 , Figure 1 This is a functional block diagram of the first embodiment of the active trigger PMOS circuit for ESD protection according to the present invention.

[0046] like Figure 1 As shown, in this embodiment of the invention, the active triggering PMOS circuit for ESD protection includes a flyback module 10 and a PMOS device P.

[0047] One end of the flyback module 10 is connected to the source of the PMOS device P and the power supply, the other end of the flyback module 10 is connected to the gate of the PMOS device P, and the other end of the flyback module 10 is grounded to the drain of the PMOS device P.

[0048] It should be noted that the power supply is an external power supply connected to the active trigger PMOS circuit for ESD protection in this embodiment. This embodiment does not specifically limit the specific power supply voltage value, which can be set according to the size of each component in the circuit.

[0049] The flyback module 10 is used to generate an induction signal when an ESD pulse signal is present in the power supply, so as to cause the PMOS device P to enter the conduction state.

[0050] It is understandable that an ESD pulse signal refers to an electrostatic discharge pulse signal, which may exist on the power supply. When an ESD pulse signal exists in the power supply, it is necessary to discharge the ESD pulse signal to prevent damage to the load connected to the power supply.

[0051] It should be understood that when the flyback module 10 receives an ESD pulse signal from the power supply, the flyback module will be broken down. The signal obtained after the breakdown is the induction signal, and the PMOS device P can be turned on through the induction signal.

[0052] The PMOS device P is used to discharge the ESD pulse signal in the power supply when it is in the on state.

[0053] In a practical implementation, when the PMOS device P is in the on state, the source and drain of the PMOS device P will be connected. At this time, the ESD pulse signal in the power supply will pass through the source and drain of the PMOS device P and then be discharged to ground.

[0054] Furthermore, the flyback module 10 is also used to enter a breakdown state when an ESD pulse signal exists in the power supply, generate an induction signal, and transmit the induction signal to the gate of the PMOS device P.

[0055] The PMOS device P is also used to discharge the built-in gate-source parasitic capacitance when receiving the sensing signal, so as to reduce the gate voltage and enable the PMOS device P to enter the conduction state.

[0056] It is understood that in this embodiment, the power supply voltage is assumed to be VDD. After the ESD pulse signal appears on the power supply, as the ESD pulse signal increases, when the power supply voltage plus the ESD voltage is greater than the breakdown voltage corresponding to the flyback module 10, the flyback module 10 will enter the breakdown state. At this time, the flyback module 10 will quickly generate a flyback effect. The flyback effect refers to the effect of the current corresponding to the flyback module 10 increasing while the voltage decreases.

[0057] In a specific implementation, after the flyback module 10 generates the flyback effect, the flyback module 10 will generate an induction signal, namely a negative dV / dt. This negative dV / dt will discharge from the power supply VDD through the gate-source parasitic capacitance Cgs built into the PMOS device P, so that the gate potential of the PMOS device P will be much smaller than VDD for a moment, and the PMOS device P will be turned on at this moment.

[0058] In this embodiment, the active triggering PMOS circuit for ESD protection includes a flyback module and a PMOS device. One end of the flyback module and the source of the PMOS device are connected to the power supply, the other end of the flyback module is connected to the gate of the PMOS device, and the other end of the flyback module and the drain of the PMOS device are grounded. This invention first generates an induction signal when an ESD pulse signal exists in the power supply via the flyback module, causing the PMOS device to enter a conducting state. Then, when the PMOS device is in the conducting state, it discharges the ESD pulse signal in the power supply. Compared to existing methods that actively identify the rising edge of the ESD pulse waveform and then actively trigger the ESD clamping device through RC delay, this embodiment can identify the ESD pulse signal via the flyback module to quickly drive the PMOS device, perform ESD protection through the PMOS device, and reduce the chip area occupied by the circuit.

[0059] Furthermore, referring to Figure 2 , Figure 2 This is a functional block diagram of the second embodiment of the active trigger PMOS circuit for ESD protection of the present invention.

[0060] like Figure 2 As shown, the active trigger PMOS circuit for ESD protection also includes: an anti-latch-up module 20;

[0061] One end of the anti-latch-up module 20 is connected to the power supply, and the other end of the anti-latch-up module 20 is connected to one end of the flyback module 10 and the gate of the PMOS device P, respectively.

[0062] The anti-latch-up module 20 is used to reduce the operating current of the flyback module 10 so that the flyback module 10 can achieve anti-latch-up.

[0063] It should be noted that the latch-up effect refers to a low-impedance path formed between the power supply VDD and the ground line in a CMOS chip due to the interaction of parasitic PNP and NPN bipolar BJTs.

[0064] It is understood that by adding the anti-latch-up module 20, the operating current of the flyback module 10 can be reduced, that is, the current of the flyback module 10 during operation. At this time, the flyback module 10 will achieve anti-latch-up.

[0065] Furthermore, referring to Figure 3 , Figure 3 This is a schematic diagram of the active trigger PMOS circuit for ESD protection according to the present invention.

[0066] like Figure 3 As shown, the anti-latch-up module includes 20: a first resistor R1;

[0067] The first end of the first resistor R1 is connected to the power supply, and the second end of the first resistor R1 is connected to one end of the flyback module 10 and the gate of the PMOS device P.

[0068] It is understood that the first resistor R1 in this embodiment can reduce the operating current of the flyback module 10 so that the flyback module 10 can achieve anti-latch-up function.

[0069] Furthermore, the resistance value of the first resistor R1 is greater than the ratio of the power supply voltage to the minimum holding current of the flyback module 10.

[0070] It should be noted that the minimum sustaining current of the flyback module 10 refers to the minimum current that the flyback module 10 can operate under, and the magnitude of this current is related to the components in the flyback module 10.

[0071] In a specific implementation, the resistance value of the first resistor R1 is greater than the ratio of the power supply voltage to the minimum holding current of the flyback module 10, which enables the flyback module 10 to achieve anti-latch-up function.

[0072] Furthermore, the flyback module 10 includes: a PNP transistor Q1 and an NPN transistor Q2;

[0073] The emitter of the PNP transistor Q1 is connected to the other end of the anti-latch-up module 20 and the gate of the PMOS device P, respectively. The base of the PNP transistor Q1 is connected to the other end of the anti-latch-up module 20, the gate of the PMOS device P, and the collector of the NPN transistor Q2, respectively. The collector of the PNP transistor Q1, the base of the NPN transistor Q2, and the emitter of the NPN transistor Q2 are grounded.

[0074] Furthermore, the flyback module also includes: a second resistor R2 and a third resistor R3;

[0075] The first end of the second resistor R2 is connected to the other end of the anti-latch-up module 20 and the gate of the PMOS device P, respectively. The second end of the second resistor R2 is connected to the base of the PNP transistor Q2 and the collector of the NPN transistor Q2, respectively. The first end of the third resistor R3 is connected to the collector of the PNP transistor Q1 and the base of the NPN transistor Q2, respectively. The second end of the third resistor R3 is grounded.

[0076] It should be understood that the function of the second resistor R2 and the third resistor R3 is to limit the current in order to protect the PNP transistor Q1 and the NPN transistor Q2 and prevent them from being damaged.

[0077] Furthermore, referring to Figure 4 , Figure 4 This is a schematic diagram of the working principle of the active trigger PMOS circuit for ESD protection of the present invention.

[0078] like Figure 4 As shown, Figure 4 The voltage curve corresponding to point B in the diagram refers to the voltage curve composed of the power supply voltage plus the ESD voltage, while the voltage curve corresponding to point A is the gate voltage curve of the PMOS device P.

[0079] Understandably, Figure 4 The voltage at point A initially increases, indicating a gradually increasing ESD voltage on the power supply; subsequently, the voltage at point A decreases, indicating that the ESD voltage is discharged through the PMOS device P. Similarly, the voltage at point B initially increases, also indicating a gradually increasing ESD voltage on the power supply, causing the gate voltage of the PMOS device P to gradually increase; subsequently, the voltage at point B decreases, indicating that the flyback module 10 has experienced a flyback effect, and the voltage at point A will momentarily decrease before the PMOS device P is turned on. Figure 4 In the process, the timing of voltage drop at point A and the timing of voltage drop at point B are not necessarily the same, depending on the components in the flyback module.

[0080] In the specific implementation, Figure 3 The flyback module in the design uses an SCR device. When an ESD voltage much greater than the power supply VDD appears on VDD, VDD charges the gate of the pull-down SCR and the PMOS device P through the first resistor R1. At this time, the gate and source potentials of the PMOS device P are equal. The design can be implemented to allow the ESD voltage to continue rising and eventually break down the SCR. After the pull-down SCR breaks down, it will quickly undergo a flyback effect, rapidly pulling the potential at point A down from its breakdown voltage to a very low value (approximately 1-2V). This induces a large negative dV / dt at the gate of the PMOS device P. This negative dV / dt discharges from VDD through the gate-source parasitic capacitance Cgs of the PMOS device P, causing the potential at point A to momentarily fall significantly below VDD. At this instant, the PMOS device P will turn on, electrostatically discharging the ESD voltage and thus limiting the ESD voltage on the VDD line to prevent overvoltage.

[0081] Furthermore, referring to Figure 5 , Figure 5This is another circuit structure diagram of the active trigger PMOS circuit for ESD protection according to the present invention.

[0082] like Figure 5 As shown, the flyback module 10 includes: a gate-grounded MOS transistor G;

[0083] The drain of the gate-grounded MOS transistor G is connected to the other end of the anti-latch-up module 20, and the source and gate of the gate-grounded MOS transistor G are grounded.

[0084] It should be understood that the gate-grounded NMOS transistor G in this embodiment is used for electrostatic protection of the integrated circuit leads, and the gate-grounded NMOS transistor G also has a flyback capability.

[0085] In the specific implementation, Figure 5 The flyback module in the design uses a gate-grounded NMOS transistor G. When an ESD voltage much greater than the power supply VDD appears on VDD, VDD charges the gate of the pull-down gate-grounded NMOS transistor G and the gate of the PMOS device P through the first resistor R1. At this time, the gate and source potentials of the PMOS device P are equal. The design can be implemented so that the ESD voltage continues to rise and eventually breaks down the gate-grounded NMOS transistor G first. After the pull-down gate-grounded NMOS transistor G breaks down, it will quickly undergo a flyback effect, rapidly pulling the potential at point A down from its breakdown voltage to a very low value (approximately 1-2V). This induces a large negative dV / dt at the gate of the PMOS device P. This negative dV / dt will discharge from VDD through the gate-source parasitic capacitance Cgs of the PMOS device P, causing the potential at point A to momentarily fall significantly below VDD. At this instant, the PMOS device P will turn on to electrostatic discharge the ESD voltage, thereby limiting the ESD voltage on the VDD line to prevent overvoltage.

[0086] The active trigger PMOS circuit for ESD protection proposed in this embodiment does not require a large capacitor for ESD detection. It only needs a flyback module 10 with flyback characteristics and a carefully calculated resistor (i.e., the first resistor R1) to achieve a fast trigger response for the PMOS. This solves the problem that traditional trigger circuits can only trigger NMOS transistors and have an excessively large area. The active trigger PMOS circuit for ESD protection proposed in this embodiment is very suitable for high-voltage power supply ESD protection.

[0087] To achieve the above objectives, the present invention also proposes an active triggering PMOS control method for ESD protection, wherein the active triggering PMOS control method for ESD protection is applied to the active triggering PMOS circuit for ESD protection as described above. (Refer to...) Figure 6 Figure 6 is a flowchart illustrating the first embodiment of the active triggering PMOS control method for ESD protection according to the present invention.

[0088] like Figure 6 As shown, in this embodiment, the active triggering PMOS control method for ESD protection includes:

[0089] Step S10: When an ESD pulse signal exists in the power supply, the flyback module generates an induction signal to cause the PMOS device to enter the conduction state.

[0090] It should be noted that the power supply is an external power supply connected to the active trigger PMOS circuit for ESD protection in this embodiment. This embodiment does not specifically limit the specific power supply voltage value, which can be set according to the size of each component in the circuit.

[0091] It is understandable that an ESD pulse signal refers to an electrostatic discharge pulse signal, which may exist on the power supply. When an ESD pulse signal exists in the power supply, it is necessary to discharge the ESD pulse signal to prevent damage to the load connected to the power supply.

[0092] It should be understood that when the flyback module 10 receives an ESD pulse signal from the power supply, the flyback module will be broken down. The signal obtained after the breakdown is the induction signal, and the PMOS device P can be turned on through the induction signal.

[0093] Further, step S10 includes: when an ESD pulse signal exists in the power supply, the flyback module enters a breakdown state, generates an induction signal, and transmits the induction signal to the gate of the PMOS device; when the PMOS device receives the induction signal, it discharges to the built-in gate-source parasitic capacitance to reduce the gate voltage and enable the PMOS device to enter a conduction state.

[0094] It is understood that in this embodiment, the power supply voltage is assumed to be VDD. After the ESD pulse signal appears on the power supply, as the ESD pulse signal increases, when the power supply voltage plus the ESD voltage is greater than the breakdown voltage corresponding to the flyback module 10, the flyback module 10 will enter the breakdown state. At this time, the flyback module 10 will quickly generate a flyback effect. The flyback effect refers to the effect of the current corresponding to the flyback module 10 increasing while the voltage decreases.

[0095] In a specific implementation, after the flyback module 10 generates the flyback effect, the flyback module 10 will generate an induction signal, namely a negative dV / dt. This negative dV / dt will discharge from the power supply VDD through the gate-source parasitic capacitance Cgs built into the PMOS device P, so that the gate potential of the PMOS device P will be much smaller than VDD for a moment, and the PMOS device P will be turned on at this moment.

[0096] Step S20: When the PMOS device is in the on state, it discharges the ESD pulse signal in the power supply.

[0097] In a practical implementation, when the PMOS device P is in the on state, the source and drain of the PMOS device P will be connected. At this time, the ESD pulse signal in the power supply will pass through the source and drain of the PMOS device P and then be discharged to ground.

[0098] In this embodiment, the active triggering PMOS circuit for ESD protection includes a flyback module and a PMOS device. One end of the flyback module and the source of the PMOS device are connected to the power supply, the other end of the flyback module is connected to the gate of the PMOS device, and the other end of the flyback module and the drain of the PMOS device are grounded. This invention first generates an induction signal when an ESD pulse signal exists in the power supply via the flyback module, causing the PMOS device to enter a conducting state. Then, when the PMOS device is in the conducting state, it discharges the ESD pulse signal in the power supply. Compared to existing methods that actively identify the rising edge of the ESD pulse waveform and then actively trigger the ESD clamping device through RC delay, this embodiment can identify the ESD pulse signal via the flyback module to quickly drive the PMOS device, perform ESD protection through the PMOS device, and reduce the chip area occupied by the circuit.

[0099] The above description is merely a preferred embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural transformations made using the contents of the present invention's specification and drawings under the inventive concept of the present invention, or direct / indirect applications in other related technical fields, are included within the patent protection scope of the present invention.

Claims

1. An actively triggered PMOS circuit for ESD protection, characterized in that, The active trigger PMOS circuit for ESD protection includes: a flyback module and a PMOS device; The source of the PMOS device is connected to the power supply, one end of the flyback module is connected to the gate of the PMOS device, and the other end of the flyback module is grounded to the drain of the PMOS device. The flyback module is also used to enter a breakdown state when an ESD pulse signal is present in the power supply, generate an induction signal, and transmit the induction signal to the gate of the PMOS device. The PMOS device is also used to discharge the built-in gate-source parasitic capacitance when receiving the sensing signal, so as to reduce the gate voltage and enable the PMOS device to enter the conduction state. The sensing signal is negative dV / dt. The PMOS device is used to discharge ESD pulse signals in the power supply when it is in the on state. The active trigger PMOS circuit for ESD protection also includes: an anti-latch-up module; One end of the anti-latch-up module is connected to the power supply, and the other end of the anti-latch-up module is connected to one end of the flyback module and the gate of the PMOS device, respectively. The anti-latch-up module is used to reduce the operating current of the flyback module so that the flyback module can achieve anti-latch-up. The flyback module includes: a PNP transistor and an NPN transistor; The emitter of the PNP transistor is connected to the other end of the anti-latch-up module and the gate of the PMOS device, respectively. The base of the PNP transistor is connected to the other end of the anti-latch-up module, the gate of the PMOS device, and the collector of the NPN transistor, respectively. The collector of the PNP transistor, the base of the NPN transistor, and the emitter of the NPN transistor are grounded.

2. The active-triggered PMOS circuit for ESD protection as described in claim 1, characterized in that, The anti-latch-off module includes: a first resistor; The first end of the first resistor is connected to the power supply, and the second end of the first resistor is connected to one end of the flyback module and the gate of the PMOS device.

3. The active-triggered PMOS circuit for ESD protection as described in claim 2, characterized in that, The resistance of the first resistor is greater than the ratio of the power supply voltage to the minimum holding current of the flyback module.

4. The active-triggered PMOS circuit for ESD protection as described in claim 3, characterized in that, The flyback module further includes: a second resistor and a third resistor; The first end of the second resistor is connected to the other end of the anti-latch-up module and the gate of the PMOS device, the second end of the second resistor is connected to the base of the PNP transistor and the collector of the NPN transistor, the first end of the third resistor is connected to the collector of the PNP transistor and the base of the NPN transistor, and the second end of the third resistor is grounded.

5. An active triggering PMOS control method for ESD protection, characterized in that, The active triggering PMOS control method for ESD protection is applied to the active triggering PMOS circuit for ESD protection as described in any one of claims 1 to 4. The active triggering PMOS control method for ESD protection includes: When an ESD pulse signal is present in the power supply, the flyback module enters a breakdown state, generates an induction signal, and transmits the induction signal to the gate of the PMOS device. When the PMOS device receives the sensing signal, it discharges into the built-in gate-source parasitic capacitance to reduce the gate voltage and enable the PMOS device to enter the conduction state. When the PMOS device is in the ON state, it discharges the ESD pulse signal in the power supply.

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