Link quality estimation and anomaly detection in high-speed wired receivers

Abstract

Embodiments of the present disclosure relate to link quality estimation and anomaly detection in high-speed wired receivers. An integrated circuit (IC) for use in a network device includes a receiver and a link quality estimation circuit (LQEC). The receiver is configured to receive a signal over a link and process the received signal. The LQEC is configured to predict a link quality measurement indicative of future communication quality over the link by analyzing at least one or more settings of circuitry of the receiver, and initiate a responsive action in accordance with the predicted link quality measurement.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of U.S. Provisional Patent Application 63 / 143,577, filed January 29, 2021, the disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure generally relates to high-speed receivers, and more particularly to methods and systems for link quality estimation in high-speed wired receivers. Background Technology

[0004] High-speed receivers, and particularly receivers incorporating high-speed deserializers (SERDES), may include circuitry for estimating link quality. Summary of the Invention

[0005] The embodiments described herein provide an integrated circuit (IC) referenced for use in network devices. The IC includes a receiver and a link quality estimation circuit (LQEC). The receiver is configured to receive signals on a link and to process the received signals. The LQEC is configured to predict link quality measurements indicative of future communication quality on the link by analyzing at least one or more settings of the receiver's circuitry, and to initiate a response action based on the predicted link quality measurements.

[0006] In one embodiment, LQEC is configured to initiate a response action from one link to another by at least partially initiating a transfer of subsequent communication. In the disclosed embodiments, by analyzing the settings of the receiver's circuitry over time, LQEC is configured to predict future values ​​or trends in link quality measurements and is configured to initiate a response action based on the predicted future values ​​or trends. In an example embodiment, LQEC is configured to initiate a response action in response to determining that a link quality measurement is predicted to drop below a quality threshold.

[0007] In some embodiments, LQEC is configured to predict link quality measurements by jointly analyzing (i) one or more settings of the receiver's circuitry and (ii) one or more parameters of the received signal. In the disclosed embodiments, LQEC is configured to predict link quality measurements by operating a pre-trained machine learning (ML) model on at least one or more settings of the receiver's circuitry.

[0008] In one embodiment, LQEC is configured to initiate a response action by reducing the data rate of the initiated signal. In another embodiment, LQEC is configured to initiate a response action by initiating a change in the encoding scheme used to encode the signal. In an example embodiment, LQEC is configured to predict link quality measurements by analyzing at least one setting of the receiver's circuitry over time, the setting being selected from: (i) the gain of the clock data recovery (CDR) circuitry, (ii) the bandwidth of the CDR circuitry, (iii) the response of the analog equalizer filter, (iv) the settings of the analog-to-digital converter (ADC), (v) the tap values ​​of the digital equalizer, (vi) the automatic gain control (AGC) settings, and (vii) the limiter threshold.

[0009] In some embodiments, the IC further includes: one or more additional receivers configured to receive, process, and demodulate one or more additional signals on one or more additional links; and one or more additional LQECs configured to predict one or more additional link quality measurements for communication on the one or more additional links based on analysis of link quality measurements on the one or more additional links. In one embodiment, the IC further includes a processor configured to calculate system-level health measurements for a network system or a portion of the network system based on the link quality measurements and the one or more additional link quality measurements, and to manage traffic allocation in response to the calculated system-level health measurements.

[0010] In some embodiments, the receiver is located in the deserializer.

[0011] According to the embodiments described herein, a method for use in a network device is also provided. The method includes receiving and processing signals via a link using a receiver. A link quality measurement indicative of future communication quality on the link is predicted by analyzing at least one or more settings of the receiver's circuitry. A response action is initiated based on the predicted link quality measurement.

[0012] The invention will be more fully understood from the following detailed description of embodiments of the invention, taken in conjunction with the accompanying drawings, in which: Attached Figure Description

[0013] Figure 1 This is a block diagram illustrating a high-speed wired receiver with link quality estimation circuitry (LQEC) according to the embodiments described herein;

[0014] Figure 2 The embodiments described herein are schematically illustrated for simulation. Figure 1A block diagram of the structure of a data transmission simulation environment for the receiver and link, which generates input data for a machine learning (ML) model for link quality estimation;

[0015] Figure 3 The embodiments described herein are schematically illustrated for generating Figure 1 A block diagram of the ML training environment for link quality estimation of ML parameters in LQEC;

[0016] Figure 4 The embodiments described herein schematically illustrate the use of... Figure 1 Waveform diagram of link quality prediction performed by LQEC;

[0017] Figure 5A This is a block diagram illustrating a distributed system with a main routing path, based on the embodiments described herein.

[0018] Figure 5B This is a block diagram illustrating a distributed system having a secondary routing path selected in response to a low link quality prediction, based on the embodiments described herein.

[0019] Figure 6 This is a block diagram schematically illustrating a network device configured to optimize communication performance in response to link quality prediction, according to embodiments described herein.

[0020] Figure 7A The flowchart illustrates, according to the embodiments described herein, a method for generating ML-based link quality estimation and prediction models;

[0021] Figure 7B The flowcharts illustrating methods for estimating and predicting link quality are shown schematically according to embodiments described herein; and

[0022] Figure 7C This is a flowchart schematically illustrating a method for improving the performance of a network device by utilizing link quality estimation and link quality prediction, according to embodiments described herein. Detailed Implementation

[0023] Fast receivers, particularly serializer-deserializer (SerDes) receivers, are critical building blocks for high-speed serial links in networking, computing, and storage applications. As signaling speeds increase, channel loss for the required physical arrival increases, and link tolerance decreases. Therefore, more sophisticated receiver designs are needed to meet given bit error rate (BER) requirements. Consequently, SerDes receivers have evolved from simple boost filters at the input port to complex receivers with advanced equalization structures such as multi-tap feedforward equalizers (FFEs) and decision feedback equalizers (DFEs).

[0024] The move to higher speeds, including the adoption of higher-order coding schemes such as PAM4, leads to more complex receiver architectures and implementations. In some applications, blind adaptation (no-training mode) is used to tune receivers that can typically have up to 40 or 50 operating parameters, resulting in variations between adaptation runs. Accurate link quality measurements and the detection of anomalous links and operating conditions are crucial for ensuring highly reliable operation of systems employing high-speed SerDes inputs.

[0025] Receivers can use measurements of link quality indicators such as limiter signal-to-noise ratio (SNR), bit error rate (BER), and eye margins such as vertical and horizontal eye opening; however, these measurements are inherently variable due to circuit variations (e.g., manufacturing-related variations in transistor dimensions) and adaptive variations (e.g., variations in the calculation of link quality indicators), and are therefore not necessarily sufficient for high-precision link tolerance measurements or robust detection of anomalies such as suboptimal fit.

[0026] For example, a high AGC gain setting can indicate high link attenuation, but it can also be associated with bursts of low logic level symbols. Therefore, a gain setting cannot be used as a reliable indicator of link quality unless supported by other settings. Furthermore, such an indicator does not predict future link quality and typically cannot predict whether a link is trending towards failure or will fail until it is too late to take remedial action to prevent data loss.

[0027] The embodiments disclosed herein provide highly accurate link quality estimates and predictions by analyzing one or more settings of a receiver. In some embodiments, receiver settings are jointly analyzed with one or more parameters of the received signal to produce a desired link quality estimate and / or prediction. In one embodiment, joint analysis of receiver parameters is performed in the time domain to generate a metric predicting the future quality of the link. In other embodiments, machine learning (ML) and sequence detection and classification techniques are used to perform the analysis.

[0028] By predicting that the link quality of a given link is likely to degrade below the minimum required link quality, remedial measures can be taken at the appropriate time to divert some or all data traffic on the deteriorating link to a different link. Conversely, by predicting that the link quality of a given link is likely to exceed a specified link quality metric, data traffic on that link can be increased above a specified maximum capacity to provide increased data carrying capacity for the network.

[0029] In one embodiment, the receiver includes submodules comprising automatic gain control (AGC), a continuous-time linear equalizer (CTLE), an analog-to-digital converter (ADC), a feedforward equalizer (FFE), a decision feedback equalizer (DFE), and a multi-level decoder limiter. The receiver attempts to optimize the settings of the various submodules for better performance (e.g., better signal-to-noise ratio (SNR), wider eyemargin, and better bit error rate (BER)). In one embodiment, the receiver further includes link quality estimation circuitry (LQEC) configured to estimate link quality and / or predict future link quality based on the current and historical settings of the submodules.

[0030] In some embodiments, LQEC includes a machine learning (ML) inference model that uses the current and historical settings of the submodules as input and leverages weights and activation functions preset by the ML training session to estimate and predict future link quality. In one embodiment, a full data transmission path simulation environment is used to generate the ML input. In some embodiments, the simulation environment includes a model of a transmitter, a cable with connectors, and a receiver.

[0031] In an embodiment, when an ML input is generated, a computer (or multiple coupled computers) modifies simulation parameters, including (but not limited to) transmitter phase and gain noise subjected to process voltage-temperature (PVT) variations, transmitter nonlinearity, jitter, cable attenuation, cable crosstalk, cable reflections, and receiver parameters. Receiver setup, signal parameters, and link quality are monitored, and the ML model is then trained to obtain the minimum link quality estimation error. Then, in response to receiver setup and signal parameters, optimized parameters, including weights and activation functions (which in some embodiments may include a history of parameters), can be used to set the parameters of the ML inference model (i.e., LQEC) to accurately estimate and predict link quality.

[0032] In some embodiments, a network device in a distributed system connected to a communication network includes a processor and one or more receivers, each receiver including an LQEC (in embodiments, multiple receivers may share an LQEC). The network device receives data from peer network devices via the network and through receivers coupled to a first input port. When the LQEC predicts that a corresponding link is about to fail (e.g., a predicted link quality measurement will fall below a preset threshold), the processor (also referred to as the "host processor") sends a rerouting message to the peer network device, which can then send further data to a second port (and thus to a second receiver via a second link). If the prediction is early enough, data integrity can be maintained.

[0033] In some embodiments, LQEC generates link quality measurements that can be aggregated and jointly analyzed with link quality measurements from other receivers in the system to generate additional predictive measurements related to system-level tolerances. In these embodiments, machine learning (ML) and deep learning (DL) techniques are used for the joint analysis of link quality measurements from a large number of ports (we will use the term machine learning (ML) below as an inclusive representation of the term deep learning (DL)). In some embodiments, this joint analysis incorporates other system-level measurements besides link quality measurements to enhance the accuracy of the predictions. This particular embodiment of the invention is applicable and valuable for applications utilizing a large number of instances of such high-speed wired receivers.

[0034] Finally, in some embodiments, the bit rate may need to change as link quality changes. In such embodiments, the processor may increase or decrease the receiver data bit rate in response to link quality estimates and predictions.

[0035] In the embodiments described herein, machine learning (ML) and deep learning (DL) techniques are used to reliably estimate and predict link quality in high-speed SerDes receivers.

[0036] Figure 1 This is a block diagram schematically illustrating a high-speed wired receiver 100 with link quality estimation circuitry according to an embodiment described herein. In a non-limiting example embodiment, receiver 100 is part of a deserializer in a port of a network device.

[0037] In one embodiment, receiver 100 includes automatic gain control (AGC) circuitry 102, continuous-time linear equalizer (CTLE) 104, analog-to-digital converter (ADC) 106, feedforward equalizer (FFE) 108, decision feedback equalizer (DFE) 110, high-threshold limiter 112, medium-threshold limiter 114, and low-threshold limiter 116. In other embodiments, fewer signal processing circuits or additional signal processing circuits not discussed herein may be used.

[0038] In this embodiment, AGC 102 is a circuit that automatically sets the gain applied to the input signal. Tutorials on high-speed variable gain amplifiers and automatic gain control circuits can be found in the analog device "High-Speed ​​Variable Gain Amplifier" MT-073 tutorial (Rev.0, 10 / 08).

[0039] The CTLE 104 is a core analog building block for wired receiver front-ends used for signal equalization. An example of an inverter-based CTLE can be found in U.S. Patent Application Publication 2021 / 0288590.

[0040] The ADC 106 converts high-speed input analog signals into a digital representation to allow for more accurate digital processing in other stages. In some embodiments, the ADC 106 includes a flashing ADC that compares the input signal to a plurality of reference voltages.

[0041] FFE 108 and DFE 110 are feedforward equalizer and decision feedback equalizer, respectively; a description of high-speed equalization techniques including FFE and DFE can be found, for example, in A. Suleiman’s MIT master’s thesis, entitled “Model predictive control equalization for high-speed IO Links”, MIT, June 2013.

[0042] In one embodiment, limiters 112, 114, and 116 compare the equalized input signal to three thresholds—DL, DZ, and DH. In Pulse Amplitude Modulation-4 (PAM4), there are four nominal signal levels—V0, V1, V2, and V3. Ideally, DL can be set to the average of V0 and V1; DZ can be set to the average of V1 and V2; and DH can be set to the average of V2 and V3. Therefore, by examining the outputs of the three limiters, the transmitted PAM4 value can be determined. In this embodiment, the limiters continuously change the threshold voltages to adjust for DC variations (including DC noise) in the input signal.

[0043] While some (or all) of the signal processing circuitry, including AGC 102, CTLE 104, ADC 106, FFE 108, and limiters 112, 114, 116, can adjust their respective operating parameters to improve performance, better results can be obtained through system-level parameter optimization. In this embodiment, the wired receiver 100 also includes an adapter control circuitry 117. The adapter control circuitry receives link quality measurements, including BER, and includes quality measurements from some or all of the signal processing circuitry. In response, the adapter control circuitry can set some or all of the operating parameters of the signal processing circuitry (in some embodiments, some signal processing circuitry can set operating parameters in response to instructions sent by the adapter control circuitry and signal quality estimates performed by the signal processing circuitry).

[0044] The high-speed wired receiver 100 also includes a link quality estimation circuit (LQEC) 120, which in one embodiment further includes a parameter history memory 122 for storing receiver parameter history and an ML / deep learning (DL) inference engine 124. In one embodiment, the LQEC is configured to estimate a measurement of link quality and predict future values ​​of the link quality measurement in response to receiver parameters and the history of receiver parameters. In some embodiments, the ML / DL inference engine of the LQEC is a pre-trained inference machine learning (ML) model, and the LQEC outputs a link quality indication in response to the pre-trained inference model parameters (e.g., weights and decision functions) and in response to parameters received by the LQEC ML / DL inference engine from a submodule of the receiver and from the parameter history memory.

[0045] The parameters received by LQEC from the receiver's submodule may include, for example:

[0046] Gain settings for I.AGC 102.

[0047] II. Selected CTLE 104 curve features (e.g., G1 and G2 of CTLE as described in U.S. Patent Application 2021 / 0288590).

[0048] III. Offsets measured at different points along the data path

[0049] IV. ADC 106 offset, full range settings, and limiting ratio.

[0050] Bandwidth, peak value, and adaptation value of V.CDR (Clock and Data Recovery) circuitry

[0051] VI. Threshold voltages (DL, DZ, DH) of limiters 112, 114 and 116.

[0052] VII. Link Bit Error Rate (BER) Measurement (e.g., when link data includes error detection codes).

[0053] VIII. Signal-to-noise ratio (SNR), which can be measured, for example, by limiters 112, 114 and 116.

[0054] IX. Parameters used for adapting the loop in the tuning receiver block.

[0055] In an embodiment, LQEC receives initial ML parameters during initial setup and may receive updated parameters during operation (e.g., if the ML model is trained with additional data including additional operation parameters and operation parameter history).

[0056] In the above text, we were referring to link failure prediction; in the current context, link failure is defined as a link quality measurement falling below a preset threshold.

[0057] In some embodiments, LQEC outputs only a link quality estimate; in other embodiments, LQEC may output a near-future link quality prediction (e.g., the probability of failure within the next 1 millisecond); in one embodiment, LQEC may output link quality measurements that can be aggregated at the system level. As described below, in some embodiments, having an early indication that a link may fail can prevent data loss; conversely, an early indication that the link quality will exceed a preset threshold can be used to increase link bandwidth, thereby optimizing computational performance. In embodiments, link bandwidth can be increased or decreased in response to link quality indications and predictions, as well as other criteria (e.g., queue congestion).

[0058] exist Figure 1 The configuration of receiver 100 shown and described above is referenced by way of example. Other receiver configurations may be used in alternative embodiments. For example, in some embodiments, an NRZ receiver may be used, eliminating the need for three limiters; in one embodiment, FFE 108 is analog (and therefore connected between CTLE 104 and ADC 106); in another embodiment, the ADC may be absent, resulting in a fully analog implementation of the equalization function.

[0059] In some embodiments, an ML model is trained to estimate and predict link quality measurements in response to parameters (static and / or historical) of the high-speed wired receiver 100. Training data for the ML model is obtained through simulation.

[0060] Figure 2 This is a block diagram schematically illustrating the configuration of a data transmission simulation environment 200 for simulating a receiver link, based on embodiments described herein, which generates input data for a link quality estimation ML model. The simulation model 200 can be written, for example, in a high-level programming language such as C / C++, Python, Matlab, and includes a transmitter model 202, a link model 204, and a receiver model 206.

[0061] The data transmission simulation model 200 includes a software model of the communication path. In an embodiment, the data transmission simulation simulates the process from transmitting data to receiver 100 (…). Figure 1 The transmitter connects to the reference via a typical link (including cables and connectors) modeled by link model 204. Figure 1 The described receiver structure matches the complete path of the receiver model. The simulation operation is managed by the simulation control software (SCSW) 208 and executed by the computer 210.

[0062] To generate a set of ML training data, SCSW typically inputs a random data sequence into the transmitter model input (e.g., communication packets with random payloads); in response, the transmitter model generates an output signal that is input into the link model. The link model applies a link transfer function to the transmitter output and sends the resulting signal to the receiver model.

[0063] In the embodiments, SCSW modifies the parameters of the communication path model in multiple simulations to simulate possible variations in a real communication path. For example, in the transmitter model, SCSW can add phase, gain, and offset errors, as well as various transmitter-level nonlinearities. In the link model, SCSW can change the link's frequency response to represent various cable lengths, fluctuate cable parameters (e.g., attenuation and characteristic impedance) to represent aging, bending, temperature, etc., add a return signal to simulate mismatched termination, and add line-to-line crosstalk. In the receiver model, SCSW can change the process voltage-temperature (PVT), add noise, and add crosstalk.

[0064] SCSW monitors various receiver parameters, as well as measurements indicating link quality corresponding to different receiver parameters such as SNR and BER. The monitored parameters can then be used to train an ML model.

[0065] exist Figure 2 The structure of the data transmission simulation environment 200 shown and described above is an example cited for conceptual clarity. Other structures may be used in alternative embodiments. For example, in some embodiments, the simulation may be guided by an ML-trained model, thereby emphasizing the low variability in prediction accuracy against the ML model.

[0066] Figure 3 This is a block diagram illustrating a link quality estimation (ML) training environment 300 for generating ML parameters for a link quality estimation circuit, according to embodiments described herein. The ML training environment includes a machine learning prediction model 302, an input feature set 304, a training data input set 306, and a comparator 308. Training is managed by a computer 310.

[0067] In one embodiment, the machine learning prediction model 302 is a multi-layer deep learning model trained to predict link quality by adjusting the weights and activation functions of at least some nodes in the ML model. In this embodiment, the machine learning prediction model 302 can be, for example, an autoregressive deep learning model, or any other suitable machine learning or deep learning model (for an autoregressive context, see, for example, "Deep autoregressive Networks," K. Gregor et al. A1, Proceedings of the 31st International Conference on Machine Learning, Beijing, China, 2014).

[0068] The input feature set 304 is typically derived from simulations (e.g., using...) Figure 2 The data transmission simulation environment (200) generates an input list. Inputs may include device PVT and receiver parameters such as AGC gain (see reference). Figure 1 (A list of LQEC inputs described).

[0069] Comparator 308 is configured to compare the link quality predicted by the machine learning prediction model with the actual link quality (e.g., SNR and BER) calculated during simulation, and feed the error gradient back to the machine learning prediction model; the machine learning prediction model can then modify its model parameters to minimize the error.

[0070] In one embodiment, a machine learning prediction model attempts to predict link failures within a preset time (e.g., 1 ms); comparator 308 compares the future value of the link quality with the predicted link quality, such that the difference represents the error in the prediction of the future link quality.

[0071] exist Figure 3 The configuration of the ML training environment 300 shown and described above is an example cited for conceptual clarity only. Other configurations may be used in alternative embodiments. For example, in some embodiments, other link quality measurements, such as lost synchronization signals generated by clock data recovery (CDR) circuitry, may be used.

[0072] Figure 4 The waveform diagram 400 schematically illustrates fault prediction via LQEC according to the embodiments described herein. Figure 4 The graph shown indicates that LQEC monitors a set of receiver parameters, including digital parameter A 402 and analog parameter B 404.

[0073] In some cases, examining receiver parameters (potentially in combination with signal parameters) over time can reveal trends indicative of future link quality. LQEC outputs predictions of current link quality and future link quality. According to... Figure 4 As a simplified example, LQEC's predictions are limited to the probability of a link failing within a preset time interval (e.g., 1ms).

[0074] Curve 406 represents the fault prediction from the LQEC output, expressed as a percentage. Curve 408 represents the link quality, expressed as the bit error rate (BER), on a logarithmic scale. As can be observed, the link quality is initially good, with a score of 10. －10 Up to 10 －8 The error rate continues until a link fails at some point and the BER rises sharply to 10. －0(Errors exist in all bits). (The BER number cited above is just an example; in reality, the acceptable error rate varies depending on the application and the error control coding scheme applied.)

[0075] When LQEC is properly trained, link failures can be predicted by monitoring and tracking the trajectory of receiver parameters. As can be observed, based on... Figure 4 In the example embodiment shown, LQEC predicts that the network will fail with approximately 75% confidence before the link fails. As described below, the processor can use this "early warning" to take appropriate measures to ensure data integrity.

[0076] exist Figure 4 The waveform 400 shown and described above is an example cited for conceptual clarity only. Other waveforms may represent alternative embodiments. For example, in some embodiments, BER is also the input to LQEC, improving prediction accuracy.

[0077] In this embodiment, the processor can receive a link quality prediction and take appropriate measurements. The following will refer to... Figure 5A , Figure 5B and 6 Two embodiments are discussed. The embodiments relate to network devices connected to peer network devices via a communication network.

[0078] Figure 5A This is a block diagram illustrating a distributed system 500 with a master routing path, based on embodiments described herein. The distributed system 500 may, for example, be a distributed computing system.

[0079] Data sink 502 receives data from data source 504 via communication network 506. Data sink 502 and data source 504 can be, for example, network devices configured to interface with a communication network. Network 506 can be, for example, Ethernet or InfiniBand. TM Or any other suitable communication network.

[0080] The data sink includes a processor 508 configured to perform computational tasks; the processor is coupled to a network 506 via a first ingress port 510 and a second ingress port 512. Data from the data source to the data sink via network 506 traverses to the first ingress port 510 via a main path 514, and from the ingress port to the processor. Ingress ports 510 and 512 include machine learning-based inference circuitry for predicting link quality, such as... Figure 1 The LQEC circuit 120, and each input port outputs a Link Quality Prediction (LQP) signal to the processor. (Path 514 should not be confused with the link described above - path 514 may include multiple switching nodes, and the link described above is the last lag in the path.)

[0081] according to Figure 5A In the example embodiment shown, the LQEC at ingress port 510 predicts an impending input link failure. As described above, the LQEC has been trained to predict link failures in response to parameters from the ingress port receiver; therefore, the processor receives a link failure indication before an actual link failure occurs. In response to the failure prediction, the processor can send a message to the data source (e.g., via network 506) requesting the data source to reroute other data sent from the data source to the data sink.

[0082] Figure 5B This is a block diagram schematically illustrating a distributed system 550 with a secondary routing path selected in response to low link quality prediction, according to an embodiment described herein. Distributed system 550 is identical to distributed system 500, except that it uses a different path between data source 504 and data sink 502. When data source 504 receives a rerouting message from the data sink, the data source sends additional data to the same destination address but to a different destination port. The network then reroutes the additional data to ingress port 512 via secondary path 552. Because link failure prediction occurs before actual link failure, data integrity can be maintained.

[0083] exist Figure 5A The configurations of the distributed systems 500 and 550 shown in Figure 5B and described above are examples cited for conceptual clarity. Other configurations may be used in alternative embodiments. For example, in some embodiments, when link quality degrades, the link may cease transmitting PAM4 data, but NRZ may still be used. In response to link failure prediction, processor 508 will signal to the data source that NRZ should be used for further data transmission. If LQEC prediction still fails, the processor may request rerouting.

[0084] Figure 6 This is a block diagram schematically illustrating a network device 600 configured to optimize communication performance in response to link quality prediction according to embodiments described herein. Network device 600 includes a processor 602 coupled to one or more ingress ports 604. Some (or all) of the ingress ports may include LQEC and output link quality measurements and / or link failure predictions. In one embodiment, processor 600 is at the system level; the processor aggregates LQEC measurements from all ports along with other system-level quality measurements to generate system-level and port-level quality measurements.

[0085] System-level quality measurements are sometimes referred to as "system health measurements" or "system-level health metrics." In one embodiment, a processor calculates system-level health measurements for a network system (e.g., network devices) or a portion of the network system. The processor can then manage service allocation based on these calculated system-level health measurements.

[0086] In some embodiments, link quality can be improved when the transmission rate is reduced. According to Figure 6 In the illustrated example embodiment, network device 602 is configured to control the data input rate by signaling congestion status to peer network devices, which in turn reduce their transmission rates in response. When an ingress port indicates poor (or is predicted to decrease) link quality to processor 602, the processor can control the ingress port to reduce its bandwidth (which in turn results in sending congestion notifications to peer network devices and a corresponding reduction in communication bandwidth). If the link quality is good, the processor can control the corresponding ingress port to increase the data rate (in this embodiment, peer network devices can increase their transmission rates even without congestion notifications). Therefore, in this embodiment, the network device can use link quality indicators and predictions to optimize communication bandwidth.

[0087] Figure 6 The configuration of the network device 600 shown and described above is referenced as an example. Other suitable configurations may be used in alternative embodiments. For example, in some embodiments, the processor sets the bandwidth of the ingress port (rather than controlling the increase and decrease of bandwidth).

[0088] Figure 7A This is a flowchart 700 according to an embodiment described herein, which schematically illustrates a method for generating ML-based link quality estimation and prediction models. This flowchart is executed by a computer (which may be a multiprocessor computing system in the embodiment).

[0089] The flowchart begins with operation 702, which builds a simulation model, where a computer-based environment is constructed to simulate the target data path, including the high-speed wired transmitter (Tx), the link, and the high-speed wired receiver (Rx) (see above for reference). Figure 2 (Example simulation model described).

[0090] Next, in simulation operation 704, the computer runs multiple simulations on the simulation model under various conditions, including: i) random input mode; ii) signal distortion in the transmitter (e.g., phase noise, gain noise, nonlinear distortion); iii) changing link conditions (e.g., gain and phase response); iv) crosstalk noise; v) PVT variation in the receiver; and vi) random additional noise. The computer monitors BER, SNR, and receiver parameters.

[0091] At operation 706 in training the ML model, the computer uses, for example, an autoregression mechanism to train the ML model, applies the monitored simulated values, and attempts to find a set of weights and activation functions that minimizes the prediction error (see above). Figure 3 (Describes the training process).

[0092] Next, at inference model generation 708, the computer generates the inference model to be implemented in the receivers, including all weights and activation functions. In some embodiments, the inference model runs on a low-power inference processor embedded in each receiver; in other embodiments, a system-level CPU aggregates measurements from multiple receiver instantiations and runs the inference model. In embodiments, the inference model can be improved "in-situ" at weight update operation 710, where the computer runs further simulations with newly acquired data (e.g., if some or all network cables are replaced with a new type).

[0093] Therefore, according to Figure 7A The example method shown and described above, in order to avoid data loss (and in one embodiment, to increase total communication capacity), can use a set of parameters derived from a full communication path simulation with varying conditions to build and train an ML link quality estimator / predictor.

[0094] exist Figure 7A The configuration of flowchart 700 shown and described above is referenced as an example. Other configurations may be used in alternative embodiments. For example, in some embodiments, the simulation may be adjusted to favor conditions with high prediction errors; for example, if the prediction error is high at high receiver temperatures, more simulations may be run at high receiver temperatures.

[0095] Figure 7B This is a flowchart 720 schematically illustrating a method for estimating and predicting link quality according to embodiments described herein. This flowchart is based on LQEC 120 (…). Figure 1 The continuous loop is executed. During the monitoring of Rx parameters in operation 722, LQEC monitors various receiver parameters (see above for reference). Figure 1 (A list of examples describing the parameters of the monitored receiver).

[0096] Next, in the history storage operation 723, LQEC stores the history of the RX parameters. In various embodiments, the depth of the stored history can be preset individually for each parameter. In one embodiment, link quality estimation and prediction require the history of the parameters as well as the parameters themselves.

[0097] Then, in the ML inference model running operation 724, LQEC runs the ML inference model on the monitored receiver parameters (and, in this embodiment, on the history of the parameters), applying preset weights and activation functions. Then, in the link quality estimation sending operation 726, LQEC sends the link quality estimate (e.g., to the processor); and, in the link quality prediction sending operation 728, sends the predicted link quality. After operation 728, LQEC loops back to operation 722.

[0098] exist Figure 7BThe configuration of flowchart 720 shown and described above is an example cited for conceptual clarity. Other configurations may be used in alternative embodiments. For example, in one embodiment, all or some operations may be performed simultaneously; in another embodiment, link quality prediction includes predictions of various delays, including predictions of no delay (and in this case, operation 726 may be skipped).

[0099] In other embodiments, LQEC outputs only the link quality prediction and not the current link quality (the processor can estimate the link quality by observing the BER).

[0100] Figure 7C This is flowchart 740 according to an embodiment described herein, which schematically illustrates a method for improving the performance of a network device by utilizing link quality estimation and link quality prediction. The flowchart is generated by a processor (e.g., Figure 6 The processor 602) executes.

[0101] The flowchart begins with receiving link quality and link quality prediction operation 742, where the processor receives link quality and link quality predictions belonging to one or more ingress ports. Next, at initiating input rerouting operation 744, the processor may, in response to the link quality estimation and prediction and according to preset rerouting criteria, initiate routing of ingress data to different (unused) ingress ports (see reference). Figure 5A 5B, the rerouting mechanism is described above.

[0102] The processor then enters bandwidth reduction operation 746, wherein the processor may respond to a low link quality estimate or low link quality prediction and reduce the bandwidth of the ingress port according to a preset bandwidth reduction criterion. In embodiments, the processor may use one or more techniques to reduce bandwidth, including, for example, redirecting some services to other links, changing the coding scheme (e.g., from PAM4 to NRZ), etc.

[0103] Finally, in the bandwidth increase operation 748, the processor can respond to a high link quality estimate or a high link quality prediction and increase bandwidth according to a preset standard (see above). Figure 6 It describes bandwidth reduction and bandwidth increase to increase the bandwidth of the ingress port.

[0104] exist Figure 7C The configuration shown in and described above in flowchart 740 is referenced as an example. Other suitable configurations may be used in alternative embodiments. For example, in some configurations, rerouting is only performed if reducing bandwidth fails to significantly alter link failure prediction.

[0105] The configuration of receiver 100 includes: LEQC 120; configuration of simulation environment 200, training environment 300, distributed system 500, and network device 600; the methods in flowcharts 700, 720, and 740 are illustrative configurations and methods shown for clarity of concept only. Any other suitable configurations and methods may be used in alternative embodiments.

[0106] In various embodiments, the various ML training, ML inference, and network device element tasks described above can be performed by hardware, software, or a combination of hardware and software.

[0107] In various embodiments, the LQEC120 can be implemented using appropriate hardware, such as one or more application-specific integrated circuits (ASICs) or field-programmable gate arrays (FPGAs), or a combination of ASICs and FPGAs.

[0108] Processors 508 and 602, computer 210, and computer 310, or any and all thereof, typically include one or more general-purpose processors that are software-programmed to perform the functions described herein. For example, software may be downloaded to the processor electronically via a network, or alternatively or additionally, the software may be provided and / or stored on a non-transient tangible medium such as magnetic, optical, or electronic memory.

[0109] Although the embodiments described herein are primarily directed to link quality estimation and prediction in high-speed wired receivers, the methods and systems described herein can also be used in other wired communication applications that utilize adaptive equalizer receivers to recover transmitted messages, such as automotive applications, computing applications utilizing the PCIe / CXL link layer; and, by analogy, are applicable to wireless applications.

[0110] Therefore, it should be noted that the above embodiments are cited by way of example, and the invention is not limited to what has been specifically shown and described above. Rather, the scope of the invention includes combinations and sub-combinations of the various features described above, as well as variations and modifications thereof that would occur to those skilled in the art upon reading the foregoing description and which are not disclosed in the prior art. Documents incorporated herein by reference are considered an integral part of this application, and the definitions in this specification should be considered only to the extent that any terms defined in these incorporated documents conflict with the explicit or implicit definitions in this specification.

Claims

1. An apparatus for use in a network device, the apparatus comprising: A receiver is configured to receive signals on a link and process the received signals; as well as The Link Quality Estimation Circuit (LQEC) is configured to run a pre-trained machine learning (ML) model that predicts a link quality measurement indicating the probability that the link will fail within a future time interval of a predetermined length. The pre-trained ML model predicts the link quality measurement by analyzing at least one or more settings of the receiver's circuitry and is configured to initiate a response action based on the predicted link quality measurement.

2. The apparatus of claim 1, wherein the LQEC is configured to initiate the response action by initiating a redirection of at least part of subsequent communication from the link to another link.

3. The apparatus of claim 1, wherein by analyzing the settings of the circuitry of the receiver over time, the LQEC is configured to predict future values ​​or trends of the link quality measurement, and the LQEC is configured to initiate the response action based on the predicted future values ​​or trends.

4. The apparatus of claim 1, wherein the LQEC is configured to predict the link quality measurement by jointly analyzing (i) one or more settings of the circuitry of the receiver and (ii) one or more parameters of the received signal.

5. The apparatus of claim 1, wherein the LQEC is configured to initiate the response action by initiating a reduction in the data rate of the signal.

6. The apparatus of claim 1, wherein the LQEC is configured to initiate the response action by initiating a change to the encoding scheme used to encode the signal.

7. The apparatus of claim 1, wherein the LQEC is configured to predict the link quality measurement by analyzing at least one setting of the circuitry of the receiver over time, said at least one setting being selected from: Gain of the clock data recovery (CDR) circuit; The bandwidth of the CDR circuit; The response of a simulated equalization filter; Setting up the analog-to-digital converter (ADC); The tap values ​​of a digital equalizer; Automatic gain control (AGC) settings; as well as Limiter threshold.

8. The apparatus of claim 1, wherein the receiver is disposed in the deserializer.

9. A method for use in a network device, the method comprising: Use a receiver to receive signals on the link and process the received signals; Running a pre-trained machine learning (ML) model that predicts a link quality measurement indicating the probability that the link will fail within a future time interval of a predetermined length, wherein the pre-trained ML model predicts the link quality measurement by analyzing at least one or more settings of the receiver's circuitry. as well as Initiate a response action based on the predicted link quality measurement.

10. The method of claim 9, wherein initiating the response action comprises: Initiate a redirection of subsequent communication from the said link to another link, at least in part.

11. The method of claim 9, wherein analyzing the settings of the circuitry of the receiver over time includes predicting future values ​​or trends of the link quality measurement, and wherein initiating the response action is performed based on the predicted future values ​​or trends.

12. The method of claim 9, wherein predicting the link quality measurement comprises: The analysis combines (i) one or more settings of the circuitry of the receiver, and (ii) one or more parameters of the received signal.

13. The method of claim 9, wherein initiating the response action comprises: The data rate of the signal is reduced.

14. The method of claim 9, wherein initiating the response action comprises: Initiate a change to the encoding scheme used to encode the signal.

15. The method of claim 9, wherein predicting the link quality measurement includes analyzing at least one setting of the receiver's circuitry over time, said at least one setting being selected from: Gain of the clock data recovery (CDR) circuit; The bandwidth of the CDR circuit; The response of a simulated equalization filter; Setting up the analog-to-digital converter (ADC); The tap values ​​of a digital equalizer; Automatic gain control (AGC) settings; as well as Limiter threshold.

16. The method of claim 9, wherein the receiver is disposed in the deserializer.

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