Address verification for memory devices

Abstract

This application relates to address verification for memory devices. When a memory device receives a write command, the memory device can store an indication of a write address associated with the write command in association with the data written. When the memory device receives a read command, the memory device can retrieve data and a previously stored write address associated with the retrieved data, and the memory device can verify a read address associated with the read command against the previously stored write address associated with the retrieved data. Thus, for example, the memory device can verify that data read from the memory array based on an address associated with a read command is data that was written in response to a write command associated with a matching address when the memory array was previously written.

Description

[0001] Cross-references

[0002] This patent application is the national phase application of International Patent Application No. PCT / US2020 / 061247, filed November 19, 2020, entitled “ADDRESS VERIFICATION FOR A MEMORY DEVICE”, filed by Boehm et al., which claims priority to U.S. Patent Application No. 17 / 098,096, filed December 13, 2020, entitled “ADDRESS VERIFICATION FOR A MEMORY DEVICE”, filed by Boehm et al., which claims priority to U.S. Provisional Patent Application No. 62 / 951,517, filed December 20, 2019, entitled “ADDRESS VERIFICATION FOR AMEMORY DEVICE”; each of these applications is assigned to the assignee, and each of these applications is incorporated herein by reference in its entirety. Technical Field

[0003] This technical field relates to address verification of memory devices. Background Technology

[0004] The following text generally refers to one or more memory systems, and more specifically, to address verification of memory devices.

[0005] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, and digital displays. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed to support one of two states, often represented by logic 1 or logic 0. In some instances, a single memory cell can support more than two states, any of which can be stored. To access the stored information, a component can read or sense at least one stored state in the memory device. To store information, a component can write states into the memory device or program states.

[0006] Various types of memory devices and memory cells exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), auto-select memory, and chalcogenide memory technology. Memory cells can be volatile or non-volatile. Non-volatile memory, such as FeRAM, can maintain its stored logic state for a long time, even without external power. Volatile memory devices, such as DRAM, may lose their stored state when disconnected from external power. Summary of the Invention

[0007] Describe a method. The method may include: at a memory device including an array of memory cells, receiving a command to write data to an address within the array; writing the data to the array at least in part based on the command; and writing an indication of the address to the array at least in part based on the command.

[0008] Describe an apparatus. The apparatus may include: a memory cell array; a command component for receiving write commands and read commands associated with addresses within the array; and a verification component coupled to the array and the command component, the verification component being configured to: in response to a write command for data, write an indication of an address associated with the write command for the data into the array; and in response to a read command for the data, receive from the array the indication of the address associated with the write command for the data.

[0009] Describe a method. The method may include: at a memory device including an array of memory cells, receiving a second command to read data from the array, the second command being associated with a second address within the array; reading the data from the array based at least in part on the second command and the second address; reading a first indication from the array based at least in part on the second command on a first address within the array, the first address being associated with a first command to write the data to the array; and transmitting the data and a second indication of whether the second address matches the first address, based at least in part on the second command. Attached Figure Description

[0010] Figure 1 Examples of systems that support address verification of memory devices according to the examples disclosed herein are shown.

[0011] Figure 2Examples of memory dies that support address verification of memory devices according to the examples disclosed herein are shown.

[0012] Figure 3 Examples of memory devices that support address verification according to the examples disclosed herein are shown.

[0013] Figure 4 A block diagram illustrating an example disclosed herein shows a storage scheme for write address indication at a memory device that supports address verification.

[0014] Figure 5 A block diagram of a memory device supporting address verification of the memory device according to aspects of this disclosure is shown.

[0015] Figures 6 to 8 A flowchart illustrating an example disclosed herein demonstrates one or more methods for supporting address verification of memory devices. Detailed Implementation

[0016] Memory devices can operate as part of electronic devices under various conditions, such as personal computers, wireless communication devices, servers, Internet of Things (IoT) devices, and electronic components of motor vehicles. In some cases, the reliability constraints of memory devices supporting certain implementations (e.g., motor vehicles, in some cases having autonomous or semi-autonomous driving capabilities) may increase. Therefore, memory devices used in some applications (e.g., DRAM) are expected to operate with reliability subject to relatively high industry standards (e.g., higher reliability constraints). For other applications, improving the reliability of memory devices may still be beneficial.

[0017] Some memory systems incorporate error detection techniques that focus on whether data includes correct logical values ​​(e.g., correct bit values). Such error detection techniques can detect whether data is corrupted during transmission between the host device and the memory device (e.g., due to misunderstanding or loss of one or more bit values) or while stored in the memory array (e.g., due to incorrect writing, maintenance, or reading of the state of one or more memory cells). However, it is possible for valid data (e.g., uncorrupted data) to be written to or read from incorrect addresses within the memory array. For example, some error detection techniques may fail to detect errors if an address is incorrectly decoded at the memory device, or if an error occurs at a row decoder, column decoder, or other internal component within the memory device (e.g., a decoder activates an incorrect access line). Even if the data is valid (e.g., no transmission or storage errors exist), errors can still occur in this case due to the transmission of erroneous data between the host device and the memory array (e.g., reading data from an incorrect location in the memory array, or reading data from a correct (expected) location but after an erroneous write to that location). Failure to detect such address and location-related errors can adversely affect the reliability of the system.

[0018] As described herein, a memory system can be configured to determine whether data read from a location within a memory array (e.g., a location identified by an address within the array) is data previously correctly written to that location (e.g., whether reading data from a location in the memory array implies that the location was previously written to). For example, when a memory device receives a write command, an indication of the address associated with the write command (e.g., a logical or physical address associated with the data constrained by the write command, which may be referred to as the write address) can be stored in a portion of the memory array designated for storing copies of the write address. For example, the indication of the write address may include the write address, a subset of the write addresses, parity information based on part or all of the write addresses, or any combination thereof. Furthermore, any number of copies of such indications can be stored, where in some cases, multiple copies provide redundancy and associated reliability advantages (e.g., two or more copies of the write address may be stored). The indication of the write address can be stored in the memory array and associated with the relevant data (e.g., within the same row or page as the data written in response to the write command).

[0019] When a memory device reads data in response to a read command, it can verify the write address previously stored in association with the retrieved data relative to the read address associated with the read command. That is, for example, the memory device can receive an address associated with a read command (e.g., a logical or physical address associated with the data constrained by the read command, which may be referred to as the read address), retrieve data from the memory array based on the read address (e.g., from the location corresponding to the read address), and also retrieve from the memory array an indication of a write address previously stored in association with the retrieved data (e.g., in the same row as the retrieved data, in the same page as the retrieved data). The memory device can then compare the indication of the retrieved write address with a similar indication of the read address (e.g., a similar indication of the read address can be calculated, generated, or otherwise obtained to support a one-to-one comparison with the indication of the retrieved write address). Typically, as an example, the technique described herein may be referred to as Address Data Copy Verification (ADCV).

[0020] By verifying the read address associated with a read command and a previously received write address associated with data retrieved in response to the read command (e.g., comparing their indications), a memory system can determine whether data read from an address within the array (e.g., data associated with the read command) is data previously intended to be written to that address. Such address verification can improve the reliability of a memory device or a memory system containing said memory device. Furthermore, in some cases, a portion of the memory array (e.g., one or more subarrays of the array, a subset of columns of the array or subarrays) can be designated for (e.g., dedicated to) indicating the storage write address, and address verification can be performed using existing memory (e.g., without increasing the overall array size or die size).

[0021] First, as referenced Figure 1 and 2 The features of this disclosure are described in the context of a memory system die. (See references...) Figure 3-5 Features of this disclosure are described in the context of the circuit and device diagrams described herein. Further details are provided by reference to, for example, [reference 2]. Figure 6-8 The device diagrams and flowcharts relating to address verification of the memory device described herein illustrate and describe these and other features of the present disclosure with reference to the device diagrams and flowcharts.

[0022] Figure 1An example of a system 100 supporting address verification of a memory device according to the examples disclosed herein is shown. System 100 may include a host device 105, a memory device 110, and a plurality of channels 115 coupling the host device 105 to the memory device 110. System 100 may include one or more memory devices 110, but aspects of the one or more memory devices 110 may be described in the context of a single memory device (e.g., memory device 110).

[0023] System 100 may include portions of electronic devices such as computing devices, mobile computing devices, wireless devices, graphics processing devices, vehicles, or other systems. For example, system 100 may represent aspects of computers, laptops, tablets, smartphones, cellular phones, wearable devices, networked devices, vehicle controllers, etc. Memory device 110 may be a component of the system for storing data for one or more other components of system 100.

[0024] At least a portion of system 100 may be an example of host device 105. Host device 105 may be an example of a processor or other circuitry within a device that uses memory to execute processes, such as in a computing device, mobile computing device, wireless device, graphics processing device, computer, laptop computer, tablet computer, smartphone, cellular phone, wearable device, internet-connected device, vehicle controller, or other fixed or portable electronic device, and other examples. In some examples, host device 105 may refer to the hardware, firmware, software, or a combination thereof that implements the functions of external memory controller 120. In some examples, external memory controller 120 may be referred to as a host or host device 105.

[0025] Memory device 110 may be a separate device or component for providing physical memory address / space that can be used or referenced by system 100. In some instances, memory device 110 may be configurable to work with one or more different types of host devices. Signaling between host device 105 and memory device 110 may be used to support one or more of the following: modulation schemes for modulating signals, various pin configurations for transmitting signals, various form factors for the physical packages of host device 105 and memory device 110, clock signaling and synchronization between host device 105 and memory device 110, timing conventions, or other factors.

[0026] Memory device 110 may be used to store data for components of host device 105. In some instances, memory device 110 may act as a slave device to host device 105 (e.g., responding to and executing commands provided by host device 105 via external memory controller 120). Such commands may include one or more of write commands for write operations, read commands for read operations, refresh commands for refresh operations, or other commands.

[0027] The host device 105 may include one or more of the following: an external memory controller 120, a processor 125, a basic input / output system (BIOS) component 130, or other components such as one or more peripheral components or one or more input / output controllers. The components of the host device may be coupled to each other using bus 135.

[0028] Processor 125 may be used to provide control or other functions for at least a portion of system 100 or at least a portion of host device 105. Processor 125 may be a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or combinations thereof. In such instances, processor 125 may be an instance of a central processing unit (CPU), graphics processing unit (GPU), general-purpose GPU (GPGPU), or system-on-a-chip (SoC), as well as other instances. In some instances, external memory controller 120 may be implemented by processor 125 or be part of said processor.

[0029] BIOS component 130 may be a software component containing a BIOS operating as firmware, which can initialize and run various hardware components of system 100 or host device 105. BIOS component 130 may also manage data flow between processor 125 and various components of system 100 or host device 105. BIOS component 130 may contain programs or software stored in one or more of read-only memory (ROM), flash memory, or other non-volatile memory.

[0030] Memory device 110 may include a device memory controller 155 and one or more memory dies 160 (e.g., memory chips) to support a desired or specified capacity for data storage. Each memory die 160 may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, and / or local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, and / or memory array 170-N). Memory array 170 may be a collection of memory cells (e.g., one or more grids, one or more memory banks, one or more tiles, one or more segments), wherein each memory cell is used to store at least one bit of data. Memory device 110 containing two or more memory dies may be referred to as a multi-die memory or multi-die package, or a multi-chip memory or multi-chip package. In some instances, memory array 170 may include one or more subarrays (e.g., reference...). Figure 3 (As described). At least one subarray can be configured to store a copy of the address associated with a write command (e.g., a write address). The stored copy of the address can be compared with the data subject to a read command.

[0031] The device memory controller 155 may include circuitry, logic, or components for controlling the operation of the memory device 110. The device memory controller 155 may include hardware, firmware, or instructions that enable the memory device 110 to perform various operations, and may be used to receive, transmit, or execute commands, data, or control information related to components of the memory device 110. The device memory controller 155 may be used to communicate with one or more of an external memory controller 120, one or more memory dies 160, or a processor 125. In some instances, the device memory controller 155 may control the operation of the memory device 110 described herein in conjunction with a local memory controller 165 of the memory die 160.

[0032] In some instances, memory device 110 may receive data or commands, or both, from host device 105. For example, memory device 110 may receive a write command instructing memory device 110 to store data for host device 105 or a read command instructing memory device 110 to provide data stored in memory die 160 to host device 105. As described herein, a copy of the address associated with the write command (e.g., the write address) may be stored in a portion of memory array 170. The stored copy of the address can be compared with the data subject to the read command, which improves the reliability of the memory system.

[0033] A local memory controller 165 (e.g., local to memory die 160) can be used to control the operation of memory die 160. In some instances, the local memory controller 165 can be used to communicate with the device memory controller 155 (e.g., to receive or transmit data or commands, or both). In some instances, memory device 110 may not include a device memory controller 155 and a local memory controller 165 or an external memory controller 120 capable of performing the various functions described herein. Thus, the local memory controller 165 can be used to communicate with the device memory controller 155, with other local memory controllers 165, or directly with the external memory controller 120 or the processor 125, or combinations thereof. Examples of components that may be included in the device memory controller 155 or the local memory controller 165 or both may include a receiver for receiving signals (e.g., from the external memory controller 120), a transmitter for transmitting signals (e.g., to the external memory controller 120), a decoder for decoding or demodulating the received signals, an encoder for encoding or modulating the signals to be transmitted, or various other circuitry or controllers for supporting the operation of the described device memory controller 155 or the local memory controller 165 or both.

[0034] External memory controller 120 can be used to enable the transfer of one or more of information, data, or commands between components of system 100 or host device 105 (e.g., processor 125) and memory device 110. External memory controller 120 can translate or interpret communications exchanged between components of host device 105 and memory device 110. In some instances, external memory controller 120 or other components of system 100 or host device 105, or the functionality described herein, may be implemented by processor 125. For example, external memory controller 120 may be hardware, firmware, or software, or a combination thereof, implemented by processor 125 or other components of system 100 or host device 105. Although external memory controller 120 is depicted as external to memory device 110, in some instances, external memory controller 120 or the functionality described herein may be implemented by one or more components of memory device 110 (e.g., device memory controller 155, local memory controller 165), or vice versa.

[0035] Components of host device 105 may exchange information with memory device 110 using one or more channels 115. Channels 115 may be used to support communication between external memory controller 120 and memory device 110. Each channel 115 may be an example of a transmission medium carrying information between host device 105 and memory device. Each channel 115 may contain one or more signal paths or transmission media (e.g., conductors) between terminals associated with components of system 100. Signal paths may be examples of conductive paths operable to carry signals. For example, channel 115 may include a first terminal comprising one or more pins or pads at host device 105 and one or more pins or pads at memory device 110. Pins may be examples of conductive input or output points of devices of system 100, and pins may be used to serve as portions of channels.

[0036] Channel 115 (and associated signal paths and terminals) may be dedicated to transmitting one or more types of information. For example, channel 115 may include one or more command and address (CA) channels 186, one or more clock signal (CK) channels 188, one or more data (DQ) channels 190, one or more other channels 192, or combinations thereof. In some instances, information may be transmitted via channel 115 using single data rate (SDR) signaling or double data rate (DDR) signaling. In SDR signaling, one modulation symbol (e.g., signal level) of the signal may be registered for each clock cycle (e.g., on the rising or falling edge of the clock signal). In DDR signaling, two modulation symbols (e.g., signal levels) of the signal may be registered for each clock cycle (e.g., on both the rising and falling edges of the clock signal).

[0037] Memory device 110 may be configured to determine whether data read from a location within memory array 170 is data correctly written to said location in response to a previous write command. As discussed herein, memory device 110 may receive write commands from host device 105. When memory device 110 receives a write command, it may store an indication of the address associated with the write command (e.g., an indication of the write address) in a portion of memory array 170. Memory device 110 may also receive read commands from host device 105. In response to a read command, memory device 110 may verify a read address associated with the read command against an indication of the write address associated with data stored in memory array 170 at the location corresponding to the read address. If the address (e.g., its indication) matches or is otherwise determined not to indicate an error condition, the read data may be output by memory device 110. In some instances, if the address (e.g., its indication) does not match, memory device 110 may notify host device 105 of the address mismatch (e.g., by outputting an error flag or by storing an error flag for host device 105 to poll later). If the address does not match, the memory device 110 may or may not output the read data; if the address matches, the memory device may or may not notify the host device 105, depending on the implementation. This address verification can improve the reliability of the memory device 110.

[0038] Figure 2 An example of a memory die 200 supporting address verification of a memory device is shown according to the examples disclosed herein. The memory die 200 may be a reference. Figure 1 Examples of memory die 160 described herein. In some instances, memory die 200 may be referred to as a memory chip, memory device, or electronic memory device. Memory die 200 may include one or more memory cells 205, each of which may be programmed to store different logical states (e.g., programmed to be one of a set of two or more possible states). For example, memory cell 205 may be operable to store one bit of information at a time (e.g., logic 0 or logic 1). In some instances, memory cell 205 (e.g., multi-level memory cell) may be used to store more than one bit of information at a time (e.g., logic 00, logic 01, logic 10, logic 11). In some instances, memory cells 205 may be arranged in an array, as shown in the reference. Figure 1 The memory array 170 is described.

[0039] Memory cell 205 can store charge representing a programmable state in a capacitor. A DRAM architecture may include a capacitor containing a dielectric material to store charge representing a programmable state. Other memory devices and components are also possible in other memory architectures. For example, a nonlinear dielectric material may be used. Memory cell 205 may include logic storage components, such as capacitor 230 and switching component 235. Capacitor 230 may be an example of a dielectric capacitor or a ferroelectric capacitor. Nodes of capacitor 230 may be coupled to a voltage source 240, which may be, for example, a cell board reference voltage Vpl, or ground, for example, Vss.

[0040] The memory die 200 may include one or more access lines (e.g., one or more word lines 210 and one or more digital lines 215) arranged in a pattern, such as a grid pattern. Access lines may be wires coupled to memory cells 205 and may be used to perform access operations on memory cells 205. In some instances, word lines 210 may be referred to as row lines. In some instances, digital lines 215 may be referred to as column lines or bit lines. References to access lines, row lines, column lines, word lines, digital lines, or bit lines, or the like, may be interchanged without affecting understanding or operation. Memory cells 205 may be located at the intersection of word lines 210 and digital lines 215.

[0041] Memory cell 205 can be accessed, for example, by activating or selecting one or more access lines, such as word line 210 or digital line 215. A single memory cell 205 can be accessed at its intersection by biasing word line 210 and digital line 215 (e.g., by applying a voltage to word line 210 or digital line 215). The intersection of word line 210 and digital line 215, arranged in a two-dimensional or three-dimensional configuration, can be referred to as the address of memory cell 205.

[0042] Access to memory cell 205 can be controlled via row decoder 220 or column decoder 225. For example, row decoder 220 can receive a row address from local memory controller 260 and activate word line 210 based on the received row address. Column decoder 225 can receive a column address from local memory controller 260 and activate digital line 215 based on the received column address. In some instances, memory die 200 can receive write commands (e.g., from a host device). Row decoder 220 and column decoder 225 can decode the write address and store the associated data in one or more memory cells 205. A copy of the write address can be stored in a portion of memory die 200. When memory die 200 receives a read command for data associated with the stored write address, the address associated with the read command (e.g., the read address) can be compared with the stored write address. If the addresses match, data can be read from memory die 200.

[0043] Selecting or deselecting memory cell 205 can be achieved by activating or deactivating activation switch assembly 235 using word line 210. Capacitor 230 can be coupled to digital line 215 using switch assembly 235. For example, capacitor 230 can be isolated from digital line 215 when switch assembly 235 is deactivated, and can be coupled to digital line 215 when switch assembly 235 is activated.

[0044] Sensing component 245 can be used to detect the state (e.g., charge) stored on capacitor 230 of memory cell 205 and determine the logic state of memory cell 205 based on (e.g., using) the stored state. Sensing component 245 may include one or more sensing amplifiers to amplify or additionally convert signals generated by accessing memory cell 205. Sensing component 245 can compare the signal detected from memory cell 205 with reference 250 (e.g., reference voltage). The detected logic state of memory cell 205 can be provided as an output of sensing component 245 (e.g., to input / output component 255) and can indicate the detected logic state to another component of the memory device including memory die 200.

[0045] The local memory controller 260 can control access to the memory cell 205 through various components (e.g., row decoder 220, column decoder 225, sensing component 245). The local memory controller 260 can be a reference. Figure 1An example of a local memory controller 165 is described. In some instances, one or more of the row decoder 220, column decoder 225, and sensing component 245 may be located in the same position as the local memory controller 260. The local memory controller 260 may be used to receive one or more commands or data from one or more different memory controllers (e.g., an external memory controller 120 associated with host device 105, another controller associated with memory die 200), translate the commands or data (or both) into information usable by memory die 200, perform one or more operations on memory die 200, and transfer data from memory die 200 to host device 105 based on the performance of said one or more operations. The local memory controller 260 may generate row and column address signals to activate target word line 210 and target digital line 215.

[0046] The local memory controller 260 can also generate and control various voltages or currents used during the operation of the memory die 200. Generally, the amplitude, shape, or duration of the applied voltage or current discussed herein can be adjusted or varied, and can differ for the various operations discussed in operating the memory die 200.

[0047] The local memory controller 260 can be used to perform one or more access operations on one or more memory cells 205 of the memory die 200. Examples of access operations may include write operations, read operations, refresh operations, precharge operations, or activation operations, etc. The local memory controller 260 can also be used to perform other access operations not listed herein or other operations related to the operation of the memory die 200 that are not directly related to accessing the memory cells 205.

[0048] The memory die 200 can be configured to determine whether data read from one or more memory cells 205 is the same data previously associated with write commands to those same memory cells 205. As discussed herein, when a write command is received for the memory die 200, the row decoder 220 and column decoder 225 can decode the associated address and activate one or more appropriate word lines 210 and bit lines 215 to write data to one or more memory cells 205 corresponding to the write address associated with the write command. Furthermore, an indication of the write address can be stored in a portion of the memory die 200 so that when a read command is subsequently received that causes access to the same memory cells 205, the previously stored indication of the write address can be verified against the read address associated with the read command. Verifying that data read from the array is correctly written to the address of the read data improves the reliability of the memory die 200.

[0049] Figure 3An example of a memory device 300 supporting address verification according to the examples disclosed herein is shown. The memory device 300 may include references herein. Figure 1 and 2 One or more components are described. For example, memory device 300 may include line decoder 330 (which may be a reference). Figure 2 The described row decoder 220 (an instance) and column decoder 335 (which may be a reference) Figure 2 (Example of column decoder 225 described). Memory device 300 may also include memory array 305, command component 325, verification component 340, output component 360, and mode register 365. In some instances, verification component 340 may include write address component 345, read address component 350, and comparison component 355. Verification component 340 may be configured to verify a read address associated with a read command for data by comparing it to a write address associated with a previously received write command for memory array 305. By verifying the read and write addresses associated with data read from memory array 305, memory device 300 can determine, based on the write address matching the read address, whether data read from the array (e.g., data read in response to a read command associated with the read address) has previously been written to memory array 305, which can improve the reliability of memory device 300.

[0050] Memory array 305 may contain multiple memory cells. The memory cells of memory array 305 may be organized into groups from which data can be read or written simultaneously (e.g., in response to a single access command), and these groups may be referred to as pages (e.g., memory cell pages, data pages). For example, memory cells having memory array 305 may be arranged in rows and columns, and each row of memory cells may correspond to a different page. In some instances, memory array 305 may also be divided into any number of subarrays 315. For example, different subsets of columns may correspond to different subarrays 315. In some cases, each subarray 315 may be coupled to a sensing component 310 (e.g., to one or more corresponding sensing amplifiers within sensing component 310), the sensing component being as referenced... Figure 2 Examples of the described sensing component 245. For example, a memory array may contain 2,048 columns of memory cells, which are divided into eight (8) subarrays 315, each containing 256 columns. It should be understood that these and other specific figures used herein are purely for illustrative purposes and are not limiting.

[0051] A portion 380 of memory array 305 may be dedicated to storing indications of write addresses. For example, a subset of columns of memory array 305 or subarray 315 may be dedicated to storing indications of write addresses. Within a row of memory cells, memory cells within portion 380 may be used to store indications of write addresses associated with data stored in other memory cells of that row. In some cases, portion 380 may be a subset of columns of memory array 305. Alternatively, in some cases, portion 380 may include one or more subarrays 315 (e.g., such as...). Figure 3 As shown in the example, portion 380 corresponds to subarray 315-a), but it should be understood that the boundaries of portion 380 do not need to be aligned with the boundaries of subarray 315. When portion 380 corresponds to one or more subarrays 315, the page size of the applied data can be reduced accordingly, for example, in... Figure 3 In one example, memory array 305 may support a page size of 2,048 bits (e.g., due to having 2,048 columns), but when address verification is enabled and portion 380 corresponds to subarray 315-a, the page size of the application data can be reduced to 1,792 bits. In some cases, different subsets of columns (or other cell groups) within portion 380 may correspond to different subarrays 315 (e.g., within portion 380, a first subset of columns may be used to store an indication of a write address associated with subarray 315-b, a first subset of columns may be used to store an indication of a write address associated with subarray 315-c, etc.).

[0052] Memory array 305 may be coupled to command component 325 via row decoder 330 and / or column decoder 335. In some instances, command component 325 may communicate with a host device (not shown) to receive write or read commands to memory array 305. For example, command component 325 may receive commands from the host device containing instructions for an access operation (e.g., read, refresh, write) at memory array 305. The commands may also include or otherwise indicate the address of memory array 305 to which the access operation is directed. The address may include, for example, row addresses and column addresses corresponding to one or more rows and columns of memory array 305. Memory device 300 may utilize verification component 340 to determine (e.g., identify, detect) errors associated with the transmission, decoding, or execution of commands received from the host device. In some cases, determining errors can improve the reliability of memory device 300. For example, memory device 300 can ensure that data is written to or read from the correct address.

[0053] The memory device 300 can utilize the verification component 340 to ensure that data is written to or read from the correct address. For example, when the command component 325 receives a write command for the memory array 305, the write address component 345 can receive a write address or its indication from the command component 325, and the write address component 345 can store (e.g., write) the indication of the write address in portion 380. The stored indication of the write address can be stored in association with the data corresponding to the write command (e.g., stored in the same page). For example, data can be stored in a portion (or portions of multiple rows) of a row within the memory array 305 (e.g., at least in part based on the operation of the row decoder 330, column decoder 335, or sensing component 310, or any combination thereof), and the indication of the associated write address can be stored in some or all of the remaining portion (or the remaining portion of multiple rows) of the row within portion 380.

[0054] When command component 325 receives a read command for data stored in memory array 305, it can read the data from memory array 305 (e.g., based at least in part on the operation of row decoder 330, column decoder 335, or sensing component 310, or any combination thereof), and read address component 350 can receive an indication of the read address associated with the read command from command component 325. It can also read an indication of a write address previously associated with read data stored in portion 380 (e.g., based at least in part on the operation of row decoder 330, column decoder 335, or sensing component 310, or any combination thereof) from memory array 305, and read address component 350 can receive (e.g., from sensing component 310) a previously stored write address indication.

[0055] In some instances, when data is read from memory array 305 in response to a read command, comparison component 355 may compare (i) an indication of a write address retrieved from portion 380 based on the data stored in association with the read command with (ii) a similar indication of a read address associated with the read command. This verification may indicate whether the two indications match, and thus whether the data read in response to the read command was read from the location where the data associated with the matching write address was previously written (and thus whether the read command and the previous write command were executed at the correct location in memory array 305). For example, comparison component 355 may receive an indication of the retrieved write address from read address component 350, and comparison component 355 may receive a read address from command component 325 and generate its appropriate indication (or receive an indication from command component 325). The indication of the write address may include a copy of the write address, a copy of a subset of the write addresses, parity information based on the write address, or any combination thereof; therefore, a similar indication of the read address may include a copy of the read address, a copy of a subset of the read addresses, parity information based on the read address, or any combination thereof.

[0056] If comparison component 355 determines (e.g., based on comparison association indication) that (i) the read address associated with the read command and (ii) the write address associated with the data retrieved from memory array 305 match, then comparison component 355 can identify an address error that is not associated with the data. If comparison component 355 determines (e.g., based on comparison association indication) that (i) the read address associated with the read command and (ii) the write address associated with the data retrieved from memory array 305 do not match, then comparison component 355 can identify an address error that is associated with the data.

[0057] If an address error is associated with the read command, the comparison component 355 can indicate the address error to an external device (e.g., host device 105). For example, the comparison component 355 can send an address error indication to the output component 360, which in turn can indicate the address error to the external device. Alternatively, the comparison component 355 can update the mode register 365 to include the address error indication (e.g., for subsequent polling by the external device, for error logging, or for performance tracing). When the read data is associated with an address error, the output component 360 may or may not output the read data to the external device, depending on the implementation.

[0058] If there is no address error associated with the read command, the comparison component 355 can indicate to the output component 360 that there is no (non-existent) address error, which can then output the read data to an external device (e.g., host device 105). When the read data is not associated with an address error, the output component 360 may or may not indicate that there is no address error, and the comparison component 355 may or may not update the mode register 365, depending on the implementation.

[0059] In some instances, address verification is not performed internally. The memory device may output one or more pieces of low-level information (e.g., one or more indications of previously stored write addresses) in response to a read command (and data read from memory array 305 based on the read command), and an external device, such as a host device, may perform address verification (e.g., it may receive information as described herein received by verification component 340 and perform one or more operations attributed herein to verification component 340). In such instances, output component 360 may output verification-supporting information to an external device.

[0060] As previously stated, the indication of a write address can be a copy of the write address, a copy of a subset of the write addresses, or based on some or all of the parity information in the write address, or any combination thereof. In some cases, data can be addressed and accessed (e.g., written and read) on a per-subarray 315 basis. In some such cases, portions of memory cell rows within different subarrays 315 can be operated independently and can be referred to as subrows or subpages.

[0061] For example, the write address of a single subpage of data can contain a finite number of address bits, such as twenty-eight (28) bits. Therefore, the write address received by command component 325 can contain a number of bits that are multiples of the number of subarrays. For example, shelving portion 380 can allow memory array 305 to have seven (7) subarrays for storing data (also referred to as operational data or application data). In such an example, the write address received by command component 325 can contain 196 bits. Therefore, if the write instruction is a complete copy of the write address, write address component 345 can store a copy of the write address (e.g., 196 bits) into portion 380 of memory array 305.

[0062] In other instances where the write instruction is a copy of a subset of the write address, the write address component 345 may store a copy of the write address subset into a portion 380 of the memory array 305. For example, the write address of a single subpage of data may contain a finite number of bits, such as twenty-eight (28) bits, and the stored subset may contain nine (9) most significant bits and nine (9) least significant bits per subpage address, so the total number of bits per subpage address is eighteen (18) bits, and the total is 126 bits, so the write address component 345 may store a copy (e.g., 126 bits) of the write address subset into a portion 380 of the memory array 305.

[0063] In some instances, multiple copies of the write address indication can be stored in section 380, which can provide enhanced reliability or other benefits. For example, as described in the previous example, if a 126-bit subset of the write address is stored as its indication, two copies (thus a total of 252 bits) can be stored in section 380. Furthermore, as a substitute for or supplement to some or all of the bits of the write address, the write address indication can include parity information (one or more parity bits) calculated based on some or all of the bits of the write address. The read address component 350 can process the bits of the read address to obtain its indication using the same algorithm used by the write address component 345 to obtain the write address indication, thereby supporting one-to-one comparisons performed by the comparison component 355.

[0064] Multiple copies of the write address indication are stored in one instance of section 380. Comparison component 355 can compare the stored copies before comparing any copy with the corresponding indication of the read address. If the stored copies of the write address indication match, comparison component 355 can compare any copy with the corresponding indication of the read address to determine if an address error exists. If not all the stored copies of the write address indication match each other, such indications can be output to an external device (e.g., a host device) or stored in mode register 365 via output component 360. For example, the number of stored copies of the write address indications that match or do not match the corresponding indication of the read address can be indicated to provide a confidence indication of the existence of an address error (e.g., a potential address error). Such a confidence indication can be provided in lieu of or supplement a binary (e.g., yes / no) indication of the existence of an address error (e.g., a binary indication could indicate the existence of an address error if any one or more of the stored indications of the write address do not match the corresponding indication of the read address).

[0065] Multiple copies of the write address indication are stored in another instance within section 380, and comparison component 355 can compare each stored copy with a corresponding indication of the read address (e.g., in parallel to gain a latency advantage). If any stored copy of the write address indication does not match the corresponding indication of the read address, such an indication can be output to an external device (e.g., a host device) or stored in mode register 365 via output component 360. For example, the number of stored copies of the write address indication that match or do not match the corresponding indication of the read address can be indicated, thereby providing a confidence indication regarding the presence of an address error (e.g., the presence of a potential address error). Such a confidence indication can be provided in lieu of or supplement a binary (e.g., yes / no) indication regarding the presence of an address error (e.g., a binary indication could indicate the presence of an address error if any one or more stored indications of the write address do not match the corresponding indication of the read address).

[0066] Multiple copies of the write address indication are stored in another instance within section 380, and comparison component 355 can sequentially compare each stored copy with a corresponding indication of the read address (e.g., comparing the stored copies one after another with the corresponding indication of the read address). In some cases, subsequent comparisons can be skipped once one of the stored indications of the write address does not match the corresponding indication of the read address (e.g., to gain a latency advantage). Alternatively, the number of stored copies of the write address indication that match or do not match the corresponding indication of the read address can be indicated, thereby providing a confidence indication regarding the presence of an address error (e.g., the presence of a potential address error). Such a confidence indication can be provided instead of or supplement a binary (e.g., yes / no) indication regarding the presence of an address error (e.g., a binary indication could indicate the presence of an address error if any one or more of the stored indications of the write address do not match the corresponding indication of the read address).

[0067] In some cases, the write address indication may contain some or all of the bits of the write address, and parity information based thereon may be stored in association within section 380 (e.g., on the same page or in the same row). In this case, in response to a read command, comparison component 355 may perform parity checking on the retrieved write address indication based on the associated stored parity information. In such cases, even if all one or more stored and retrieved write address indications and corresponding read address indications match, a potential address error may be indicated if the parity check identifies a parity error between the stored parity information and the newly calculated parity information of the indicated write address.

[0068] It should be understood that any indication of an address error or potential address error as described herein may be output by output component 360 to an external device (e.g., a host device) and may additionally or alternatively be stored in mode register 365 (e.g., for subsequent polling by the external device, or for error logging or performance tracking). Furthermore, the operations (e.g., comparisons) and indications described herein may be at the level of memory array 305, subarray 315, or have any other granularity (e.g., different indications of write addresses may be stored and subsequently evaluated on a per-row, per-subrow, or other basis).

[0069] In some cases, whether to enable and use address verification, and thus whether to store instructions for writing addresses and related information in section 380, or whether to use section 380 instead to store other data, and therefore the total amount of data contained in a page, can be based on the settings of mode register 365 (e.g., the contents of fields).

[0070] Figure 4 Block diagram 400, illustrating an example disclosed herein, shows a storage scheme for write address indication at a memory device supporting address verification. Block diagram 400 may show multiple subarrays 415 to 415-g within a memory array 405. Subarrays 415 and memory array 405 may be as described in reference... Figure 3 Examples of subarray 315 and memory array 305 are discussed. The block diagram may also show a verification dataset 410, which may contain one or more indications of write addresses and possibly other verification-related data. In some cases, verification dataset 410 may correspond to a data page (e.g., a row), and verification dataset 410 may contain multiple subsets 420. Each subset 420 may contain one or more verification data bits corresponding to data stored in a corresponding subpage (e.g., a subpage, such as a subrow). For example, subset 420-a may contain one or more verification data bits corresponding to data stored in a subrow within subarray 415-a, subset 420-b may contain one or more verification data bits corresponding to data stored in a subrow within subarray 415-b, and so on, where each of the subrows is located in the same row of memory array 405. Verification dataset 410 or its subset 420 may contain indications of write addresses as described herein.

[0071] For reference Figure 3 As described, a portion of the memory array 305 can be configured to store data, and another portion 380 of the memory array 305 can be configured to store a verification dataset 410. The verification dataset 410 can be stored for each write command received by the memory device and its associated dataset. For example, as... Figure 4As shown, for illustrative purposes only, the memory array may comprise eight (8) subarrays 415, and seven (7) subarrays 415 may be configured to store data, while one (1) subarray 415 or a portion thereof may be configured to store a verification dataset 410. For example, subarray 415 may be configured to store a verification dataset 410, and subarrays 415-a to 415-g may be configured to store data (e.g., as portions of pages or rows within the memory array 405 that correspond to the corresponding verification dataset 410). For example, subarray 415 may correspond to, as referenced in [reference] Figure 3 The portion 380 is described. In other instances (not shown), portion 380 may include any number of different subarrays 415, any other set of one or more columns within memory array 305, or a portion or all of any other grouping of memory cells within memory array 305. Furthermore, in some cases, different columns or other subsets of memory cells having subarrays 415 may be configured to store different subsets 420 associated with data stored in the respective subarrays 415.

[0072] In some cases, each subset 420 may contain at least one indication of a subpage write address for writing data to a subarray associated with subset 420 (e.g., where the write address of a page (e.g., a row) includes a subpage write address for each subpage (e.g., a subrow) within the page). As an example, each subpage write address may contain a number of address bits (e.g., 28 bits), and in response to a write command for a subrow within one of subarrays 415-a to 415-g, some or all of the subpage write address bits may be stored in subarray 415 as part of the corresponding subset 420. In some instances, the number of most significant bits and the number of least significant bits of each subpage address in subarray 415 may be included in the indication of the subpage write address. For example, nine (9) most significant bits and nine (9) least significant bits of each subpage write address may be included in the indication of the subpage write address, such that each subset 420 contains at least eighteen (18) bits. If each subset 420 contains an 18-bit indication of the subpage write address, then in Figure 4 In the example, the validation dataset 410 can contain at least 126 bits because there are seven subarrays 415-a to 415-g used to store data, so there are seven subsets 420 in the validation dataset 410.

[0073] Furthermore, in some cases, as described herein, multiple copies of each indication of a subpage write address can be stored as part of the verification dataset 410. For example, if each indication of a subpage write address contains eighteen (18) bits as shown in the example above, and each subset 420 contains two copies of the indication of the subpage write address of the associated subarray 415, then in Figure 4In this instance, the validation dataset 410 can contain at least 252 bits.

[0074] In some instances, each subset 420 may contain one or more parity bits associated with a subpage write address or data subpage of the corresponding subarray 415. For example, the memory device may support an internal error correction or detection process to correct or detect errors associated with the transmission or storage of data; this may be referred to as an Error Correction Code (ECC) process. In some cases, the ECC process may be Single Error Correction (SEC) or Single Error Correction and Double Error Detection (SECDED). Some SEC schemes may use a fixed number of parity bits for each data bit group of a specific size (e.g., 8 parity bits for each 128 data bit group). Some SECDED schemes may use an additional bit for each such group (e.g., a 9th parity bit for each 128 data bit group), and said additional bit may be referred to as a DED bit. The DED bit indicates whether the mismatch between two evaluated bit sets is odd or even (e.g., allowing the SEC parity bit to be used to detect and correct single-bit (odd-numbered) errors but not double-bit (even-numbered) errors, thus avoiding aliasing of third bits and unintentional three-bit errors). For example, the DED bit can be computed by performing an XOR operation on all bits in the associated group. In some cases, the memory device can compute the DED bit internally based on the bit group written to the memory array, or the memory device can receive the DED bit for the bit group (e.g., as part of an ECC scheme, the host device can transmit the DED bit in association with the bit group to detect transmission errors associated with transmitting the bit group to the memory device for writing to the memory array).

[0075] As an example, each subset 420 may contain one or more DED bits, each DED bit being used to write the corresponding bit group of the subarray 415 associated with subset 420. For example, each subarray 415 may be 256 column wide, and therefore each data subpage may contain 256 bits (e.g., 256 memory cells stored in a subrow). DED bits may be computed for each 128-bit group within a subpage, and therefore each subpage may be associated with two (2) DED bits, so each subset 420 may contain two (2) DED bits. In some cases, redundant copies of DED bits may be included in subset 420, for example, each DED bit may be stored in triplicate in portion 380 (as an example of a redundancy factor), so each subset 420 may contain six (6) DED bits. Therefore, 42 DED bits, and thus at least 42 parity bits, can be stored in subarray 415 (six (6) DED bits per subpage of application data) in association with the application data pages written in response to a write command. In some cases, storing DED bits in the memory array may be referred to as internal double-bit error detection (ISDD).

[0076] In some cases, the number of bits included in each indication of the write address may depend on other information contained in the verification dataset 410 (if any) (e.g., based on a portion 380 of the memory array and a fixed number of memory cells contained in the row portions therein). For example, the number of bits included in each indication of the write address may be adjusted depending on whether other verification schemes are enabled and therefore whether some memory cells in portion 380 can be used for other purposes. As an example, if both ISDD and ADCV are enabled, each indication of the subpage write address may be reduced from eighteen (18) bits to fourteen (14) bits, for example, from nine (9) MSBs and nine (9) LSBs to seven (7) MSBs and seven (7) LSBs. Therefore, in Figure 4 In the example, if each indication of the subpage write address is stored repeatedly, the verification dataset 410 can contain 196 bits (fourteen (14) bits per subarray 415 multiplied by seven (7) subarrays 415 multiplied by two (2)), which can accommodate 42 DED bits within subarray 415 as described above (e.g., because 196 plus 42 is less than 256).

[0077] In some cases, whether ADCV, ISDD, or both are enabled may depend on one or more settings in the mode register (e.g., mode register 365). In one case, certain verification schemes, such as ADCV and ISDD, may be enabled or disabled simultaneously based on a single setting in the mode register (e.g., a single field, a single bit).

[0078] Figure 5A block diagram 500 illustrates a memory device 505 supporting address verification of the memory device according to aspects of this disclosure. The memory device 505 may be as shown in reference... Figure 3 and 4 Examples of aspects of the described memory device. Memory device 505 may include a write component 510, a receive component 515, a receive component 520, a read component 525, a determine component 530, and a transmit component 535. Each of these modules may communicate with each other directly or indirectly (e.g., via one or more buses).

[0079] The receiving component 520 can receive a command at a memory device containing an array of memory cells to write data to an address within the array. The writing component 510 can write data to the array based on the command. In some instances, the writing component 510 can write an address indication to the array based on the command.

[0080] In some instances, receiving component 520 may receive a second command to read data from the array, the second command being associated with a second address within the array. In some instances, reading component 525 may read data from the array and an address indication based on the received second command. In some instances, transmitting component 535 may transmit signaling to the host device of the memory device based on the data and address indication.

[0081] Determining component 530 can determine whether a second address matches an address based on an address indication, wherein signaling indicates data and whether the second address matches an address. In some instances, writing component 510 can write an indication that the second address and the first address do not match to a mode register at the memory device. In some instances, signaling indicates data and the first address.

[0082] In some instances, write component 510 can write data to the first portion of a memory cell page within the array. In some instances, write component 510 can write an address to the second portion of the page.

[0083] In some instances, a page address contains memory cells associated with the same row address. In some instances, a memory cell page contains memory cells within multiple subarrays, with a first portion of the page within a first subarray and a second portion of the page within a second subarray.

[0084] In some instances, the address contains multiple bits, and the address indication contains at least a subset of the multiple bits. In some instances, the address contains multiple bits, and one or more parity bits can be calculated based on the multiple bits, wherein the address indication contains one or more parity bits.

[0085] In some instances, the write component 510 can write a copy of the address indication to the array based on a command.

[0086] In some instances, receiving component 520 may receive a second command to read data from the array, the second command being associated with a second address within the array. In some instances, reading component 525 may read data, an address indication, and a copy of the address indication based on the second command. In some instances, determining component 530 may determine whether the second address corresponds to at least one of the address indication or a copy of the address indication. Transmitting component 535 may transmit signaling indicating data and the validity of the data to a host device of the memory device, the validity of the data being based on whether the second address corresponds to at least one of the address indication or a copy of the address indication.

[0087] The receiving component 520 may receive a second command to read data from the array at a memory device comprising an array of memory cells, the second command being associated with a second address within the array. The reading component 525 may read data from the array based on the second command and the second address. In some instances, the reading component 525 may read an indication of a first address within the array based on the second command, the first address being associated with a first command to write data to the memory array. In some instances, the transmitting component 535 may transmit data based on the second command and an indication of whether the second address matches the first address.

[0088] In some instances, a memory cell row corresponding to a second address can be accessed, where data is read from the first part of the row and the indication of the first address is retrieved from the second part of the row.

[0089] In some instances, receiving component 520 may receive the first command at the memory device before receiving the second command. In some instances, writing component 510 may write data to the array based on the first address and the instruction from the first address to the array, based on the receipt of the first command.

[0090] In some instances, the reading component 525 can read a second indication of the first address based on a second command. In some instances, the determining component 530 can determine whether a second address matches a first address based on the indication of the first address and the second indication of the first address.

[0091] In some instances, the indication of the first address includes one or more bits contained in the first address, or parity information of the first address, or any combination thereof.

[0092] Figure 6A flowchart illustrating aspects of this disclosure shows one or more methods 600 supporting address verification of a memory device. Operation of method 600 can be implemented by the memory device or its components described herein. For example, operation of method 600 can be performed by, as referenced... Figure 5 The described memory device is used for execution. In some instances, the memory device may execute a set of instructions to control the functional elements of the memory device to perform the described function. Alternatively, the memory device may use dedicated hardware to perform aspects of the described function.

[0093] At 605, the memory device may receive a command at a memory device containing an array of memory cells to write data to an address within the array. The operation of 605 may be performed according to the method described herein. In some instances, aspects of the operation of 605 may be as described in references... Figure 5 The described receiving component is used for execution.

[0094] In 610, the memory device can write data to the array based on commands. The operation of 610 can be performed according to the methods described herein. In some instances, aspects of the operation of 610 may be as described in the references... Figure 5 The description is written to the component for execution.

[0095] In 615, the memory device can write an address indication to the array based on a command. The operation of 615 can be performed according to the methods described herein. In some instances, aspects of the operation of 615 can be as described in the references... Figure 5 The description is written to the component for execution.

[0096] In some instances, the device described herein can perform one or more methods, such as method 600. The device may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: receiving a command at a memory device comprising an array of memory cells to write data to an address within the array; writing data to the array based on the command; and writing an indication of the address to the array based on the command.

[0097] Some examples of the method 600 and apparatus described herein may further include operations, features, means, or instructions for: receiving a second command to read data from an array, the second command being associated with a second address within the array; an indication to read data and an address from the array based on receiving the second command; and transmitting signaling to a host device of the memory device based on the indication of data and address.

[0098] Some examples of the method 600 and device described herein may further include operations, features, means, or instructions for determining whether a second address matches an address based on an address indication, wherein signaling indicates data and whether the second address matches an address.

[0099] Some instances of the method 600 and device described herein may further include operations, features, means, or instructions for writing a second address and a second indication that do not match at the memory device into a mode register.

[0100] In some instances of the method 600 and device described herein, signaling indicates data and address.

[0101] In some instances of the method 600 and apparatus described herein, writing instructions for data and addresses to an array may include operations, features, means, or instructions for writing data to a first portion of a memory cell page within the array and writing addresses to a second portion of the memory cell page.

[0102] In some instances of the method 600 and device described herein, a memory cell page contains memory cells associated with the same row address.

[0103] In some instances of the method 600 and apparatus described herein, a memory cell page contains memory cells within a subarray set, a first portion of the page may be within a first subarray of the subarray set, and a second portion of the page may be within a second subarray of the subarray set.

[0104] In some instances of the method 600 and device described herein, the address contains a set of bits, and the indication of the address contains at least one subset of the set of bits.

[0105] In some instances of the method 600 and apparatus described herein, the address may contain operations, features, means, or instructions for: calculating one or more parity bits based on a bit set, wherein the indication of the address contains one or more parity bits.

[0106] Some instances of the method 600 and device described herein may further include operations, features, means, or instructions for writing a copy of the address indication (e.g., a second copy) to an array based on a command.

[0107] Some examples of the method 600 and apparatus described herein may further include operations, features, means, or instructions for: receiving a second command to read data from an array, the second command being associated with a second address within the array; reading data, an indication of the address, and a copy of the address indication based on the second command; determining whether the second address corresponds to at least one of the address indication or a copy of the address indication; and transmitting signaling indicating data and the validity of the data to a host device of the memory device, the validity of the data being based on whether the second address corresponds to at least one of the address indication or a copy of the address indication.

[0108] Figure 7A flowchart illustrating an aspect of this disclosure shows one or more methods 700 supporting address verification of a memory device. Operation of method 700 may be implemented by a memory device or its components as described herein. For example, operation of method 700 may be performed by, as referenced... Figure 5 The described memory device is used for execution. In some instances, the memory device may execute a set of instructions to control the functional elements of the memory device to perform the described function. Alternatively, the memory device may use dedicated hardware to perform aspects of the described function.

[0109] At 705, the memory device may receive a command to write data to an address within the array at a memory device comprising an array of memory cells. The operation of 705 may be performed according to the method described herein. In some instances, aspects of the operation of 705 may be as described in references... Figure 5 The described receiving component is used for execution.

[0110] In 710, the memory device can write data to the array based on commands. The operation of 710 can be performed according to the methods described herein. In some instances, aspects of the operation of 710 may be as described in the references... Figure 5 The description is written to the component for execution.

[0111] In 715, the memory device can write an address indication to the array based on a command. The operation of 715 can be performed according to the methods described herein. In some instances, aspects of the operation of 715 can be derived from, as referenced... Figure 5 The description is written to the component for execution.

[0112] At 720, the memory device can receive a second command to read data from the array, the second command being associated with a second address within the array. The operation of 720 can be performed according to the methods described herein. In some instances, aspects of the operation of 720 may be as described in references... Figure 5 The described receiving component is used for execution.

[0113] In 725, the memory device can read data and addresses from the array based on an instruction received from a second command. The operation of 725 can be performed according to the method described herein. In some instances, aspects of the operation of 725 can be as described in references... Figure 5 The described read component is used for execution.

[0114] In 730, the memory device can transmit signaling to the host device of the memory device based on data and address instructions. The operation of 730 can be performed according to the methods described herein. In some instances, aspects of the operation of 730 can be derived from, as referenced... Figure 5 The described transport component is used to perform this.

[0115] Figure 8A flowchart illustrating an aspect of this disclosure shows one or more methods 800 supporting address verification of a memory device. Operation of method 800 may be implemented by the memory device or its components described herein. For example, operation of method 800 may be performed by, as referenced... Figure 5 The described memory device is used for execution. In some instances, the memory device may execute a set of instructions to control the functional elements of the memory device to perform the described function. Alternatively, the memory device may use dedicated hardware to perform aspects of the described function.

[0116] At 805, the memory device may receive a second command at a memory device comprising an array of memory cells to read data from the array, the second command being associated with a second address within the array. Operation of 805 may be performed according to the methods described herein. In some instances, aspects of operation of 805 may be as described in references... Figure 5 The described receiving component is used for execution.

[0117] In 810, the memory device can read data from the array based on a second command and a second address. The operation of 810 can be performed according to the methods described herein. In some instances, aspects of the operation of 810 can be derived from, as referenced... Figure 5 The described read component is used for execution.

[0118] In 815, the memory device can read a first indication of a first address within the array based on a second command, the first address being associated with a first command to write data to the array. The operation of 815 can be performed according to the methods described herein. In some instances, aspects of the operation of 815 may be as described in references... Figure 5 The described read component is used for execution.

[0119] In 820, the memory device can transfer data based on a second command and a second indication of whether the second address matches the first address. The operation of 820 can be performed according to the method described herein. In some instances, aspects of the operation of 820 can be as described in references... Figure 5 The described transport component is used to perform this.

[0120] In some instances, the device described herein can perform one or more methods, such as method 800. The device may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: receiving, at a memory device comprising an array of memory cells, a second command to read data from the array, the second command being associated with a second address within the array; reading data from the array based on the second command and the second address; a first indication to read a first address within the array based on the second command, the first address being associated with a first command to write data to the array; and a second indication to transfer data based on the second command and whether the second address matches the first address.

[0121] Some examples of the 800 and device described herein may further include operations, features, means, or instructions for: accessing a memory cell row corresponding to a second address based on a second command, wherein data is read from a first portion of the memory cell row, and a first indication of the first address is retrieved from a second portion of the memory cell row.

[0122] Some examples of the 800 and device described herein may further include operations, features, means, or instructions for: receiving a first command at a memory device prior to receiving a second command; and writing data to an array based on a first address and a first instruction to the array based on the first address, upon receiving the first command.

[0123] Some examples of the 800 and device described herein may further include operations, features, means, or instructions for: reading a third indication of a first address based on a second command; and determining whether a second address matches a first address based on the first indication and the third indication of the first address.

[0124] In some instances of the 800 and device described herein, the first indication of the first address includes one or more bits contained in the first address, or parity information of the first address, or any combination thereof.

[0125] It should be noted that the methods described above describe possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more parts from the methods can be combined.

[0126] Describe an apparatus. The apparatus may include a memory cell array; a command component for receiving write commands and read commands associated with addresses within the array; and a verification component coupled to the array and the command component, the verification component being configured to: write an indication of an address associated with a write command to the array in response to a write command for data; and receive an indication of an address associated with a write command for data from the array in response to a read command for data.

[0127] In some instances, the verification component may be further used to: determine, based on an address indication, whether a second address associated with a read command matches an address associated with a write command; and to transmit a second indication to the host device of the device regarding whether the second address associated with the read command matches an address associated with a write command.

[0128] In some instances, the verification component may be further configured to: store a copy of the indication of the address associated with the write command to the array in response to a write command for data; receive a copy of the indication of the address associated with the write command from the array in response to a read command for data; and determine that the second address associated with the read command and the address associated with the write command match when the second address associated with the read command corresponds to at least one of the indication of the address associated with the write command or the copy of the indication of the address associated with the write command.

[0129] Some instances of the device may include a mode register coupled to a verification component, wherein the verification component may further be used to store an erroneous third indication in the mode register when a second address associated with a read command and an address associated with a write command do not match.

[0130] Some instances of the device may include an output component coupled to an authentication component and used to transmit signals to the outside of the device, wherein the authentication component may further be used to transmit to the output component an indication of an address associated with a write command to data.

[0131] Some instances of the device may include a decoding component for writing data to a first portion of a memory cell page within the array in response to a write command, wherein a verification component may be used to write an indication of an address associated with the write command to a second portion of the memory cell page.

[0132] In some instances, the address associated with the write command contains a set of bits; and the indication of the address associated with the write command contains at least one subset of the set of bits.

[0133] In some instances, the address indication associated with the write command includes parity information for the address.

[0134] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some diagrams may illustrate signaling as a single signal; however, those skilled in the art will understand that a signal can represent a bus of signals, where the bus can have various bit widths.

[0135] The terms "electronic connectivity," "conductive contact," "connection," and "coupling" can refer to a relationship between components that supports the flow of electrons between them. Components are considered electronically connected (or electrically contacting, connected, or coupled) to each other if any conductive path exists between them that can support the flow of signals between them at any given time. At any given time, the conductive path between components that are electronically connected (or electrically contacting, connected, or coupled) can be open or closed, depending on the operation of the device containing the connected components. The conductive path between connected components can be a direct conductive path between the components, or it can be an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some instances, one or more intermediate components, such as switches or transistors, can be used to interrupt the signal flow between connected components for a period of time.

[0136] The term "coupling" refers to the condition that shifts from an open-circuit relationship between components to a closed-circuit relationship. In an open-circuit relationship, signals cannot currently travel between components via a conductive path, while in a closed-circuit relationship, signals can travel between components via a conductive path. When a component, such as a controller, couples other components together, the component initially allows a change in the flow of signals between the other components via conductive paths that were previously not permitted.

[0137] The term "isolation" refers to the relationship between components where signals cannot currently flow between them. Components are isolated from each other if there is an open circuit between them. For example, components separated by a switch positioned between two components are isolated from each other when the switch is open. When a controller separates two components, it prevents signals from flowing between the components using previously permitted conductive paths.

[0138] As used in this article, the term “generally” means that the modified feature (e.g., a verb or adjective modified by the term “generally”) does not have to be absolute but must be close enough to obtain the advantage of the feature.

[0139] The devices discussed herein, including memory arrays, can be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, and gallium nitride. In some instances, the substrate is a semiconductor wafer. In others, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemicals including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate, either by ion implantation or by any other doping method.

[0140] The switching components or transistors discussed in this article can represent field-effect transistors (FETs) and include three-terminal devices comprising a source, drain, and gate. These terminals can be connected to other electronic components via a conductive material (e.g., a metal). The source and drain can be conductive and can comprise heavily doped semiconductor regions, such as degenerate semiconductor regions. The source and drain can be separated via lightly doped semiconductor regions or channels. If the channel is n-type (e.g., the majority carriers are signals), then the FET can be called an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), then the FET can be called a p-type FET. The channel can be capped by an insulating gate oxide. The conductivity of the channel can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. When a voltage greater than or equal to the threshold voltage of the transistor is applied to the gate, the transistor can be “turned on” or “activated.” When a voltage less than the threshold voltage of the transistor is applied to the gate, the transistor can be “turned off” or “deactivated.”

[0141] The description herein, illustrated with reference to the accompanying drawings, describes exemplary configurations and does not represent all instances that can be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description," not "preferred" or "superior to other instances." The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques can be practiced without these specific details. In some cases, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0142] In the accompanying drawings, similar components or features may have the same reference numerals. Additionally, various components of the same type can be distinguished by a dash following the reference numeral and a second numeral used to differentiate them among similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral, regardless of the second reference numeral.

[0143] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof.

[0144] The various illustrative blocks and modules described herein can be implemented or performed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The general-purpose processor may be a microprocessor, but alternatively, the processor may be any processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration).

[0145] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored as one or more instructions or code on or transmitted via a computer-readable medium. Other examples and implementations are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described above can be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functions can also be physically located in various locations, including distributed implementations such that portions of the functions are implemented in different physical locations. And, as used herein, the word “or” used in the list of items included in the claims (e.g., a list of items beginning with phrases such as “at least one of” or “one or more of”) indicates an inclusive list, such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Additionally, as used herein, the phrase “based on” should not be construed as referring to a closed set of conditions. For example, without departing from the scope of this disclosure, an exemplary step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should also be interpreted as the phrase "at least partially based on".

[0146] The description provided herein enables those skilled in the art to make or use this disclosure. Those skilled in the art will appreciate the various modifications that can be made to this disclosure, and that the general principles defined herein can be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but is given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for operating a memory device, comprising: At the memory device comprising an array of memory cells, a command is received to write data to an address within the array; One or more parity bits are calculated, at least in part, based on multiple bits of the address; The data is written to a first portion of a memory cell page in a first subarray of the array, at least in part, based on the command. as well as At least in part based on the command, one or more double error detection (DED) bits and an indication of the address are written into a second portion of a page in a second subarray of the array, wherein the indication of the address includes the one or more parity bits and is associated with address verification.

2. The method according to claim 1, further comprising: Receive a second command to read the data from the array, the second command being associated with a second address within the array; The instruction to read the data and the address from the array is based at least in part on receiving the second command; as well as The data and error indication are transmitted to the host device of the memory device, at least in part, based on the indication of the data and the address.

3. The method according to claim 2, further comprising: Whether the second address matches the address is determined at least in part based on the indication of the address, wherein the error indication indicates whether the second address matches the address.

4. The method according to claim 3, wherein the second address and the address do not match, the method further comprising: Write a second indication that the second address and the address do not match into the mode register at the memory device.

5. The method of claim 2, wherein the error indication indicates the data and the address.

6. The method of claim 1, wherein the memory cell page comprises memory cells associated with the same row address.

7. The method according to claim 1, wherein The indication of the address includes at least one subset of the plurality of bits.

8. The method of claim 1, further comprising: A copy of the instruction at the address is written to the array, at least in part based on the command.

9. The method of claim 8, further comprising: Receive a second command to read the data from the array, the second command being associated with a second address within the array; Based at least in part on the second command, the data, the indication of the address, and the copy of the indication of the address are read; Determine whether the second address corresponds to at least one of the indication of the address or the copy of the indication of the address; as well as The host device of the memory device transmits signaling indicating the data and the validity of the data, the validity of the data being based at least in part on whether the second address corresponds to at least one of the indication of the address or the copy of the indication of the address.

10. A memory device comprising: Memory cell array, A command component, coupled to the array and configured to receive write and read commands associated with addresses within a first subarray of the array. A decoding component, configured to write the data to a first portion of a memory cell page in the first subarray of the array in response to a write command for the data, and A verification component, coupled to the array and the command component, is used for: One or more parity bits are calculated, at least in part, based on multiple bits of the address associated with the write command; In response to the write command for the data, one or more double error detection (DED) bits and an indication of the address associated with the write command for the data are written to a second portion of the page in a second subarray of the array, wherein the indication of the address includes the one or more parity bits and is associated with address verification; and In response to a read command for the data, the array receives an indication of the address associated with the write command for the data.

11. The memory device of claim 10, wherein the verification component is further configured to: Based at least in part on the indication of the address, determine whether the second address associated with the read command matches the address associated with the write command; and A second indication is transmitted to the host device of the memory device as to whether the second address associated with the read command matches the address associated with the write command.

12. The memory device of claim 11, wherein the verification component is further configured to: In response to the write command on the data, a copy of the indication of the address associated with the write command on the data is stored in the second subarray of the array; In response to the read command for the data, a copy of the indication of the address associated with the write command for the data is received from the second subarray of the array; as well as When the second address associated with the read command corresponds to at least one of the indication of the address associated with the write command or a copy of the indication of the address associated with the write command, it is determined that the second address associated with the read command and the address associated with the write command match.

13. The memory device of claim 11, further comprising: A mode register, coupled to the verification component, wherein the verification component is further configured to store an erroneous third indication in the mode register when the second address associated with the read command and the address associated with the write command do not match.

14. The memory device of claim 10, further comprising: An output component, coupled to the verification component and used to transmit signals to the outside of the memory device, wherein the verification component is further used to transmit to the output component the indication of the address associated with the write command to the data.

15. The memory device according to claim 10, wherein: The address associated with the write command includes multiple bits; and The indication of the address associated with the write command includes at least a subset of the plurality of bits.

16. The memory device of claim 10, wherein the indication of the address associated with the write command includes parity information of the address.

17. A method for operating a memory device, comprising: At a memory device including an array of memory cells, a second command is received to read data from a first subarray of the array, the second command being associated with a second address within the array; The data is read from a first portion of a memory cell page in the first subarray of the array, based at least in part on the second command and the second address; Based at least in part on the second command, one or more double error detection (DED) bits and a first indication of a first address are read from a second portion of a memory cell page in a second subarray of the array, the first address being associated with a first command to write the data to the first subarray of the array, wherein the first indication of the first address includes one or more parity bits for the first address and is associated with address verification; and The data and a second indication of whether the second address matches the first address are transmitted, at least in part based on the second command.

18. The method of claim 17, further comprising: The first command is received at the memory device before the second command is received. as well as The data is written to the first portion of the page in the first subarray of the array, at least in part based on receiving the first command and at least in part based on the first instruction to the first address and the first address to the second portion of the page in the second subarray of the array.

19. The method of claim 17, further comprising: At least in part based on the second command, read the third instruction at the first address; as well as Whether the second address matches the first address is determined at least in part based on the first indication of the first address and the third indication of the first address.

20. The method of claim 17, wherein the first indication of the first address comprises one or more bits contained in the first address.

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