Multistate programming of memory cells

Abstract

The present disclosure includes apparatuses, methods, and systems for polymorphic programming of memory cells. Embodiments include a memory having a plurality of memory cells and a circuit configured to program a memory cell of the plurality of memory cells to one of a plurality of possible data states by: applying a voltage pulse to the memory cell; determining that the memory cell flipped in response to the applied voltage pulse; after determining that the memory cell flipped, turning off current to the memory cell; and after turning off the current to the memory cell, applying a plurality of additional voltage pulses to the memory cell.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor memories and methods, and more specifically, to polymorphic programming of memory cells. Background Technology

[0002] Memory devices are typically provided as internal, semiconductor, integrated circuit, and / or external removable devices in computers or other electronic devices. Many different types of memory exist, including volatile and non-volatile memory. Volatile memory may require power to maintain its data and can include random access memory (RAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM), among others. Non-volatile memory provides permanent data by retaining the stored data when no power is supplied and can include NAND flash memory, NOR flash memory, read-only memory (ROM), and resistive variable memory, such as phase-change random access memory (PCRAM), resistive random access memory (RRAM), magnetic random access memory (MRAM), and programmable conductive memory, among others.

[0003] Memory devices can be used as volatile and non-volatile memories for a wide range of electronic applications requiring high memory density, high reliability, and low power consumption. Non-volatile memories can be used in, for example, personal computers, portable memory sticks, solid-state drives (SSDs), digital cameras, cellular phones, portable music players (e.g., MP3 players) and movie players, and other electronic devices.

[0004] A variable resistance memory device may include a variable resistance memory cell capable of storing data based on the resistance state of a storage element (e.g., a memory element with variable resistance). Thus, the variable resistance memory cell can be programmed to store data corresponding to a target data state by varying the resistance level of the memory element. The variable resistance memory cell can be programmed to a target data state (e.g., corresponding to a specific resistance state) by applying an electric field source or energy source (e.g., a positive or negative electrical pulse (e.g., a positive or negative voltage pulse or a positive or negative current pulse)) to the cell (e.g., the memory element applied to the cell) for a specific duration. The state of the variable resistance memory cell can be determined by sensing the current through the cell in response to an applied interrogation voltage. The sensed current, varying based on the resistance level of the cell, indicates the state of the cell.

[0005] Various memory arrays can be organized using a crosspoint architecture, where memory cells (e.g., variable-resistance cells) are located at the intersection of a first signal line and a second signal line used for accessing the cell (e.g., the intersection of a word line and a bit line). Some variable-resistance memory cells may include a selection element (e.g., a diode, transistor, or other switching device) connected in series with a storage element (e.g., a phase-change material, metal oxide material, and / or some other material programmable to different resistance levels). Some variable-resistance memory cells (which may be referred to as auto-select memory cells) may include a single material that can serve as both a selection element and a storage element for the memory cell. Attached Figure Description

[0006] Figure 1 A three-dimensional view of an example of a memory array according to an embodiment of the present disclosure.

[0007] Figure 2A This describes the threshold voltage distribution associated with the memory state of a memory cell according to embodiments of the present disclosure.

[0008] Figure 2B For the embodiments of this disclosure corresponding to Figure 2A An example of current versus voltage curves for memory states.

[0009] Figure 2C For the embodiments of this disclosure corresponding to Figure 2A Another example of current versus voltage curves for a memory state.

[0010] Figure 3A This describes the threshold voltage distribution associated with the memory state of a memory cell according to embodiments of the present disclosure.

[0011] Figure 3B This describes the threshold voltage distribution associated with the memory state of a memory cell according to embodiments of the present disclosure.

[0012] Figure 4 Examples of a portion of a memory array and associated circuitry according to embodiments of the present disclosure are described.

[0013] Figure 5 Examples of a portion of a memory array and associated circuitry according to embodiments of the present disclosure are described.

[0014] Figure 6 Examples of voltage applied to a memory cell and current flowing through a memory cell according to embodiments of the present disclosure are described.

[0015] Figure 7 This is a block diagram illustration of an example device according to an embodiment of the present disclosure. Detailed Implementation

[0016] This disclosure includes apparatus, methods, and systems for polymorphic programming of memory cells. Embodiments include: a memory having a plurality of memory cells; and circuitry configured to program a memory cell among the plurality of memory cells to one of a plurality of possible data states by: applying a voltage pulse to the memory cell; determining that the memory cell surges back in response to the applied voltage pulse; after determining that the memory cell surges back, shutting off current to the memory cell; and after shutting off current to the memory cell, applying a plurality of additional voltage pulses to the memory cell.

[0017] Compared to prior art memory devices, embodiments of this disclosure offer benefits such as increased density, reduced cost, increased performance, reduced power consumption, and / or faster and / or more complex operation. For example, prior approaches for programming resistive variable memory cells (e.g., selectable memory cells) may be able to generate two different states for the cell, allowing the cell to be programmed into one of two possible data states (e.g., state 0 or state 1). However, the programming approach for resistive variable memory cells according to this disclosure can generate additional (e.g., more than two) data states for the cell, allowing the cell to be programmed into at least three possible data states.

[0018] This type of polymorphic programming can leverage multiple threshold voltages to support complex memory operations, such as in machine learning applications where data is encoded and matching or partial matching functions (e.g., Hamming distance) are computed. For example, this type of polymorphic programming can efficiently support the computation of matching or partial matching functions for input vector models with many stored vectors.

[0019] Furthermore, this type of polymorphic programming can be used to reduce costs and / or increase the density of standard memory applications. For example, such polymorphic programming can utilize the previous two-state programming approach to reduce the number of bits required to encode the same number of data states. These extra bits can be used, for example, for error correction codes (ECC) and / or data redundancy operations.

[0020] Additionally, this type of polymorphic programming can be used to increase memory performance. For example, it can be used to place a memory cell (e.g., a variable-resistance memory cell) in a state that provides lower leakage in the memory array. Furthermore, it can be used to place a memory cell in a state that allows the use of higher suppression voltages on the array without making it difficult to select cells within the array. This can be useful, for example, during array initialization (e.g., first boot), when higher voltages may need to be applied to the array.

[0021] As used herein, “a / an” or “a plurality” can refer to one or more of something, and “a plurality” can refer to two or more such things. For example, a memory device can refer to one or more memory devices, and a plurality of memory devices can refer to two or more memory devices. Additionally, as used herein, specifically with respect to reference numerals in the drawings, the designations “N” and “M” indicate that a plurality of specific features so specified may be included within various embodiments of this disclosure.

[0022] The diagrams in this document follow a numbering convention where the first or first few digits correspond to the diagram number, and the remaining digits identify the elements or components within the diagram. Similar elements or components between different diagrams can be identified using similar numbers.

[0023] Figure 1 This is a three-dimensional view of an example of a memory array 100 (e.g., a cross-point memory array) according to an embodiment of the present disclosure. The memory array 100 may include a plurality of first signal lines (e.g., first access lines) and a plurality of second signal lines (e.g., second access lines) that intersect each other (e.g., in different planes). The plurality of first signal lines may be referred to as word lines 110-0 to 110-N, and the plurality of second signal lines may be referred to as bit lines 120-0 to 120-M. For example, each of the word lines 110-0 to 110-N may intersect with the bit lines 120-0 to 120-M. Memory cells 125 may be located between bit lines and word lines (e.g., at each bit line / word line intersection).

[0024] For example, memory cell 125 may be a variable-resistance memory cell. Memory cell 125 may contain a material programmable to different data states. In some instances, each of memory cells 125 may contain a single material that can be used as a selection element (e.g., a switching material) and a storage element, such that each memory cell 125 can function as both a selector device and a memory element. Such memory cells may be referred to herein as selectable memory cells. For example, each memory cell may contain a chalcogenide material, which may be formed from various doped or undoped materials, may or may not be a phase-change material, and / or may or may not undergo a phase change during reading and / or writing to the memory cell. In some instances, each memory cell 125 may contain: a ternary composition, which may contain selenium (Se), arsenic (As), and germanium (Ge); or a quaternary composition, which may contain silicon (Si), Se, As, and Ge, etc.

[0025] In various embodiments, the threshold voltage of memory cell 125 may buck back in response to an applied voltage difference exceeding its threshold voltage. Such a memory cell may be referred to as a buck-back memory cell. For example, memory cell 125 may change (e.g., buck back) from a non-conductive (e.g., high impedance) state to a conductive (e.g., lower impedance) state in response to an applied voltage difference exceeding its threshold voltage. For example, a memory cell buck back may refer to a memory cell changing from a high impedance state to a lower impedance state in response to an applied voltage difference greater than the memory cell's threshold voltage. The threshold voltage of a memory cell buck back may be referred to as, for example, a buck back event.

[0026] Figure 2A The description of the memory cell (e.g., according to embodiments of the present disclosure) is as follows. Figure 1 The threshold distribution associated with various states of the memory cell 125 described herein. For example, as Figure 2A As shown, the memory cell can be programmed into one of three possible data states (e.g., state 0, state 1, or state T). That is, Figure 2A This describes the distribution of threshold voltages associated with three possible data states that a memory cell can be programmed into.

[0027] exist Figure 2A In this context, the voltage VCELL can correspond to the voltage difference applied to a memory cell (e.g., on the memory cell), such as the difference between the bit line voltage (VBL) and the word line voltage (VWL) (e.g., VCELL = VBL - VWL). Threshold voltage distributions (e.g., ranges) 200-1, 200-2, 201-1, 201-2, 202-T1, and 202-T2 can represent the statistical variation of the threshold voltage of a memory cell programmed into a specific state. (Illustrated in...) Figure 2A The distribution in corresponds to further binding Figure 2B and 2C The described current and voltage curves, Figure 2B and 2C This describes the sudden reversal asymmetry associated with the assigned data state.

[0028] In some instances, the threshold voltage of memory cell 125 in a specific state can be asymmetric for different polarities, such as... Figure 2A , 2B As shown in 2C. For example, the threshold voltage of a memory cell 125 programmed to state 0 or state 1 may have a different value in one polarity than in the opposite polarity. For example, in Figure 2AIn the example described, a first data state (e.g., state 0) is associated with a first asymmetric threshold voltage distribution (e.g., threshold voltage distributions 201-1 and 201-2), the magnitude of which is greater for negative polarity than for positive polarity, and a second data state (e.g., state 1) is associated with a second asymmetric threshold voltage distribution (e.g., threshold voltage distributions 200-1 and 200-2), the magnitude of which is greater for positive polarity than for negative polarity. In this example, the applied voltage magnitude sufficient to cause a sudden return of memory cell 125 may differ (e.g., higher or lower) for one applied voltage polarity than for the other.

[0029] In some instances, the threshold voltage of memory cell 125 in a specific state can be symmetrical with respect to different polarities, such as... Figure 2A As shown in the diagram. For example, the threshold voltage of memory cell 125 programmed to state T can have the same value under opposite polarities. For example, in Figure 2A In the example described, the third data state (e.g., state T) is associated with a symmetrical threshold voltage distribution (e.g., threshold voltage distributions 202-T1 and 202-T2), the magnitude of which is substantially equal (e.g., higher) for both positive and negative polarities. In such examples, the applied voltage magnitude sufficient to cause a sudden return of memory cell 125 may be the same for different applied voltage polarities.

[0030] Figure 2A The description uses boundary voltages VDM1 and VDM2 to determine the state of a memory cell (e.g., to distinguish the state as a read operation portion). In this example, VDM1 is a positive voltage used to distinguish a cell in state 0 (e.g., under threshold voltage distribution 201-2) from a cell in state 1 (e.g., threshold voltage distribution 200-2) or state T (e.g., threshold voltage distribution 202-T2). Similarly, VDM2 is a negative voltage used to distinguish a cell in state 1 (e.g., threshold voltage distribution 200-1) from a cell in state 0 (e.g., threshold voltage distribution 201-1) or state T (e.g., threshold voltage distribution 202-T1). Figures 2A to 2C In the example, memory cell 125 in positive state 1 or T does not suddenly return in response to the application of VDM1; memory cell 125 in positive state 0 suddenly returns in response to the application of VDM1; memory cell 125 in negative state 1 suddenly returns in response to the application of VDM2; and memory cell 125 in negative state 0 or T does not suddenly return in response to the application of VDM2.

[0031] Examples are not limited to Figure 2AExamples are shown in the document. For instance, the designation of state 0 and state 1 can be interchanged (e.g., distributions 201-1 and 201-2 can be designated as state 1, and distributions 200-1 and 200-2 can be designated as state 0). Additionally, embodiments may include memory cells that can be programmed to more than three possible data states, as will be discussed herein (e.g., in conjunction with...). Figures 3A to 3B Further description.

[0032] Figure 2B and 2C For the embodiments of this disclosure corresponding to Figure 2A An example of current versus voltage curves for memory states. Thus, in this example, Figure 2B and 2C The curves in the diagram correspond to the following units: where state 1 is specified as a higher threshold voltage state under a specific polarity (positive polarity in this example), and where state 0 is specified as a higher threshold voltage state under the opposite polarity (negative polarity in this example). As noted above, the state designations are interchangeable, such that state 0 can correspond to a higher threshold voltage state in the positive polarity direction, and state 1 can correspond to a higher threshold voltage state in the negative polarity direction.

[0033] Figure 2B and 2C This describes a memory cell burst as described herein. VCELL can represent the voltage applied to the memory cell. For example, VCELL can be the voltage applied to the top electrode corresponding to the cell minus the voltage applied to the bottom electrode corresponding to the cell (e.g., via the corresponding word line and bit line). Figure 2B As shown, in response to an applied positive polarity voltage (VCELL), a memory cell programmed to state 1 (e.g., threshold voltage distribution 200-2) remains in a non-conductive state until VCELL reaches voltage Vtst02, at which point the cell transitions to a conductive (e.g., lower resistance) state. This transition can be termed a backflip event, which occurs when the voltage applied to the cell (of a specific polarity) exceeds the cell's threshold voltage. Therefore, voltage Vtst02 can be referred to as the backflip voltage. Figure 2B In this context, voltage Vtst01 corresponds to the sudden return voltage of a cell programmed to state 1 (e.g., threshold voltage distribution 200-1). That is, as... Figure 2B As shown, when VCELL crosses Vtst01 in the negative polarity direction, the memory cell transitions (e.g., switches) to a conductive state.

[0034] Similarly, such as Figure 2CAs shown, in response to an applied negative polarity voltage (VCELL), a memory cell programmed to state 0 (e.g., threshold voltage distribution 201-1) remains in a non-conductive state until VCELL reaches voltage Vtst11, at which point the cell abruptly reverts to a conductive (e.g., lower resistance) state. Figure 2C In this context, voltage Vtst12 corresponds to the sudden return voltage of a cell programmed to state 0 (e.g., threshold voltage distribution 201-2). That is, as... Figure 2C As shown in the figure, when VCELL exceeds Vtst12 in the positive polarity direction, the memory cell suddenly changes from a high-impedance non-conductive state to a low-impedance conductive state.

[0035] In various situations, a backslip event can cause a memory cell to switch states. For example, if a VCELL greater than Vtst02 is applied to a state 1 cell, the resulting backslip event can reduce the cell's threshold voltage to a level below VDM1, which will cause the cell to be read as state 0 (e.g., threshold voltage distribution 201-2). Thus, in several embodiments, a backslip event can be used to write a cell to the opposite state (e.g., from state 1 to state 0, and vice versa).

[0036] Figure 3A and 3B Each describes the memory cell (e.g., according to embodiments of this disclosure) Figure 1 The threshold distribution associated with various states of the memory cell 125 described herein. For example, in Figure 3A In the example shown, the memory cell can be programmed to one of four possible data states (e.g., state 0, state 1, state 2, or state 3). That is, Figure 3A This describes the threshold voltage distribution associated with the four possible data states that a memory cell can be programmed into. Figure 3B In the example shown, the memory cell can be programmed to one of six possible data states (e.g., state 0, state 1, state 2, state 3, state 4, or state 5). That is, Figure 3B This describes the distribution of threshold voltages associated with six possible data states that a memory cell can be programmed into.

[0037] exist Figure 3A and 3B In this context, the voltage VCELL can correspond to the voltage difference applied to the memory cell (e.g., on the memory cell) (e.g., VCELL = VBL - VWL), as previously discussed. Figure 2AThe threshold voltage distributions (e.g., ranges) 303-1, 303-2, 305-1, 305-2, 307-1, 307-2, 309-1, 309-2, 311-1, 311-2, 313-1, 313-2, 315-1, 315-2, 317-1, 317-2, 318-1, 318-2, 319-1, and 319-2 can represent the statistical variation of the threshold voltage of a memory cell programmed into a specific state.

[0038] In some instances, the threshold voltage of memory cell 125 in a specific state can be asymmetric for different polarities, such as... Figure 3A and 3B As shown in [the document]. For example, in [the document] Figure 3A In the examples described, a first data state (e.g., state 2) is associated with a first asymmetric threshold voltage distribution (e.g., threshold voltage distributions 303-1 and 303-2), the magnitude of which is larger for negative polarity than for positive polarity; a second data state (e.g., state 1) is associated with a second asymmetric threshold voltage distribution (e.g., threshold voltage distributions 305-1 and 305-2), the magnitude of which is larger for positive polarity than for negative polarity; a third data state (e.g., state 0) is associated with a third asymmetric threshold voltage distribution (e.g., threshold voltage distributions 307-1 and 307-2), the magnitude of which is larger for positive polarity than for negative polarity; and a fourth data state (e.g., state 3) is associated with a fourth asymmetric threshold voltage distribution (e.g., threshold voltage distributions 309-1 and 309-2), the magnitude of which is larger for negative polarity than for positive polarity. Additionally, as... Figure 3A As shown, the values ​​of threshold voltage distributions 303-1 and 309-1 can be substantially equal to and greater than the value of threshold voltage distribution 305-1, the value of threshold voltage distribution 305-1 can be greater than the value of threshold voltage distribution 307-1, and the values ​​of threshold voltage distributions 305-2 and 307-2 can be substantially equal to and greater than the value of threshold voltage distribution 309-2, the value of threshold voltage distribution 309-2 can be greater than the value of threshold voltage distribution 303-2.

[0039] In addition, Figure 3BIn the examples described, a first data state (e.g., state 3) is associated with a first asymmetric threshold voltage distribution (e.g., threshold voltage distributions 311-1 and 311-2), the magnitude of which is larger for negative polarity than for positive polarity; a second data state (e.g., state 2) is associated with a second asymmetric threshold voltage distribution (e.g., threshold voltage distributions 313-1 and 313-2), the magnitude of which is larger for positive polarity than for negative polarity; and a third data state (e.g., state 1) is associated with a third asymmetric threshold voltage distribution (e.g., threshold voltage distributions 315-1 and 315-2), the magnitude of which is larger for positive polarity than for negative polarity. The negative polarity is greater; the fourth data state (e.g., state 0) is associated with a fourth asymmetric voltage distribution (e.g., threshold voltage distributions 317-1 and 317-2), the magnitude of which is greater with respect to positive polarity than negative polarity; the fifth data state (e.g., state 5) is associated with a fifth asymmetric threshold voltage distribution (e.g., threshold voltage distributions 318-1 and 318-2), the magnitude of which is greater with respect to negative polarity than positive polarity; and the sixth data state (e.g., state 4) is associated with a sixth asymmetric threshold voltage distribution (e.g., threshold voltage distributions 319-1 and 319-2), the magnitude of which is greater with respect to negative polarity than positive polarity. Additionally, as... Figure 3B As shown, the values ​​of threshold voltage distributions 311-1, 318-1, and 319-1 are substantially equal to and greater than the value of threshold voltage distribution 313-1. The value of threshold voltage distribution 313-1 is greater than the value of threshold voltage distribution 315-1, which is greater than the value of threshold voltage distribution 317-1. The values ​​of threshold voltage distributions 313-2, 315-2, and 317-2 are substantially equal to and greater than the value of threshold voltage distribution 318-2. The value of threshold voltage distribution 318-2 is greater than the value of threshold voltage distribution 319-2, which is greater than the value of threshold voltage distribution 311-2.

[0040] Figure 3A The description can be used to determine the programming as Figure 3AThe diagram describes four data states for memory cells, defined by boundary voltages VDM1, VDM2, VDM3, and VDM4, used to distinguish states as parts of a read operation. In this example, VDM1 and VDM2 are positive voltages with different values ​​(e.g., VDM2 is greater than VDM1), used to distinguish cells in state 2 or 3 (e.g., threshold voltage distributions 303-2 and 309-2) from cells in state 1 or 0 (e.g., threshold voltage distributions 305-2 or 307-2). Similarly, VDM3 and VDM4 are negative voltages with different values ​​(e.g., VDM4 is greater than VDM3), used to distinguish cells in state 0 or 1 (e.g., threshold voltage distributions 307-1 or 305-1) from cells in state 2 or 3 (e.g., threshold voltage distributions 303-1 or 309-1).

[0041] exist Figure 3A In the example, memory cell 125 in state 0 returns in response to the application of VDM3, memory cell 125 in state 1 returns in response to the application of VDM4, memory cell 125 in state 2 returns in response to the application of VDM1, and memory cell 125 in state 3 returns in response to the application of VDM2. Therefore, the state to which memory cell 125 has been programmed can be determined (e.g., read) by sequentially applying boundary voltages to the cell (e.g., first applying VDM3 to the cell, then applying VDM4 to the cell, then applying VDM1 to the cell, then applying VDM2 to the cell) until the cell returns in response to one of the applied boundary voltages.

[0042] Figure 3B The description can be used to determine the programming as Figure 3BThe six data states described herein are defined by boundary voltages VDM1, VDM2, VDM3, VDM4, VDM5, and VDM6, which distinguish the states of memory cells as part of a read operation. In this example, VDM1, VDM2, and VDM3 are positive voltages with different values ​​(e.g., the value of VDM3 is greater than the value of VDM2, which is greater than the value of VDM1), used to distinguish cells in states 3, 4, or 5 (e.g., threshold voltage distributions 311-2, 319-2, or 318-2) from cells in states 2, 1, or 0 (e.g., threshold voltage distributions 313-2, 315-2, or 317-2). Similarly, VDM4, VDM5, and VDM6 are negative voltages with different values ​​(e.g., the value of VDM6 is greater than the value of VDM5, and the value of VDM5 is greater than the value of VDM4), which are used to distinguish the cells in state 0, 1, or 2 (e.g., threshold voltage distribution 317-1, 315-1, or 313-1) from the cells in state 3, 4, or 5 (e.g., threshold voltage distribution 311-1, 319-1, or 318-1).

[0043] exist Figure 3B In the example, memory cell 125 in state 0 returns in response to the application of VDM4, memory cell 125 in state 1 returns in response to the application of VDM5, memory cell 125 in state 2 returns in response to the application of VDM6, memory cell 125 in state 3 returns in response to the application of VDM1, memory cell 125 in state 4 returns in response to the application of VDM2, and memory cell in state 5 returns in response to the application of VDM3. Therefore, the state to which memory cell 125 has been programmed can be determined (e.g., read) by sequentially applying boundary voltages to the cell (e.g., first applying VDM4 to the cell, then applying VDM5 to the cell, then applying VDM6 to the cell, then applying VDM1 to the cell, then applying VDM2 to the cell, then applying VDM3 to the cell) until the cell returns in response to one of the applied boundary voltages.

[0044] Examples are not limited to Figure 3A and 3B The examples shown in the document illustrate this. For instance, the numerical specifications for different states are interchangeable.

[0045] In embodiments of this disclosure, for example Figure 1 The memory cell 125 described herein can be programmed into one of a plurality of possible data states. For example, the memory cell can be programmed to combine Figure 2A One of the three possible data states described, combined Figure 3A One or a combination of the four possible data states described Figure 3B One of six possible data states is described. The cell can be programmed into one of the multiple possible data states, for example, by changing (e.g., adjusting) the cell's threshold voltage to one of the multiple possible values, as will be further described herein.

[0046] For example, a voltage pulse may be applied to a memory cell. The voltage pulse may be, for example, a bias voltage pulse (e.g., VCELL) having a sufficiently high value to cause (e.g., to cause) a jump back in the memory cell. The bias voltage pulse may include, for example, a voltage pulse having a first polarity and / or a voltage pulse having a second polarity opposite to the first polarity, as previously described herein. For example, applying a bias voltage pulse may include applying a positive 5.5 volt (V) pulse and / or a negative 5.5 V pulse to the memory cell. Additionally, the bias voltage pulse may include a voltage applied to a word line coupled to the cell (e.g., VWL) and a voltage applied to a bit line coupled to the cell (e.g., VBL), as previously described herein. (E.g., in conjunction with...) Figure 6 Further descriptions illustrate instances of such voltage pulses (e.g., VWL and VBL).

[0047] Once (for example, if) a memory cell abruptly returns to a conductive state in response to an applied bias voltage pulse, a current pulse (e.g., a transient current) can flow through the memory cell. After a certain amount of time, the transient current through the cell can dissipate, and a DC current can be established on the cell. This will be (e.g., in conjunction with...) Figure 6 Further description illustrates examples of such currents passing through memory cells.

[0048] After a voltage pulse (e.g., a bias voltage pulse) has been applied to a memory cell, it can be determined (e.g., sensed and / or detected) that the memory cell has jerked back in response to the applied voltage pulse (e.g., in response to a positive or negative pulse). This determination can be made, for example, by sensing a voltage change associated with the memory cell (e.g., on a signal line coupled to the cell) that has occurred in response to the applied voltage pulse. For example, sensing such a voltage change may include sensing that the voltage on the signal line coupled to the cell (e.g., a word line) meets or exceeds a specific voltage threshold (e.g., 0.45V). This will be referred to herein (e.g., in conjunction with...) Figure 4 and 6 Further descriptions and examples of such determinations and circuits that can be used to perform such determinations are provided.

[0049] Once it is determined that a memory cell has surged back, the current to the memory cell can be shut off (e.g., disabled). This can be achieved, for example, by shutting off (e.g., disabling) the drivers coupled to the memory cell (e.g., word line drivers and / or bit line drivers coupled to word lines and / or bit lines (coupled to cells), as will be described herein (e.g., in conjunction with...). Figure 5 Further description.

[0050] The current to the memory cell can be switched off quickly enough that the cell's back-current includes events below the nominal back-current trigger event (e.g., below the condition that allows the transient current through the memory cell to be completely dissipated to establish a DC current on the cell). For example, the current can be switched off immediately after determining that the memory cell has back-current (e.g., without delay), or the current can be switched off after a certain amount of time (e.g., a short delay) has elapsed after determining that the memory cell has back-current. This will be discussed herein (e.g., in conjunction with...). Figure 5 and 6 Further describe this delay and the circuitry that can be used to provide such a delay.

[0051] After the current to the memory cell has been turned off, multiple additional voltage pulses can be sequentially applied to the memory cell. As used herein, a short pulse may refer to a pulse with a duration shorter than the duration of the bias voltage. For example, the duration of each corresponding additional voltage pulse may be 5 nanoseconds (ns). The magnitude of each corresponding additional voltage pulse may be the same as the magnitude of the bias voltage. As an additional example, the magnitude of the additional voltage pulses may be different (e.g., variable), which may change the effect of each corresponding additional pulse on the memory cell (e.g., the threshold voltage of the cell). Additionally, each additional voltage pulse may each include a voltage applied to the word line coupled to the cell (e.g., VWL) and a voltage applied to the bit line coupled to the cell (e.g., VBL). (As used herein, in conjunction with...) Figure 6 Further descriptions illustrate instances of such additional voltage pulses (e.g., VWL and VBL).

[0052] Applying multiple additional voltage pulses to a memory cell can incrementally change (e.g., adjust) the threshold voltage of the memory cell. For example, applying a first short additional voltage pulse can change the threshold voltage of the cell to a first value within a first threshold voltage distribution, applying a second short additional voltage pulse can change the threshold voltage of the cell to a second value within a second threshold voltage distribution, and so on. In this way, the memory cell can be programmed into one of multiple possible data states. (As will be used herein, for example, in conjunction with...) Figure 6 Further description illustrates an example of the current flowing through a memory cell when an additional voltage pulse is applied to the cell.

[0053] As an example, refer to Figure 2A In order to program the memory cell as Figure 2A The state T described herein allows a single short additional voltage pulse with a first polarity or a second polarity opposite to the first polarity to be applied to the memory cell. For example, a single short voltage pulse with a negative polarity can be applied to... Figure 2A The memory cell described in the diagram, currently in state 0, can be programmed to state T (e.g., changing the cell's state from 0 to T). For example, a single short negative voltage pulse may not change the threshold voltage of a cell observed (e.g., measured) as a high magnitude threshold in the negative direction, but may increase the threshold voltage of a cell observed as a low magnitude threshold in the positive direction to a high magnitude threshold (e.g., from threshold voltage distribution 201-2 to threshold voltage distribution 202-T2). As an additional example, a single short voltage pulse with positive polarity is applied to... Figure 2A The memory cell described in the diagram, which is in state 1, can be programmed to state T (e.g., changing the state of the cell from 1 to T). For example, a single short positive voltage pulse may not change the threshold voltage of a cell that is observed (e.g., measured) as a high magnitude threshold in the positive direction, but may increase the threshold voltage of a cell that is observed as a low magnitude threshold in the negative direction to a high magnitude threshold (e.g., from threshold voltage distribution 200-1 to threshold voltage distribution 202-T1).

[0054] As an additional example, see [reference] Figure 3A A short, additional voltage pulse with a first polarity or a second polarity opposite to the first polarity can be applied to a memory cell. For example, a short voltage pulse with a negative polarity can be applied to... Figure 3A The memory cell in state 2 described herein can be programmed to state 1 (e.g., changing the state of the cell from 2 to 1). For example, a short negative voltage pulse can reduce the threshold voltage of a cell that is observed (e.g., measured) as having the highest magnitude threshold in the negative direction to a lower magnitude threshold (e.g., from threshold voltage distribution 303-1 to threshold voltage distribution 305-1), and can increase the threshold voltage of a cell that is observed as having the lowest magnitude threshold in the positive direction to the highest magnitude threshold (e.g., from threshold voltage distribution 303-2 to threshold voltage distribution 305-2). As an additional example, a short voltage pulse with positive polarity is applied to... Figure 3AThe memory cell described in the diagram, which is in state 0, can be programmed to state 3 (e.g., changing the cell's state from 0 to 3). For example, a short positive voltage pulse can increase the threshold voltage of a cell that is observed (e.g., measured) as having the lowest magnitude threshold in the negative direction to the highest magnitude threshold (e.g., from threshold voltage distribution 307-1 to threshold voltage distribution 309-1), and can decrease the threshold voltage of a cell that is observed as having the highest magnitude threshold in the positive direction to a lower magnitude threshold (e.g., from threshold voltage distribution 307-2 to threshold voltage distribution 309-2).

[0055] As an additional example, see [reference] Figure 3A Two short, additional voltage pulses, each with a first polarity or a second polarity opposite to the first polarity, can be applied to a memory cell. For example, two short voltage pulses, each with a negative polarity, can be applied to... Figure 3A The memory cell in state 2 described herein can be programmed to state 0 (e.g., changing the state of the cell from 2 to 0). For example, the first of two short negative voltage pulses can reduce the threshold voltage of the cell observed (e.g., measured) as the highest magnitude threshold in the negative direction to a lower magnitude threshold (e.g., from threshold voltage distribution 303-1 to threshold voltage distribution 305-1), and can increase the threshold voltage of the cell observed as the lowest magnitude threshold in the positive direction to the highest magnitude threshold (e.g., from threshold voltage distribution 303-2 to threshold voltage distribution 307-2), and the second of the two short negative voltage pulses can further reduce the threshold voltage of the cell observed in the negative direction to the lowest magnitude threshold (e.g., from threshold voltage distribution 305-1 to threshold voltage distribution 307-1), but can not change the threshold voltage of the cell observed as the highest magnitude threshold in the positive direction.

[0056] As an additional example, two short voltage pulses, each with a positive polarity, are applied to... Figure 3A The memory cell described in the diagram, which is in state 0, can be programmed to state 2 (e.g., changing the state of the cell from 0 to 2). For example, the first of two short positive voltage pulses can increase the threshold voltage of the cell observed (e.g., measured) as the lowest magnitude threshold in the negative direction to the highest magnitude threshold (e.g., from threshold voltage distribution 307-1 to threshold voltage distribution 303-1), and can decrease the threshold voltage of the cell observed as the highest magnitude threshold in the positive direction to a lower magnitude threshold (e.g., from threshold voltage distribution 307-2 to threshold voltage distribution 309-2). The second of the two short positive voltage pulses can further decrease the threshold voltage of the cell observed in the positive direction to the lowest magnitude threshold (e.g., from threshold voltage distribution 309-2 to threshold voltage distribution 303-2), but can not change the threshold voltage of the cell observed as the highest magnitude threshold in the negative direction.

[0057] As an additional example, see [reference] Figure 3B Two short, additional voltage pulses, each with a first polarity or a second polarity opposite to the first polarity, can be applied to a memory cell. For example, two short voltage pulses, each with a negative polarity, can be applied to... Figure 3B The memory cell in state 3 described herein can be programmed to state 2 (e.g., changing the state of the cell from 3 to 2). For example, two short negative voltage pulses can reduce the threshold voltage of a cell that is observed (e.g., measured) as having the highest magnitude threshold in the negative direction to a lower magnitude threshold (e.g., from threshold voltage distribution 311-1 to threshold voltage distribution 313-1), and can increase the threshold voltage of a cell that is observed as having the lowest magnitude threshold in the positive direction to the highest magnitude threshold (e.g., from threshold voltage distribution 311-2 to threshold voltage distribution 313-2). As an additional example, two short voltage pulses, each having a positive polarity, are applied to... Figure 3B The memory cell described in the diagram, which is in state 0, can be programmed to state 5 (e.g., changing the state of the cell from 0 to 5). For example, two short positive voltage pulses can increase the threshold voltage of a cell that is observed (e.g., measured) as having the lowest magnitude threshold in the negative direction to the highest magnitude threshold (e.g., from threshold voltage distribution 317-1 to threshold voltage distribution 318-1), and can decrease the threshold voltage of a cell that is observed as having the highest magnitude threshold in the positive direction to a lower magnitude threshold (e.g., from threshold voltage distribution 317-2 to threshold voltage distribution 318-2).

[0058] As an additional example, see [reference] Figure 3B Four short additional voltage pulses, each with a first polarity or a second polarity opposite to the first polarity, can be applied to the memory cell. For example, four short voltage pulses, each with a negative polarity, can be applied to... Figure 3BThe memory cell in state 3 described herein can be programmed to state 1 (e.g., changing the state of the cell from 3 to 1). For example, the first and second short negative voltage pulses of the four short negative voltage pulses can reduce the threshold voltage of the cell that is observed (e.g., measured) as the highest magnitude threshold in the negative direction to a lower magnitude threshold (e.g., from threshold voltage distribution 311-1 to threshold voltage distribution 313-1), and can increase the threshold voltage of the cell that is observed as the lowest magnitude threshold in the positive direction to the highest magnitude threshold (e.g., from threshold voltage distribution 311-2 to threshold voltage distribution 315-2). The third and fourth short negative voltage pulses of the four short negative voltage pulses can further reduce the threshold voltage of the cell observed in the negative direction to a lower magnitude threshold (e.g., from threshold voltage distribution 313-1 to threshold voltage distribution 315-1), but can not change the threshold voltage of the cell that is observed as the highest magnitude threshold in the positive direction.

[0059] As an additional example, four short voltage pulses, each with a positive polarity, are applied to... Figure 3B The memory cell described in the diagram, which is in state 0, can be programmed to state 4 (e.g., changing the state of the cell from 0 to 4). For example, the first and second short positive voltage pulses of the four short positive voltage pulses can increase the threshold voltage of the cell that is observed (e.g., measured) as the lowest magnitude threshold in the negative direction to the highest magnitude threshold (e.g., from threshold voltage distribution 317-1 to threshold voltage distribution 319-1), and can decrease the threshold voltage of the cell that is observed as the highest magnitude threshold in the positive direction to a lower magnitude threshold (e.g., from threshold voltage distribution 317-2 to threshold voltage distribution 318-2). The third and fourth short positive voltage pulses of the four short positive voltage pulses can further decrease the threshold voltage of the cell observed in the positive direction to a lower magnitude threshold (e.g., from threshold voltage distribution 318-2 to threshold voltage distribution 319-2), but can not change the threshold voltage of the cell that is observed as the highest magnitude threshold in the negative direction.

[0060] As an additional example, see [reference] Figure 3B Six short additional voltage pulses, each with a first polarity or a second polarity opposite to the first polarity, can be applied to the memory cell. For example, six short voltage pulses, each with a negative polarity, can be applied to... Figure 3BThe memory cell in state 3 described herein can be programmed to state 0 (e.g., changing the state of the cell from 3 to 0). For example, the first and second short negative voltage pulses of the six short negative voltage pulses can reduce the threshold voltage of the cell that is observed (e.g., measured) as the highest magnitude threshold in the negative direction to a lower magnitude threshold (e.g., from threshold voltage distribution 311-1 to threshold voltage distribution 313-1), and can increase the threshold voltage of the cell that is observed as the lowest magnitude threshold in the positive direction to the highest magnitude threshold (e.g., from threshold voltage distribution 311-2 to threshold voltage distribution 317-2). The third and fourth short negative voltage pulses of the six short negative voltage pulses can... The threshold voltage of the cell observed in the negative direction is further reduced to a lower magnitude threshold (e.g., from threshold voltage distribution 313-1 to threshold voltage distribution 315-1), but the threshold voltage of the cell observed in the positive direction as the highest magnitude threshold may not be changed. The fifth and sixth short negative voltage pulses of the six short negative voltage pulses may further reduce the threshold voltage of the cell observed in the negative direction to the lowest magnitude threshold (e.g., from threshold voltage distribution 315-1 to threshold voltage distribution 317-1), but the threshold voltage of the cell observed in the positive direction as the highest magnitude threshold may not be changed.

[0061] As an additional example, six short voltage pulses, each with a positive polarity, are applied to Figure 3B The memory cell described in the diagram, currently in state 0, can be programmed to state 3 (e.g., changing the cell's state from 0 to 3). For example, the first and second short positive voltage pulses of the six short positive voltage pulses can increase the threshold voltage of a cell observed (e.g., measured) as having the lowest magnitude threshold in the negative direction to the highest magnitude threshold (e.g., from threshold voltage distribution 317-1 to threshold voltage distribution 311-1), and can decrease the threshold voltage of a cell observed as having the highest magnitude threshold in the positive direction to a lower magnitude threshold (e.g., from threshold voltage distribution 317-2 to threshold voltage distribution 318-2). The third and fourth short positive voltage pulses of the six short positive voltage pulses can... The threshold voltage of the cell observed in the positive direction is further reduced to a lower magnitude threshold (e.g., from threshold voltage distribution 318-2 to threshold voltage distribution 319-2), but the threshold voltage of the cell observed in the negative direction as the highest magnitude threshold may not be changed. The fifth and sixth short positive voltage pulses of the six short positive voltage pulses can further reduce the threshold voltage of the cell observed in the positive direction to the lowest magnitude threshold (e.g., from threshold voltage distribution 319-2 to threshold voltage distribution 311-2), but the threshold voltage of the cell observed in the negative direction as the highest magnitude threshold may not be changed.

[0062] Figure 4 This section describes an example of a portion of a memory array 400 and associated circuitry for detecting a sudden return event according to embodiments of the present disclosure. The memory array 400 may be a previously combined... Figure 1 This is a portion of the memory array 100 described herein. Memory cell 425 is coupled to word line 410 and bit line 420 and can operate as described herein.

[0063] Figure 4 The example shown includes a driver 450 (e.g., word line driver 450) coupled to word line 410. Word line driver 450 may supply bipolar (e.g., positive and negative) current and / or voltage signals to word line 410. A sense amplifier 430, which may include a cross-coupled latch, may be coupled to word line driver 450 and may detect positive and negative currents and / or positive and negative voltages on word line 410. In some instances, sense amplifier 430 may be part of word line driver 450 (e.g., included within word line driver 450). For example, word line driver 450 may include the sensing functionality of sense amplifier 430. Bit line driver 452 is coupled to bit line 420 to supply positive and / or negative current and / or voltage signals to bit line 420.

[0064] The sense amplifier 430 and word line driver 450 are coupled to a latch 440 for storing a data value indicating whether a burst event of the memory cell 425 has occurred in response to an applied voltage difference. For example, the output signal 454 of the sense amplifier 430 is coupled to the latch 440 such that, in response to a burst event of the memory cell 425 detected via the sense amplifier 430, the output signal 454 causes an appropriate data value to be latched in the latch 440 (e.g., a data value "1" or "0", depending on which data value is used to indicate the detected burst event). As an example, if the latched data value "1" is used to indicate a detected burst event, then signal 454 will cause the latch 440 to latch a logic data value of 1 in response to a detected burst event of cell 425, and vice versa. The output signal 454 of the sense amplifier 430 may also be coupled to a delay circuit, as will be referred to herein (e.g., in conjunction with...). Figure 5 Further description.

[0065] When a positive voltage difference VDM1 is applied to memory cell 425 (e.g., word line voltage VWL1 is low and bit line voltage VBL1 is high) and memory cell 425 is in storage state 0, the voltage difference VDM1 can be greater than the threshold voltage Vtst12. Figure 2C Furthermore, memory cell 425 can suddenly revert to a conductive state, thereby causing Figure 2CThe positive current shown flows from bit line 420 through memory cell 425 to word line 410. Sensing amplifier 430 can detect this current and / or its associated voltage, and can output signal 454 to latch 440 in response to the detection of this current and / or voltage. For example, signal 454 can indicate to latch 440 (e.g., by having a logic high value) that the current is positive, and therefore the word line voltage is high. In response to signal 454 indicating a high word line voltage, latch 440 can output signal 456 (e.g., voltage) to circuitry 458 of word line driver 450 or circuitry 458 coupled to word line driver 450, which shuts off (e.g., disables) the current through word line 410 and therefore through memory cell 425.

[0066] In this example, when a negative voltage difference VDM2 is applied to memory cell 425 (e.g., word line voltage VWL2 is high and bit line voltage VBL2 is low) and memory cell 425 is in state 1, the voltage difference VDM2 (in the negative direction) is greater than the threshold voltage Vtst01. Figure 2B Furthermore, memory cell 425 can suddenly revert to a conductive state, thereby causing Figure 2B The negative current shown flows from word line 410 through memory cell 425 to bit line 420. Sensing amplifier 430 can detect this current and / or its associated voltage, and can output signal 454 to latch 440 in response to the detection of this current and / or voltage. For example, signal 454 can indicate to latch 440 (e.g., by having a logic low value) that the current is negative, and therefore the word line voltage is low. In response to signal 454 indicating a low word line voltage, latch 440 can output signal 460 (e.g., voltage) to circuitry 462 of word line driver 450 or circuitry 462 coupled to word line driver 450, which shuts off the current through word line 410. In some instances, sensing amplifier 430 and circuitry 458 and 462 may be referred to as detection circuitry.

[0067] Figure 5 This describes an example of a portion of a memory array 500 according to an embodiment of the present disclosure. The memory array 500 may be a previously combined... Figure 1 and 4 A portion of the memory arrays 100 and / or 400 described herein. For example, memory array 500 may include a plurality of intersecting word lines 510-1 to 510-N and bit lines 520-1 to 520-M, wherein memory cells 525 are coupled to word lines 510-N and bit lines 520-M that can operate as described herein.

[0068] Different corresponding word line drivers can be coupled to each corresponding word line 510-1 to 510-N, and each different corresponding word line driver is similar to a combination Figure 4 The described drive 450 and in Figure 5 The common specification is word line driver 550. Similarly, different corresponding bit line drivers can be coupled to each corresponding bit line 520-1 to 520-M, each different corresponding bit line driver being similar to a combination of Figure 4 The described driver 452 and in Figure 5 The common description is bit line driver 552. The current supplied to word lines 510-1 to 510-N by each corresponding word line driver 550 can be controlled by... Figure 5 The current control circuit 574 shown in the figure controls the current supplied to bit lines 520-1 to 520-M by each corresponding bit line driver 552. Figure 5 The current control circuit shown in the image is controlled by 576.

[0069] like Figure 5 As shown, the sense amplifier 530 can be coupled to word line driver 550 and bit line driver 552, and / or coupled to current control circuits 574 and 576, respectively. The sense amplifier 530 can be, for example, combined with... Figure 4 The described sense amplifier 430 is capable of sensing a burst event occurring in memory cell 525, as previously described herein. After sense amplifier 530 senses a burst event in memory cell 525, sense amplifier 530 (e.g., the output of sense amplifier 530) can provide feedback to turn off (e.g., disable) word line drivers 550 and / or bit line drivers 552, respectively coupled to word lines 510-N and / or bit lines 520-M, and / or to turn off current control circuits 574 and / or 576, respectively coupled to word line drivers 550 and / or bit line drivers 552, to cut off current to memory cell 525. After the current to memory cell 525 has been cut off, multiple short voltage pulses can be applied to memory cell 525 to program the cell into one of multiple possible data states, as previously described herein.

[0070] like Figure 5 As shown, delay circuitry 572 may be coupled to sense amplifier 530 (e.g., coupled to the output of sense amplifier 530). Delay circuitry 572 may be used (e.g., programmed to) provide a short delay, such as (e.g.) 4 ns, between the time when sense amplifier 530 senses a backflow event in memory cell 525 and the time when feedback is provided to turn off the current to memory cell 525. Such delay may alter the effect of a short voltage pulse applied to memory cell 525 after the current has been turned off on the memory cell (e.g., on the cell's threshold voltage). Alternatively, delay circuitry 572 may be bypassed so that no such delay is provided and feedback is provided to turn off the current to memory cell 525 as quickly as possible (e.g., immediately after sense amplifier senses a backflow event in the cell).

[0071] Figure 6 An example of the voltage applied to a memory cell and the current flowing through the memory cell according to an embodiment of the present disclosure is illustrated in the form of graph 635. For example, graph 635 may illustrate the voltage applied to the memory cell and the current flowing through the memory cell during operation of programming the memory cell into one of a plurality of possible data states, according to the present disclosure. The memory cell may be, for example, previously combined with… Figure 1 , 4 The memory cells 125, 425 and / or 525 described in 5.

[0072] exist Figure 6 Prior to time t1 shown, a bias voltage pulse with a sufficiently high magnitude to cause a memory cell to buckle back is applied to the memory cell. The bias voltage pulse may include a voltage pulse 641 (e.g., VBL) applied to the bit line coupled to the memory cell and a voltage pulse 643 (e.g., VWL) applied to the word line coupled to the memory cell. Figure 6 In the example described herein, the intermediate level voltage of curve 635 can be 2.75V, and the high level voltage of curve 635 can be 5.5V.

[0073] exist Figure 6 At time t1, as shown in the diagram, the memory cell bucks back in response to an applied bias voltage pulse. When the memory cell bucks back, a current pulse 637 flows through the cell, which can be used to detect the bucking event, as previously described herein. For example, as the current dissipates after time t1, the voltage (e.g., VWL) coupled to the word line of the memory cell increases, as in... Figure 6 As explained in [the document / reference]. Figure 6 At time t2, as shown in the diagram, VWL reaches the voltage threshold level. When VWL reaches the voltage threshold level, it can be determined that the memory cell has experienced a sudden return. For example, the sense amplifier (e.g., previously combined with...) Figure 4 and 5 The described sensing amplifiers 430 and / or 530 can sense that VWL has reached a voltage threshold level, as previously described herein. Figure 6 In the example described, the voltage threshold level can be 0.45V. Additionally, the time interval between t1 and t2 can be 1ns.

[0074] Once it is determined that a memory cell has surged back, the current to the memory cell can be shut off (e.g., disabled), as previously described herein. For example, in Figure 6 In the example described, the current to the memory cell is turned off at time t3. That is, at... Figure 6In the example described, there is a short delay between the time t2 when the memory cell is determined to have returned and the time t3 when the current to the memory cell is turned off. This delay (e.g., the amount of time between t2 and t3) can be, for example, 4 ns. When the current to the memory cell is turned off, no current flows through the cell, as... Figure 6 As explained in the text.

[0075] After the current to the memory cell has been turned off, multiple (e.g., N) additional voltage pulses may be sequentially applied to the memory cell, as previously described herein. Each corresponding additional voltage pulse may include a voltage pulse (e.g., VBL) applied to a bit line coupled to the memory cell and a voltage pulse (VWL) applied to a word line coupled to the memory cell. For example, in Figure 6 In the example described herein, at time t4, a first additional voltage pulse, including a voltage pulse 645-1 applied to the bit line and a voltage pulse 647-1 applied to the word line, is applied to the memory cell; at time t6, a second additional voltage pulse, including a voltage pulse 645-2 applied to the bit line and a voltage pulse 647-2 applied to the word line, is applied to the memory cell; and at time tN-1, a Nth additional voltage pulse, including a voltage pulse 645-N applied to the bit line and a voltage pulse 647-N applied to the word line, is applied to the memory cell.

[0076] Additionally, each corresponding additional voltage pulse is applied to the memory cell within a short time interval (e.g., a first additional pulse is applied from time t4 to time t5, a second additional pulse is applied from time t6 to time t7, and an Nth additional pulse is applied from time tN-1 to time tN), as in Figure 6 As explained in the document. For example, the duration of each corresponding additional voltage pulse (e.g., the amount of time between time t4 and time t5, the amount of time between time t6 and time t7, and the amount of time between time tN-1 and time tN) can be 5 ns.

[0077] When each corresponding additional voltage pulse is applied to a memory cell, an additional current pulse flows through the memory cell. For example, in Figure 6 In the example described herein, when a first additional voltage pulse is applied to the cell, current pulse 639-1 flows through the memory cell; when a second additional voltage pulse is applied to the cell, current pulse 639-2 flows through the memory cell; and when an Nth additional voltage pulse is applied to the cell, current pulse 639-N flows through the memory cell. The additional current pulses can be used to program the memory cell into one of a plurality of possible data states, as previously described herein.

[0078] Figure 7This is a block diagram illustration of an example device (e.g., electronic memory system 700) according to an embodiment of the present disclosure. The memory system 700 includes devices, such as memory means 702; and a controller 704, such as a memory controller (e.g., a host controller). The controller 704 may include, for example, a processor. The controller 704 may be coupled to, for example, a host and may receive command signals (or commands), address signals (or addresses), and data signals (or data) from the host, and may output data to the host.

[0079] Memory device 702 includes a memory array 706 of memory cells. For example, memory array 706 may include one or more of the memory arrays of memory cells disclosed herein, such as a cross-point array.

[0080] Memory device 702 includes address circuitry 708 for latching address signals provided via I / O connection 710 through I / O circuitry 712. The address signals are received and decoded by row decoder 714 and column decoder 716 to access memory array 706. For example, row decoder 714 and / or column decoder 716 may include drivers, such as those previously described. Figure 4 and 5 The described drives are 450, 452, 550 and / or 552.

[0081] Memory device 702 can sense (e.g., read) data in memory array 706 by sensing voltage and / or current changes in the memory array columns using a sensing / buffering circuit, which in some instances may be a read / latch circuit 720. The read / latch circuit 720 can read and latch data from memory array 706. I / O circuitry 712 is included for bidirectional data communication with controller 704 via I / O connection 710. Write circuitry 722 is included for writing data to memory array 706.

[0082] The control circuit 724 can decode signals provided by the control connection 726 from the controller 704. These signals may include chip signals, write enable signals, and address latch signals for controlling operations on the memory array 706 (including data read and data write operations).

[0083] Control circuitry 724 may be included, for example, in controller 704. Controller 704 may include other circuitry, firmware, software, or the like, whether individually or in combination. Controller 704 may be an external controller (e.g., in a die separate from memory array 706, whether wholly or partially) or an internal controller (e.g., contained in the same die as memory array 706). For example, an internal controller may be a state machine or a memory sequencer.

[0084] In some instances, controller 704 may be configured to cause memory device 702 to perform at least the methods disclosed herein, such as programming memory cells of array 706 into one of a plurality of possible data states. In some instances, memory device 702 may include previously combined... Figure 4 And / or the circuit described in 5. For example, memory device 702 may include sense amplifier circuitry and latches, such as sense amplifiers 430 and / or 530, latches 440 and / or delay circuitry 572 disclosed herein.

[0085] As used herein, the term “coupled” may include electrical coupling, direct coupling, and / or direct connection (e.g., through direct physical contact) without an intervening element, or indirect coupling and / or connection with an intervening element. The term “coupled” may further include two or more elements that cooperate or interact with each other (e.g., causally related).

[0086] Those skilled in the art will understand that additional circuitry and signals can be provided, and the process has been simplified. Figure 7 The memory system 700. It should be recognized that, reference... Figure 7 The functionality of the various block components described may not necessarily be separated into different components or component parts of the integrated circuit device. For example, a single component or component part of the integrated circuit device may be adapted to perform... Figure 7 The functionality of more than one block component. Alternatively, one or more components or component portions of an integrated circuit device can be combined to perform... Figure 7 The functionality of a single block component.

[0087] Although specific embodiments have been illustrated and described herein, those skilled in the art will understand that arrangements that achieve the same results can replace the specific embodiments shown. This disclosure is intended to cover adaptations or variations of various embodiments of this disclosure. It should be understood that the above description is made in an illustrative rather than limiting manner. After reviewing the above description, combinations of the above embodiments and other embodiments not specifically described herein will be apparent to those skilled in the art. The scope of the various embodiments of this disclosure includes other applications using the above structures and methods. Therefore, the scope of the various embodiments of this disclosure should be determined by referring to the full scope of the appended claims together with the equivalents granted by such claims.

[0088] In the foregoing embodiments, for the purpose of simplification, some features are grouped together in a single embodiment. This approach of the present disclosure should not be interpreted as reflecting an intention that the disclosed embodiments of the present disclosure must use more features than are expressly stated in each technical solution. Rather, as reflected in the following claims, the subject matter of the invention lies in fewer than all the features of a single disclosed embodiment. Therefore, the following claims are hereby incorporated into the embodiments, wherein each technical solution is an individual embodiment in itself.

Claims

1. A memory device (700) comprising: The memory (100, 400, 500, 706) has multiple memory cells (125, 425, 525); and Circuit (704) configured to program memory cells (125, 425, 525) of the plurality of memory cells (125, 425, 525) into one of a plurality of possible data states by means of: Voltage pulses (641, 643) are applied to the memory cells (125, 425, 525); It is determined that the memory cells (125, 425, 525) suddenly return in response to the applied voltage pulse (641, 643); After a sudden return is detected in the memory cells (125, 425, 525), the current to the memory cells (125, 425, 525) is turned off. and After the current to the memory cell is turned off, multiple additional voltage pulses (645-1, 645-2...645-N, 647-1, 647-2...647-N) are applied to the memory cell (125, 425, 525). The plurality of possible data states include: A first data state, which is associated with a first threshold voltage distribution, the magnitude of which is greater for a first polarity than for a second polarity; A second data state, which is associated with a second threshold voltage distribution, the magnitude of which is greater with respect to the second polarity than to the first polarity; A third data state, which is associated with a third threshold voltage distribution, wherein the magnitude of the third threshold voltage distribution is greater for the second polarity than for the first polarity; and A fourth data state, which is associated with a fourth threshold voltage distribution, the magnitude of which is greater for the first polarity than for the second polarity.

2. The memory device of claim 1, wherein the circuitry includes a sensing circuit having a sensing amplifier (430, 530) configured to sense the surge of the memory cell in response to the applied voltage pulse.

3. The memory device according to claim 1 or 2, wherein each of the plurality of memory cells is a selectable memory cell in which a single material is used as both a selection element and a storage element.

4. The memory device of claim 1 or 2, wherein the circuitry is configured to immediately shut off the current to the memory cell upon determining that the memory cell has experienced a sudden return.

5. The memory device of claim 1 or 2, wherein the circuitry is configured to shut off the current to the memory cell after a specific amount of time has elapsed following a determination that the memory cell has experienced a sudden return.

6. The memory device of claim 1, wherein the circuitry is configured to determine one of the plurality of possible data states of the memory cell by applying a series of different voltages to the memory cell until it is determined that the memory cell abruptly returns in response to one of the series of applied voltages.

7. A method for operating a memory (100, 400, 500, 706), comprising: The memory cells (125, 425, 525) are programmed to one of at least four possible data states using the following operations: Voltage pulses (641, 643) are applied to the memory cells (125, 425, 525); It is determined that the memory cells (125, 425, 525) suddenly return in response to the applied voltage pulse (641, 643); After a sudden return is detected in the memory cells (125, 425, 525), the current to the memory cells (125, 425, 525) is turned off. and After the current to the memory cells (125, 425, 525) is turned off, multiple additional voltage pulses (645-1, 645-2...645-N, 647-1, 647-2...647-N) are applied to the memory cells (125, 425, 525). The four possible data states include: A first data state, which is associated with a first threshold voltage distribution, the magnitude of which is greater for a first polarity than for a second polarity; A second data state, which is associated with a second threshold voltage distribution, the magnitude of which is greater with respect to the second polarity than to the first polarity; A third data state, which is associated with a third threshold voltage distribution, wherein the magnitude of the third threshold voltage distribution is greater for the second polarity than for the first polarity; and A fourth data state, which is associated with a fourth threshold voltage distribution, the magnitude of which is greater for the first polarity than for the second polarity.

8. The method of claim 7, wherein the plurality of additional voltage pulses are applied to the memory cell to incrementally change the threshold voltage of the memory cell.

9. The method of claim 7 or 8, wherein determining that the memory cell suddenly returns in response to the applied voltage pulse includes sensing a voltage change associated with the memory cell in response to the applied voltage pulse, and wherein sensing the voltage change associated with the memory cell includes sensing that the voltage on the signal lines (110, 410, 510) coupled to the memory cell meets or exceeds a specific voltage threshold.

10. The method of claim 7 or 8, wherein the method comprises turning off the current to the memory cell by turning off the driver (450, 452, 550, 552) coupled to the memory cell.

11. A method for operating a memory (100, 400, 500, 706), comprising: The memory cells (125, 425, 525) are programmed into one of four possible data states using the following operations: Voltage pulses (641, 643) are applied to the memory cells (125, 425, 525); It is determined that the memory cells (125, 425, 525) suddenly return in response to the applied voltage pulse (641, 643); After a sudden return is detected in the memory cells (125, 425, 525), the current to the memory cells (125, 425, 525) is turned off. and After the current to the memory cells (125, 425, 525) is turned off, a first number of additional voltage pulses (645-1, 645-2...645-N, 647-1, 647-2...647-N) are applied to the memory cells (125, 425, 525), wherein each of the first number of additional voltage pulses (645-1, 645-2...645-N, 647-1, 647-2...647-N) has a first polarity or each of the first number of additional voltage pulses (645-1, 645-2...645-N, 647-1, 647-2...647-N) has a second polarity opposite to the first polarity; or After the current to the memory cells (125, 425, 525) is turned off, a second number of additional voltage pulses (645-1, 645-2...645-N, 647-1, 647-2...647-N) are applied to the memory cells (125, 425, 525), wherein each of the second number of additional voltage pulses (645-1, 645-2...645-N, 647-1, 647-2...647-N) has the first polarity or each of the second number of additional voltage pulses (645-1, 645-2...645-N, 647-1, 647-2...647-N) has the second polarity. The four possible data states include: A first data state, which is associated with a first threshold voltage distribution, wherein the magnitude of the first threshold voltage distribution is greater with respect to the first polarity than to the second polarity; A second data state, which is associated with a second threshold voltage distribution, the magnitude of which is greater with respect to the second polarity than to the first polarity; A third data state, which is associated with a third threshold voltage distribution, wherein the magnitude of the third threshold voltage distribution is greater for the second polarity than for the first polarity; and A fourth data state, which is associated with a fourth threshold voltage distribution, the magnitude of which is greater for the first polarity than for the second polarity.

12. The method according to claim 11, wherein: The first number of additional voltage pulses includes one additional voltage pulse; and The second number of additional voltage pulses includes two additional voltage pulses.

13. The method according to claim 12, wherein: An additional voltage pulse is applied to the memory cell, and the memory cell is programmed to the first data state when the additional voltage pulse has a negative polarity, and programmed to the second data state when the additional voltage pulse has a positive polarity. and The two additional voltage pulses are applied to the memory cell, and the memory cell is programmed to the third data state if each of the two additional voltage pulses has a negative polarity, and the memory cell is programmed to the fourth data state if each of the two additional voltage pulses has a positive polarity.

14. A memory device (700) comprising: Memory (100, 400, 500, 706), which has multiple memory cells (125, 425, 525); and Circuit (704) configured to program memory cells (125, 425, 525) of the plurality of memory cells (125, 425, 525) into one of six possible data states by means of: Voltage pulses (641, 643) are applied to the memory cells (125, 425, 525); It is determined that the memory cells (125, 425, 525) suddenly return in response to the applied voltage pulse (641, 643); After a sudden return is detected in the memory cells (125, 425, 525), the current to the memory cells (125, 425, 525) is turned off. and After the current to the memory cells (125, 425, 525) is turned off, a first number of additional voltage pulses (645-1, 645-2...645-N, 647-1, 647-2...647-N) are applied to the memory cells (125, 425, 525), wherein each of the first number of additional voltage pulses (645-1, 645-2...645-N, 647-1, 647-2...647-N) has a first polarity or each of the first number of additional voltage pulses (645-1, 645-2...645-N, 647-1, 647-2...647-N) has a second polarity opposite to the first polarity; or After the current to the memory cells (125, 425, 525) is turned off, a second number of additional voltage pulses (645-1, 645-2...645-N, 647-1, 647-2...647-N) are applied to the memory cells (125, 425, 525), wherein each of the second number of additional voltage pulses (645-1, 645-2...645-N, 647-1, 647-2...647-N) has the first polarity or each of the second number of additional voltage pulses (645-1, 645-2...645-N, 647-1, 647-2...647-N) has the second polarity; or After the current to the memory cells (125, 425, 525) is turned off, a third number of additional voltage pulses (645-1, 645-2...645-N, 647-1, 647-2...647-N) are applied to the memory cells (125, 425, 525), each of the third number of additional voltage pulses (645-1, 645-2...645-N, 647-1, 647-2...647-N) having the first polarity or each of the third number of additional voltage pulses (645-1, 645-2...645-N, 647-1, 647-2...647-N) having the second polarity. The six possible data states include: A first data state, which is associated with a first threshold voltage distribution, wherein the magnitude of the first threshold voltage distribution is greater with respect to the first polarity than to the second polarity; A second data state, which is associated with a second threshold voltage distribution, the magnitude of which is greater with respect to the second polarity than to the first polarity; A third data state, which is associated with a third threshold voltage distribution, the magnitude of which is greater for the second polarity than for the first polarity; and A fourth data state, which is associated with a fourth threshold voltage distribution, the magnitude of which is greater for the first polarity than for the second polarity.

15. The memory device of claim 14, wherein: The first number of additional voltage pulses includes two additional voltage pulses; The second number of additional voltage pulses includes four additional voltage pulses; and The third number of additional voltage pulses includes six additional voltage pulses.

16. The memory device of claim 15, wherein: If the threshold voltage is the first polarity, then the third and fourth additional voltage pulses of the four additional voltage pulses are applied to the memory cell to change the value of the threshold voltage of the memory cell. and If the threshold voltage is the second polarity, then applying the third and fourth additional voltage pulses of the four additional voltage pulses to the memory cell does not change the magnitude of the threshold voltage of the memory cell.

17. The memory device according to claim 15, wherein: If the threshold voltage is the first polarity, then the fifth and sixth additional voltage pulses of the six additional voltage pulses are applied to the memory cell to change the value of the threshold voltage of the memory cell; and If the threshold voltage is the second polarity, then applying the fifth and sixth additional voltage pulses of the four additional voltage pulses to the memory cell does not change the magnitude of the threshold voltage of the memory cell.

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