Multi-chip stacked device

Abstract

The examples described in this application generally relate to multi-chip devices having stacked chips. In one example, the multi-chip device includes a chip stack comprising multiple chips. Each of one or more chips includes a selection circuit and a disconnected via pillar, the disconnected via pillar including first and second continuous portions. The first continuous portion includes a substrate through-via and a first metal line. The second continuous portion includes a second metal line. The first and second metal lines are disposed within a dielectric layer disposed on one side of a semiconductor substrate of their respective chips. The first and second continuous portions are aligned in a direction perpendicular to one side of the semiconductor substrate. An input node of the selection circuit is connected to one of the first or second metal lines. An output node of the selection circuit is connected to the other of the first or second metal lines.

Description

Technical Field

[0001] The examples disclosed herein generally relate to multi-chip devices that include stacked chips. Technical Background

[0002] Devices comprising multiple integrated circuit chips have been developed, including modules and / or packages. Such devices take many forms. By forming such devices, electronic devices can integrate multiple chips to form a device, where each chip can be manufactured using standard semiconductor processes, and then assembled and packaged to form a larger, more versatile device. By having different chips, semiconductor processes that are difficult to integrate in certain situations can be separated, such as when a portion of one chip requires a different process than another chip.

[0003] On the other hand, there's the ability to build devices with different functionalities (e.g., some are field-programmable gate array (FPGA) chips, and some are memory chips) into the same device with a smaller size, more functionality, and lower power consumption. Semiconductor processes for the chip can then be more focused on providing greater advantages to the device, such as improved chip performance, reduced costs, and increased manufacturing yield. Such devices can also achieve other benefits. Summary of the Invention

[0004] The examples described herein generally relate to multi-chip devices with vertically stacked chips. More specifically, some examples described herein relate to the in-chip structure and circuitry of a chip stack for inputting and outputting signals between chips. Some examples can reduce the number of substrate through-holes (TSVs) in the chip, reduce bottlenecks in wiring in the metal layers of the chip, enable flexibility in signal communication, and allow different chips in the chip stack to have the same integrated circuits and hardware, etc.

[0005] The example described herein is a multi-chip device. A multi-chip device includes a chip stack. The chip stack includes multiple chips. Adjacent chip pairs in the chip stack are interconnected. One or more of the multiple chips each include a first disconnected via pillar and a first selection circuit. The first disconnected via pillar includes a first continuous portion and a second continuous portion. The first continuous portion includes a first TSV and a first metal line. The first TSV passes through the semiconductor substrate of the respective chip. The first metal line is disposed within a dielectric layer group disposed on one side of the semiconductor substrate of the respective chip. The second continuous portion includes a second metal line. The second metal line is disposed within the dielectric layer group. The first continuous portion and the second continuous portion are aligned in a direction perpendicular to one side of the semiconductor substrate. The first continuous portion is not connected to the second continuous portion. A first input node of the first selection circuit is connected to one of the first metal line or the second metal line. An output node of the first selection circuit is connected to the other of the first metal line or the second metal line.

[0006] Another example described herein is a method of operating a multi-chip device. A first signal is received at a first selection circuit from a first continuous portion of a first disconnected via post. The first disconnected via post is located in the first chip of a plurality of chips in a chip stack. Adjacent chip pairs in the chip stack are attached to each other. A second signal from the first selection circuit is transmitted through a second continuous portion of the first disconnected via post. One of the first and second continuous portions includes a first TSV (Transient Via) passing through a semiconductor substrate of the first chip. The first and second continuous portions are aligned in a direction perpendicular to one side of the semiconductor substrate. The first continuous portion is not connected to the second continuous portion.

[0007] Another example described herein is a multi-chip device. The multi-chip device includes a first chip and a second chip attached to the first chip. The first chip includes a first selection circuit, a first disconnected via post, a second selection circuit, and a second disconnected via post. The first disconnected via post extends through a first semiconductor substrate of the first chip and a first set of dielectric layers on a first side of the first semiconductor substrate. The first disconnected via post includes a first continuous portion and a second continuous portion. The first continuous portion includes a first TSV (Transient Voltage Segment) extending through the first semiconductor substrate. The output node of the first selection circuit is connected to the first continuous portion. The second continuous portion is aligned with the first continuous portion in a direction perpendicular to the first side of the first semiconductor substrate. The second continuous portion is connected to a first input node of the first selection circuit. The second disconnected via post extends through the first semiconductor substrate and the first set of dielectric layers. The second disconnected via post includes a third continuous portion and a fourth continuous portion. The third continuous portion includes a second TSV (Transient Voltage Segment) extending through the first semiconductor substrate. The third continuous portion is connected to a first input node of the second selection circuit. The fourth continuous portion is aligned with the third continuous portion in a direction perpendicular to the first side of the first semiconductor substrate. The output node of the second selection circuit is connected to the fourth continuous portion.

[0008] Some additional, non-limiting examples of this disclosure may be expressed as follows.

[0009] Example 1: A multi-chip device, comprising:

[0010] A chip stack comprising a plurality of chips, wherein adjacent chips in the chip stack are attached to each other, and one or more of the plurality of chips each include a first disconnected via post and a first selection circuit, the first disconnected via post comprising:

[0011] A first continuous portion includes a first substrate through-hole (TSV) and a first metal line, the first TSV passing through the semiconductor substrate of the respective chip, the first metal line being disposed within a dielectric layer group disposed on one side of the semiconductor substrate of the respective chip; and

[0012] The second continuous portion includes a second metal line disposed within a dielectric layer group. The first continuous portion and the second continuous portion are aligned in a direction perpendicular to one side of the semiconductor substrate. The first continuous portion is not connected to the second continuous portion. The first input node of the first selection circuit is connected to one of the first metal line or the second metal line, and the output node of the first selection circuit is connected to the other of the first metal line or the second metal line.

[0013] Example 2: According to the multi-chip device of Example 1, each of the one or more chips further includes another circuit, wherein a second input node of the first selection circuit is connected to the output node of the other circuit.

[0014] Example 3: In the multi-chip device according to Example 2, the first metal line or the second metal line connected to the first input node of the first selection circuit is also connected to the input node of the other circuit.

[0015] Example 4: The multi-chip device according to Example 2, wherein the first selection circuit is configured to selectively output a signal received from a first input node or a second input node of the first selection circuit at the output node of the first selection circuit.

[0016] Example 5: The multi-chip device according to Example 2, wherein the other circuit includes programmable logic circuitry.

[0017] Example 6: The multi-chip device according to Example 1, wherein the first input node of the first selection circuit is connected to the first metal line, and the output node of the first selection circuit is connected to the second metal line.

[0018] Example 7: The multi-chip device according to Example 1, wherein the first input node of the first selection circuit is connected to the second metal line, and the output node of the first selection circuit is connected to the first metal line.

[0019] Example 8: The multi-chip device according to Example 1, wherein each of the one or more chips includes a second disconnected via post and a second selection circuit, the second disconnected via post comprising:

[0020] The third continuous portion includes a second TSV and a third metal line, the second TSV passing through the semiconductor substrate of its respective chip, and the third metal line disposed within a dielectric layer group; and

[0021] The fourth continuous portion includes a fourth metal line disposed within the dielectric layer group. The third and fourth continuous portions are aligned in a direction perpendicular to one side of the semiconductor substrate. The third continuous portion is not connected to the fourth continuous portion. The input node of the second selection circuit is connected to the third metal line, and the output node of the second selection circuit is connected to the fourth metal line. The first input node of the first selection circuit is connected to the second metal line, and the output node of the first selection circuit is connected to the first metal line.

[0022] Example 9: The multi-chip device according to Example 1, wherein the first selection circuit includes a multiplexer, the first input node of the first selection circuit is the first input node of the multiplexer, and the output node of the first selection circuit is the output node of the multiplexer.

[0023] Example 10: A method for operating a multi-chip device, the method comprising:

[0024] A first signal is received at a first selection circuit from a first continuous portion of a first disconnected via post, the first disconnected via post being in the first chip of a plurality of chips in a chip stack, adjacent chip pairs in the chip stack being attached to each other; and

[0025] A second signal from the first selection circuit is transmitted through a second continuous portion of the first disconnected via post. One of the first and second continuous portions includes a first substrate through-hole (TSV) through the semiconductor substrate of the first chip. The first and second continuous portions are aligned in a direction perpendicular to one side of the semiconductor substrate. The first continuous portion is not connected to the second continuous portion.

[0026] Example 11: The method according to Example 10 further includes receiving the first signal at another circuit of the first chip.

[0027] Example 12: The method according to Example 10 further includes receiving a third signal from another circuit of the first chip at the first selection circuit, wherein the first selection circuit selectively transmits either the first signal or the third signal as the second signal.

[0028] Example 13: The method according to Example 12 further includes configuring the first selection circuit to transmit the first signal or the third signal as the second signal.

[0029] Example 14: The method according to Example 10, wherein the first continuous portion includes the first TSV.

[0030] Example 15: The method according to Example 10, wherein the second continuous portion includes the first TSV.

[0031] Example 16: The method described in Example 10 further includes:

[0032] A third signal is received at the second selection circuit from a third continuous portion of the second disconnected via post, the second disconnected via post being in the first chip, the third continuous portion including a second TSV passing through the semiconductor substrate, and the second continuous portion including a first TSV; and

[0033] The fourth signal from the second selection circuit is transmitted through the fourth continuous portion of the second disconnected through-hole post. The third and fourth continuous portions are aligned in a direction perpendicular to one side of the semiconductor substrate, and the third continuous portion is not connected to the fourth continuous portion.

[0034] Example 17: According to the method described in Example 10, wherein:

[0035] The first signal is received from a second chip in a stack of chips via a first continuous portion; and

[0036] The second signal is transmitted through a second continuous section to a third chip in a chip stack, wherein the first chip is disposed between the second and third chips in the chip stack.

[0037] Example 18: A multi-chip device, comprising:

[0038] The first chip includes:

[0039] First selection circuit;

[0040] A first disconnected via post extends through a first semiconductor substrate of the first chip and a first set of dielectric layers on a first side of the first semiconductor substrate, the first disconnected via post comprising:

[0041] A first continuous portion, including a first substrate through-hole (TSV) through a first semiconductor substrate, wherein the output node of a first selection circuit is connected to the first continuous portion; and

[0042] The second continuous portion is aligned with the first continuous portion in a direction perpendicular to the first side of the first semiconductor substrate, and the second continuous portion is connected to the first input node of the first selection circuit.

[0043] Second selection circuit; and

[0044] The second disconnected via post extends through the first semiconductor substrate and the first set of dielectric layers, and the second disconnected via post includes:

[0045] The third continuous portion includes a second TSV passing through the first semiconductor substrate, and the third continuous portion is connected to the first input node of the second selection circuit; and

[0046] A fourth continuous portion, aligned with the third continuous portion in a direction perpendicular to a first side of the first semiconductor substrate, wherein the output node of the second selection circuit is connected to the fourth continuous portion; and

[0047] A second chip is attached to the first chip.

[0048] Example 19: The multi-chip device according to Example 18, wherein the first chip further includes:

[0049] A first other circuit having an input node connected to a second continuous portion and an output node connected to a second input node of a first selection circuit; and

[0050] The second other circuit has an input node connected to the third continuous section and an output node connected to the second input node of the second selection circuit.

[0051] Example 20: The multi-chip device according to Example 18, wherein the second chip comprises:

[0052] Third selection circuit;

[0053] The third disconnected via post extends through the second semiconductor substrate of the second chip and the second set of dielectric layers on the second side of the second semiconductor substrate, the third disconnected via post comprising:

[0054] The fifth continuous portion includes a third TSV passing through the second semiconductor substrate, and the output node of the third selection circuit is connected to the fifth continuous portion; and

[0055] A sixth continuous portion, which is aligned with the fifth continuous portion in a direction perpendicular to the second side of the second semiconductor substrate, is connected to the first input node of the third selection circuit, and the first continuous portion is connected to the sixth continuous portion.

[0056] Fourth selection circuit; and

[0057] The fourth disconnected via post extends through the second semiconductor substrate and the second set of dielectric layers, and includes:

[0058] A seventh continuous portion, comprising a fourth TSV extending through the second semiconductor substrate, the seventh continuous portion being connected to the first input node of the fourth selection circuit; and

[0059] The eighth continuous portion is aligned with the seventh continuous portion in a direction perpendicular to the second side of the second semiconductor substrate, and the output node of the fourth selection circuit is connected to the eighth continuous portion; the third continuous portion is connected to the eighth continuous portion.

[0060] These and other aspects can be understood by referring to the following detailed explanation. Attached Figure Description

[0061] To gain a more detailed understanding of the features listed above, a more specific description of the above-brief summary can be obtained by referring to exemplary embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings illustrate only typical exemplary embodiments and should not be considered as limiting the scope thereof.

[0062] Figure 1 It is based on some examples of the structure of multi-chip devices with chip stacking.

[0063] Figure 2 It describes based on some examples. Figure 1 A block diagram of a multi-chip device, a stacked integrated circuit.

[0064] Figure 3 It is a simplified structure based on a portion of the Z-interface of some chips in a chip stack, as shown in some examples.

[0065] Figure 4 It is based on some examples and formed Figure 1 The flowchart shows the method for multi-chip devices.

[0066] Figure 5 It is a flowchart of a method for operating a multi-chip device, based on some examples.

[0067] For ease of understanding, the same reference numerals are used where possible to denote common elements in the figures. It is anticipated that elements of one example can be beneficially incorporated into other examples. Detailed Implementation

[0068] The examples described herein generally relate to multi-chip devices with vertically stacked chips. More specifically, some examples described herein relate to in-chip structures and circuitry for chip stacks used to transmit input and output signals between chips. One or more chips in a chip stack may include one or more disconnected via pillars and respective selection circuitry. Disconnected via pillars may include a first continuous portion and a second continuous portion aligned in a direction perpendicular to one side of the semiconductor substrate of the chip. As an example, the first continuous portion may include metal lines and / or vias in a backside dielectric layer on the backside of the semiconductor substrate, through-substrate vias (TSVs) through the semiconductor substrate, and metal lines and / or vias in a frontside dielectric layer on the front side of the semiconductor substrate. As an example, the second continuous portion may include metal lines and / or vias in a frontside dielectric layer on the front side of the semiconductor substrate. The first continuous portion is not connected to the second continuous portion.

[0069] The selection circuit is connected between the first and second continuous sections. One of the first and second continuous sections is connected to the first input node of the selection circuit and can be further connected to the input nodes of other circuits on the chip. The second input node of the selection circuit can be connected to the output node of other circuits on the chip. The other of the first and second continuous sections is connected to the output node of the selection circuit.

[0070] Disconnected via pillars and selection circuitry enable signal reception from, for example, an upper or lower chip in a chip stack, and signal output to, respectively, an upper or lower chip in the same stack via pillar. In some cases, signals received from, for example, an upper or lower chip can be transmitted through the disconnected via pillar and output to, for example, an upper or lower chip. Such a structure and selection circuitry can reduce the number of TSVs in a chip, for example, by half. Previously, via pillars including TSVs were dedicated to either input or output signals. Some examples described herein allow input and output signals to share disconnected via pillars (e.g., within the same region of the chip), which can reduce the total number of TSVs used for input and output signals by half. This can reduce bottlenecks in metal layer wiring within the chip. Furthermore, disconnected via pillars enable flexibility in signal communication and allow different chips in a chip stack to have the same integrated circuits (ICs) and hardware, which can reduce the number of chip variants to be designed and fabricated. Moreover, in some examples, control over the configurability of disconnected via pillars can be simplified compared to, for example, tri-state buffer solutions. These and other aspects of the examples will be described below. As will be readily apparent to those skilled in the art upon reading this disclosure, additional or other benefits may be obtained through various examples.

[0071] Various features will be described below with reference to the accompanying drawings. It should be noted that the drawings may or may not be drawn to scale, and elements with similar structures or functions are indicated by similar reference numerals in all the drawings. It should be noted that the drawings are intended only to facilitate the description of features. They are not intended as an exhaustive description of the claimed invention or as a limitation on the scope of the claimed invention. Furthermore, the illustrated examples do not need to possess all the aspects or advantages shown. Aspects or advantages described in conjunction with a particular example are not necessarily limited to that example and can be practiced in any other example, even if not so stated or explicitly described. Moreover, the methods described herein may be described in a particular order of operations, but other methods according to other examples may also be implemented in various other orders with more or fewer operations (e.g., including different sequential or parallel executions of various operations).

[0072] Figure 1 It is based on the structure of some example multi-chip devices. Figure 1The multi-chip device comprises a chip stack including a base chip 102 and fabric chips 104, 106, and 108. Base chip 102 and fabric chips 104-108 are described herein as examples. Although different chips are described or include various ICs or components (e.g., fabric, base, programmable logic, etc.) herein, the aspects described herein are generally applicable to chips in multi-chip devices having any type of IC or component.

[0073] exist Figure 1 In one multi-chip device, structure chips 104-108 are arranged with their active or front side facing downward toward the base chip 102, while the base chip 102 is arranged with its active or front side facing upward toward the structure chips 104-108. In other multi-chip devices, the intermediate structure chip is arranged with its active or front side facing upward away from the base chip 102, and the distal structure chip is arranged with its active or front side facing downward toward the base chip 102, while the base chip 102 is arranged with its active or front side facing upward toward the structure chips 104-108. Various other multi-chip devices may have different structures, different numbers of chips, additional components, etc.

[0074] Typically, chips 102-108 are stacked, forming a chip stack in a multi-chip device. In some examples, chips 102-108 are stacked to form an Active Die-on-Active Die (AoA) device. In some examples, more or fewer chips can be included in the chip stack. For example, a multi-chip device may have two chips, such as a base chip and a structure chip, or two structure chips. In other examples, a multi-chip device may have three chips, four chips, five chips, etc.

[0075] Each of chips 102-108 includes a respective semiconductor substrate 112, 114, 116, 118 and a respective front-side dielectric layer 122, 124, 126, 128 on the front side of the respective semiconductor substrate 112-118. The front-side dielectric layers 122-128 include metallization (e.g., metal lines and / or vias) formed therein, which can electrically connect various components in the IC. Each of chips 102-106 includes a respective back-side dielectric layer 132, 134, 136 on the back side of the respective semiconductor substrate 112-116. The back-side dielectric layers 132-136 include metallization (e.g., metal lines and / or vias) formed therein, which can electrically connect various components in the IC. As shown in the figure, the metallization in the front dielectric layers 124 and 126 of the structural chips 104 and 106 is connected to the respective circuit regions 143 and 145 of the structural chips 104 and 106, which will be described in more detail in the context of the following figures.

[0076] Each semiconductor substrate 112-118 of chips 102-108 includes, for example, transistors 142, 144, 146, 148 formed on and / or in the front surface of their respective semiconductor substrates 112-118. Transistors 142-148 and any other components may be connected to metallizations in the front dielectric layers 122-128. Transistors 144, 146 are shown in their respective circuit regions 143, 145 of the structure chips 104, 106; however, transistors 144, 146 and / or other transistors may be outside the circuit regions 143, 145. Each semiconductor substrate 112-116 of each chip 102-106 has back substrate through-holes (TSVs) 162, 164, 166 through which metallizations in the front dielectric layers 122-126 can be connected to metallizations in the back dielectric layers 132-136 of their respective chips 102-106.

[0077] Front bonding pads 152, 154, 156, 158 (e.g., metal (e.g., Cu) bonding pads) are formed in the respective front dielectric layers 122-128 of chips 102-108, at the outer surface remote from the respective semiconductor substrates 112-118. The front bonding pads 152-158 may be arranged to form their respective chip-to-chip interfaces. The front bonding pads 152-158 are connected to metallizations in their respective front dielectric layers 122-128. Back bonding pads 174, 176 (e.g., metal (e.g., Cu) bonding pads) are formed in the respective back dielectric layers 134, 136 of structure chips 104, 106, at the outer surface remote from the respective semiconductor substrates 114, 116. The back bonding pads 174, 176 may be arranged to form their respective chip-to-chip interfaces. Backside bonding pads 174 and 176 are connected to metallizations in their respective backside dielectric layers 134 and 136.

[0078] External connector back-side pads 172 (e.g., metal (e.g., aluminum) pads) are formed in the back-side dielectric layer 132 of the base chip 102, on the outer surface of the semiconductor substrate 112 away from the base chip 102. The external connector back-side pads 172 are connected to metallization in the back-side dielectric layer 132 of the base chip 102. A passivation layer 180 is formed on the outer surface of the semiconductor substrate 112 of the base chip 102, having respective openings that expose the external connector back-side pads 172. External connectors 182 (e.g., controlled collapse chip connections (C4), microbumps, etc.) are formed on the respective external connector back-side pads 172 through the openings in the passivation layer 180.

[0079] External connector 182 can be attached to the package substrate. The package substrate can be further attached to, for example, a printed circuit board (PCB) to attach the package substrate (and thus the multi-chip device) to the PCB. Various other components can be included in the multi-chip device. For example, interposers, sealants (e.g., molding compounds (MUFs), etc.) can be included in the multi-chip device. Various modifications that can be made to the multi-chip device will be readily apparent to those skilled in the art.

[0080] Chips 102-108 are bonded together (e.g., using a hybrid bonding method of metal-to-metal and oxide-to-oxide bonding) to form a chip stack. Base chip 102 is front-to-front bonded to structure chip 104 such that the outer surfaces of the front bonding pads 152 and the front dielectric layer 122 of base chip 102 are bonded to the outer surfaces of the front bonding pads 154 and the front dielectric layer 124 of structure chip 104. Structure chip 104 is back-to-front bonded to structure chip 106 such that the outer surfaces of the back bonding pads 174 and the back dielectric layer 134 of structure chip 104 are bonded to the outer surfaces of the front bonding pads 156 and the front dielectric layer 126 of structure chip 106. The structural chip 106 is bonded to the structural chip 108 from back to front, such that the outer surfaces of the back bonding pad 176 and the back dielectric layer 136 of the structural chip 106 are bonded to the outer surfaces of the front bonding pad 158 and the front dielectric layer 128 of the structural chip 108.

[0081] Other bonding methods can be implemented. For example, the base chip 102 can be bonded to the structure chip 104 from front to back, such that the outer surfaces of the front bonding pads 152 and the front dielectric layer 122 of the base chip 102 are bonded to the outer surfaces of the back bonding pads 174 and the back dielectric layer 134 of the structure chip 104. The structure chip 104 can be bonded to the structure chip 106 from front to back, such that the outer surfaces of the front bonding pads 154 and the front dielectric layer 124 of the structure chip 104 are bonded to the outer surfaces of the back bonding pads 176 and the back dielectric layer 136 of the structure chip 106. The structure chip 106 can be bonded to the structure chip 108 from front to front, such that the outer surfaces of the front bonding pads 176 and the front dielectric layer 126 of the structure chip 106 are bonded to the outer surfaces of the front bonding pads 158 and the front dielectric layer 128 of the structure chip 108.

[0082] In other examples, chips 102-108 can be connected together using external connectors (e.g., microbumps, solder, etc.). In some examples, some of chips 102-108 can be attached together via external connectors, while others can be bonded together without using external connectors. Any substitution of bonding and the use of external connectors can be achieved.

[0083] Any chip in the chip stack can include Z-interface circuitry. Z-interface circuitry is configurable and enables signal communication between chips in the chip stack. Z-interface circuitry can include select circuitry and disconnected via pillars including TSVs. Disconnected via pillars are connected to transmit signals from the select circuitry to the overlying or underlying chip. Signals from the select circuitry can selectively be (i) signals transmitted from and received by the disconnected via pillars, or (ii) signals transmitted from and received by another circuit on the chip. In some examples, the disconnected via pillars are disconnected, meaning that the disconnected via pillars may not be connected via metallization through the respective front dielectric layer of the chip, and a continuous portion of the disconnected via pillar is connected to an intermediate select circuitry. Further details of the Z-interface circuitry are described below. Any of chips 102-108 can include Z-interface circuitry, although in some examples, since the remote structure chip 108 may not undergo back-side processing, the TSVs and / or metallization in the back dielectric layer may be omitted from the remote structure chip 108.

[0084] In some examples, each structure chip 104-108 may include a processing IC. The processing ICs of structure chips 104-108 can typically be the same IC. In some examples, the hardware topology, architecture, and layout of structure chips 104-108 can be identical across structure chips 104, except that components formed by back-side processing, such as back-side TSVs, back-side dielectric layers, and / or metallizations in the back-side dielectric layers, may be omitted from the far-end structure chip 108. In some examples, the processing ICs of structure chips 104-108 may include one or more programmable logic regions (e.g., FPGA architecture) that can have the same hardware topology, architecture, and layout across structure chips 104-108. Having a Z-interface in structure chips 104-108 allows for the integration of chips undergoing the same front-side processing into multi-chip devices, while also allowing for flexibility in how structure chips 104-108 are interconnected.

[0085] In other examples, chips 102-108 may each be or include different ICs, or may have any substitutions including the same IC and / or different ICs. For example, any of the structure chips 104-108 may be or include a processing IC or memory. In some examples, chip 108 is an ASIC. Any chips 102-108 can generally be collectively referred to as active chips.

[0086] Figure 2 It is based on some examples and descriptions Figure 1 A block diagram illustrating the circuit schematic of a multi-chip device, specifically a stacked IC. In the example shown, the multi-chip device is a multi-chip programmable device. This circuit schematic can be found in... Figure 1It can be implemented in multi-chip devices, for example, regardless of the orientation of structure chips 104 and 106.

[0087] In the example shown, base chip 102 includes a base IC on base chip 102, which can be a System-on-a-Chip (SoC). Structure chips 104, 106, and 108 include respective programmable logic (PL) ICs 224, 226, and 228; in some examples, they may be the same IC and have the same hardware layout and topology. These ICs are provided as an example implementation. Other ICs (e.g., with additional hard IP blocks) may be implemented in the chip. Structure chips 104, 106, and 108 also include respective Z-interfaces 234, 236, and 238.

[0088] The basic IC on the base chip 102 includes a processing system 202, input / output (I / O) circuitry 204, IP core circuitry 206, on-chip network (NoC) 210, and Z-interface 232. The processing system 202 can be or includes any of a variety of different processor types and processor core numbers. For example, the processing system 202 can be implemented as a single processor, such as a single core capable of executing program instruction code. In another example, the processing system 202 can be implemented as a multi-core processor. The processing system 202 can be implemented using any of a variety of different architectures. Example architectures that can be used to implement the processing system 202 include ARM processor architecture, x86 processor architecture, graphics processing unit (GPU) architecture, mobile processor architecture, reduced instruction set computer (RISC) architecture (e.g., RISC-V), or other suitable architectures capable of executing computer-readable program instruction code.

[0089] Input / output circuitry 204 may include extreme performance input / output (XPIO), multi-gigabit transceivers (MGT), high-bandwidth memory (HBM) interfaces, analog-to-digital converters (ADCs), digital-to-analog converters (DACs), or any other input / output modules. Input / output circuitry 204 may be configured to receive and / or transmit signals to circuitry external to the multi-chip device. IP core circuitry 206 may include memory controllers (e.g., double data rate (DDR) memory controllers, high-bandwidth memory (HBM) memory controllers, etc.), peripheral component interconnect fast (PCIe) interfaces, cached coherent interconnect (CCIX) interfaces for accelerators, Ethernet cores (e.g., media address controllers (MACs), etc.), forward error correction (FEC) blocks, and / or any other hardened circuitry. Either input / output circuitry 204 and / or IP core circuitry 206 may be programmable.

[0090] NoC 210 includes a programmable network 212 and NoC peripheral interconnects (NPIs) 214. Programmable network 212 communicatively couples the subsystems of the base IC on base chip 102 with any other circuitry. Programmable network 212 includes NoC packet switches and interconnects connecting the NoC packet switches. Each NoC packet switch performs NoC packet switching within programmable network 212. Programmable network 212 has interface circuitry at its edges. The interface circuitry includes NoC master units (NMUs) and NoC slave units (NSUs). Each NMU is an entry circuit connecting master circuitry to programmable network 212, and each NSU is an exit circuit connecting programmable network 212 to slave endpoint circuitry. The NMUs are communicatively coupled to the NSUs via the NoC packet switches and interconnects of programmable network 212. The NoC packet switches are interconnected and connected to the NMUs and NSUs via interconnects to implement multiple physical channels within programmable network 212. NoC packet switches, NMUs, and NSUs include register blocks that determine the operation of their respective NoC packet switches, NMUs, or NSUs.

[0091] NPI 214 includes circuitry for writing register blocks that define the functionality of the NMU, NSU, and NoC packet switches. NPI 214 includes peripheral interconnects coupled to the register blocks for programming them to configure their functionality. The register blocks in the NMU, NSU, and NoC packet switches of programmable network 212 support interrupts, Quality of Service (QoS), error handling and reporting, transaction control, power management, and address mapping control. NPI 214 may include an NPI root node residing on processing system 202 (e.g., the Platform Management Controller (PMC) of processing system 202), interconnected NPI switches connected to the NPI root node, and protocol blocks connected to the interconnected NPI switches and their respective register blocks. NPI 214 can be used to program any programmable circuitry of the underlying IC on base chip 102. For example, NPI 214 can be used to program any programmable input / output circuitry 204 and / or IP core circuitry 206.

[0092] Z-interface 232 may include active circuitry, such as buffers for driving signals and / or selecting circuitry. Z-interface 232 provides the processing system 202, input / output circuitry 204, IP core circuitry 206, and the programmable network 212 of NoC 210 with an interface to a chip overlying the base chip 102 and / or a substrate (e.g., a package substrate) beneath the base chip 102, including via metal lines and vias 102 in the metallization layer. Additionally, Z-interface 232 may provide a pass-through interface through the base chip 102.

[0093] Various subsystems and circuits of the base IC on base chip 102 are communicatively coupled. As shown, processing system 202, input / output circuitry 204, and IP core circuitry 206 are connected to NoC 210 (e.g., to programmable network 212), and therefore communicatively coupled to each other. Processing system 202 is also connected to NPI 214 for transferring configuration data to various programmable components on base chip 102. Processing system 202 is also connected to programmable network 212 of NoC 210 for transferring configuration data to chips overlaid on base chip NoC 210. Programmable network 212 of NoC 210 is connected to Z-interface 232, allowing data such as transaction data and configuration data to be transferred to another chip via Z-interface 232. Each of processing system 202, input / output circuitry 204, and IP core circuitry 206 is connected to Z-interface 232 for communicating with programmable logic in PL ICs 224, 226, and 228 in overlaid structure chips 104 and 106. It can enable other communication mechanisms between various subsystems and circuits, such as direct connection.

[0094] Each PL IC 224-228 on each structure chip 104-108 includes one or more programmable logic regions. A programmable logic region is a logic circuit that can be programmed to perform a specified function. A programmable logic region can include any number or arrangement of programmable tiles. As an example, a programmable logic region can be implemented as an FPGA structure. For example, a programmable logic region can include any number of configurable logic blocks (CLBs), lookup tables (LUTs), digital signal processing blocks (DSPs), random access memory blocks (BRAMs), etc. Each programmable tile (e.g., CLB, LUT, DSP, BRAM, etc.) can include one or more programmable interconnect elements. For example, various corresponding types of programmable tiles can be arranged in rows and / or columns, and associated programmable interconnect elements can be connected to adjacent programmable logic elements in the same column and row. Programmable interconnect elements can form an interconnect network for the programmable logic region. Any logic and connections can be implemented by the programmable logic region through programming or configuring any programmable tile within the programmable logic region.

[0095] Z-interfaces 234-238 on each of the structure chips 104-108 may include active circuitry, such as buffers for driving signals and / or selecting circuitry. Z-interfaces 234-238 provide interfaces, including through-hole metal lines and through-holes in the metallization layer, for communication between the respective PL IC 224-228 and chips overlaid on or under the respective structure chips 104-108. Furthermore, Z-interfaces 234-238 may provide pass-through interfaces through the respective structure chips 104-108. For example, configuration data for the PL IC 224-228 can be transmitted via passive connections through Z-interfaces 234-238.

[0096] Each PL IC 224-228 may also include a configuration interconnect, which includes a configuration frame (CFRAME) driver. The CFRAME driver may be or include control logic to transmit configuration data (e.g., a bitstream) to configure programmable logic. Each programmable logic region can be configured or programmable via configuration data received through Z-interface 232, the respective Z-interfaces 234-238 of the respective structure chips 104-108, and any intermediate Z-interfaces 234, 236. For example, processing system 202 (e.g., the PMC of processing system 202) can transmit configuration data to the respective PL IC 224-228 via the programmable network 212 of NoC 210 and Z-interface 232. In some examples, the configuration interconnect (e.g., including a CFRAME driver) can direct configuration data to the appropriate programmable cell block and control the configuration of such programmable cell blocks.

[0097] Figure 3 The diagram illustrates a simplified structure of at least a portion of each of the Z-interfaces 234 and 236 of structural chips 104 and 106 according to some examples. Although described with respect to structural chips 104 and 106, the described aspects of the Z-interface apply to the Z-interface 232 of the base chip 102 and / or the Z-interface 238 of the structural chip 108 (e.g., components not formed via back-side processing). It is worth noting that... Figure 3 No passive pass-through connections that may exist in the Z interface are shown. Figure 3 The illustration shows an exemplary disconnected through-hole post and selection circuit that may exist in the Z interface.

[0098] Z-interface 234 includes a disconnected via post 302, a selection circuit 312, a disconnected via post 304, and a selection circuit 314. Z-interface 236 includes a disconnected via post 306, a selection circuit 316, a disconnected via post 308, and a selection circuit 318.

[0099] Each broken via pillar typically includes a first continuous portion and a second continuous portion. The first and second continuous portions are aligned (e.g., vertically) in a direction perpendicular to one side (e.g., front or back) of the semiconductor substrate on which the respective broken via pillar is disposed. The first continuous portion typically includes vertically stacked back-side bonding pads, metal lines and / or vias in the back-side dielectric layer, TSVs, and metal lines and / or vias in the front-side dielectric layer, all continuously connected together. The second continuous portion typically includes vertically stacked metal lines and / or vias in the front-side dielectric layer and front-side bonding pads, all continuously connected together.

[0100] As shown in the figure, the disconnected via post 302 in the structure chip 104 includes a first continuous portion 302-1 and a second continuous portion 302-2. The first continuous portion 302-1 includes a back-side bonding pad 174-1, a metal line and via (shown but not specifically identified) in the back-side dielectric layer 134, a back-side TSV 164-1, a metal line 302x in the front-side dielectric layer 124, and a metal line and via (shown but not specifically identified) in the front-side dielectric layer 124 between the back-side TSV 164-1 and the metal line 302x, which are continuously connected together. The second continuous portion 302-2 includes a metal line 302y in the front-side dielectric layer 124, a front-side bonding pad 154-1, and a metal line and via (shown but not specifically identified) in the front-side dielectric layer 124 between the front-side bonding pad 154-1 and the metal line 302y.

[0101] As shown in the figure, the disconnected via post 304 in the structure chip 104 includes a first continuous portion 304-1 and a second continuous portion 304-2. The first continuous portion 304-1 includes a back-side bonding pad 174-2, a metal line and via (shown but not specifically identified) in the back-side dielectric layer 134, a back-side TSV 164-2, a metal line 304x in the front-side dielectric layer 124, and a metal line and via (shown but not specifically identified) in the front-side dielectric layer 124 between the back-side TSV 164-2 and the metal line 304x, which are continuously connected together. The second continuous portion 304-2 includes a metal line 304y in the front-side dielectric layer 124, a front-side bonding pad 154-2, and a metal line and via (shown but not specifically identified) in the front-side dielectric layer 124 between the front-side bonding pad 154-2 and the metal line 304y.

[0102] As shown in the figure, the disconnected via post 306 in the structure chip 106 includes a first continuous portion 306-1 and a second continuous portion 306-2. The first continuous portion 306-1 includes a back-side bonding pad 176-1, a metal line and via (shown but not specifically identified) in the back-side dielectric layer 136, a back-side TSV 166-1, a metal line 306x in the front-side dielectric layer 126, and a metal line and via (shown but not specifically identified) in the front-side dielectric layer 126 between the back-side TSV 166-1 and the metal line 306x, which are continuously connected together. The second continuous portion 306-2 includes a metal line 306y in the front-side dielectric layer 126, a front-side bonding pad 156-1, and a metal line and via (shown but not specifically identified) in the front-side dielectric layer 126 between the front-side bonding pad 156-1 and the metal line 306y.

[0103] As shown in the figure, the disconnected via post 308 in the structure chip 106 includes a first continuous portion 308-1 and a second continuous portion 308-2. The first continuous portion 308-1 includes a back-side bonding pad 176-2, a metal line and via (shown but not specifically identified) in the back-side dielectric layer 136, a back-side TSV 166-2, a metal line 308x in the front-side dielectric layer 126, and a metal line and via (shown but not specifically identified) in the front-side dielectric layer 126 between the back-side TSV 166-2 and the metal line 308x, which are continuously connected together. The second continuous portion 308-2 includes a metal line 308y in the front-side dielectric layer 126, a front-side bonding pad 156-2, and a metal line and via (shown but not specifically identified) in the front-side dielectric layer 126 between the front-side bonding pad 156-2 and the metal line 308y.

[0104] Typically, a broken via pin on one chip can be connected to a broken via pin on another chip. As shown, a broken via pin 302 is connected to a broken via pin 306 by bonding and connecting the back-side bonding pad 174-1 of the structure chip 104 to the front-side bonding pad 156-1 of the structure chip 106. Similarly, a broken via pin 304 is connected to a broken via pin 308 by bonding and connecting the back-side bonding pad 174-2 of the structure chip 104 to the front-side bonding pad 156-2 of the structure chip 106. Broken via pins 302 and 304 can be similarly connected (e.g., via front-side bonding pads 154-1 and 154-2) to their respective broken via pins on the base chip 102, and broken via pins 306 and 308 (e.g., via back-side bonding pads 176-1 and 176-2) can be connected to their respective broken via pins on the structure chip 108.

[0105] Typically, each disconnected via post 302, 304, 306, 308 is not continuously connected by the metallization of the respective front dielectric layers 124, 126 of the structure chips 104, 106. More specifically, the respective first continuous portions 302-1, 304-1, 306-1, 308-1 of the disconnected via posts 302, 304, 306, 308 are not connected to the respective second continuous portions 302-2, 304-2, 306-2, 308-2 of the disconnected via posts 302, 304, 306, 308. For example, there are no through holes directly connecting to the metal wires 302x and 302y in the disconnected through-hole post 302, and no direct connection between the metal wires 302x and 302y; there are no through holes directly connecting to the metal wires 304x and 304y in the disconnected through-hole post 304, and no direct connection between the metal wires 304x and 304y; there are no through holes directly connecting to the metal wires 306x and 306y in the disconnected through-hole post 306, and no direct connection between the metal wires 306x and 306y; and there are no through holes directly connecting to the metal wires 308x and 308y in the disconnected through-hole post 308, and no direct connection between the metal wires 308x and 308y.

[0106] The selection circuits are connected between the first and second consecutive portions of the disconnected through-hole posts. Each selection circuit 312, 314, 316, 318 may include any logic circuit, and as shown, each selection circuit 312, 314, 316, 318 includes a respective multiplexer 312a, 314a, 316a, 318a. As shown, metal line 302y of the second consecutive portion 302-2 is connected to the input node of multiplexer 312a, and the output node of multiplexer 312a is connected to metal line 302x of the first consecutive portion 302-1. Metal line 304x of the first consecutive portion 304-1 is connected to the input node of multiplexer 314a, and the output node of multiplexer 314a is connected to metal line 304y of the second consecutive portion 304-2. The metal line 306y of the second continuous portion 306-2 is connected to the input node of the multiplexer 316a, and the output node of the multiplexer 316a is connected to the metal line 306x of the first continuous portion 306-1. The metal line 308x of the first continuous portion 308-1 is connected to the input node of the multiplexer 318a, and the output node of the multiplexer 318a is connected to the metal line 308y of the second continuous portion 308-2. In some examples, the selection circuit can be connected between different portions of a broken via post by metal lines of broken via posts in their respective metal layers, each metal layer having more than one metal layer disposed therebetween.

[0107] The metal traces of the first or second consecutive portion of the disconnected via post are connected to the input node of another circuit (e.g., a PL IC) on the chip. As shown, the metal trace 302y of the second consecutive portion 302-2 is further connected to the input node of the PL IC 224; the metal trace 304x of the first consecutive portion 304-1 is further connected to the input node of the PL IC 224; the metal trace 306y of the second consecutive portion 306-2 is further connected to the input node of the PL IC 226; and the metal trace 308x of the first consecutive portion 308-1 is further connected to the input node of the PL IC 226.

[0108] The output node of another circuit (e.g., a PL IC) is connected to the input node of the selection circuit. As shown, one output node of the PLIC 224 is connected to the input node of the multiplexer 312a, and another output node of the PL IC 224 is connected to the input node of the multiplexer 314a. One output node of the PL IC 226 is connected to the input node of the multiplexer 316a, and another output node of the PL IC 226 is connected to the input node of the multiplexer 318a.

[0109] Although not shown, the selection circuitry may include configuration memory (e.g., static random access memory (SRAM)) to configure the selection circuitry. For example, logic high or low values ​​may be written to configuration memory cells (e.g., via a passive Z-interface connected to processing system 202), and the configuration memory cells may be connected to control input nodes of the selection circuitry (e.g., multiplexers) to selectively configure the selection circuitry based on the logic high or low values ​​written to the configuration memory cells. In some examples, the control input nodes of the selection circuitry may be connected to other circuitry that can dynamically control the configuration of the selection circuitry during operation of the multi-chip device.

[0110] In operation, the structure chip 104 can receive a signal at the front bonding pad 154-1 and transmit it to the metal line 302y through the second continuous portion 302-2 of the disconnected via post 302. This signal is then transmitted to the input node of multiplexer 312a and the input node of PL IC 224. PL IC 224 can process the received signal or another signal and can output a signal to another input node of multiplexer 312a, which may or may not be based on the received signal. Multiplexer 312a selectively outputs the signal received from metal line 302y or the signal received from PL IC 224 based on the signal received at the control input node of multiplexer 312a. The signal output by multiplexer 312a is transmitted to metal line 302x and further transmitted to the back bonding pad 174-1 through the first continuous portion 302-1 of the disconnected via post 302. In some cases, for example, a signal received from the base chip 102 can be transmitted to the structure chip 106 through the disconnected via post 302 and the selection circuit 312, and can also be transmitted to the PL IC 224 through the second continuous portion 302-2 of the disconnected via post 302. In other cases, for example, a signal received from the base chip 102 can be transmitted to the PL IC 224 through the second continuous portion 302-2 of the disconnected via post 302, processed by the PL IC 224, and a response signal based on the received signal can be output by the PL IC 224 and transmitted to the structure chip 106 through the selection circuit 312 and the first continuous portion 302-1 of the disconnected via post 302. In some cases, for example, a signal received from the base chip 102 can be transmitted to the PL IC 224 through the second continuous portion 302-2 of the disconnected via post 302, and can be output by the PL IC 224 independently of the received signal, and transmitted to the structure chip 106 through the selection circuit 312 and the first continuous portion 302-1 of the disconnected via post 302.

[0111] In operation, the structure chip 104 can receive a signal at the back-side bonding pad 174-1 and transmit it to the metal line 304x through the first continuous portion 304-1 of the broken via post 304. The signal is then transmitted to the input nodes of multiplexer 314a and PL IC 224. PL IC 224 can process the received signal or another signal and can output a signal to another input node of multiplexer 314a, which may or may not be based on the received signal. Multiplexer 314a selectively outputs the signal received from metal line 304x or the signal received from PL IC 224 based on the signal received at its control input node. The signal output by multiplexer 314a is transmitted to metal line 304y and further transmitted to the front-side bonding pad 154-2 through the second continuous portion 304-2 of the broken via post 304. In some cases, signals received from, for example, structure chip 106 can be transmitted to base chip 102 through the disconnected via post 304 and selection circuit 314, and can also be transmitted to PL IC 224 through the first continuous portion 304-1 of the disconnected via post 304. In some cases, signals received from, for example, structure chip 106 can be transmitted to PL IC 224 through the first continuous portion 304-1 of the disconnected via post 304, and can be processed by PL IC 224. A response signal based on the received signal can be output by PL IC 224 and transmitted to base chip 102 through selection circuit 314 and the second continuous portion 304-2 of the disconnected via post 304. In some cases, signals received from, for example, structure chip 106 can be transmitted to PL IC 224 through a first continuous portion 304-1 of the disconnected via post 304, and signals independent of the received signals can be output by PL IC 224 and transmitted to base chip 102 through selection circuit 314 and a second continuous portion 304-2 of the disconnected via post 304.

[0112] The disconnected through-hole posts 306 and 308 and the selection circuits 316 and 318 can operate similarly to the disconnected through-hole posts 302 and 304 and the selection circuits 312 and 314, respectively. This operation will be readily understood by those skilled in the art, and therefore, for the sake of brevity, a description of this operation is omitted here.

[0113] Those skilled in the art will readily understand Figure 3The illustrations are simplified. In some examples, the front dielectric layers 122-128 of each chip 102-108 are or include a set of dielectric layers, such as eighteen or more dielectric layers, for example, depending on the technology node of the chip 102-108. Furthermore, in some examples, each of the front dielectric layers 122-128 may have or include eighteen metal layers (e.g., M0 to M17 layers), although the number of metal layers may vary, for example, depending on the technology node of the chip. In some examples where each chip has eighteen metal layers in the front dielectric layers, metal lines 302x, 304x, 306x, and 308x are in the M5 layer, and metal lines 302y, 304y, 306y, and 308y are in the M7 layer. In other examples, the various metal lines may be in different metal layers.

[0114] Disconnected vias can enable input from, for example, an underlying chip to an overlying chip, and output from that chip to, for example, an overlying chip within the same region of that chip (e.g., parallel to the front or back side). For example, a disconnected via can be used to receive input signals and transmit output signals. This avoids the need for two vias, each with a TSV, one for the input signal and the other for the output signal. Therefore, some examples can achieve reduced area usage for Z-axis communication. Reduced area usage also reduces bottlenecks in the metal layers surrounding the vias on the chip. Furthermore, disconnected vias offer flexibility in signal communication and allow different chips in a chip stack to have the same IC and hardware, reducing the number of chip variants to be designed and fabricated. Moreover, in some examples, control over the configurability of disconnected vias can be simplified compared to, for example, tri-state buffer solutions.

[0115] Figure 4 It is based on some examples and formed Figure 1 The flowchart of the method 400 for multi-chip devices. Figure 4 The processing of method 400 has been generally described, and those skilled in the art will readily understand that more specific processing can be performed. More specific processing can be based on any semiconductor processing used to form an IC on a substrate, which will be diced into chips. For ease of description, a wafer on which one or more base chips 102 are formed is referred to as a base wafer, and a wafer on which one or more structural chips 104, 106, 108 are formed is referred to as a structural wafer. Any wafer can be of any shape and / or size.

[0116] In block 402, front-side processing is performed on the chips on each wafer. For example, the front-side processing of each semiconductor substrate 112, 114, 116, 118 (e.g., a wafer) may include forming devices (e.g., transistors 142, 144, 146, 148) in and / or on the front surface of the semiconductor substrate, and forming front-side dielectric layers 122, 124, 126, 128 having metallization and front-side bonding pads 152, 154, 156, 158 on the front surface of the semiconductor substrates 112, 114, 116, 118. Multiple base chips 102 may be formed on the base wafers. Multiple structural chips 104, 106, or 108 may be formed on multiple structural wafers. For example, the front-side processing may form Z-interface selection circuitry and disconnected via posts, the Z-interface being located on and / or within the respective semiconductor substrate and front-side dielectric layer.

[0117] In box 404, the base wafer is bonded to the first structure wafer, for example as follows: Figure 1 The front-to-front joint is shown. (See example.) Figure 1 As shown, as a result of the bonding, the front side of the base chip 102 is bonded to the front side of the structure chip 104. The bonding can be a hybrid bonding, for example, bonding the front bonding pad 152 on the base wafer to the front bonding pad 154 on the first structure wafer, and bonding the outer surface of the front dielectric layer 122 on the base wafer to the outer surface of the front dielectric layer 124 on the first structure wafer.

[0118] In frame 406, the semiconductor substrate of the first structure wafer is thinned from the back side. For example... Figure 1 As shown, the semiconductor substrate 114 of the structure chip 104 is thinned from the back side. Thinning can be achieved by chemical mechanical polishing (CMP) or other suitable processes. In block 408, the structure chip on the first structure wafer undergoes a back-side processing. Figure 1 As shown, the back-side processing may include forming a back-side TSV 164 through the semiconductor substrate 114 of the first structure wafer and connecting it to a metallization in the front-side dielectric layer 124 on the first structure wafer. The back-side processing may also include forming a back-side dielectric layer 134 having a metallization and a back-side bonding pad 174 on the back side of the semiconductor substrate 114. The metallization in the back-side dielectric layer 134 can be connected to the metallization in the front-side dielectric layer 124 via the back-side TSV 164. Typically, the formation of the back-side TSV and the metallization in the back-side dielectric layer may be formed on and / or within the respective semiconductor substrate and back-side dielectric layer via disconnected through-hole pillars at Z-interfaces.

[0119] In frame 410, the first structural wafer is bonded to the second structural wafer, such as... Figure 1 The back-to-front bonding is shown. As a result of the bonding, the back side of structure chip 104 is bonded to the front side of structure chip 106, as shown. Figure 1 As shown. The bonding can be a hybrid bonding, such as bonding the back-side bonding pad 174 on the first structure wafer to the front-side bonding pad 156 on the second structure wafer, and bonding the outer surface of the back-side dielectric layer 134 on the first structure wafer to the outer surface of the front-side dielectric layer 126 on the second structure wafer.

[0120] In box 412, the semiconductor substrate of the second structure wafer is thinned from the back side, as described with respect to box 406. Figure 1 As shown, the semiconductor substrate 116 of the structure chip 106 is thinned from the back side.

[0121] In block 414, back-side processing is performed on the structural chip on the second structural wafer, as described with respect to block 408. Figure 1 As shown, the back-side processing may include forming a back-side TSV 166 through the semiconductor substrate 116 of the second structure wafer and connecting it to a metallization in the front-side dielectric layer 126 on the second structure wafer. The back-side processing may further include forming a back-side dielectric layer 136 having a metallization and a back-side bonding pad 176 on the back side of the semiconductor substrate 116. The metallization in the back-side dielectric layer 136 can be connected to the metallization in the front-side dielectric layer 126 via the back-side TSV 166.

[0122] In box 416, the second structure wafer is bonded to the third structure wafer, for example as follows: Figure 1 The back-to-front bonding is shown. As a result of the bonding, the back side of structure chip 106 is bonded to the front side of structure chip 108, as shown. Figure 1 As shown. The bonding can be a hybrid bonding, such as bonding the back-side bonding pad 176 on the second structure wafer to the front-side bonding pad 158 on the third structure wafer, and bonding the outer surface of the back-side dielectric layer 136 on the second structure wafer to the outer surface of the front-side dielectric layer 128 on the third structure wafer.

[0123] In block 418, the semiconductor substrate of the base wafer is thinned from the back side of the base wafer, as described with respect to block 406. Figure 1 As shown, the semiconductor substrate 112 of the base chip 102 is thinned from the back side.

[0124] In box 420, the base chip on the base wafer undergoes back-side processing, as described with respect to box 408. Figure 1As shown, the back-side processing may include forming a back-side TSV 162 through the semiconductor substrate 112 of the base wafer and connecting it to a metallization in the front-side dielectric layer 122 on the base wafer. The back-side processing may also include forming a back-side dielectric layer 132 on the back side of the semiconductor substrate 112, having a metallization and an external connector back-side pad 172. The metallization in the back-side dielectric layer 132 can be connected to the metallization in the front-side dielectric layer 122 via the back-side TSV 162. The back-side processing of the base chip 102 may also include forming a passivation layer 180 and an external connector 182. At block 422, the bonded wafer is diced (e.g., by sawing) to separate the formed individual multi-chip devices. Each multi-chip device may be as follows: Figure 1 As shown.

[0125] Various operations within the blocks of method 400 can be repeated and / or omitted to form various multi-chip devices. Method 400 has been provided as an example of how to form some multi-chip devices. In other examples, some operations can be performed in parallel. For example, multiple different wafer stacks can be formed in parallel (e.g., by bonding and processing their respective wafers) before multiple different wafer stacks are bonded together and further processed to form a multi-chip device. Based on the above description of method 400, those skilled in the art will readily understand how other multi-chip devices can be formed.

[0126] Figure 5 This is a flowchart of a method 500 for operating a multi-chip device based on some examples. For example, a multi-chip device can be as follows: Figures 1 to 3 As shown. For illustrative purposes, various operations of method 500 are described in the context of structure chip 104. Those skilled in the art will readily understand that such operations can be similarly performed or replicated on other chips such as structure chip 106.

[0127] In block 502, the chip's selection circuitry is configured to selectively output and transmit received signals from a plurality of received signals. For example, the processing system 202 of base chip 102 can transmit configuration data to respective structure chips 104-108 via passive connections of Z interfaces 232-238, where selection circuitry of Z interfaces 234-238 is configured, for example, by writing configuration data to the configuration memory of the selection circuitry. Any selection circuitry of base chip 102 can be directly configured by processing system 202 without transmitting the corresponding configuration data via the Z interface. As a further detail of the example, selection circuitry 312, 314 of structure chip 104 can be configured, for example, by writing configuration data to configuration memory. Selection circuitry 312 can be configured to selectively output a signal received from metal line 302y or a signal received from PL IC 224. Selection circuitry 314 can be configured to selectively output a signal received from metal line 304x or a signal received from PL IC 224.

[0128] In block 504, a first signal is received at the selection circuit from each successive portion of the disconnected via pillar. The first signal can be received from either the overlay or underlay chip in the chip stack. For example, the first signal can be received at the front bonding pad 154-1 from the base chip 102 (e.g., the underlay chip) and transmitted through the second successive portion 302-2 of the disconnected via pillar 302 for reception at the selection circuit 312. Another first signal can be received at the back bonding pad 174-2 from the structure chip 104 (e.g., the overlay chip) and transmitted through the first successive portion 304-1 of the disconnected via pillar 304 for reception at the selection circuit 312.

[0129] In block 506, the first signal received in block 504 is further received at its respective other circuitry (e.g., PL IC). Continuing the example above, the first signal may be received at PL IC 224 from the second continuous portion 302-2 of the broken through-hole post 302, while another first signal may be received at PL IC 224 from the first continuous portion 304-1 of the broken through-hole post 304.

[0130] In block 508, a second signal is received at the selection circuit from its respective other circuitry (e.g., a PL IC). For example, a second signal may be received at selection circuit 312 from PL IC 224, and another second signal may be received at selection circuit 314 from PL IC 224. These second signals may be based on their respective first signals (e.g., signals generated by processing their respective first signals) or may be independent of their respective first signals.

[0131] In block 510, a third signal is selectively output from various selection circuits and transmitted through a continuous portion of a disconnected via post 302. Which signal is selectively output from the selection circuits can be based on the configuration of the selection circuits provided in block 502. For example, selection circuit 312 can output a first or second signal, which is further transmitted through a first continuous portion 302-1 of the disconnected via post 302 and output to the structure chip 106 (e.g., overlay chip) at back-side bonding pad 174-1. If a first signal is output from selection circuit 312, the first signal can be transmitted through the disconnected via post 302 and selection circuit 312 through the structure chip 104. Otherwise, the disconnected via post 302 can serve as an input to the first signal and as an output to a different second signal. Selection circuit 314 can output another first or second signal, which is further transmitted through a second continuous portion 304-2 of the disconnected via post 304 and output to the base chip 102 (e.g., overlay chip) at front-side bonding pad 154-2. If another first signal is output from the selection circuit 314, then the other first signal can be transmitted through the structure chip 104 via the open via post 304 and the selection circuit 314. Otherwise, the open via post 304 can serve as the input of another first signal and as the output of a different second signal.

[0132] While the foregoing is directed to specific examples, other and further examples may be devised without departing from its basic scope, the scope of which is determined by the appended claims.

Claims

1. A multi-chip device, characterized in that, The multi-chip device includes: A chip stack comprising a plurality of chips, wherein adjacent chips in the chip stack are attached to each other, and one or more chips in the plurality of chips each include a first disconnected via post and a first selection circuit, the first disconnected via post comprising: A first continuous portion includes a first substrate through-hole (TSV) and a first metal line, the first TSV passing through the semiconductor substrate of a respective chip, the first metal line being disposed within a dielectric layer group disposed on one side of the semiconductor substrate of the respective chip; and The second continuous portion includes a second metal line disposed within the dielectric layer group. The first continuous portion and the second continuous portion are aligned in a direction perpendicular to one side of the semiconductor substrate. The first continuous portion is not connected to the second continuous portion. A first input node of the first selection circuit is connected to one of the first metal line or the second metal line, and an output node of the first selection circuit is connected to the other of the first metal line or the second metal line. Each of the one or more chips further includes another circuit, wherein a second input node of the first selection circuit is connected to an output node of the other circuit, and the first metal line or the second metal line connected to the first input node of the first selection circuit is also connected to an input node of the other circuit.

2. The multi-chip device according to claim 1, characterized in that, The first selection circuit is configured to selectively output a signal received from a first input node of the first selection circuit or from a second input node of the first selection circuit at the output node of the first selection circuit.

3. The multi-chip device according to claim 1, characterized in that, The other circuit includes programmable logic circuitry.

4. The multi-chip device according to claim 1, characterized in that, The first input node of the first selection circuit is connected to the first metal line, and the output node of the first selection circuit is connected to the second metal line.

5. The multi-chip device according to claim 1, characterized in that, The first input node of the first selection circuit is connected to the second metal line, and the output node of the first selection circuit is connected to the first metal line.

6. The multi-chip device according to claim 1, characterized in that, Each of the one or more chips includes a second disconnected via post and a second selection circuit, the second disconnected via post comprising: The third continuous portion includes a second TSV and a third metal line, the second TSV passing through the semiconductor substrate of its respective chip, and the third metal line disposed within the dielectric layer group; and A fourth continuous portion includes a fourth metal line disposed within the dielectric layer group. The third continuous portion and the fourth continuous portion are aligned in a direction perpendicular to one side of the semiconductor substrate. The third continuous portion is not connected to the fourth continuous portion. The input node of the second selection circuit is connected to the third metal line, and the output node of the second selection circuit is connected to the fourth metal line. The first input node of the first selection circuit is connected to the second metal line, and the output node of the first selection circuit is connected to the first metal line.

7. The multi-chip device according to claim 1, characterized in that, The first selection circuit includes a multiplexer, the first input node of the first selection circuit is the first input node of the multiplexer, and the output node of the first selection circuit is the output node of the multiplexer.

8. A method for operating a multi-chip device, characterized in that, The method includes: A first signal is received at a first selection circuit from a first continuous portion of a first disconnected via post, the first disconnected via post being in the first chip of a plurality of chips in a chip stack, wherein adjacent chip pairs in the chip stack are attached to each other. A second signal from the first selection circuit is transmitted through a second continuous portion of the first disconnected via post. One of the first and second continuous portions includes a first substrate through-hole (TSV) passing through the semiconductor substrate of the first chip. The first and second continuous portions are aligned in a direction perpendicular to one side of the semiconductor substrate. The first continuous portion is not connected to the second continuous portion. The first selection circuit receives a third signal from another circuit of the first chip, wherein the first selection circuit selectively transmits either the first signal or the third signal as the second signal.

9. The method according to claim 8, characterized in that, One or both of the first continuous portion and the second continuous portion include the first TSV.

10. The method according to claim 8, characterized in that, The method further includes: A fourth signal is received at the second selection circuit from a third continuous portion of the second disconnected via pillar, the second disconnected via pillar being in the first chip, the third continuous portion including a second TSV passing through the semiconductor substrate, the second continuous portion including the first TSV; and A fifth signal from the second selection circuit is transmitted through a fourth continuous portion of the second disconnected via post, wherein the third and fourth continuous portions are aligned in a direction perpendicular to one side of the semiconductor substrate, and the third continuous portion is not connected to the fourth continuous portion.

11. The method according to claim 8, characterized in that: The first signal is received from a second chip in the stack of chips via the first continuous portion; and The second signal is transmitted through the second continuous portion to a third chip in the chip stack, wherein the first chip is disposed between the second chip and the third chip in the chip stack.

12. A multi-chip device, characterized in that, The multi-chip device includes: The first chip includes: First selection circuit; A first disconnected via post extends through a first semiconductor substrate of the first chip and a first set of dielectric layers on a first side of the first semiconductor substrate, the first disconnected via post comprising: A first continuous portion includes a first substrate through-hole (TSV) through the first semiconductor substrate, and the output node of the first selection circuit is connected to the first continuous portion; and The second continuous portion is aligned with the first continuous portion in a direction perpendicular to the first side of the first semiconductor substrate, and the second continuous portion is connected to the first input node of the first selection circuit. The integrated circuit has a second input node of the first selection circuit connected to the output node of the integrated circuit, and the second continuous portion connected to the first input node of the first selection circuit is also connected to the input node of the integrated circuit. Second selection circuit; and The second disconnected via post extends through the first semiconductor substrate and the first set of dielectric layers, the second disconnected via post comprising: A third continuous portion, comprising a second TSV extending through the first semiconductor substrate, is connected to a first input node of the second selection circuit; and A fourth continuous portion, aligned with the third continuous portion in a direction perpendicular to a first side of the first semiconductor substrate, wherein the output node of the second selection circuit is connected to the fourth continuous portion; and The second chip is attached to the first chip.

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