Field effect transistor device

Abstract

The present application relates to a kind of FET devices (10), comprising: substrate (11);GaN structure (15), cover the part of substrate (11);Gate metal layer (17), located at the top of the GaN structure (15). The GaN structure (15) includes: at least one first part, with first height;Second part, with second height less than the first height;Wherein, the first interface (41) between the at least one first part of the GaN structure (15) and the gate metal layer (17) has ohmic contact characteristics;Second interface (43) between the second part of the GaN structure (15) and the gate metal layer (17) has non-ohmic contact characteristics.

Description

Technical Field

[0001] This invention relates to a field-effect transistor (FET) device, and more particularly to a high electron mobility transistor (HEMT) device. The invention also relates to a method for manufacturing such a FET device. Background Technology

[0002] Field-effect transistors (FETs) are key components in many electronic devices. An FET typically consists of three parts: a source, a gate, and a drain. The current between the source and drain can be controlled by applying a voltage to the gate.

[0003] A high-electron-mobility transistor (HEMT) is a special type of FET whose channel is formed by a heterojunction (i.e., a junction between two materials with different band gaps). Different material combinations can be used to form heterojunctions, such as AlGaAs / GaAs or AlGaN / GaN.

[0004] The HEMT market is dominated by two technological concepts: the ohmic gate concept and the Schottky gate concept. Therefore, the terms "ohmic gate" and "Schottky gate" refer to the interface between the gate structure and the metal gate contact in an HEMT. Both concepts have inherent limitations and technical problems. The main difference between the two concepts is the gate current; in the case of a Schottky contact, the gate current is small, while in the case of an ohmic contact, the gate current is large. The choice of one of these concepts has a significant impact on the electrical characteristics of the HEMT, such as its voltage rating, resistance rating, or reliability requirements, thus limiting the types of devices that can be manufactured using a particular HEMT.

[0005] Figure 1 An example of a gallium nitride (GaN) HEMT structure provided in a conventional example is shown. This HEMT structure includes an aluminum gallium nitride (AlGaN) layer on top of a substrate. The gallium nitride (GaN) layer is disposed on top of the AlGaN layer and contacts a gate metal layer. The GaN and AlGaN layers form a specific portion of the HEMT, which can be modeled to form an ohmic contact or a Schottky contact.

[0006] Figure 2 a shows a device with ohmic contact. Figure 1The diagram shows the equivalent circuit of the gate of a GaN HEMT. HEMTs with this type of ohmic gate have the following advantages: the voltage at the intermediate node (V) m ) by the applied gate voltage (V g Because it is directly controlled, there is no floating region in the GaN layer. Furthermore, carriers can be dissipated under both positive and negative bias, resulting in a robust and stable gate with good dynamic and long-term performance. However, the current required to drive the gate can be very large, leading to high current consumption in the entire system and necessitating a complex drive design.

[0007] Figure 2 b shows a Schottky contact. Figure 1 The diagram shows the equivalent circuit of the gate of a GaN HEMT. HEMTs with this type of Schottky gate have the following advantages: due to the possibility of applying a gate voltage (V) g ) and intermediate node voltage (V m The Schottky contacts are reverse-biased between the terminals, which may reduce the gate current. Therefore, a simpler drive mode can be selected, and scalability in terms of voltage and resistance levels is enhanced. However, the intermediate node voltage (V...) m The gate is electrically floating, which may result in poor dynamic performance. Furthermore, depletion at the Schottky contact may lead to reduced gate reliability.

[0008] In summary, an ohmic gate is a robust and reliable concept for high-voltage devices, but it is less suitable for low-voltage and / or low on-resistance (R0). on On the other hand, Schottky gates are more suitable for low voltage and / or low R-value devices. on While both FET and HEMT technologies have their own inherent weaknesses, developing different types of HEMTs that combine both technologies and characteristics is extremely difficult and costly. Therefore, there is a need for improved FET devices, especially improved HEMT devices. Summary of the Invention

[0009] In view of the above-mentioned problems and disadvantages, the present invention aims to improve field-effect transistor devices (especially HEMT devices) and their manufacturing methods. Therefore, the object of the present invention is to provide an improved field-effect transistor device.

[0010] The object of the invention is achieved by means of the embodiments provided in the appended independent claims. Advantageous embodiments of the invention are further defined in the dependent claims.

[0011] According to a first aspect, a field-effect transistor (FET) device is provided, the FET device comprising: a substrate; a gallium nitride (GaN) structure covering a portion of the substrate; and a gate metal layer located on top of the GaN structure; wherein the GaN structure comprises: at least one first portion having a first height; and a second portion having a second height less than the first height; wherein a first interface between the at least one first portion of the GaN structure and the gate metal layer has ohmic contact characteristics; and a second interface between the second portion of the GaN structure and the gate metal layer has non-ohmic contact characteristics.

[0012] This has the advantage of forming a FET device with a hybrid gate, which possesses electrical characteristics combining aspects of ohmic and non-ohmic gates (e.g., Schottky gates). Specifically, gate characteristics such as gate current levels can be controlled by the aspect ratio between the at least one first portion of the GaN structure and the second portion of the GaN structure, i.e., by the aspect ratio between an interface with ohmic contact characteristics and an interface with non-ohmic contact characteristics.

[0013] The substrate may include a substrate structure having one or more layers on top. Specifically, the substrate includes an aluminum gallium nitride (AlGaN) top layer. The GaN structure may be disposed on top of the AlGaN layer. A trench may be formed beneath the AlGaN layer in a region below the GaN structure.

[0014] Furthermore, the source and drain structures of the FET device can be arranged at both ends of the GaN structure.

[0015] In one implementation of the first aspect, the first interface forms an ohmic contact, and the second interface forms a Schottky junction or a pn junction.

[0016] Specifically, the ohmic contact of the first interface can also be formed by a tunnel junction or quasi-ohmic contact between the GaN structure and the gate metal layer.

[0017] In one implementation of the first aspect, the first interface occupies less than 10%, particularly less than 5%, and more specifically, less than 1%, of the total interface area between the GaN structure and the gate metal layer; the total interface area includes the first interface and the second interface. This has the advantage that the electrical characteristics of the gate, such as the gate current, can be efficiently adjusted.

[0018] For example, the gate current of the FET device can be reduced by decreasing the ohmic interface portion on the total interface.

[0019] Alternatively, the first interface may occupy more than 10% of the total interface area. In this way, the gate current of the FET device can be increased.

[0020] In one implementation of the first aspect, the GaN structure includes a plurality of first portions that are separated from each other.

[0021] Specifically, the plurality of first portions may be distributed in the gate region.

[0022] In one implementation of the first aspect, a separation layer is arranged around the first interface of the GaN structure to physically separate the first interface from the second interface.

[0023] Specifically, the separation layer is disposed around at least one first portion of the GaN structure. More specifically, a corresponding separation layer is disposed around each of the first portions of the GaN structure. The separation layer may be formed of an insulating material. For example, the separation layer is a dielectric.

[0024] In one implementation of the first aspect, the GaN structure includes a sloping transition region from the first portion to the second portion.

[0025] Alternatively, the transition from the at least one first portion to the second portion of the GaN structure can be an abrupt transition, i.e., the height of the GaN structure decreases at a 90° angle.

[0026] In one implementation of the first aspect, the GaN structure further includes a third portion having a third height different from the first and second heights. This has the advantage that the FET device may include a third interface formed between the third portion and the gate metal layer. Specifically, the electrical characteristics of the third interface may be ohmic or non-ohmic.

[0027] In one implementation of the first aspect, the GaN structure includes a p-doped GaN (pGaN) layer; the region below the first interface has a higher concentration of p-type dopant than the region below the second interface in terms of the concentration of p-type dopant in the pGaN layer. This has the advantage that the electrical characteristics of the first interface and / or the second interface can be adjusted.

[0028] Specifically, the first and second portions of the GaN structure are at least partially formed by the pGaN layer.

[0029] The first interface can be transformed into an ohmic interface by increasing the doping in the region beneath it. The exact electrical properties of the first interface can be further tuned by adjusting the concentration of dopant (e.g., magnesium) in the pGaN layer near the interface.

[0030] In one implementation of the first aspect, the GaN structure includes an n-type doped GaN (nGaN) layer disposed above the pGaN layer; wherein the nGaN layer at least partially covers the pGaN layer.

[0031] Specifically, by adding the nGaN layer, the electrical characteristics of the first interface and / or the second interface can be further adjusted. For example, if the nGaN layer is disposed on top of the pGaN layer in the second portion of the GaN structure, the Schottky junction formed by the second interface can become a pn junction. If the nGaN layer is disposed on top of the pGaN layer in the first portion of the GaN structure, the first interface can form a tunnel junction, which primarily has ohmic contact characteristics.

[0032] The first and second portions of the GaN structure may each include portions of the pGaN layer and the nGaN layer.

[0033] In one implementation of the first aspect, the nGaN layer is disposed only above the pGaN layer in the at least one first portion of the GaN structure; or, the nGaN layer is disposed only above the pGaN layer in the second portion of the GaN structure. This has the advantage that the electrical characteristics of one of the two interfaces are further adjusted only by the nGaN layer, while the other interface remains unaffected.

[0034] In one implementation of the first aspect, the nGaN layer is disposed above the pGaN layer in the first and second portions of the GaN structure. This has the advantage that the electrical characteristics of the two interfaces can be adjusted through the nGaN layer.

[0035] In one implementation of the first aspect, the thickness of the nGaN layer in the first portion of the GaN structure is greater than its thickness in the second portion. This has the advantage that the electrical properties of the two interfaces can be adjusted using the nGaN layer.

[0036] In one implementation of the first aspect, the nGaN layer covers only a portion of the pGaN layer in the first and / or second portions of the GaN structure. This has the advantage that a hybrid gate structure can be generated by only partially covering the pGaN layer in the first and / or second portions with the nGaN layer.

[0037] In one implementation of the first aspect, the first portion of the GaN structure has a higher concentration of n-type dopant than the second portion in terms of the concentration of n-type dopant in the nGaN layer. This has the advantage that the electrical properties of the first interface and / or the second interface can be further adjusted.

[0038] In one implementation of the first aspect, the GaN structure further includes an undoped GaN layer. For example, the undoped GaN layer may form the base layer of the GaN structure. The pGaN layer and / or the nGaN layer may be disposed on the base layer.

[0039] In one implementation of the first aspect, the gate metal layer is formed of a metal stack, wherein the metal stack comprises any one of the following material combinations: Ni / Au, Ni / Ag, Pd / Au, Cr / Au, Pt / Au, Ti / Pt / Au, Ni / Si, W / Si, Ti / Al, Ti / Al / Ti, or TiN / Al / TiN.

[0040] In one implementation of the first aspect, the FET device is a GaN gate high electron mobility transistor (HEMT) device.

[0041] According to a second aspect, a method for manufacturing a FET device is provided, the method comprising the following steps:

[0042] -Set the substrate;

[0043] - A GaN structure is formed on top of the substrate, wherein the GaN structure includes at least one first portion,

[0044] It has a first height; the second part has a second height that is less than the first height;

[0045] - A gate metal layer is formed on top of the GaN structure;

[0046] Wherein, the first interface between the at least one first portion of the GaN structure and the gate metal layer has ohmic contact characteristics; the second interface between the second portion of the GaN structure and the gate metal layer has non-ohmic contact characteristics.

[0047] This has the advantage of forming a FET device with a hybrid gate, which possesses electrical characteristics combining aspects of ohmic and non-ohmic gates (e.g., Schottky gates). Specifically, gate characteristics such as gate current levels can be controlled by the aspect ratio between the at least one first portion of the GaN structure and the second portion of the GaN structure, i.e., by the aspect ratio between an interface with ohmic contact characteristics and an interface with non-ohmic contact characteristics.

[0048] In one implementation of the second aspect, the first interface forms an ohmic contact, and / or the second interface forms a Schottky junction or a pn junction.

[0049] In one implementation of the second aspect, the first interface accounts for less than 10% of the total interface area between the GaN structure and the gate metal layer, particularly less than 5%, and more specifically, less than 1%; the total interface area includes the first interface and the second interface.

[0050] In one implementation of the second aspect, the GaN structure includes a plurality of first parts that are separated from each other.

[0051] In one implementation of the second aspect, a separation layer is arranged around the first interface of the GaN structure to physically separate the first interface from the second interface.

[0052] In one implementation of the second aspect, the GaN structure includes a sloping transition region from the first portion to the second portion.

[0053] In one implementation of the second aspect, the GaN structure further includes a third portion having a third height different from the first height and the second height.

[0054] In one implementation of the second aspect, the GaN structure includes a pGaN layer; the region below the first interface has a higher concentration of p-type dopant than the region below the second interface in terms of the concentration of p-type dopant in the pGaN layer.

[0055] In one implementation of the second aspect, the GaN structure includes an nGaN layer disposed above the pGaN layer; wherein the nGaN layer at least partially covers the pGaN layer.

[0056] In one implementation of the second aspect, the nGaN layer is disposed only above the pGaN layer in the at least one first portion of the GaN structure; or, the nGaN layer is disposed only above the pGaN layer in the second portion of the GaN structure.

[0057] In one implementation of the second aspect, the nGaN layer is disposed above the pGaN layer in the first and second portions of the GaN structure.

[0058] In one implementation of the second aspect, the thickness of the nGaN layer in the first portion of the GaN structure is greater than its thickness in the second portion.

[0059] In one implementation of the second aspect, the nGaN layer covers only a portion of the pGaN layer in the first and / or second portions of the GaN structure.

[0060] In one implementation of the second aspect, the first portion of the GaN structure has a higher concentration of n-type dopant than the second portion in terms of the concentration of n-type dopant in the nGaN layer.

[0061] In one implementation of the second aspect, the GaN structure further includes an undoped GaN layer.

[0062] In one implementation of the second aspect, the gate metal layer is formed of a metal stack, wherein the metal stack comprises any one of the following material combinations: Ni / Au, Ni / Ag, Pd / Au, Cr / Au, Pt / Au, Ti / Pt / Au, Ni / Si, W / Si, Ti / Al, Ti / Al / Ti, or TiN / Al / TiN.

[0063] In one implementation of the second aspect, the FET device is a GaN gate high electron mobility transistor (HEMT) device.

[0064] It should be noted that all devices, elements, units, and modules described in this application can be implemented in software or hardware elements or any combination thereof. All steps performed by the various entities described in this application, and the functions described as being performed by the various entities, are intended to indicate that the respective entities are suitable for or used to perform the corresponding steps and functions. Although in the following description of specific embodiments, a particular function or step performed by an external entity is not reflected in the detailed description of the specific element of the entity performing that particular step or function, it should be apparent to those skilled in the art that these methods and functions can be implemented in the corresponding hardware or software elements or any combination thereof. Attached Figure Description

[0065] The following description of specific embodiments, in conjunction with the accompanying drawings, illustrates various aspects and implementations of the present invention, wherein:

[0066] Figure 1 An example of the HEMT structure provided in the standard examples is shown;

[0067] Figure 2 a and Figure 2 b shows Figure 1 The equivalent circuit diagram of the gate of the HEMT structure shown;

[0068] Figures 3a to 3e Schematic diagrams of FET devices provided in different embodiments are shown;

[0069] Figure 4 a and Figure 4 b shows a perspective view and a top view of a FET device provided in one embodiment;

[0070] Figure 5 An equivalent circuit diagram of a FET device provided in one embodiment is shown;

[0071] Figure 6 A graph showing the relationship between the gate current and the interface characteristics of the corresponding gate of a FET device provided in one embodiment is shown.

[0072] Figure 7 a to Figure 7 d shows a top view of the gate region of the FET device provided in different embodiments;

[0073] Figure 8 a to Figure 8 c illustrates the steps of a method for manufacturing a FET device provided in one embodiment. Detailed Implementation

[0074] Figures 3a to 3e A schematic diagram of a FET device 10 provided in different embodiments is shown.

[0075] according to Figures 3a to 3e In the illustrated embodiment, the FET device 10 includes: a substrate 11; a GaN structure 15 covering a portion of the substrate 11; and a gate metal layer 17 located on top of the GaN structure 15. The GaN structure 15 includes: at least one first portion having a first height; and a second portion having a second height less than the first height; wherein the first interface between the at least one first portion of the GaN structure 15 and the gate metal layer 17 has ohmic contact characteristics; and the second interface between the second portion of the GaN structure 15 and the gate metal layer has non-ohmic contact characteristics.

[0076] The substrate 11 may include a substrate structure having one or more layers on top. Specifically, the substrate includes an AlGaN top layer 13. The GaN structure 15 may be disposed on top of the AlGaN layer 13.

[0077] The substrate 11 may include heteroepitaxial matrix materials such as GaN-on-SOI, sapphire-based GaN, or GaN-on-SiC. The substrate 11 may also include GaN-on-GaN material. Specifically, the substrate 11 includes layers formed by epitaxial growth processes.

[0078] The channel of the FET device 10 may be formed in the region below the AlGaN layer 13, particularly at the interface between the AlGaN layer 13 and the bottom layer of the substrate 11.

[0079] Furthermore, the source and drain structures of the FET device 10 can be arranged at both ends of the GaN structure 15. Figures 3a to 3e (Not shown in the image).

[0080] A FET device 10 with a hybrid gate is formed by employing two different interfaces within a single gate. Such a FET device 10 can possess gate characteristics combining aspects of ohmic and non-ohmic gates. For example, the first interface forms an ohmic contact, and the second interface forms a Schottky junction (i.e., a Schottky barrier) or a pn junction. The electrical characteristics of the gate, such as gate current, gate reliability, or on-resistance (R0), are considered. on An ohmic contact is a combination of the characteristics of the ohmic and Schottky or pn portions of the gate. The electrical characteristics of the gate of the FET device 10 can be adjusted by controlling the design parameters of these portions, particularly their aspect ratio and / or material composition. Therefore, an ohmic contact can refer to any contact that behaves like an ohmic contact, i.e., a contact that exhibits the electrical characteristics of an ohmic contact.

[0081] Specifically, interfaces with ohmic contact characteristics have a larger leakage current than interfaces with non-ohmic contact characteristics.

[0082] The GaN structure 15 can be formed on a plane, such as... Figures 3a to 3e As shown, or formed on a liner, for example, in the case of regenerating the GaN structure 15 in a trench gate.

[0083] The GaN structure 15 may further include a p-type doped GaN (pGaN) layer 15-1. Figure 3a In the illustrated embodiment, the GaN structure 15 is formed from the pGaN layer 15-1, while... Figures 3b to 3eIn the illustrated embodiment, the GaN structure 15 includes the pGaN layer 15-1 and an additional n-type doped GaN layer 15-2 on top of the pGaN layer 15-1. Through the p-type doping of the pGaN layer 15-1, the interface characteristics between the first portion and the second portion of the GaN structure 15 and the gate metal layer 17 can be further adjusted. For example, by adjusting the doping concentration of the pGaN layer 15-1, the p-n junction at any interface can be changed to an ohmic contact.

[0084] The doping of the pGaN layer 15-1 may be non-uniform. For example, at the top of the pGaN layer 15-1 in the first portion of the GaN structure 15, close to the interface with the gate metal layer 17, the concentration of the p-type dopant (e.g., magnesium, Mg) in the pGaN layer 15-1 is increased. Therefore, in terms of the concentration of the p-type dopant in the pGaN layer 15-1, the region below the first interface is higher than the region below the second interface.

[0085] Figure 3a and Figure 3b contains a graph showing the change of the doping concentration (magnesium concentration) of the p-type dopant in the pGaN layer 15-1 along with the distance (depth) from the first interface. The doping concentration is highest at the first interface, and drops to a lower level at a position farther away from the gate metal layer 17. Further, in Figures 3a to 3e , the increased doping concentration close to the first interface is represented by a darker shade of the pGaN layer 15-1.

[0086] For example, due to the higher magnesium concentration of the pGaN layer 15-1 under the gate metal layer 17 in the first portion, the first interface is an ohmic interface; due to the reduced magnesium concentration of the pGaN layer under the gate metal layer 17 in the second portion, the second interface is a Schottky interface.

[0087] As shown in Figure 3a and Figure 3b , the pGaN layer 15-1 in the first portion of the GaN structure 15 has a first height T, which is generally between 50 nm and 1000 nm, but this is not exclusive. The pGaN layer 15-1 in the second portion of the GaN structure has a second height T1 where T1<T, and T=T1+T2. The two thicknesses T1 and T2 can be optimized such that the GaN layer 15-1 has a very high Mg doping degree (e.g., >5e19) at the first interface and a medium-low doping degree (e.g., <5e19) at the second interface.

[0088] The pGaN layer can be formed from any p-type GaN, regardless of its doping element (e.g., magnesium, Mg) and its formation method (e.g., metal-organic chemical vapor deposition (MOCVD) growth, molecular-beam epitaxy (MBE), delta doping or other deposition / doping techniques).

[0089] like Figures 3a to 3e As illustrated in the example described, the transition from the at least one first portion to the second portion of the GaN structure can be an abrupt transition, i.e., the height of the GaN structure decreases at a 90° angle. Alternatively, the GaN structure 15 may include a gradual transition from the first portion to the second portion, for example, in the form of a transition region.

[0090] The GaN structure 15 may further include: a third portion having a third height different from the first height and the second height. Figures 3a to 3e (Not shown in the image). For example, the third portion may have a third interface with the gate metal layer 17, the third interface having ohmic contact characteristics or non-ohmic contact characteristics.

[0091] The gate metal layer 17 may be formed of at least one metal stack. The metal stack contacts the GaN structure 15 to form the first interface and the second interface, respectively. For example, the metal stack includes any of the following material combinations: Ni / Au, Ni / Ag, Pd / Au, Cr / Au, Pt / Au, Ti / Pt / Au, Ni / Si, W / Si, Ti / Al, Ti / Al / Ti, or TiN / Al / TiN. However, other suitable material combinations may also be used.

[0092] Specifically, the gate metal layer 17 may include different portions formed of different materials, i.e., having different material compositions. For example, the first portion of the gate metal layer 17 in contact with the first portion of the GaN structure 15 is formed of a first metal stack, and the second portion of the gate metal layer 17 in contact with the second portion of the GaN structure 15 is formed of a second metal stack. Viewed in cross-section in the xy plane, the edges of these metal stacks may be straight, slanted, or V-shaped. The shape of the metal stacks may depend on the metal properties and the etching method used to fabricate the FET device 10. The metal stacks may also be self-aligned or non-self-aligned, for example, extending or retracting from each other or from the GaN structure 15.

[0093] As an alternative to these metal stacks, the gate metal layer 17 may also be formed of a single material, such as indium tin oxide (ITO) or a magnesium film / electrode.

[0094] exist Figures 3b to 3e In the illustrated embodiment, the GaN structure 15 includes an additional n-type doped GaN (n-doped GaN, nGaN) layer 15-2 disposed above the pGaN layer 15-1 of the GaN structure 15.

[0095] The nGaN layer 15-2 can also be arranged to cover only a portion of the pGaN layer 15-1 in the first and / or second portions of the GaN structure 15. In this way, a hybrid gate structure can be produced.

[0096] The nGaN layer 15-2 can be formed of any n-type GaN, regardless of its doping element (e.g., silicon (Si)) and its formation method (e.g., MOCVD growth, MBE, implantation, or deposition and diffusion of a silicon-rich layer). The thickness of the n-type GaN layer 15-2 can be as small as 1 nm to 10 nm or greater than 10 nm (depending on technological constraints). Specifically, the electrical properties of the first interface and / or the second interface can be further adjusted through the nGaN layer 15-2.

[0097] exist Figure 3b In the illustrated embodiment, the nGaN layer 15-2 is disposed on the pGaN layer 15-1 in the first portion of the GaN structure 15, that is, disposed on the pGaN layer 15-1 with a thickness of T.

[0098] Specifically, adding the n-GaN layer 15-1 to the first portion allows for the formation of a tunnel junction in the first interface, which has ohmic contact characteristics. Therefore, the doping level of the n-type GaN at the interface with the p-type GaN is high enough to squeeze the band structure and induce carrier tunneling.

[0099] exist Figure 3c In the embodiment shown, the nGaN layer 15-2 is disposed on the pGaN layer 15-1 in the second part of the GaN structure 15, that is, disposed on the pGaN layer 15-1 with a thickness of T1.

[0100] Specifically, inserting the n-type GaN layer 15-2 on top of the pGaN layer 15-1 in the first part can transform the second interface from a Schottky junction to a pn junction. This can improve the gate breakdown voltage, especially the gate overdrive, and increase gate reliability. Furthermore, it can alleviate the high dependence on interface quality and metal work function.

[0101] exist Figure 3d In the illustrated embodiment, the nGaN layer 15-2 is disposed on the pGaN layer 15-1 in the first and second portions of the GaN structure 15. For example, the nGaN layer 15-2 may have the same height in both portions.

[0102] Specifically, inserting the nGaN layer 15-2 into the first and second portions of the GaN structure 15 can adjust the gate leakage current at the two interfaces between the GaN structure 15 and the gate metal layer 17. For example, because the pGaN layer 15-1 has more p-type doping, the leakage current at the first interface is larger, while the leakage current at the second interface is smaller.

[0103] exist Figure 3e In the illustrated embodiment, the nGaN layer 15-2 is disposed on the pGaN layer 15-1 in the first and second portions of the GaN structure 15. Therefore, the nGaN layer 15-2 in the first portion and the nGaN layer 15-2 in the second portion have different thicknesses and / or different doping degrees.

[0104] For example, the nGaN layer 15-2 has a height of D1 in the first part and a height of D2 in the second part, where D1 > D2.

[0105] Furthermore, the nGaN layer 15-2 in the first part can be heavily doped with an n-type dopant to enable tunneling between the pGaN layer 15-1 and the gate metal layer 17, while the nGaN layer 15-2 in the second part can have a lower doping concentration to enable the formation of a pn junction at the second interface (instead of a conventional Schottky junction).

[0106] For example, such nGaN layers 15-2 with different doping concentrations and / or thicknesses D1 and D2 are fabricated by MOCVD growth combined with etching and patterned regeneration, by MBE, by deposition and diffusion of implanted or silicon-rich layers.

[0107] For example, the nGaN layer 15-2 can be optimized in terms of its thickness or doping level to meet various target specifications. For instance, the n-type doping can be sufficiently high to enhance band bending and create a tunnel junction. The nGaN layer 15-2 can also be used to transform a Schottky junction into a pn junction.

[0108] In addition to the pGaN layer 15-1 and the nGaN layer 15-2, the GaN structure 15 of the FET device 10 may also include an undoped GaN layer. The undoped GaN layer may form the base layer of the GaN structure 15. The GaN structure 15 may also include multiple pGaN layers 15-1 and / or nGaN layers 15-2. Specifically, the GaN structure 15 is formed by a stack of multiple GaN layers.

[0109] exist Figures 3a to 3e The example shown illustrates a FET device 10 with a GaN structure 15 having a single first portion surrounded by a second portion. However, the FET device 10 may also include multiple first portions, each having a first height greater than a second height of the second portion.

[0110] like Figures 3a to 3e As shown, the FET device 10 can be used in power semiconductor devices, specifically in GaN high electron mobility transistor (HEMT) devices. Specifically, the FET device 10 forms a pGaN gate HEMT, i.e., a GaN HEMT, where the gate is formed of pGaN semiconductor to achieve E-type (enhancement-mode) functionality. Such HEMT devices can be applied in a variety of different technical fields, such as power supplies, automotive, LiDAR, servers, adapters, or DC / DC converters.

[0111] Specifically, the FET device 10 can form a general HEMT structure, which further includes a back barrier, multiple conductive channels, multiple barrier thicknesses, and a recessed gate AlGaN or a recessed gate pGaN.

[0112] Figure 4 a and Figure 4 b shows a perspective view and a top view of a FET device 10 provided in one embodiment.

[0113] exist Figure 4 a and Figure 4 In the example shown in b, the gate region is divided into two interfaces: the first interface 41 has ohmic contact characteristics (ohmic interface 41), and the second interface 43 has Schottky contact characteristics (Schottky interface 43). Therefore, the first interface 41 is the interface between the first portion of the GAN structure 15 and the gate metal layer 17, and the second interface 43 is the interface between the second portion of the GAN structure 15 and the gate metal layer 17. For simplicity, Figure 4 a and Figure 4 The gate metal layer 17 is not shown in b.

[0114] exist Figure 4 a and Figure 4 In the example shown in b, the FET device 10 has a hybrid gate, where approximately 1% of the total gate area is defined as an ohmic contact, and the remainder is defined as a Schottky contact. A simplified equivalent circuit for such a hybrid gate is shown below. Figure 5 As shown.

[0115] The aspect ratio between the first interface 41 and the second interface 43 can be adjusted by the aspect ratio of the first portion to the second portion of the GaN structure 15. In this way, the electrical characteristics of the gate of the FET device 10, especially the gate current, can be adjusted. In this document, the aspect ratio between the first interface and the second interface can refer to the ratio of the size of the first interface to the size of the second interface, wherein the total gate interface of the FET device 10 is composed of the first interface and the second interface.

[0116] Figure 6 A graph showing the relationship between the gate current of a FET device 10 provided in one embodiment and the interface characteristics of the corresponding gate (in particular the aspect ratio between the ohmic interface 41 and the Schottky interface 43) is shown.

[0117] like Figure 6 As shown, adjusting the aspect ratio between the ohmic interface 41 and the Schottky interface 43 can modulate the gate current of the FET device 10. In this way, the gate current level can be controlled by the aspect ratio between two different gate regions.

[0118] Specifically, reducing the interface area of ​​the ohmic interface 41 (and thus increasing the interface area of ​​the Schottky interface 43) results in a decrease in gate current, while increasing the interface area of ​​the ohmic interface 41 (and thus reducing the interface area of ​​the Schottky interface 43) results in an increase in gate current. Therefore, in order to generate a FET device with a smaller gate current, the ohmic interface 41 can be designed to occupy less than 10% of the total interface area of ​​the gate, especially less than 5%, and more specifically, less than 1%.

[0119] By adjusting the aspect ratio between the ohmic interface 41 and the Schottky interface 43 of the gate, a hybrid (or distributed) gate is formed. This hybrid (or distributed) gate can combine the advantages of an all-ohmic gate or an all-Schottky gate while reducing their disadvantages. In this way, high-voltage (HV) and low-voltage (LV) GaN technology platforms can be integrated into a single device, and the device's specifications can be adjusted by optimizing its layout to meet the needs of specific products. Therefore, the resources and time spent developing multiple technology platforms, such as Schottky gate HEMT devices and ohmic gate HEMT devices, can be reduced.

[0120] Figure 7 a to Figure 7 Figure d shows a top view of the gate region of the FET device 10 provided in different embodiments. Specifically, Figure 7 a to Figure 7 Figure d shows the interface between the GaN structure 15 and the gate metal layer 17 of the FET structure 10. Therefore, for simplicity, the gate metal layer 17 is omitted. Figure 7 a to Figure 7 The embodiment shown in d represents several possibilities for hybrid (i.e., distributed) ohm-Schottky gate layouts.

[0121] like Figure 7 a to Figure 7 As shown in diagram d, the main gate region can be defined as a Schottky interface 43. Depending on the target aspect ratio, several smaller regions of the gate can be defined as ohmic interfaces 41, and vice versa. Specifically, whether a particular gate region forms an ohmic interface or a Schottky interface with the gate metal layer 17 depends on the height of the GaN structure and / or the doping of the pGaN layer 15-1 of the GaN structure 15 in that region.

[0122] The ohmic interface 41 can be distributed in the gate region. The distributed ohmic interface 41 can have different shapes such as square, rectangle, circle or ellipse, and different sizes.

[0123] Furthermore, the ohmic interface 41 and the Schottky interface 43 can be physically separated by a separation layer 21 (e.g., a dielectric), such as... Figure 7 As shown in b. The separation layer 21 may be arranged around each or some of the at least one first portion on the GaN structure. Alternatively, the separation layer 21 may be arranged in the gate metal layer 17, separating the gate metal layer 17 into a first contact region for contacting the first portion of the GaN structure 15 and a second contact region for contacting the second portion of the GaN structure 15.

[0124] Figure 8 a to Figure 8 d illustrate respective steps of a method for manufacturing FET device 10 provided in an embodiment.

[0125] In Figure 8 the first step shown in a, a substrate 11 is provided. The substrate 11 may include a base structure having one or more layers on a top thereof, for example an AlGaN top layer 13.

[0126] Specifically, the substrate 11 comprises a heteroepitaxial base material such as GaN-on-SOI, sapphire-based GaN or GaN-on-SiC. The substrate 11 may also comprise GaN-on-GaN material. Specifically, the substrate 11 comprises a layer formed by an epitaxial growth process.

[0127] In Figure 8 the second step shown in b, a GaN structure 15 is formed on top of the substrate 11, wherein the GaN structure 15 comprises: at least one first portion having a first height T; and a second portion having a second height T1 smaller than the first height T.

[0128] Specifically, the GaN structure comprises or is formed of a pGaN layer 15-1. The doping concentration of the pGaN layer 15-1 can be increased at the top of the first portion of the GaN structure 15.

[0129] The pGaN layer can be formed in two different ways: (i) depositing a full pGaN layer 15-1 with a thickness of T, then recessing the pGaN layer 15-1 to a thickness of T1 in a region of the GaN structure 15 where the second portion is to be formed, wherein T1<T; or (ii) depositing a full pGaN layer 15-1 with a thickness of T1, then forming a highly doped layer with a thickness of T2 by a patterned regrowth process on top of the layer with a thickness of T1 in a region of the GaN structure 15 where the at least one first portion is to be formed.

[0130] Optionally, a structured nGaN layer 15-2 can be formed on top of the pGaN layer 15-1 in the first portion and / or the second portion of the GaN structure 15 ( Figure 8 a to Figure 8 not shown in c).

[0131] The pGaN layer 15-1 and / or the nGaN layer 15-2 can be formed by a suitable manufacturing process, such as MOCVD growth, MBE, implantation, delta doping and / or deposition and diffusion of a silicon-rich layer.

[0132] In Figure 8In the third step shown in c, the gate metal layer 17 is formed on top of the GaN structure 15, wherein the first interface between the at least one first portion (height T) of the GaN structure 15 and the gate metal layer 17 has ohmic contact characteristics; and the second interface between the second portion (height T1) of the GaN structure 15 and the gate metal layer 17 has non-ohmic contact characteristics.

[0133] For example, the gate metal layer 17 may be formed of at least one metal stack. The metal stack may include any of the following material combinations: Ni / Au, Ni / Ag, Pd / Au, Cr / Au, Pt / Au, Ti / Pt / Au, Ni / Si, W / Si, Ti / Al, Ti / Al / Ti, or TiN / Al / TiN.

[0134] Figure 8 a to Figure 8 The various layer and structure designs shown in c are merely examples. The same main method can be used to manufacture... Figures 3a to 3e as well as Figure 4 a and Figure 4 b shows any of the FET device designs 10.

[0135] The invention has been described in conjunction with various embodiments and implementations as examples. However, based on a study of the drawings, the invention, and the independent claims, those skilled in the art will be able to understand and implement other variations in implementing the claimed invention. In the claims and the description, the word "comprising" does not exclude other elements or steps, and the indefinite article "a" does not exclude a plurality. A single element or other unit may fulfill the function of several entities or items recited in the claims. The mere fact that certain measures are described in mutually different dependent claims does not mean that a combination of these measures cannot be used effectively.

Claims

1. A field-effect transistor (FET) device (10), characterized in that, The field-effect transistor device (10) includes: substrate(11); A gallium nitride (GaN) structure (15) covers a portion of the substrate (11); A gate metal layer (17) is located on top of the gallium nitride structure (15), and the gate metal layer (17) is formed of a single material; The gallium nitride structure (15) includes: At least one first part, having a first height; The second part has a second height that is less than the first height; Wherein, the first interface (41) between the at least one first portion of the gallium nitride structure (15) and the gate metal layer (17) has ohmic contact characteristics; The second interface (43) between the second portion of the gallium nitride structure (15) and the gate metal layer (17) has non-ohmic contact characteristics; The gallium nitride structure (15) includes a p-doped GaN (pGaN) layer (15-1). Regarding the concentration of p-type dopant in the p-type doped GaN layer (15-1), the region below the first interface (41) is higher than the region below the second interface (43).

2. The field-effect transistor device (10) according to claim 1, characterized in that, The first interface (41) forms an ohmic contact, and / or; The second interface (43) forms a Schottky junction or a pn junction.

3. The field-effect transistor device (10) according to claim 1 or 2, characterized in that, The first interface (41) is less than 10% of the total interface area between the gallium nitride structure (15) and the gate metal layer (17); the total interface area includes the first interface (41) and the second interface (43).

4. The field-effect transistor device (10) according to claim 1 or 2 above, characterized in that, The gallium nitride structure (15) comprises multiple first parts that are separated from each other.

5. The field-effect transistor device (10) according to claim 1 or 2 above, characterized in that, A separation layer (21) is arranged around the first interface (41) of the gallium nitride structure (15) to physically separate the first interface (41) from the second interface (43).

6. The field-effect transistor device (10) according to claim 1 or 2 above, characterized in that, The gallium nitride structure (15) includes a sloping transition region from the first portion to the second portion.

7. The field-effect transistor device (10) according to claim 1 or 2 above, characterized in that, The gallium nitride structure (15) further includes a third portion having a third height different from the first height and the second height.

8. The field-effect transistor device (10) according to claim 1 or 2, characterized in that, The gallium nitride structure (15) includes an n-type doped GaN (nGaN) layer (15-2) disposed above the p-type doped GaN layer (15-1); wherein the n-type doped GaN layer (15-2) at least partially covers the p-type doped GaN layer (15-1).

9. The field-effect transistor device (10) according to claim 8, characterized in that, The n-type doped GaN layer (15-2) is disposed only above the p-type doped GaN layer (15-1) in at least one first portion of the gallium nitride structure (15); or The n-type doped GaN layer (15-2) is arranged only above the p-type doped GaN layer (15-1) in the second part of the gallium nitride structure (15).

10. The field-effect transistor device (10) according to claim 8, characterized in that, The n-type doped GaN layer (15-2) is disposed above the p-type doped GaN layer (15-1) in the first and second portions of the gallium nitride structure (15).

11. The field-effect transistor device (10) according to claim 10, characterized in that, The thickness of the n-type doped GaN layer (15-2) in the first portion of the gallium nitride structure (15) is greater than its thickness in the second portion.

12. The field-effect transistor device (10) according to any one of claims 9 to 11, characterized in that, The n-type doped GaN layer (15-2) covers only a portion of the p-type doped GaN layer (15-1) in the first and / or second portions of the gallium nitride structure (15).

13. The field-effect transistor device (10) according to any one of claims 9 to 11, characterized in that, Regarding the concentration of the n-type dopant in the n-type doped GaN layer (15-2), the first portion of the gallium nitride structure (15) is higher than the second portion.

14. The field-effect transistor device (10) according to claim 1 or 2, characterized in that, The gallium nitride structure (15) also includes an undoped gallium nitride layer.

15. The field-effect transistor device (10) according to claim 1 or 2, characterized in that, The gate metal layer (17) is formed of a metal stack, wherein the metal stack comprises any one of the following material combinations: Ni / Au, Ni / Ag, Pd / Au, Cr / Au, Pt / Au, Ti / Pt / Au, Ni / Si, W / Si, Ti / Al, Ti / Al / Ti or TiN / Al / TiN.

16. The field-effect transistor device (10) according to claim 1 or 2, characterized in that, The field-effect transistor device (10) is a GaN gate high electron mobility transistor (HEMT) device.

17. A method for manufacturing a field-effect transistor (FET) device (10), characterized in that, The method includes the following steps: Set up a substrate (11); A gallium nitride (GaN) structure is formed on the top of the substrate (11), wherein the gallium nitride structure (15) includes: at least one first portion having a first height; and a second portion having a second height less than the first height; A gate metal layer (17) is formed on top of the gallium nitride structure (15), the gate metal layer (17) being formed of a single material; Wherein, the first interface (41) between the at least one first portion of the gallium nitride structure (15) and the gate metal layer (17) has ohmic contact characteristics; The second interface (43) between the second portion of the gallium nitride structure (15) and the gate metal layer (17) has non-ohmic contact characteristics; the gallium nitride structure (15) includes a p-doped GaN (pGaN) layer; Regarding the concentration of p-type dopant in the p-type doped GaN layer (15-1), the region below the first interface (41) is higher than the region below the second interface (43).

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