Semiconductor device

Abstract

A semiconductor device is provided, which includes: a drift region of a first conductivity type provided in a semiconductor substrate; a field stop region of the first conductivity type provided below the drift region, having one or more peaks; and a collector region of a second conductivity type provided below the field stop region, having an integrated concentration of the collector region set as x [cm ‑2 ] and a depth of a first peak, which is the shallowest of the one or more peaks from a back surface of the semiconductor substrate, set as y1 [μm], and in a case where a line A1: y1 = (-7.4699E-01)ln(x) + (2.7810E+01), a line B1: y1 = (-4.7772E-01)ln(x) + (1.7960E+01) are provided, the depth of the first peak and the integrated concentration are in a range between the line A1 and the line B1.

Description

Technical Field

[0001] This invention relates to semiconductor devices. Background Technology

[0002] Previously, semiconductor devices having field-stop regions were known (for example, see Patent Document 1).

[0003] Patent Document 1: Japanese Patent Application Publication No. 2015-135954 Summary of the Invention

[0004] Technical issues

[0005] The aim is to prevent component damage caused by surge voltage during current interruption.

[0006] Technical solution

[0007] In a first aspect of the present invention, a semiconductor device is provided, comprising: a drift region of a first conductivity type disposed on a semiconductor substrate; a field-stop region of the first conductivity type disposed below the drift region and having one or more peaks; and a collector region of a second conductivity type disposed below the field-stop region, wherein the integral concentration of the collector region is set to x [cm]. -2 Let the depth of the shallowest first peak among one or more peaks, measured from the back side of the semiconductor substrate, be y1 [μm]. And let the depth and integral concentration of the first peak be between line A1 and line B1, where line A1: y1 = (-7.4699E-01)ln(x) + (2.7810E+01) and line B1: y1 = (-4.7772E-01)ln(x) + (1.7960E+01).

[0008] The integrated concentration in the collector region can be 8.00E15cm. -2 the following.

[0009] The integrated concentration in the collector region can be 3.00E14cm. -2 the following.

[0010] The integrated concentration in the collector region can be 2.00E14cm⁻¹. -2 the following.

[0011] The integrated concentration in the collector region can be 1.00E14cm⁻¹. -2 the following.

[0012] The integrated concentration in the collector region can be 5.00E13cm. -2 the following.

[0013] The integrated concentration in the collector region can be 3.00E13cm. -2 the following.

[0014] The integrated concentration in the collector region can be 1.00E13cm. -2 the following.

[0015] The depth of the first peak can be greater than 0.5 μm and less than 7.2 μm.

[0016] The depth of the first peak can be greater than 2.0 μm and less than 7.2 μm.

[0017] If the depth of the second shallowest peak, measured from the back side, is set as y2 [μm], and line A2: y2 = (-3.1095E+00)ln(x) + (1.1416E+02) and line B2: y2 = (-1.9239E+00)ln(x) + (7.1030E+01), the depth and integrated concentration of the second peak can be within the range between line A2 and line B2.

[0018] The depth of the second peak can be greater than 3.5 μm and less than 28 μm.

[0019] Let the stray inductance Ls of the circuit connected to the semiconductor device be Xc[nH], the collector current reduction rate dIce / dt be Yc[A / μs], and let line C1: Yc=10000Xc -1 In this case, the stray inductance Ls and the collector current reduction rate dIce / dt can be in a range larger than that of line C1.

[0020] One or more peaks can be doped with hydrogen.

[0021] A semiconductor device may include: an active region disposed on a semiconductor substrate; and an outer peripheral region disposed on the outer periphery of the active region when viewed from above the semiconductor substrate.

[0022] The semiconductor device may include: a base region of a second conductivity type disposed above a drift region; an emitter region of a first conductivity type disposed above the base region, and having a higher doping concentration than the drift region; a contact region of the second conductivity type disposed above the base region, and having a higher doping concentration than the base region; and a plurality of gate trenches disposed on a semiconductor substrate.

[0023] The doping concentration at the boundary between the field cutoff region and the collector region can be 1E16cm. -3 the following.

[0024] The doping concentration at the boundary between the field cutoff region and the collector region can be 5E15cm. -3 the following.

[0025] The doping concentration at the boundary between the field cutoff region and the collector region can be 2E15cm. -3 the following.

[0026] The hydrogen chemical concentration at the boundary between the field cutoff region and the collector region can be 1E18cm⁻¹ -3 the following.

[0027] The hydrogen chemical concentration at the boundary between the field cutoff region and the collector region can be 1E17cm⁻¹ -3 the following.

[0028] The hydrogen chemical concentration at the boundary between the field cutoff region and the collector region can be 1E15cm⁻¹ -3 above.

[0029] The hydrogen chemical concentration at the boundary between the field cutoff region and the collector region can be 1E16cm⁻¹ -3 above.

[0030] It should be noted that the above summary of the invention does not list all the features of the invention. Furthermore, sub-combinations of these feature groups can also constitute inventions. Attached Figure Description

[0031] Figure 1A This is an example of a top view of a semiconductor device 100.

[0032] Figure 1B Is with Figure 1A An example of a top view of the semiconductor device 100 corresponding to region A.

[0033] Figure 1C It is shown Figure 1B A diagram of an example of section b-b' in the figure.

[0034] Figure 1D It is shown Figure 1C A diagram showing an example of the doping concentration distribution along the depth direction at the location of the c-c' line.

[0035] Figure 1E yes Figure 1D Enlarged view of the field cutoff region 20 and collector region 22 in the figure.

[0036] Figure 1F This is a diagram illustrating an example of the distribution of net doping concentration and hydrogen chemical concentration in the depth direction of the first concentration peak and collector region 22.

[0037] Figure 1G Is with Figure 1A An example of a top view of the semiconductor device 100 corresponding to region B.

[0038] Figure 1H It is shown Figure 1A A diagram of an example of section a-a' in the figure.

[0039] Figure 2AThis is an example of a circuit used in the clamping withstand test of a semiconductor device 100.

[0040] Figure 2B This is a diagram used to illustrate the clamping energy of the semiconductor device 100.

[0041] Figure 3A The relationship between the doping concentration and clamping energy of collector region 22 is shown.

[0042] Figure 3B The relationship between the doping concentration of collector region 22 and the breakdown voltage of the device is shown.

[0043] Figure 4A An example of the current-voltage characteristics of the semiconductor device 100 of the embodiment is shown.

[0044] Figure 4B An example of the current-voltage characteristics of a comparative semiconductor device 500 is shown.

[0045] Figure 5A An example showing the relationship between the integrated concentration of collector region 22 and the depth of the first peak P1 is given.

[0046] Figure 5B This illustrates another example of the relationship between the integrated concentration of collector region 22 and the depth of the first peak P1.

[0047] Figure 5C This illustrates another example of the relationship between the integrated concentration of collector region 22 and the depth of the first peak P1.

[0048] Figure 6A This illustrates another example of the relationship between the integrated concentration of collector region 22 and the depth of the first peak P1.

[0049] Figure 6B This illustrates another example of the relationship between the integrated concentration of collector region 22 and the depth of the first peak P1.

[0050] Figure 6C This illustrates another example of the relationship between the integrated concentration of collector region 22 and the depth of the first peak P1.

[0051] Figure 6D This illustrates another example of the relationship between the integrated concentration of collector region 22 and the depth of the first peak P1.

[0052] Figure 6E This illustrates another example of the relationship between the integrated concentration of collector region 22 and the depth of the first peak P1.

[0053] Figure 6F This illustrates another example of the relationship between the integrated concentration of collector region 22 and the depth of the first peak P1.

[0054] Figure 7A The relationship between the integrated concentration of collector region 22 and the depth of the second peak P2 is shown.

[0055] Figure 7B This illustrates another example of the relationship between the integrated concentration of the collector region 22 and the depth of the second peak P2.

[0056] Figure 7C The relationship between the integrated concentration of collector region 22 and the depth of the second peak P2 is shown.

[0057] Figure 8A This is a graph used to illustrate the relationship between stray inductance Ls and collector current reduction rate dIce / dt.

[0058] Figure 8B This is a graph used to illustrate the relationship between the stray inductance Ls·A and the current density dJce / dt.

[0059] Figure 9 This is a graph used to illustrate the relationship between specific stray inductance Ls·A and specific gate resistance Rg·A.

[0060] Symbol Explanation

[0061] 10: Semiconductor substrate; 12: Emitter region; 14: Base region; 15: Contact region; 16: Accumulation region; 17: Well region; 18: Drift region; 20: Field cutoff region; 21: Front side; 22: Collector region; 23: Back side; 24: Collector electrode; 25: Connector portion; 30: Dummy trench portion; 31: Extension portion; 32: Dummy insulating film; 33: Connector portion; 34: Dummy conductive portion; 38: Interlayer insulating film; 39: Oxide film; 40: Gate trench portion; 41: Extension portion; 42: Gate insulating film; 43: Connector portion; 44: Gate conductive portion; 50: Gate metal layer; 51: Gate channel; 52: Emitter electrode. 54: Contact hole, 55: Contact hole, 56: Contact hole, 60: Dummy trench region, 61: Mesa region, 65: Well contact region, 70: Transistor section, 71: Mesa region, 76: Temperature sensing section, 80: Diode section, 81: Mesa region, 82: Cathode region, 90: Boundary section, 91: Mesa region, 92: Guard ring section, 94: Electrode layer, 96: Channel cutoff region, 100: Semiconductor device, 110: Active region, 120: Peripheral region, 130: Pad region, 131: Gate pad, 132: Sensing IGBT, 133: Sensing emitter pad, 134: Anode pad, 135: Cathode pad, 500: Semiconductor device Detailed Implementation

[0062] The present invention will now be described through embodiments thereof; however, these embodiments do not limit the invention as defined in the claims. Furthermore, not all combinations of the features described in the embodiments are necessarily required for the solution of the invention.

[0063] In this specification, the side parallel to the depth direction of the semiconductor substrate is referred to as "upper" and the other side as "lower". One of the two main surfaces of the substrate, layer or other component is referred to as the upper surface and the other as the lower surface. The directions of "upper", "lower", "front" and "back" are not limited to the direction of gravity or the mounting direction towards the substrate when mounting a semiconductor device.

[0064] In this specification, orthogonal coordinate axes of X, Y, and Z are sometimes used to illustrate technical matters. Orthogonal coordinate axes only determine the relative positions of constituent elements and do not limit specific directions. For example, the Z-axis is not limited to representing the height direction relative to the ground. It should be noted that the +Z-axis direction and the -Z-axis direction are opposite to each other. When a direction is referred to as the Z-axis without specifying positive or negative, it refers to a direction parallel to the +Z-axis and -Z-axis.

[0065] In this specification, the plane parallel to the upper surface of the semiconductor substrate is designated as the XY plane, and the orthogonal axes parallel to the upper and lower surfaces of the semiconductor substrate are designated as the X-axis and Y-axis. Furthermore, the axis perpendicular to the upper and lower surfaces of the semiconductor substrate is designated as the Z-axis. Sometimes, the depth direction of the semiconductor substrate is referred to as the Z-axis. It should be noted that in this specification, the view of the semiconductor substrate along the Z-axis direction is referred to as a top view. Furthermore, in this specification, the direction parallel to the upper and lower surfaces of the semiconductor substrate, including the X-axis and Y-axis, is sometimes referred to as the horizontal direction.

[0066] Examples are shown in various embodiments where the first conductivity type is N-type and the second conductivity type is P-type, but it is also possible to set the first conductivity type to P-type and the second conductivity type to N-type. In this case, the conductivity types of the substrate, layer, region, etc., in each embodiment become opposite polarities.

[0067] In this specification, the terms "same" or "equal" may also include cases with errors due to manufacturing deviations, etc. Such errors are, for example, within 10%.

[0068] In this specification, the conductivity type of the doped region containing impurities is described as P-type or N-type. In this specification, impurities sometimes specifically refer to either an N-type donor or a P-type acceptor, and are sometimes referred to as dopant. In this specification, doping refers to introducing donors or acceptors into a semiconductor substrate to create a semiconductor exhibiting N-type conductivity or a semiconductor exhibiting P-type conductivity.

[0069] In this specification, doping concentration refers to the donor or acceptor concentration at thermal equilibrium. In this specification, net doping concentration refers to the net concentration obtained by adding the donor concentration as the concentration of positive ions and the acceptor concentration as the concentration of negative ions, taking into account charge polarity. As an example, if the donor concentration is set to N... D Set the acceptor concentration to N A Then the net doping concentration at any position is N. D -N A .

[0070] Donors have the function of supplying electrons to semiconductors. Acceptors have the function of accepting electrons from semiconductors. Donors and acceptors are not limited to impurities themselves. For example, VOH defects, which are formed by the combination of vacancies (V), oxygen (O), and hydrogen (H) in semiconductors, function as electron-supplying donors. Sometimes, VOH defects are simply referred to as hydrogen donors.

[0071] In this specification, when referred to as P+ or N+ type, it means that the doping concentration is higher than that of P- or N- type; when referred to as P- or N- type, it means that the doping concentration is lower than that of P- or N- type. Similarly, when referred to as P++ or N++ type, it means that the doping concentration is higher than that of P+ or N+ type.

[0072] In this specification, chemical concentration refers to the atomic density of an impurity, measured independently of its electroactivated state. Chemical concentration can be measured, for example, by secondary ion mass spectrometry (SIMS). The net doping concentration described above can be determined by voltage-capacitance measurement (CV). Alternatively, the carrier concentration measured by diffusion resistance measurement (SR) can be used as the net doping concentration. The carrier concentration measured by CV or SR can be taken as a value under thermal equilibrium conditions. Furthermore, in the N-type region, the donor concentration is much larger than the acceptor concentration; therefore, the carrier concentration in this region can be taken as the donor concentration. Similarly, in the P-type region, the carrier concentration in this region can be taken as the acceptor concentration. It should be noted that the concentrations in this invention can be values ​​at room temperature. As an example, values ​​at room temperature can be those at 300 K (Kelvin) (approximately 26.9°C).

[0073] Furthermore, when the concentration distribution of donor, acceptor, or net dopant has a peak, the peak value can be taken as the concentration of donor, acceptor, or net dopant in that region. When the concentration of donor, acceptor, or net dopant is approximately uniform, the average concentration of donor, acceptor, or net dopant in that region can be taken as the concentration of donor, acceptor, or net dopant.

[0074] The carrier concentration measured by the SR method can be lower than the donor or acceptor concentration. Within the range of current flow during diffusion resistance measurement, the carrier mobility of the semiconductor substrate is sometimes lower than that in the crystalline state. This decrease in carrier mobility is due to the dispersion of carriers caused by crystal structure disorder resulting from lattice defects, etc.

[0075] The donor or acceptor concentration calculated from the carrier concentration measured by the CV or SR method can be lower than the chemical concentration of the element representing the donor or acceptor. As an example, in silicon semiconductors, the donor concentration of phosphorus or arsenic (which are donors) or the acceptor concentration of boron (which is an acceptor) is about 99% of their chemical concentration. On the other hand, in silicon semiconductors, the donor concentration of hydrogen (which is a donor) is, for example, 0.1% to 10% of the chemical concentration of hydrogen.

[0076] Unless otherwise stated, the units in this manual are in the SI system. Although length is sometimes expressed in units such as cm, calculations can be performed after conversion to meters (m).

[0077] In this specification, doping concentration refers to the concentration of donor- or acceptor-modified dopants. Therefore, its unit is / cm². 3 In this specification, the concentration difference between donors and acceptors (i.e., net doping concentration) is sometimes used as the doping concentration. In this case, the doping concentration can be determined by the SR method. Alternatively, the chemical concentrations of donors and acceptors can be used as the doping concentration. In this case, the doping concentration can be determined by the SI MS method. Unless otherwise specified, any of the above methods can be used as the doping concentration. Unless otherwise specified, the peak value of the doping concentration distribution in the doped region can be used as the doping concentration in that doped region.

[0078] Additionally, in this specification, dosage refers to the number of ions implanted per unit area of ​​the wafer during ion implantation. Therefore, its unit is / cm². 2 It should be noted that the dose in the semiconductor region can be set as the integrated concentration obtained by integrating the doping concentration along the depth direction throughout the semiconductor region. The unit of this integrated concentration is / cm. 2 Therefore, the dose and integrated concentration can be treated as the same quantity. The integrated concentration can be set as the integral value up to the full width at half maximum (FWHM), and can be derived by removing the influence of other semiconductor regions when their spectra overlap with those of other semiconductor regions.

[0079] Therefore, in this specification, the level of doping concentration can be interpreted as the level of dose. That is, if the doping concentration in one region is higher than that in another region, it can be understood that the dose in that region is higher than that in the other region.

[0080] Figure 1A This is an example of a top view of a semiconductor device 100. The semiconductor device 100 includes an active region 110, an outer peripheral region 120, and a pad region 130. The semiconductor device 100 is a semiconductor chip including a transistor section 70 and a diode section 80. The semiconductor device 100 includes a temperature sensing section 76 and can be mounted in modules such as IPMs (Intelligent Power Modules).

[0081] The transistor section 70 includes transistors such as IGBTs (Insulated Gate Bipolar Transistors). The diode section 80 includes diodes such as freewheeling diodes (FWDs). In this example, the semiconductor device 100 is a reverse-conducting IGBT (RC-IGBT) having both the transistor section 70 and the diode section 80 on the same chip. In this example, the transistor in the transistor section 70 is an IGBT.

[0082] The semiconductor substrate 10 can be a silicon substrate, a silicon carbide substrate, or a gallium nitride semiconductor substrate, etc. In this example, the semiconductor substrate 10 is a silicon substrate. The semiconductor substrate 10 has an active region 110 and an outer peripheral region 120.

[0083] The transistor section 70 and the diode section 80 can be arranged alternately and periodically in the XY plane. The semiconductor device 100 in this example includes a plurality of transistor sections 70 and a plurality of diode sections 80. In this example, the transistor section 70 and the diode section 80 have trench sections extending along the Y-axis direction. However, the transistor section 70 and the diode section 80 may also have trench sections extending along the X-axis direction.

[0084] A temperature sensing unit 76 is disposed above the active region 110. The temperature sensing unit 76 may be formed of monocrystalline or polycrystalline silicon. If the temperature of the semiconductor device 100 changes, the forward voltage of the current flowing through the temperature sensing unit 76 changes. Based on the change in forward voltage, the temperature of the semiconductor device 100 can be detected.

[0085] The active region 110 includes a transistor section 70 and a diode section 80. The active region 110 is the area where the main current flows between the front and back surfaces of the semiconductor substrate 10 when the semiconductor device 100 is controlled to be in a conducting state. That is, it is the area within the semiconductor substrate 10 where current flows from the front surface to the back surface or from the back surface to the front surface along the depth direction. In this specification, the transistor section 70 and the diode section 80 are referred to as a device section or a device region, respectively.

[0086] It should be noted that, when viewed from above, the area sandwiched between the two component sections is also designated as the active region 110. In this example, the area sandwiched between the component sections and in which the gate flow channel 51 is provided is also included in the active region 110.

[0087] The gate current channel 51 can supply the gate potential from the gate pad 131 of the pad area 130 to the gate conductive portion of the transistor section 70. The gate current channel 51 is provided along the outer periphery of the active region 110 when viewed from above. The gate current channel 51 may also be provided in the region between the transistor section 70 and the diode section 80 when viewed from above.

[0088] The peripheral region 120, when viewed from above, is disposed around the end periphery of the semiconductor substrate 10, surrounding the active region 110 and the pad region 130. It is the region between the outer periphery of the semiconductor substrate 10 and the active region 110. The peripheral region 120, when viewed from above, surrounds the active region 110. The peripheral region 120 may have an edge termination structure. The edge termination structure mitigates the electric field concentration on the front side of the semiconductor substrate 10. For example, the edge termination structure may include a protective ring, a field plate, a surface electric field reduction section, and a structure combining these components.

[0089] The pad area 130 includes a gate pad 131, a sensing IGBT 132, a sensing emitter pad 133, an anode pad 134, and a cathode pad 135. In this example, the cathode pad 135, anode pad 134, gate pad 131, sensing IGBT 132, and sensing emitter pad 133 are arranged in this order along the X-axis. Each pad can be an electrode pad containing gold (Au), silver (Ag), copper (Cu), or aluminum (Al).

[0090] The gate pad 131 is electrically connected to the gate conductive portion of the transistor section 70 via the gate channel 51. The gate pad 131 is set to the gate potential.

[0091] The sensing IGBT 132 is an IGBT used to detect the main current flowing through the transistor section 70. A current proportional to the main current flowing through the transistor section 70 flows through the sensing IGBT 132. By introducing the sensing current flowing through the sensing IGBT 132 into a control circuit located outside the semiconductor device 100, the main current of the transistor section 70 can be detected. In this example, the sensing emitter pad 133 has the same potential as the emitter of the sensing IGBT 132. The sensing current can be introduced from the sensing emitter pad 133 through the sensing IGBT 132 into the aforementioned control circuit. The control circuit can detect the main current based on the sensing current and cut off the current flowing through the transistor section 70 in the event of an overcurrent.

[0092] The anode pad 134 is electrically connected to the temperature sensing unit 76 and is set to the anode potential of the temperature sensing unit 76. Similarly, the cathode pad 135 is electrically connected to the temperature sensing unit 76 and is set to the cathode potential of the temperature sensing unit 76. Using the anode pad 134 and the cathode pad 135, the potential difference between the anode and cathode of the temperature sensing unit 76 can be detected.

[0093] Figure 1B Is with Figure 1A An example of a top view of the semiconductor device 100 corresponding to region A is shown. Specifically, an enlarged view of the end of the active region 110 is shown.

[0094] The transistor section 70 is a region obtained by projecting the collector region 22, which is disposed on the back side of the semiconductor substrate 10, onto the front side of the semiconductor substrate 10. The collector region 22 has a second conductivity type. As an example, the collector region 22 in this example is P+ type. The transistor section 70 includes a boundary section 90 located at the boundary between the transistor section 70 and the diode section 80.

[0095] The diode section 80 is a region obtained by projecting the cathode region 82, which is disposed on the back side of the semiconductor substrate 10, onto the front side of the semiconductor substrate 10. The cathode region 82 has a first conductivity type. As an example, the cathode region 82 in this example is of the N+ type.

[0096] The semiconductor device 100 in this example has a gate trench 40, a dummy trench 30, an emitter region 12, a base region 14, a contact region 15, and a well region 17 on the front side of the semiconductor substrate 10. In addition, the semiconductor device 100 in this example has an emitter electrode 52 and a gate metal layer 50 disposed on the upper part of the front side of the semiconductor substrate 10.

[0097] The emitter electrode 52 is disposed above the gate trench portion 40, the dummy trench portion 30, the emitter region 12, the base region 14, the contact region 15, and the well region 17. Additionally, the gate metal layer 50 is disposed above the well region 17 and the gate channel 51. In this example, the emitter electrode 52 is set to the emitter potential of the transistor portion 70.

[0098] The gate metal layer 50 is electrically connected to the gate conductive portion of the transistor section 70, supplying a gate voltage to the transistor section 70. The gate metal layer 50 is electrically connected to the gate pad 131. The gate metal layer 50 is disposed along the outer periphery of the active region 110 when viewed from above. The gate metal layer 50 may also be disposed between the transistor section 70 and the diode section 80 when viewed from above.

[0099] The gate channel 51 connects the gate metal layer 50 to the gate conductive portion within the gate trench portion 40. The gate channel 51 is not connected to the dummy conductive portion within the dummy trench portion 30. For example, the gate channel 51 is formed of polysilicon or the like, which is doped with impurities.

[0100] The emitter electrode 52 and the gate metal layer 50 are formed of a metal-containing material. For example, at least a portion of the emitter electrode 52 may be formed of aluminum, an aluminum-silicon alloy, or an aluminum-silicon-copper alloy. The emitter electrode 52 may have a barrier metal formed of titanium, titanium compounds, or the like in a layer beneath the region formed of aluminum. The emitter electrode 52 and the gate metal layer 50 are disposed separately from each other.

[0101] The emitter electrode 52 and the gate metal layer 50 are disposed above the semiconductor substrate 10, separated by an interlayer insulating film 38. Figure 1B The interlayer insulating film 38 is omitted. Contact holes 54, 55 and 56 are provided through the interlayer insulating film 38.

[0102] The contact hole 55 connects the gate metal layer 50 to the gate flow channel 51. A plug made of tungsten or the like can be formed inside the contact hole 55. The contact hole 55 can be disposed along the gate flow channel 51.

[0103] The contact hole 56 connects the emitter electrode 52 to the dummy conductive part within the dummy trench portion 30. A plug made of tungsten or the like can be formed inside the contact hole 56.

[0104] The connection portion 25 electrically connects the emitter electrode 52 to the plug inside the contact hole 56. The connection portion 25 is made of a conductive material such as polycrystalline silicon doped with impurities. In this example, the connection portion 25 is polycrystalline silicon doped with N-type impurities. When viewed from above, the connection portion 25 covers an area larger than the contact hole 56. The connection portion 25 is disposed above the front side of the semiconductor substrate 10 through an insulating film such as an oxide film.

[0105] The gate trench portions 40 are arranged at predetermined intervals along a predetermined arrangement direction (X-axis direction in this example). The gate trench portions 40 in this example may have two extension portions 41 extending along an extension direction (Y-axis direction in this example) that is parallel to the front surface of the semiconductor substrate 10 and perpendicular to the arrangement direction. The connection portion 43 connects the two extension portions 41.

[0106] The connection portion 43 is preferably at least partially formed in a curved shape. By connecting the ends of the two extension portions 41 of the gate trench portion 40, the electric field concentration at the ends of the extension portions 41 can be mitigated. In the connection portion 43 of the gate trench portion 40, the gate flow channel 51 can be connected to the gate conductive portion.

[0107] The dummy trench portion 30 is a trench portion electrically connected to the emitter electrode 52. The dummy trench portion 30, like the gate trench portion 40, is arranged at predetermined intervals along a predetermined arrangement direction (the X-axis direction in this example). In this example, the dummy trench portion 30 may have a U-shape on the front side of the semiconductor substrate 10, similar to the gate trench portion 40. That is, the dummy trench portion 30 may have two extension portions 31 extending along the extension direction and a connecting portion 33 connecting the two extension portions 31.

[0108] Well region 17 is a second conductivity type region located further on the front side of the semiconductor substrate 10 than drift region 18, which will be described later. Well region 17 is an example of a well region located on the edge side of semiconductor device 100. As an example, well region 17 is P+ type. Well region 17 is formed within a predetermined range from the end of active region 110 on the side where gate metal layer 50 is provided. The diffusion depth of well region 17 can be deeper than the depth of gate trench portion 40 and dummy trench portion 30. A portion of the gate metal layer 50 side of gate trench portion 40 and dummy trench portion 30 is formed in well region 17. The bottom of the ends of the extending direction of gate trench portion 40 and dummy trench portion 30 can be covered by well region 17.

[0109] Contact holes 54 are formed in the transistor section 70 above each region of the emitter region 12 and the contact region 15. Additionally, contact holes 54 are provided in the diode section 80 above the base region 14. Contact holes 54 are provided in the boundary section 90 above the contact region 15. No contact holes 54 are provided above the well regions 17 located at either end in the extending direction. Thus, one or more contact holes 54 are formed in the interlayer insulating film 38. One or more contact holes 54 can be provided extending along the extending direction.

[0110] The boundary portion 90 is a region disposed on the transistor portion 70 and adjacent to the diode portion 80. The boundary portion 90 has a contact region 15. In this example, the boundary portion 90 does not have an emitter region 12. In this example, the boundary portion 90 is configured such that both ends in the arrangement direction become dummy trench portions 30.

[0111] Mesa portions 71, 91, and 81 are mesa portions disposed adjacent to the trench portions in a plane parallel to the front surface of the semiconductor substrate 10. A mesa portion refers to the portion of the semiconductor substrate 10 sandwiched between two adjacent trench portions, and can be the portion extending from the front surface of the semiconductor substrate 10 to the deepest bottom of each trench portion. An extension portion of each trench portion can be defined as a single trench portion. That is, the area sandwiched between two extension portions can be considered a mesa portion.

[0112] The mesa portion 71 is disposed adjacent to at least one of the dummy trench portion 30 or the gate trench portion 40 in the transistor portion 70. The mesa portion 71 has a well region 17, an emitter region 12, a base region 14, and a contact region 15 on the front side of the semiconductor substrate 10. In the mesa portion 71, the emitter region 12 and the contact region 15 are alternately disposed in the extending direction.

[0113] A mesa 91 is provided on the boundary portion 90. The mesa 91 has a base region 14, a contact region 15, and a well region 17 on the front side of the semiconductor substrate 10. In this example, both ends of the mesa 91 in the arrangement direction are in contact with the dummy trench portion 30, but at least one end may be in contact with the gate trench portion 40. In this example, one mesa 91 is provided, but multiple mesa 91s may also be provided.

[0114] The mesa portion 81 is disposed in the diode portion 80 in the region sandwiched by the adjacent dummy trench portion 30. The mesa portion 81 has a base region 14 and a well region 17 on the front side of the semiconductor substrate 10.

[0115] The base region 14 is a region of a second conductivity type disposed on the front side of the semiconductor substrate 10 in the transistor section 70 and the diode section 80. As an example, the base region 14 is P-type. The base region 14 can be disposed at both ends of the mesa 71 and mesa 91 on the front side of the semiconductor substrate 10 in the extending direction. It should be noted that... Figure 1B Only one end of the base region 14 in the direction of extension is shown.

[0116] Emitter region 12 is a region of the first conductivity type with a higher doping concentration than drift region 18. As an example, emitter region 12 in this example is N+ type. An example of the dopant for emitter region 12 is arsenic (As). Emitter region 12 is disposed on the front side of mesa 71 in contact with gate trench portion 40. Emitter region 12 can be disposed such that it extends from one of the two trench portions sandwiching mesa 71 along the arrangement direction to the other trench portion. Emitter region 12 is also disposed below contact hole 54.

[0117] Furthermore, the emitter region 12 may or may not contact the dummy trench portion 30. In this example, the emitter region 12 contacts the dummy trench portion 30. The emitter region 12 may not be provided on the platform surface 91 of the boundary portion 90.

[0118] Contact region 15 is a region of the second conductivity type with a higher doping concentration than the base region 14. As an example, contact region 15 in this example is P+ type. In this example, contact region 15 is disposed on the front side of mesa 71 and mesa 91. Contact region 15 can be disposed along the arrangement direction from one of the two trench portions sandwiching mesa 71 or mesa 91 to the other trench portion. Contact region 15 may or may not contact gate trench portion 40. Additionally, contact region 15 may or may not contact dummy trench portion 30. In this example, contact region 15 contacts both dummy trench portion 30 and gate trench portion 40. Contact region 15 is also disposed below contact hole 54. It should be noted that contact region 15 may also be disposed on mesa 81.

[0119] Figure 1C It is shown Figure 1B The diagram shows an example of a b-b' cross-section. The b-b' cross-section is the XZ plane passing through the emitter region 12 in the transistor section 70. In this example, the semiconductor device 100 has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24 in the b-b' cross-section. The emitter electrode 52 is formed above the semiconductor substrate 10 and the interlayer insulating film 38.

[0120] Drift region 18 is a region of a first conductivity type disposed on semiconductor substrate 10. As an example, drift region 18 in this example is N-type. Drift region 18 can be a region remaining in semiconductor substrate 10 where no other doped regions are formed. That is, the doping concentration of drift region 18 can be the doping concentration of semiconductor substrate 10.

[0121] The field cutoff region 20 is a region of the first conductivity type located below the drift region 18. As an example, the field cutoff region 20 in this example is N-type. The doping concentration of the field cutoff region 20 is higher than that of the drift region 18. The field cutoff region 20 prevents the depletion layer extending from the lower surface side of the base region 14 from reaching the collector region 22 of the second conductivity type and the cathode region 82 of the first conductivity type.

[0122] The field cutoff region 20 may have one or more peaks. In this example, the field cutoff region 20 has four peaks: the first peak P1 to the fourth peak P4. The dopant for one or more peaks can be hydrogen.

[0123] The first peak P1 to the fourth peak P4 are arranged sequentially from the back side 23. That is, the first peak P1 is the peak closest to the back side 23. The doping concentration of the first peak P1 can be higher than that of the other peaks. As a result, the depletion layer can be stopped slowly and reliably when voltage is applied.

[0124] The collector region 22 is disposed below the field cutoff region 20 in the transistor section 70. The cathode region 82 is disposed below the field cutoff region 20 in the diode section 80. The boundary between the collector region 22 and the cathode region 82 is the boundary between the transistor section 70 and the diode section 80.

[0125] Collector electrode 24 is formed on the back side 23 of semiconductor substrate 10. Collector electrode 24 is formed of conductive material such as metal.

[0126] The base region 14 is a second conductivity type region disposed above the drift region 18 in the mesa 71, mesa 91, and mesa 81. The base region 14 is disposed in contact with the gate trench portion 40. The base region 14 may be disposed in contact with the dummy trench portion 30.

[0127] The emitter region 12 is disposed in the mesa 91 between the base region 14 and the front surface 21. The emitter region 12 is disposed in contact with the gate trench portion 40. The emitter region 12 may or may not be in contact with the dummy trench portion 30. It should be noted that the emitter region 12 may not be disposed in the mesa 91.

[0128] The contact area 15 is provided in the table surface 91 above the base area 14. The contact area 15 is provided in the table surface 91 in such a way that it contacts the dummy groove portion 30. In other cross-sections, the contact area 15 may be provided on the front surface 21 of the table surface 71.

[0129] The accumulation region 16 is a first conductivity type region located on the front side 21 of the semiconductor substrate 10, further than the drift region 18. As an example, the accumulation region 16 in this example is N+ type. The accumulation region 16 is provided in the transistor section 70 and the diode section 80. In this example, the accumulation region 16 is also provided in the boundary section 90.

[0130] Furthermore, the accumulation region 16 is provided in contact with the gate trench portion 40. The accumulation region 16 may or may not be in contact with the dummy trench portion 30. The doping concentration of the accumulation region 16 is higher than that of the drift region 18. By providing the accumulation region 16, the carrier injection enhancement effect (IE effect) can be improved, thereby reducing the turn-on voltage of the transistor portion 70.

[0131] One or more gate trenches 40 and one or more dummy trenches 30 are disposed on the front side 21. Each trench extends from the front side 21 to the drift region 18. In regions where at least one of the emitter region 12, base region 14, contact region 15, and accumulation region 16 is disposed, each trench also extends through these regions to reach the drift region 18. The trench extending through the doped region is not limited to the case where the trenches are formed after the doped regions are formed. The case where the doped regions are formed between the trenches after the trenches are formed is also included in the case where the trenches extend through the doped regions.

[0132] The gate trench portion 40 has a gate trench formed on the front side 21, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is formed to cover the inner wall of the gate trench. The gate insulating film 42 can be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is formed inside the gate trench at a position further inward than the gate insulating film 42. The gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon. The gate trench portion 40 is covered on the front side 21 by an interlayer insulating film 38.

[0133] The gate conductive portion 44 includes a region in the depth direction of the semiconductor substrate 10 that faces the base region 14 adjacent to the mesa 71 side, separated by the gate insulating film 42. If a predetermined voltage is applied to the gate conductive portion 44, a channel formed by an electron inversion layer is formed on the surface layer of the interface in the base region 14 that contacts the gate trench.

[0134] The dummy trench portion 30 may have the same structure as the gate trench portion 40. The dummy trench portion 30 has a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 formed on the front side 21. The dummy insulating film 32 is formed to cover the inner wall of the dummy trench. The dummy conductive portion 34 is formed inside the dummy trench and is located further inward than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy trench portion 30 is covered on the front side 21 by an interlayer insulating film 38.

[0135] An interlayer insulating film 38 is disposed on the front side 21. An emitter electrode 52 is disposed above the interlayer insulating film 38. One or more contact holes 54 are provided on the interlayer insulating film 38 for electrically connecting the emitter electrode 52 to the semiconductor substrate 10. Contact holes 55 and 56 can also be provided in a manner that penetrates through the interlayer insulating film 38.

[0136] Figure 1D It is shown Figure 1CThis is a diagram illustrating an example of the doping concentration distribution along the depth direction at the location of the c-c' line. The c-c' line passes through the region from the emitter region 12 to the collector region 22 in the transistor section 70. Figure 1D The vertical axis is the logarithmic axis. It should be noted that in this example, the doping concentration distribution of the field cutoff region 20 in the transistor section 70 is described, but the field cutoff region 20 in the diode section 80 may also have the same doping concentration distribution.

[0137] In this example, the doping concentration of drift region 18 is the bulk donor concentration Db. The semiconductor substrate 10 in this example has bulk donors of the first conductivity type (N-type) distributed throughout. Bulk donors are donors formed by dopants that are substantially uniformly contained within the ingot during the manufacture of the raw material for the semiconductor substrate 10. In this example, the bulk donors are elements other than hydrogen. Examples of bulk donor dopants include phosphorus, antimony, arsenic, selenium, and sulfur, but are not limited to these. In this example, the bulk donor is phosphorus. Bulk donors are also contained in the P-type regions. The semiconductor substrate 10 can be a wafer cut from a semiconductor ingot or a chip formed by monolithically stacking wafers. The semiconductor ingot can be manufactured using any of the following methods: the Czochralski method (CZ method), the magnetic field applied Czochralski method (MCZ method), or the floating zone method (FZ method). In this example, the ingot is manufactured using the MCZ method. The bulk donor concentration Db can be the chemical concentration of donors distributed throughout the semiconductor substrate 10, or a value between 90% and 100% of that chemical concentration.

[0138] In this example, we will explain the case where the doping concentration distribution in the field stop region 20 has four concentration peaks P1, P2, P3, and P4 at different locations along the depth direction. However, the number of concentration peaks is not limited to this. In this example, the concentration peaks are donor concentration peaks. Multiple concentration peaks can be formed by injecting impurities such as hydrogen or phosphorus into multiple depth locations in the field stop region 20. As an example, phosphorus can be used at position P1, and hydrogen as a donor can be used at positions P2 to P4. In this example, all of P1 to P4 are hydrogen as a donor. The field stop region 20 can have concentration peaks of impurities such as hydrogen or phosphorus at positions corresponding to the concentration peaks. The impurity concentration peaks are peaks in the chemical concentration distribution of the impurities. By setting multiple concentration peaks, it is possible to further suppress the depletion layer from reaching the collector region 22.

[0139] Figure 1E yes Figure 1C Enlarged view of the doping concentration distribution in the field cutoff region 20 and the collector region 22. Figure 1E The vertical axis is the logarithmic axis. Figure 1E In the diagram, the peak doping concentrations of multiple concentration peaks P1, P2, P3, and P4 are d1, d2, d3, and d4, respectively. Furthermore, the depth of the pn junction between the collector region 22 and the field cutoff region 20 is set to J1.

[0140] Multiple concentration peaks include the shallowest peak closest to the back surface 23 of the semiconductor substrate 10. In this example, concentration peak P1 corresponds to the shallowest peak. In this example, concentration peak P1 is the concentration peak closest to the collector region 22. In the field cutoff region 20 of the diode section 80, concentration peak P1 is the concentration peak closest to the cathode region 82. The cathode region 82 can be formed by implanting impurities different from the concentration peaks. For example, the cathode region 82 has impurity concentration peaks such as phosphorus, and the field cutoff region 20 has impurity concentration peaks such as hydrogen.

[0141] Multiple concentration peaks include a high concentration peak located further away from the back surface 23 than the shallowest peak (concentration peak P1). The high concentration peak can be the concentration peak P2 closest to the shallowest peak, or it can be any other concentration peak. Figure 1E In the example, the concentration peak P2, which is closest to the concentration peak P1, is equivalent to the high concentration peak.

[0142] The multiple concentration peaks include a low concentration peak located further away from the back surface 23 than the high concentration peak and whose peak doping concentration is less than 1 / 5 of the high concentration peak's peak value. The low concentration peak can be the deepest peak located furthest from the back surface 23 among the multiple concentration peaks (concentration peak P4 in this example). The low concentration peak can also be any concentration peak other than the deepest peak. That is, the low concentration peak can be a concentration peak between the high concentration peak and the deepest peak.

[0143] Alternatively, two or more low-concentration peaks can be set. The low-concentration peaks are preferably arranged adjacently in the depth direction. Two or more concentration peaks furthest from the back surface 23 among multiple concentration peaks can be low-concentration peaks. Figure 1E In the example, the concentration peak P4, which is the deepest peak, the concentration peak P3, which is located towards the back surface 23 and is the second deepest peak but far from the back surface 23, and the concentration peak P2, which is the second deepest peak but close to the back surface 23, are low concentration peaks. Alternatively, any concentration peak other than the one closest to the back surface 23 can be designated as a low concentration peak. Figure 1E In the example, the peak doping concentration d3 of concentration peak P3 and the peak doping concentration d4 of concentration peak P4 are both less than 1 / 5 of the peak doping concentration d1 of concentration peak P1. The peak doping concentration d2 to d4 of low concentration peaks P2 to P4 can be less than 1 / 10 of the peak doping concentration d1 of concentration peak P1. It should be noted that in this example, the peak doping concentration d3 of P3 is lower than the peak doping concentration d4 of P4. The peak doping concentration d3 of P3 can also be higher than the peak doping concentration d4 of P4. That is, the peak values ​​of P2 to P4 can decrease towards the front 21.

[0144] In situations such as when two series-connected semiconductor devices 100 are simultaneously turned on in a short-circuit state, a high voltage is sometimes applied between the emitter and collector of the semiconductor device 100. In this case, the electric field tends to concentrate near the deepest peak (concentration peak P4 in this example) in the field-off region 20. Therefore, increasing the doping concentration near the deepest peak, as with concentration peaks P3 and P4, promotes electric field concentration. If the electric field concentrates, the gate voltage tends to fluctuate when the semiconductor device 100 is turned off.

[0145] In this example, a low-concentration peak with a sufficiently low doping concentration is positioned deeper than the high-concentration peak (concentration peak P1). Therefore, the electric field concentration at deeper locations in the field cutoff region 20 can be mitigated. As mentioned above, there can be one or more low-concentration peaks. This allows the field cutoff region 20 with a relatively low concentration to be formed longer towards the drift region 18. Figure 1E In one example, the field cutoff region 20 has three low-concentration peaks, but in other examples, the field cutoff region 20 may have four or more low-concentration peaks. Additionally, the deepest peak may be located on the front side 21 of the semiconductor substrate 10. By setting the drift region 18 side of the field cutoff region 20 as a low-concentration region and making the low-concentration region long in the depth direction, electric field concentration is mitigated, and the field cutoff function is easily maintained.

[0146] The peak value of the low-concentration peak can be less than 1 / 5, 1 / 10, or even 1 / 20 of the peak value of the high-concentration peak. By reducing the doping concentration of the low-concentration peak, the electric field concentration can be further mitigated.

[0147] Furthermore, the peak value of the low-concentration peak doping concentration is higher than the bulk donor concentration Db. The peak value of the low-concentration peak doping concentration can be less than 50 times the bulk donor concentration Db of the semiconductor substrate 10. The doping concentration of the drift region 18 can be used as the bulk donor concentration Db. The peak value of the low-concentration peak doping concentration can be less than 20 times, less than 10 times, less than 8 times, less than 5 times, less than 3 times, or less than 2 times the bulk donor concentration Db.

[0148] Furthermore, the minimum doping concentration between low-concentration peaks can be higher than the bulk donor concentration Db, and can be less than 5 times, less than 3 times, or less than 2 times the bulk donor concentration Db. The ratio of the minimum inter-peak concentration to the concentration of any adjacent low-concentration peak can be less than 0.8, less than 0.5, or less than 0.2, and can be greater than 0.1, greater than 0.2, or greater than 0.5.

[0149] Let the depth directions of concentration peaks P1, P2, P3, and P4 be Z1, Z2, Z3, and Z4, respectively. The depth direction distance between concentration peak P4 and concentration peak P2 is Z4 - Z2. Additionally, the depth direction distance between concentration peak P1 and concentration peak P2 is Z2 - Z1. Distance Z4 - Z2 can be greater than distance Z2 - Z1. Similarly, the distance between concentration peak P3 and concentration peak P4 is Z4 - Z3. The distance between concentration peak P3 and concentration peak P2 is Z3 - Z2. Distance Z4 - Z3 can be greater than distance Z3 - Z2. Furthermore, distance Z4 - Z3 can be greater than distance Z2 - Z1.

[0150] Furthermore, the peak doping concentration of concentration peak P4 can be less than 1 / 5, 1 / 10, or 1 / 20 of the peak doping concentration of the high concentration peak. The peak doping concentration of concentration peak P4 is higher than the bulk donor concentration Db. The average value of the peak doping concentrations of concentration peaks P4 and P3 can be less than 50 times, 20 times, 10 times, 8 times, 5 times, 3 times, or 2 times the bulk donor concentration Db. By reducing the average doping concentration of the two deepest concentration peaks, the electric field concentration in the field cutoff region 20 near drift region 18 can be mitigated.

[0151] In this example, the donor or acceptor concentration in the pn junction J1 between the collector region 22 and the field cutoff region 20 can be 1E16 / cm². 3 The following can be 5E15 / cm 3 The following can also be 2E15 / cm 3 The following should be noted: E refers to a power of 10, for example, 1E¹⁶ / cm². 3 It refers to 1×10 16 / cm 3 .

[0152] Figure 1F This is a graph showing an example of the distribution of net doping concentration and hydrogen chemical concentration along the depth direction in the first concentration peak and collector region 22. The solid line represents an example of the distribution of net doping concentration, and the dashed line represents an example of the distribution of hydrogen chemical concentration. Figure 1F The vertical axis is the logarithmic axis. Here, Figure 1F The area indicated by the diagonal line represents the integrated concentration of collector region 22 in this example. That is, in this specification, the integrated concentration of collector region 22 refers to the concentration obtained by integrating the net doping concentration of collector region 22 along the depth direction of the semiconductor substrate 10 from the back side to the pn junction position J1 with the field stop region 20. Furthermore, the hydrogen chemical concentration Dh in the pn junction J1 between collector region 22 and field stop region 20 can be 1E18 / cm³. 3 The following can also be 1E17 / cm3 Below, and can be 1E16 / cm 3 The above can also be expressed as 1E15 / cm 3 above.

[0153] Figure 1G Is with Figure 1A This is an example of a top view of the semiconductor device 100 corresponding to region B. In this example, an enlarged view of the end of the active region 110 is shown. Region B is the region that includes the transistor portion 70 of the active region 110 and the gate flow channel 51. The semiconductor device 100 in this example includes a dummy trench region 60 and a well contact region 65.

[0154] The dummy trench region 60 is a region that has only dummy trench portions 30 as trench portions. The dummy trench region 60 is disposed in the arrangement direction between the gate trench portion 40 closest to the outer peripheral region 120 and the outer peripheral region 120. The dummy trench region 60 has a plurality of dummy trench portions 30 arranged at predetermined intervals in the arrangement direction.

[0155] A well contact region 65 is provided in a portion of the well region 17 to draw holes injected from the collector region 22 to the emitter electrode 52. The well contact region 65 has a contact region 15. A contact hole 54 is provided on the contact region 15 of the well contact region 65. The contact region 15 is electrically connected to the emitter electrode 52 through a plurality of contact holes 54. It should be noted that the semiconductor device 100 may also be without the well contact region 65.

[0156] A base region 14, a contact region 15, and a well region 17 are provided on the mesa 61. The contact region 15 is provided in the mesa 61 from one adjacent dummy trench 30 in the arrangement direction to another dummy trench 30. In this example, the mesa 61 has a contact region 15, so it becomes easier to extract holes compared to the case without a contact region 15. This prevents damage to the semiconductor device 100 caused by the concentration of avalanche current at the end of the well region 17.

[0157] The emitter electrode 52 is also disposed above the dummy trench region 60 and the well contact region 65. The emitter electrode 52 is electrically connected to the front side 21 of the semiconductor substrate 10 via the contact hole 54 in the dummy trench region 60, the well contact region 65 and the transistor section 70, respectively.

[0158] The trap region 17 is located on the outer periphery of the active region 110 when viewed from above. The inner end of the trap region 17 is shown in dashed lines.

[0159] The accumulation region 16 is provided in a manner that extends from the transistor section 70 to the dummy trench region 60. In this example, the accumulation region 16 is provided as a mesa 61 midway along the extension from the transistor section 70 to the dummy trench region 60. By providing the accumulation region 16 in a manner that extends from the transistor section 70 to the dummy trench region 60, even if the mask used to form the accumulation region 16 deviates, the impact on the accumulation region 16 formed in the transistor section 70 is reduced. As a result, deviations in the gate threshold voltage (Vth) and saturation current can be suppressed. The outer end of the accumulation region 16 is shown in dashed lines.

[0160] Figure 1H It is shown Figure 1A A diagram illustrating an example of section a-a' in the diagram. In this example, a cross-sectional view is shown spanning the active region 110 and the outer peripheral region 120. The outer peripheral region 120 in this example has a protective ring structure and a channel cutoff structure.

[0161] The guard ring structure may include multiple guard ring portions 92. In this example, the guard ring structure includes five guard ring portions 92. Each guard ring portion 92 may be configured to surround the active area 110 and the pad area 130 on the front side 21.

[0162] The guard ring structure can extend the depletion layer generated in the active region 110 to the outside of the semiconductor substrate 10. This prevents electric field concentration inside the semiconductor substrate 10. Therefore, compared to the case without a guard ring structure, the withstand voltage of the semiconductor device 100 can be improved.

[0163] The guard ring 92 is a P+ type semiconductor region formed near the front side 21 by ion implantation. The guard ring 92 is electrically connected to the electrode layer 94. The electrode layer 94 can be made of the same material as the gate metal layer 50 or the emitter electrode 52.

[0164] Multiple guard ring portions 92 are electrically insulated from each other by interlayer insulating film 38. The bottom depth of the guard ring portion 92 can be the same as the bottom depth of the well region 17. The bottom depth of the guard ring portion 92 can be deeper than the bottom depth of the gate trench portion 40 and the dummy trench portion 30.

[0165] The channel cutoff structure has a channel cutoff region 96 and an electrode layer 94. The channel cutoff region 96 is electrically connected to the electrode layer 94 through an opening in the interlayer insulating film 38. The conductivity type of the channel cutoff region 96 can be either a first conductivity type or a second conductivity type. In this example, the conductivity type of the channel cutoff region 96 is N+. The channel cutoff region 96 has the function of terminating the depletion layer generated in the active region 110 at the outer end of the semiconductor substrate 10.

[0166] The well region 17 can extend further outward beyond the well contact region 65 in the arrangement direction. In this example, the well region 17 can be configured such that the distance between the innermost protective ring portion 92 in the outer peripheral region 120 and the outermost end of the well region 17 is close. It should be noted that, as a variation of this example, the base region 14 can be extended to the vicinity of the innermost protective ring portion 92 instead of the well region 17. It should be noted that an oxide film 39 can be provided above the well region 17 between the contact region 15 and the gate flow channel 51. The oxide film 39 can be formed in the same process as the dummy insulating film 32 or the gate insulating film 42. Alternatively, the oxide film 39 can also be formed in a process of forming a thicker field oxide film, etc.

[0167] Figure 2A This is an example of a circuit used for clamping withstand testing of a semiconductor device 100. A gate voltage Vg is applied to the gate terminal of the semiconductor device 100 via a predetermined gate resistor Rg. In the clamping withstand test, a predetermined power supply voltage Vcc is used to switch the rated current Ic. The power supply voltage Vcc can be approximately 60% of the rated voltage.

[0168] The stray inductance Ls is the stray inductance of the circuit connecting the semiconductor device 100. Because the stray inductance Ls attempts to maintain the current, a surge voltage is generated when the current is cut off. The stray inductance Ls is increased with each switching operation from a predetermined initial value, causing the semiconductor device 100 to turn off. If the stray inductance Ls is increased, the switching voltage ΔV increases. By increasing the stray inductance Ls, the electric field strength inside the semiconductor device 100 increases, making the component more susceptible to damage. Here, the result of the test preceding component damage is defined as the clamping energy (i.e., damage tolerance).

[0169] Figure 2B This is a graph used to illustrate the clamping energy of semiconductor device 100. The graph shows the behavior of the collector-emitter current Ice and the collector-emitter voltage Vce during turn-off. The graph in this example shows the waveform of the stray inductance Ls that causes component failure during a clamping withstand test, achieved by repeatedly turning off the device while increasing the stray inductance Ls. Upon turn-off of semiconductor device 100, the collector-emitter voltage Vce jumps and is maintained for a certain period. This period of constant voltage is the clamping period.

[0170] Clamping energy is the integral value of current × voltage above 0 during the period from the transition of the collector-emitter voltage Vce to its stabilization at the supply voltage Vcc. In other words, clamping energy is represented by the integral value of ∫Ice×Vce dt (i.e., the energy value). A larger clamping energy indicates greater destructive strength during turn-off.

[0171] Figure 3AThe relationship between the doping concentration of collector region 22 and clamping energy is shown. The vertical axis represents the clamping energy [mJ], and the horizontal axis represents the integral value (hereinafter referred to as the integral value of the doping concentration of collector region 22) obtained by integrating the doping concentration of collector region 22 over a depth from the back surface 23 to the PN junction between collector region 22 and field cutoff region 20 [cm]. -2 The black squares represent cases where the proton acceleration energy is 400 keV. The white squares represent cases where the proton acceleration energy is 300 keV. A proton is a type of hydrogen ion. Hydrogen donors are formed, for example, by implanting protons as ions into a semiconductor substrate.

[0172] The lower the proton acceleration energy, the lower the total proton dose, and the easier it is to increase the clamping energy. Furthermore, if the total proton dose is low, the hole concentration injected from the back side 23 increases during avalanche breakdown, making avalanche breakdown more likely to occur on the active region 110 side. Thus, if the clamping withstand voltage of the active region 110 is lower than that of the peripheral region 120, transient damage in the peripheral region 120 can be easily prevented, as described later. Transient damage refers to, for example, damage to the component that occurs before the current is cut off during turn-off.

[0173] For example, at a proton acceleration energy of 300 keV, the integral value of the doping concentration in collector region 22 is approximately 1.00E+14 [cm]. -2 The clamping energy reaches its maximum value at this point. In this case, for example, the proton range of the first peak P1 becomes 3.13 μm. It should be noted that 1.00E+14 [cm] -2 ] represents 1.00 × 10 14 [cm -2 ].

[0174] Furthermore, with a proton acceleration energy of 400 keV, the integral value of the doping concentration in collector region 22 is approximately 1.00E+13 [cm]. -2 The clamping energy reaches its maximum value at this point. In this case, for example, the proton range is 4.52 μm.

[0175] It should be noted that the integral value of the doping concentration of the collector region 22 is approximately equal to the implantation dose of boron on the back side, so the implantation dose can be set as the integral value of the doping concentration of the collector region 22.

[0176] In this example, the semiconductor device 100 controls the integral concentration of the collector region 22 and the peak depth of the field cutoff region 20, thereby making the clamping breakdown voltage of the active region 110 lower than that of the peripheral region 120. This improves the clamping energy of the semiconductor device 100.

[0177] Figure 3BThis diagram illustrates the relationship between the doping concentration of collector region 22 and the device's breakdown voltage. The vertical axis represents the device's breakdown voltage [V], and the horizontal axis represents the doping concentration of collector region 22 [cm]. -3 The collector region 22 may have a doping concentration distribution with peaks. In this case, the doping concentration of the collector region 22 may be the peak value of the doping concentration of the collector region 22. In this example, the case where the field cutoff region 20 has four peaks will be explained.

[0178] Curve G1 represents the active + edge model with four peaks in the field cutoff region 20. The active + edge model is a simulation model that considers both the active region 110 and the peripheral region 120. Curve G2 represents the active model with four peaks in the field cutoff region 20. The active model is a simulation model that only considers the active region 110 and not the peripheral region 120.

[0179] By reducing the doping concentration of the collector region 22, the breakdown voltage of the active region 110 is further reduced compared to the breakdown voltage of the outer peripheral region 120. That is, the breakdown voltage of the device becomes the breakdown voltage of the active region 110. Thus, if the breakdown voltage of the device is determined by the active region 110, the clamping energy increases.

[0180] On the other hand, by increasing the doping concentration of the collector region 22, the breakdown voltage of the active region 110 is further increased compared to the breakdown voltage of the outer peripheral region 120. That is, the breakdown voltage of the device becomes the breakdown voltage of the outer peripheral region 120. Thus, if the breakdown voltage of the device is determined by the outer peripheral region 120, the clamping energy is reduced. Based on the above, in order to improve the clamping energy, the doping concentration of the collector region 22 can be 6 × 10⁻⁶. 17 ( / cm 3 Below that, it can also be 5×10 17 ( / cm 3 )the following.

[0181] Figure 4A An example of the current-voltage characteristics of the semiconductor device 100 of this embodiment is shown. The vertical axis represents the collector-emitter current Ice [A] and the collector-emitter voltage Vce [V], and the horizontal axis represents time [s]. Furthermore, in the cross-sectional view of the semiconductor device 100, regions with high electron current density are shown by dashed lines at time T1 and time T2, respectively. In this example, the doping concentration of the collector region 22 is set at... Figure 3B The range of clamping withstand voltage is determined by the active region 110.

[0182] Time T1 is the moment when the semiconductor device 100 is turned off and the collector-emitter voltage Vce rises. At time T1, the electron current is concentrated in the region shown by the dashed line in the active region 110. That is, a peak region of electron current density is formed in a part of the region shown by the dashed line in the active region 110.

[0183] Time T2 represents the moment when the collector-emitter voltage Vce rises and is clamped at around 800V. At time T2, the temperature at the avalanche breakdown site rises. Due to the temperature rise, lattice vibrations become more intense, and electrons are scattered. If current becomes difficult to flow due to electron scattering, the peak region of the electron current density sometimes shifts from the active region 110 toward the end of the outer peripheral region 120 of the well region 17.

[0184] Thus, when the breakdown voltage of the active region 110 is lower than that of the outer peripheral region 120, the peak region of the electron current density formed on the active region 110 side shifts towards the outer peripheral region 120 side. As a result, the temperature of the active region 110 temporarily decreases. Furthermore, when the peak region of the electron current density caused by avalanche breakdown shifts towards the outer peripheral region 120 side, the power (i.e., Ice × Vce) decreases. Therefore, the temperature rise of the semiconductor device 100 can be mitigated, preventing instantaneous damage.

[0185] Figure 4B An example of the current-voltage characteristics of the comparative semiconductor device 500 is shown. The vertical axis represents the collector-emitter current Ice [A] and the collector-emitter voltage Vce [V], and the horizontal axis represents time [s]. Furthermore, in this example, the peak regions of the electron current density are shown as dashed lines at times T3 and T4, respectively. The doping concentration of the collector region 22 in this example is set at... Figure 3B The pressure resistance range is determined by the outer peripheral region 120.

[0186] The semiconductor device 500 sets the integral concentration of the collector region 22 such that the breakdown voltage of the peripheral region 120 is lower than that of the active region 110. When turned off, avalanche breakdown occurs on the peripheral region 120 side of the well region 17, forming a peak region of electron current density at the location shown by the dashed line. Between times T3 and T4, under high power conditions, the peak region of electron current density remains at the position shown by the dashed line. Therefore, the temperature continues to rise due to current concentration. Thus, in the semiconductor device 500, the components are easily damaged, and the clamping tolerance cannot be improved.

[0187] In the outer peripheral region 120, in addition to the increase in avalanche breakdown corresponding to the hole injection efficiency of the collector region 22, carriers tend to concentrate at the contact hole end on the outer peripheral region 120 side, thus easily causing avalanche breakdown. The increase in hole concentration on the back side 23 increases avalanche breakdown during clamping.

[0188] In this example, the semiconductor device 100 reduces the hole injection efficiency of the collector region 22 by appropriately setting the doping concentration and the depth of the first peak P1, thereby making the clamping breakdown voltage of the active region 110 lower than that of the peripheral region 120. Consequently, after avalanche breakdown occurs in the active region 110, the avalanche breakdown propagates towards the peripheral region 120, thus suppressing transient damage. The doping concentration of the collector region 22 and the depth of the first peak P1 can be set to maximize the clamping energy. The appropriate range for the doping concentration of the collector region 22 and the depth of the first peak P1 will be described later.

[0189] It should be noted that if the device is designed to withstand a voltage higher than the intended surge voltage (the peak value of the collector-emitter voltage being greater than the supply voltage during turn-off) to prevent damage during current interruption, then the thickness of the semiconductor substrate 10 in the depth direction needs to be increased, or the area of ​​the outer peripheral region 120 needs to be increased. To reduce chip cost, the device's withstand voltage is sometimes designed to be below the surge voltage. In this example, the semiconductor device 100 reduces chip cost and prevents device damage by inducing avalanche breakdown in the active region 110 during turn-off.

[0190] In addition, to ensure that the withstand voltage of the active region 110 is lower than that of the peripheral region 120, the total dose of the field cutoff region 20 and the total dose of the collector region 22 can be determined. For example, the total dose of the field cutoff region 20 can be less than 10 times or less than 5 times the total dose of the collector region 22.

[0191] Figure 5A An example is shown illustrating the relationship between the integrated concentration of collector region 22 and the depth of the first peak P1. The vertical axis represents the depth y1 [μm] of the first peak P1, and the horizontal axis represents the integrated concentration x [cm] of collector region 22. -2 ].

[0192] Here, based on Figure 3A The shallowest acceleration energy and clamping energy of the proton obtained in the process become the two largest aspects of the data, and the following baseline L1 is calculated.

[0193] Baseline L1: y1 = (-6.0367E-01)ln(x) + (2.2590E+01)

[0194] That is, baseline L1 represents the relationship between the integral concentration of the collector region 22 where the clamping energy is the largest and the depth of the first peak P1 where the clamping energy is the largest.

[0195] Region R1 represents the area within ±15% of baseline L1. In this example, region R1 is the area between line A1 and line B1. Lines A1 and B1 in this example are represented by the following formula.

[0196] Line A1: y1=(-7.4699E-01)ln(x)+(2.7810E+01)

[0197] Line B1: y1=(-4.7772E-01)ln(x)+(1.7960E+01)

[0198] In this case, the depth of the first peak P1 and the integrated concentration of the collector region 22 belong to region R1. If it is region R1, the hole injection efficiency of the collector region 22 can be suppressed, making the clamping withstand voltage of the active region 110 lower than that of the peripheral region 120. The integrated concentration of the collector region 22 can be 1.00E16cm. -2 The following can also be 8.00E15cm -2 The depth of the first peak P1 can be greater than 0.5 μm and less than 7.2 μm.

[0199] In this example, the semiconductor device 100 sets the integrated concentration of the collector region 22 and the depth of the first peak P1 in region R1, thereby enabling avalanche breakdown during clamping to occur on the active region 110 side. As a result, the clamping withstand voltage is improved.

[0200] Figure 5B This example illustrates the relationship between the integrated concentration of collector region 22 and the depth of the first peak P1. In this example, region R1 represents the region that conforms to baseline L1 by ±10%.

[0201] Baseline L1 and Figure 5A The baseline L1 is the same. In this example, lines A1 and B1 are represented by the following formula.

[0202] Line A1: y1=(-6.9487E-01)ln(x)+(2.5930E+01)

[0203] Line B1: y1=(-5.2115E-01)ln(x)+(1.9540E+01)

[0204] Similarly, in this case, the depth of the first peak P1 and the integrated concentration of the collector region 22 can be set to belong to region R1.

[0205] Figure 5C This example illustrates the relationship between the integrated concentration of collector region 22 and the depth of the first peak P1. In this example, region R1 represents the region that conforms to baseline L1 by ±5%.

[0206] Baseline L1 and Figure 5A The baseline L1 is the same. In this example, lines A1 and B1 are represented by the following formula.

[0207] Line A1: y1=(-6.4710E-01)ln(x)+(2.4190E+01)

[0208] Line B1: y1=(-5.6458E-01)ln(x)+(2.1130E+01)

[0209] Similarly, in this case, the depth of the first peak P1 and the integral concentration of the collector region 22 can be set to the region R1 in this example.

[0210] Figure 6A This illustrates another example of the relationship between the integrated concentration in collector region 22 and the depth of the first peak P1. Reference line L1, line A, and line B are shown alongside... Figure 5A The lines are identical. That is, it represents the region that conforms to ±15% of the baseline L1. However, in this example, region R1 represents the integrated concentration of collector region 22 as 3.00E14cm. -2 The following region. The depth of the first peak P1 can be greater than 2.0 μm and less than 7.2 μm. The depth of the first peak P1 and the integrated concentration of the collector region 22 can be set to the region R1 in this example.

[0211] Figure 6B This illustrates another example of the relationship between the integrated concentration in collector region 22 and the depth of the first peak P1. Reference line L1, line A, and line B are shown alongside... Figure 5A The lines are identical. That is, it represents the region that conforms to ±15% of the baseline L1. However, in this example, region R1 represents the integrated concentration of collector region 22 as 2.00E14cm. -2 The following region. The depth of the first peak P1 can be above 2.2 μm and below 7.2 μm. The depth of the first peak P1 and the integrated concentration of the collector region 22 can be set to the region R1 in this example.

[0212] Figure 6C This illustrates another example of the relationship between the integrated concentration in collector region 22 and the depth of the first peak P1. Reference line L1, line A, and line B are shown alongside... Figure 5A The lines are identical. That is, it represents the region that conforms to ±15% of the baseline L1. However, in this example, region R1 represents the integrated concentration of collector region 22 as 1.00E14cm. -2 The following region. The depth of the first peak P1 can be greater than 2.5 μm and less than 7.2 μm. The depth of the first peak P1 and the integrated concentration of the collector region 22 can be set to the region R1 in this example.

[0213] Figure 6D This illustrates another example of the relationship between the integrated concentration in collector region 22 and the depth of the first peak P1. Reference line L1, line A, and line B are shown alongside... Figure 5AThe lines are identical. That is, it represents the region that conforms to ±15% of the baseline L1. However, in this example, region R1 represents the integrated concentration of collector region 22 as 5.00E13cm. -2 The following region. The depth of the first peak P1 can be greater than 3.0 μm and less than 7.2 μm. The depth of the first peak P1 and the integrated concentration of the collector region 22 can be set to region R1 in this example.

[0214] Figure 6E This illustrates another example of the relationship between the integrated concentration in collector region 22 and the depth of the first peak P1. Reference line L1, line A, and line B are shown alongside... Figure 5A The lines are identical. That is, it represents the region that conforms to ±15% of the baseline L1. However, in this example, region R1 represents the integrated concentration of collector region 22 as 3.00E13cm. -2 The following region. The depth of the first peak P1 can be above 3.2 μm and below 7.2 μm. The depth of the first peak P1 and the integrated concentration of the collector region 22 can be set to the region R1 in this example.

[0215] Figure 6F This illustrates another example of the relationship between the integrated concentration in collector region 22 and the depth of the first peak P1. Reference line L1, line A, and line B are shown alongside... Figure 5A The lines are identical. That is, it represents the region that conforms to ±15% of the baseline L1. However, in this example, region R1 represents the integrated concentration of collector region 22 as 1.00E13cm. -2 The following region. The depth of the first peak P1 can be greater than 3.6 μm and less than 7.2 μm. The depth of the first peak P1 and the integrated concentration of the collector region 22 can be set to the region R1 in this example.

[0216] It should be noted that, regarding Figure 5B and Figure 5C It can also be like Figures 6A to 6F That limits the range of the integrated concentration in the collector region 22. For example, in Figure 5B and Figure 5C In this context, region R1 can be the integral concentration of collector region 22 with a concentration of 1.00E14cm. -2 The following region can be the area where the integrated concentration of collector region 22 is 5.00E13cm. -2 The following region can also be the collector region 22 with an integrated concentration of 3.00E13cm. -2 The following region can also be the collector region 22 with an integrated concentration of 1.00E13cm. -2 The following areas.

[0217] Figure 7AThe relationship between the integrated concentration in collector region 22 and the depth of the second peak P2 is shown. The vertical axis represents the depth y2 [μm] of the second peak P2, and the horizontal axis represents the integrated concentration x [cm] of collector region 22. -2 ].

[0218] Here, based on Figure 3A The shallowest acceleration energy and clamping energy of the proton obtained in the process become the two largest aspects of the data, and the following baseline L2 is calculated.

[0219] Baseline L2: y2=(-2.4885E+00)ln(x)+(9.1580E+01)

[0220] That is, baseline L2 represents the relationship between the integral concentration of the collector region 22 where the clamping energy is the largest and the depth of the second peak P2 where the clamping energy is the largest.

[0221] Region R2 represents the area within ±15% of baseline L2. In this example, region R2 is the area between line A2 and line B2. Lines A2 and B2 in this example are represented by the following formula.

[0222] Line A2: y2=(-3.1095E+00)ln(x)+(1.1416E+02)

[0223] Line B2: y2=(-1.9239E+00)ln(x)+(7.1030E+01)

[0224] In this case, the depth of the second peak P2 and the integrated concentration of the collector region 22 belong to region R2. If it is region R2, the clamping energy becomes sufficiently high. The depth of the second peak P2 can be greater than 3.5 μm and less than 28 μm.

[0225] Figure 7B This example illustrates the relationship between the integrated concentration in collector region 22 and the depth of the second peak P2. In this example, region R2 represents the region that conforms to baseline L2 by ±10%.

[0226] Baseline L2 and Figure 7A The baseline L2 is the same. Lines A2 and B2 in this example are represented by the following formula.

[0227] Line A2: y2=(-2.8924E+00)ln(x)+(1.0629E+02)

[0228] Line B2: y2=(-2.1020E+00)ln(x)+(7.7530E+01)

[0229] Similarly, in this case, the depth of the second peak P2 and the integral concentration of the collector region 22 can be set to belong to region R2.

[0230] Figure 7C This illustrates the relationship between the integrated concentration in collector region 22 and the depth of the second peak P2. In this example, region R2 represents the region that conforms to baseline L2 by ±5%.

[0231] Baseline L2 and Figure 7A The baseline L2 is the same. Lines A2 and B2 in this example are represented by the following formula.

[0232] Line A2: y2=(-2.4885E+00)ln(x)+(9.1580E+01)

[0233] Line B2: y2=(-2.2931E+00)ln(x)+(8.4470E+01)

[0234] Similarly, in this case, the depth of the second peak P2 and the integral concentration of the collector region 22 can be set to belong to region R2.

[0235] It should be noted that, regarding Figures 7A to 7C It can also be like Figures 6A to 6F That limits the range of the integrated concentration in the collector region 22. For example, in Figures 7A to 7C In this context, region R2 can be the integral concentration of collector region 22 with a concentration of 1.00E14cm. -2 The following region can be the area where the integrated concentration of collector region 22 is 5.00E13cm. -2 The following region can also be the collector region 22 with an integrated concentration of 3.00E13cm. -2 The following region can also be the collector region 22 with an integrated concentration of 1.00E13cm. -2 The following areas.

[0236] Figure 8A This is a graph used to illustrate the relationship between stray inductance Ls and collector current reduction rate dIce / dt. Let the stray inductance Ls be Xc[nH], and the collector current reduction rate dIce / dt be Yc[A / μs]. Line C1 is represented by the following equation.

[0237] Line C1: Yc = 10000Xc -1

[0238] The stray inductance Ls and the collector current reduction rate dIce / dt are set to a range larger than line C1. This range, larger than line C1, refers to the area above line C1 in the graph representing the relationship between stray inductance Ls and collector current reduction rate dIce / dt. This range is the area filled in with a pattern.

[0239] The stray inductance Ls and the collector current reduction rate dIce / dt can be set in a range larger than line C2. Line C2 is expressed by the following formula.

[0240] Line C2: Yc = 20000Xc -1

[0241] The stray inductance Ls and the collector current reduction rate dIce / dt can be set in a range larger than line C3. Line C3 is expressed by the following formula.

[0242] Line C3: Yc = 50000Xc -1

[0243] Here, the larger the stray inductance Ls, the easier it is to maintain the current, and the larger the surge voltage becomes when the current is cut off. Furthermore, the larger the collector current reduction rate dIce / dt, the larger the surge voltage becomes when the current is cut off. Therefore, if the stray inductance Ls and the collector current reduction rate dIce / dt are set within a range larger than any of lines C1 to C3, the surge voltage is prone to sudden changes. The semiconductor device 100 in this example can prevent transient damage even when the stray inductance Ls and the collector current reduction rate dIce / dt are set within a range larger than any of lines C1 to C3.

[0244] Figure 8B This is a graph used to illustrate the relationship between the specific stray inductance Ls·A and the current density dJce / dt. Let the specific stray inductance Ls·A be Xd[nH cm]. 2 Let the current density dJce / dt be Yd[A / (cm)] 2 μs)).

[0245] The stray inductance Ls·A is the stray inductance Ls multiplied by the area A (cm²) of the active region 110. 2 The intrinsic value is obtained by dividing the collector current reduction rate dIce / dt by the area A (cm²) of the active region 110. 2 The value obtained is ).

[0246] The stray inductance Ls·A and the current density dJce / dt are set to be in a range larger than that of line D1. Line D1 is represented by the following formula.

[0247] Line D1: Yd = 10000Xd -1

[0248] The stray inductance Ls·A and the current density dJce / dt can be set in a range larger than line D2. Line D2 is expressed by the following formula.

[0249] Line D2: Yd = 20000Xd -1

[0250] The stray inductance Ls·A and the current density dJce / dt can be set in a range larger than line D3. Line D3 is expressed by the following formula.

[0251] Line D3: Yd = 50000Xd -1

[0252] Here, the larger the stray inductance Ls·A or the current density dJce / dt, the larger the surge voltage becomes when the current is cut off. Therefore, if the stray inductance Ls·A or the current density dJce / dt is set to a range larger than any of the lines D1 to D3, the surge voltage is prone to jump. The semiconductor device 100 in this example can prevent instantaneous damage even if the stray inductance Ls·A or the current density dJce / dt is set to a range larger than any of the lines D1 to D3.

[0253] Figure 9 This is a graph used to illustrate the relationship between specific stray inductance Ls·A and specific gate resistance Rg·A. Let the specific stray inductance Ls·A be Xe[nH cm]. 2 Let the gate resistance Rg·A be Ye[Ωcm] 2 The gate resistance Rg·A is the gate resistance Rg of the drive circuit of semiconductor device 100 multiplied by the area A (cm²) of the active region 110. 2 The inherent value obtained is ).

[0254] The collector current reduction rate dIce / dt varies not only with respect to the stray inductance Ls, but also with respect to the gate resistance Rg of the drive circuit of the semiconductor device 100. If the gate resistance Rg decreases, the collector current reduction rate dIce / dt tends to increase.

[0255] The stray inductance Ls·A and the gate resistance Rg·A can be set within a range below line E1. Line E1 is represented by the following formula.

[0256] Line E1: Ye=(4.000E-01)Xe

[0257] The stray inductance Ls·A and the gate resistance Rg·A can be set within a range below line E2. Line E2 is expressed by the following formula.

[0258] Line E2: Ye=(2.000E-01)Xe

[0259] The stray inductance Ls·A and the gate resistance Rg·A can be set within a range below line E3. Line E3 is represented by the following formula.

[0260] Line E3: Ye=(8.000E-02)Xe

[0261] Here, the smaller the gate resistance Rg·A, the larger the surge voltage becomes when the current is cut off. Therefore, when the stray inductance Ls·A and the gate resistance Rg·A are set below any one of lines E1 to E3, the surge voltage is prone to jump. The semiconductor device 100 in this example can prevent instantaneous damage even when the stray inductance Ls·A and the gate resistance Rg·A are set below any one of lines E1 to E3.

[0262] The present invention has been described above using embodiments, but the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications or improvements can be made to the above embodiments. As can be seen from the claims, such modifications or improvements can also be included within the technical scope of the present invention.

[0263] It should be noted that the execution order of actions, sequences, steps, and stages in the apparatus, systems, programs, and methods shown in the claims, description, and drawings can be implemented in any order, unless specifically stated as "before" or "before," and the output of a previous process is not used in a later process. Even if the flow of actions in the claims, description, and drawings is described using terms such as "firstly" or "next" for convenience, it does not mean that the actions must be performed in that order.

Claims

1. A semiconductor device, characterized in that, include: A drift region of the first conductivity type is disposed on a semiconductor substrate; The field cutoff region of the first conductivity type is located below the drift region and has one or more peaks; as well as The collector region of the second conductivity type is disposed below the field cutoff region. Let the integral concentration of the collector region be x [cm] -2 Let the depth of the shallowest first peak among the one or more peaks, measured from the back side of the semiconductor substrate, be y1 [μm], and set... Line A1: y1 = (-7.4699E-01)ln(x) + (2.7810E+01), Line B1: y1 = (-4.7772E-01)ln(x) + (1.7960E+01) In this case, the depth of the first peak and the integrated concentration are within the range between line A1 and line B1. Let the depth of the second shallowest peak, measured from the back side, among the one or more peaks be y2 [μm], and set... Line A2: y2 = (-3.1095E+00)ln(x) + (1.1416E+02), Line B2: y2 = (-1.9239E+00)ln(x) + (7.1030E+01) In this case, the depth of the second peak and the integral concentration are within the range between line A2 and line B2.

2. The semiconductor device according to claim 1, characterized in that, The integrated concentration in the collector region is 8.00E15cm. -2 the following.

3. The semiconductor device according to claim 1, characterized in that, The integrated concentration in the collector region is 3.00E14cm. -2 the following.

4. The semiconductor device according to claim 1, characterized in that, The integrated concentration in the collector region is 2.00E14cm. -2 the following.

5. The semiconductor device according to claim 1, characterized in that, The integrated concentration in the collector region is 1.00E14cm. -2 the following.

6. The semiconductor device according to claim 1, characterized in that, The integrated concentration in the collector region is 5.00E13cm. -2 the following.

7. The semiconductor device according to claim 1, characterized in that, The integrated concentration in the collector region is 3.00E13cm. -2 the following.

8. The semiconductor device according to claim 1, characterized in that, The integrated concentration in the collector region is 1.00E13cm. -2 the following.

9. The semiconductor device according to any one of claims 1 to 8, characterized in that, The depth of the first peak is greater than 0.5 μm and less than 7.2 μm.

10. The semiconductor device according to any one of claims 1 to 8, characterized in that, The depth of the first peak is greater than 2.0 μm and less than 7.2 μm.

11. The semiconductor device according to claim 1, characterized in that, The depth of the second peak is greater than 3.5 μm and less than 28 μm.

12. The semiconductor device according to any one of claims 1 to 8, characterized in that, Let the stray inductance Ls of the circuit connected to the semiconductor device be Xc[nH], the collector current reduction rate dIce / dt be Yc[A / μs], and let... Line C1: Yc = 10000Xc -1 In this case, the stray inductance Ls and the collector current reduction rate dIce / dt are in a range larger than that of line C1.

13. The semiconductor device according to any one of claims 1 to 8, characterized in that, The dopant for one or more peaks is hydrogen.

14. The semiconductor device according to any one of claims 1 to 8, characterized in that, The semiconductor device includes: An active region is disposed on the semiconductor substrate; and The peripheral region is located on the periphery of the active region when the semiconductor substrate is viewed from above.

15. The semiconductor device according to any one of claims 1 to 8, characterized in that, The semiconductor device includes: The base region of the second conductivity type is disposed above the drift region; The emitter region of the first conductivity type is disposed above the base region, and the doping concentration is higher than that of the drift region; The contact region of the second conductivity type is disposed above the base region, and the doping concentration is higher than that of the base region; as well as Multiple gate trenches are disposed on the semiconductor substrate.

16. The semiconductor device according to any one of claims 1 to 8, characterized in that, The doping concentration at the boundary between the field cutoff region and the collector region is 1E16cm. -3 the following.

17. The semiconductor device according to any one of claims 1 to 8, characterized in that, The doping concentration at the boundary between the field cutoff region and the collector region is 5E15cm. -3 the following.

18. The semiconductor device according to any one of claims 1 to 8, characterized in that, The doping concentration at the boundary between the field cutoff region and the collector region is 2E15cm. -3 the following.

19. The semiconductor device according to any one of claims 1 to 8, characterized in that, The hydrogen chemical concentration at the boundary between the field cutoff region and the collector region is 1E18 cm⁻¹. -3 the following.

20. The semiconductor device according to any one of claims 1 to 8, characterized in that, The hydrogen chemical concentration at the boundary between the field cutoff region and the collector region is 1E17 cm⁻¹. -3 the following.

21. The semiconductor device according to any one of claims 1 to 8, characterized in that, The hydrogen chemical concentration at the boundary between the field cutoff region and the collector region is 1E15cm⁻¹. -3 above.

22. The semiconductor device according to any one of claims 1 to 8, characterized in that, The hydrogen chemical concentration at the boundary between the field cutoff region and the collector region is 1E16 cm⁻¹. -3 above.

23. The semiconductor device according to any one of claims 1 to 8, characterized in that, The dopant in the first peak is phosphorus.

24. The semiconductor device according to any one of claims 1 to 8, characterized in that, The dopant of the one or more peaks other than the first peak is hydrogen.

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