Lithography pattern overlay correction method and system and method for generating a mask pattern

Abstract

A lithography pattern overlay correction method includes selecting step, overlay error obtaining step, calculating step, and correction step. A selected area with a plurality of line patterns formed in front and back layers is selected on a semiconductor substrate; two overlay errors are obtained, and a correction size value is calculated; and overlay correction is performed by removing or inserting a correction pattern from the line pattern. The present application uses an image file system to calculate a correction parameter from two overlay errors of a line pattern to perform overlay correction on the line pattern, without being limited by the alignment limit of the measurement compensation of the alignment machine, to improve the accuracy of the overlay correction. In addition, the present application also provides a mask pattern generation method for generating a mask using a line pattern after overlay correction, and a lithography pattern overlay correction system for the aforementioned lithography pattern overlay correction method and mask pattern generation method.

Description

Technical Field

[0001] This invention relates to a compensation and correction method, a photomask generation method, and a system, and particularly to a photomask pattern correction method and system, and a photomask pattern generation method, applicable to semiconductor lithography processes. Background Technology

[0002] The semiconductor industry is currently developing towards highly stacked structures, with increasingly complex and dense patterns on each layer. Therefore, when one layer experiences a positioning misalignment, it affects subsequent layers, causing electrical failures or short circuits between semiconductor device layers. In current lithography processes, overlap compensation is typically achieved by using an alignment measurement machine to measure and calculate the overlap error caused by positioning misalignment between the semiconductor device layers. Generally, an alignment symbol is first defined on the semiconductor device, and the overlap error value is obtained by measuring the alignment symbols of the preceding and following layers, which is then used for overlap compensation.

[0003] Because the constituent materials or pattern density of different layers of a semiconductor device are not entirely the same, different degrees of thermal expansion or contraction will occur between the front and rear layers during the manufacturing process, resulting in overlay errors. Although the differences in thermal expansion or contraction between layers may only be minute to the nanoscale, as the precision of semiconductor devices increases, these process-related differences begin to affect the alignment accuracy between the front and rear layers. However, most current alignment equipment cannot effectively compensate for the overlay errors caused by expansion or contraction between the layers of the semiconductor device within a measurable and compensable range using alignment parameters. Therefore, it is impossible to accurately measure and compensate for the overlay errors caused by expansion or contraction between the layers of the semiconductor device.

[0004] Therefore, the focus of this invention is to provide an alignment error compensation method that, in addition to considering alignment offset, also takes into account the subtle differences (i.e., stacking errors smaller than the micrometer scale) caused by non-lithography processes within a small spacing (e.g., hundreds of micrometers) between the front and back stacks of the semiconductor element during the manufacturing process, so as to further improve the accuracy of the semiconductor element stacking error compensation. Summary of the Invention

[0005] The purpose of this invention is to provide a method for lithography pattern overlay correction, which can be used for alignment correction in semiconductor manufacturing processes to improve the accuracy of overlay error compensation.

[0006] The lithography pattern overlay correction method of the present invention includes a selection step, an overlay error acquisition step, a calculation step, and a correction step.

[0007] In the selection step, at least one selected area is selected on a semiconductor substrate, the at least one selected area includes at least one circuit pattern unit, and the at least one circuit pattern unit has a plurality of first circuit patterns and a plurality of second circuit patterns respectively formed by patterning processes on a front layer and a rear layer.

[0008] In the overlay error acquisition step, overlay errors at two different positions of the first circuit patterns and the second circuit patterns are acquired.

[0009] In the calculation step, a correction dimension value is calculated through the overlay errors at the two different positions or a preset value.

[0010] In the correction step, at least one correction pattern having the same dimension as the correction dimension value is removed from or inserted into the at least one circuit pattern unit, so as to perform overlay correction on the at least one circuit pattern unit.

[0011] Preferably, in the lithography pattern overlay correction method of the present invention, the overlay errors at the two different positions in the overlay error acquisition step are respectively obtained from the overlay errors of the first circuit patterns and the second circuit patterns located at two ends of the at least one circuit pattern unit.

[0012] Preferably, in the lithography pattern overlay correction method of the present invention, each of the first circuit patterns and the second circuit patterns is spaced apart by a non-circuit section, and in the correction step, the at least one correction pattern is selectively removed from or inserted into one of the first circuit patterns and the second circuit patterns.

[0013] Preferably, in the lithography pattern overlay correction method of the present invention, the correction dimension value is obtained by dividing the difference between the overlay errors at the two different positions or the preset value by nP, where n is a positive integer, and P is a predetermined value of electron beam resolution or unit pixel size. The correction step further includes dividing the at least one circuit pattern unit into m equal correction zones along the extending direction of the at least one circuit pattern unit, where |(m×n×p)-E|<np, E is the difference between the overlay errors at the two different positions or the preset value, and the correction step is to remove or insert the at least one correction pattern in at least one correction zone.

[0014] Preferably, in the lithography pattern overlay correction method of the present invention, the at least one selected region has a plurality of line pattern units, and the correction step is to define a correction baseline extending along a second direction perpendicular to the extension direction of one of the line pattern units, the correction baseline passing through at least one of the line pattern units, and removing or inserting the correction pattern from at least one of the line pattern units through which the correction baseline passes.

[0015] Preferably, in the lithography pattern overlay correction method of the present invention, the first line pattern and the second line pattern in at least one of the line pattern units are each separated from each other by non-line areas. When the area through which the correction baseline passes is one of the line patterns or a non-line area between the line patterns, the correction pattern and the area through which the correction baseline passes have the same properties.

[0016] Preferably, in the lithography pattern overlay correction method of the present invention, when the area through which the correction baseline passes simultaneously includes any line pattern and a non-line area adjacent to the any line pattern, or when one side of the correction baseline is located at the boundary between the any line pattern and the adjacent non-line area, the correction pattern may be selected from one of the line pattern and the non-line area having the same properties.

[0017] Preferably, the lithography pattern overlay correction method of the present invention further includes a comparison step performed after the correction step, comparing the difference in overlay error of the first line pattern or the second line pattern after the removal or insertion of the at least one correction pattern.

[0018] Preferably, in the lithography pattern overlay correction method of the present invention, the correction step is to divide the at least one line pattern unit into m equal parts, where m ≥ 2, and the correction area is a correction area, or to insert at least two correction patterns.

[0019] Another object of the present invention is to provide a method for generating photomask patterns.

[0020] The photomask pattern generation method of the present invention includes: a selection step, a step of obtaining the superposition error, a calculation step, a correction step, and a photomask pattern generation step.

[0021] The selection step involves selecting at least one selected area on a semiconductor substrate. The at least one selected area includes at least one circuit pattern unit, which has multiple first circuit patterns and multiple second circuit patterns formed in the patterning processes of the front layer and the back layer, respectively.

[0022] The step of obtaining the overlap error obtains the overlap error at two different positions of the first circuit pattern and the second circuit pattern.

[0023] The calculation step obtains the correction dimension value by calculating the overlap error or preset value at the two different positions.

[0024] The correction step involves removing or inserting at least one correction pattern with the same size as the correction dimension value from the at least one line pattern unit to perform overlap correction on the at least one line pattern unit.

[0025] The photomask pattern generation step involves digitizing the at least one line pattern unit after overlay correction to generate a corrected line pattern.

[0026] Preferably, the photomask pattern generation method of the present invention further includes a photomask drawing step, wherein the photomask is drawn using an electron beam drawing system based on the correction circuit pattern.

[0027] Another object of the present invention is to provide a lithography pattern overlay correction system.

[0028] The present invention provides a lithography pattern overlay correction system, comprising: a data selection unit, a calculation unit, and a correction unit.

[0029] The data selection unit extracts at least one selected area from a semiconductor substrate. The at least one selected area includes at least one circuit pattern unit. The at least one circuit pattern unit has multiple first circuit patterns and multiple second circuit patterns formed by patterning processes in the front layer and the back layer, respectively.

[0030] The calculation unit is used to obtain the overlap error of two different positions of the first line pattern and the second line pattern in the at least one selected area, and to obtain the correction dimension value based on the overlap error of the two different positions or a preset value.

[0031] The correction unit removes or inserts at least one correction pattern having the same size as the correction size value from the at least one line pattern unit to perform overlap correction on the at least one line pattern unit.

[0032] Preferably, the lithography pattern overlay correction system of the present invention further includes an image data generation unit for generating a corrected circuit pattern from the at least one circuit pattern unit after overlay correction.

[0033] Preferably, the lithography pattern overlay correction system of the present invention further includes a photomask drawing unit, which can draw a photomask pattern according to the correction circuit pattern to generate a photomask.

[0034] Preferably, the lithography pattern overlay correction system of the present invention further includes a comparison unit for comparing the differences between the first circuit pattern or the second circuit pattern before and after overlay correction.

[0035] Another object of the present invention is to provide a method for correcting the overlay of photolithography patterns.

[0036] The present invention provides a method for correcting the overlay of lithography patterns, comprising: an overlay error acquisition step, a calculation step, and a correction step.

[0037] The step of obtaining the overlay error involves selecting at least one line pattern unit on a semiconductor device using the pattern design system to obtain the expected before and after process imaging, and performing process simulation using process parameters to obtain the error values ​​of the first line pattern or the second line pattern at two different positions before and after the process simulation. The line pattern unit includes multiple first line patterns and multiple second line patterns.

[0038] The calculation step obtains the corrected dimension value by calculating the error value or preset value at the two different positions.

[0039] The correction step involves removing or inserting at least one correction pattern with the same size as the correction dimension value from the at least one line pattern unit to perform overlap correction on the at least one line pattern unit.

[0040] Preferably, the lithography pattern overlay correction method of the present invention further includes a size adjustment step performed after the correction step to compensate the size of the at least one line pattern unit into which the correction pattern is inserted or removed.

[0041] The beneficial effects of the present invention are as follows: the first or second circuit pattern generated by the semiconductor pre-process and post-process are used to calculate the correction size value by using an image file system to obtain the overlap error or preset value of two different positions obtained from the first and second circuit patterns, so as to perform overlap correction on the circuit pattern, without being limited by the alignment limit of the measurement compensation of the alignment machine, thereby improving the accuracy of overlap correction. The photomask pattern can be drawn by the corrected circuit pattern after overlap correction, and a photomask with the corrected pattern can be generated. Therefore, when the photomask is used for subsequent lithography processes, the overlap error caused by the same process can be compensated. Attached Figure Description

[0042] Figure 1 This is a flowchart illustrating an embodiment of the lithography pattern overlay correction method of the present invention;

[0043] Figure 2 This is a schematic diagram illustrating the lithography pattern overlay correction system of the present invention;

[0044] Figure 3 This is a side sectional view, illustrating the cross-sectional view of the circuit pattern unit in the embodiment described above;

[0045] Figure 4 This is a top view diagram illustrating the correction baseline and non-line area within the selected area in the embodiment described.

[0046] Figure 5 This is a top view diagram to illustrate the size adjustment steps of the described embodiment;

[0047] Figure 6 This is a flowchart illustrating the steps of the photomask pattern generation method of the present invention;

[0048] Figure 7 This is a schematic diagram illustrating a photomask pattern generation system applicable to the photomask pattern generation method described above. Detailed Implementation

[0049] The present invention will now be described in detail with reference to the accompanying drawings and embodiments. It should be noted that the drawings are only for illustrating the structural and positional relationships between components and are not related to the actual dimensions of each component.

[0050] See Figure 1 , Figure 2 and Figure 3 An embodiment of the lithography pattern overlay correction method of the present invention is performed using a lithography pattern overlay correction system 200. The lithography pattern overlay correction system 200 is a Graphic Data System (GDS) or a Manufacturing Electron Beam Exposure System (MEBES), and includes a data selection unit 41, a calculation unit 42, a correction unit 43, and a comparison unit 44.

[0051] The data selection unit 41 extracts at least one selected region 30 from the pattern of the semiconductor substrate. The at least one selected region 30 includes at least one circuit pattern unit 31. The at least one circuit pattern unit 31 has a plurality of first circuit patterns 311 and a plurality of second circuit patterns 312 formed in the patterning processes of the front layer and the back layer, respectively, and superimposed on each other. The pattern of the semiconductor substrate can be an image pattern extracted from the semiconductor substrate by optical imaging equipment such as a stepper, scanner, diffractometer, electron microscope, or optical microscope. The data selection unit 41 is used to extract the at least one selected region 30 from the pattern obtained from the semiconductor substrate.

[0052] The calculation unit 42 is used to obtain two different positions of the first line pattern 311 and the second line pattern 312 of the at least one selected region 30. Figure 3The overlap error (represented by P1 and P2) can be used to obtain the overlap error offset value, and the correction dimension value can be calculated by the overlap error or preset value at the two different positions.

[0053] The correction unit 43 removes or inserts at least one correction pattern with the same size as the correction size value from one of the first line pattern 311 or the second line pattern 312 in the at least one line pattern unit 31 to perform overlap error correction on the first line pattern 311 or the second line pattern 312, and can be used to adjust the size of the first line pattern 311 or the second line pattern 312.

[0054] The comparison unit 44 is used to compare the overlap error difference of the first circuit pattern 311 or the second circuit pattern 312 before and after overlap correction. The comparison unit 44 can be independent or integrated into the calculation unit 42, and there is no special limitation.

[0055] The embodiment of the lithography pattern overlay correction method includes a selection step 21, an overlay error acquisition step 22, a calculation step 23, a correction step 24, a comparison step 25, and a size adjustment step 26.

[0056] The selection step 21 involves using the data selection unit 41 to select a selected region 30 within the pattern of the semiconductor substrate. The selected region 30 includes at least one circuit pattern unit 31. Specifically, assuming the selected region 30 includes a circuit pattern unit 31, the circuit pattern unit 31 has multiple first circuit patterns 311 and multiple second circuit patterns 312 formed in patterning processes on the front and back layers and stacked on top of each other. The patterning process can be a photolithography or etching process. The first circuit patterns 311 and the second circuit patterns 312 are each equally spaced along a first direction (e.g., the X direction) with non-circuit areas 32 as intervals. Furthermore, the first circuit patterns 311 and the second circuit patterns 312 can be located on the front and back layers of the semiconductor substrate, or on the same layer.

[0057] The step 22 for obtaining the overlap error involves using the calculation unit 42 to obtain the overlap error at two different positions of the first circuit pattern 311 and the second circuit pattern 312 of the circuit pattern unit 31. Since the overlap error between the first circuit pattern 311 and the second circuit pattern 312 may be below the micro / nano scale range, it is not easy to measure accurately. Furthermore, the overlap error of a typical circuit pattern accumulates from both ends, making the difference in overlap error most significant at the two ends of the circuit pattern unit 31. Therefore, in this embodiment, the overlap errors at the two different positions are respectively taken from positions located at the two ends of the circuit pattern unit 31 (e.g., ...). Figure 3 The overlay error (shown in P1 and P2) can not only easily obtain the change in overlay error, but also simultaneously represent the overall overlay error offset of the first circuit pattern 311 and the second circuit pattern 312.

[0058] It should be noted that the aforementioned overlap error at the two different positions can also be obtained without going through the selection step 21 and the overlap error acquisition step 22. Instead, it can be obtained by simulating process parameters using process compensation software (such as overlay compensation software) from the pattern design system to obtain the first circuit pattern 311 and the second circuit pattern 312 on the semiconductor substrate before and after the process. Alternatively, process and / or material parameters, such as film stress and thermal expansion coefficient, can be used to simulate the process and obtain the simulated overlap error values ​​of the first circuit pattern 311 and the second circuit pattern 312 at two different positions before and after the process simulation.

[0059] The calculation step 23 uses the calculation unit 42 to further calculate the simulation overlay error values ​​at the two different positions obtained in step 22 through the overlay error, so as to obtain a correction size value and an overlay error offset value.

[0060] The correction dimension value is obtained by dividing the difference in the overlay error at the two different positions, or the preset value, or the error values ​​at the two different positions of the first circuit pattern 311 and the second circuit pattern 312 before and after process simulation, by a multiple of P (n), where n is a positive integer, and P is a predetermined value for electron beam resolution or unit pixel size. The preset value can be a process tolerance value or a user-defined predetermined value. The overlay error offset value is taken from the average of the overlay errors at the two different positions, and therefore the overlay error offset value is equivalent to the offset of the overall overlay center position of the first circuit pattern 311 and the second circuit pattern 312.

[0061] The correction step 24 involves removing or inserting at least one correction pattern with the same size as the correction size value from the first line pattern 311 or the second line pattern 312 in the line pattern unit 31 by the correction unit 43, so as to perform superposition correction on the first line pattern 311 or the second line pattern 312 in the line pattern unit 31.

[0062] Specifically, the correction step 24 determines whether to remove or insert the at least one correction pattern based on the nature of the overlap error, namely the difference in the offset of the overlap center position. More specifically, since the overlap error of the circuit pattern unit 31 accumulates from one end of the circuit pattern unit 31 to the opposite end, the difference in the overlap errors at the opposite ends can show that the overlap error between the first circuit pattern 311 and the second circuit pattern 312 is due to overlap offset caused by shrinkage or expansion during the manufacturing process. The result of the difference in the overlap error can be used to determine whether to remove or insert the at least one correction pattern.

[0063] See also Figure 3 Taking the first circuit pattern 311 as the front-end circuit pattern and the second circuit pattern 312 as the back-end circuit pattern, and the correction step 24 as correcting the second circuit pattern 312 as an example: Each overlapping center point of the first circuit pattern 311 and the second circuit pattern 312 is 0. Expansion causing a rightward shift is +, and contraction causing a leftward shift is -. For example, when the circuit density on the left and right edges of the second circuit pattern 312 is uneven (e.g....) Figure 3 As shown, the line density from the two ends to the edge of the second line pattern 312 is different: the distance S1 between the left and the edge is larger, and the distance S2 between the right and the edge is smaller. Therefore, in the subsequent thin film deposition and heating process, the uneven material expansion of the non-line areas 32 on the left and right sides of the second line pattern 312 will cause the second line pattern 312 to shift to the right relative to the first line pattern 311 of the underlying layer. Figure 3 In the diagram, the second circuit pattern 312 after its position shift is represented by a dashed line. Due to the expansion error caused by the different circuit density, the rightward shift of the leftmost overlap error is the largest (the positive value is the largest). Therefore, the overlap error at the rightmost end minus the overlap error at the leftmost end is a negative value, indicating that the second circuit pattern 312 has expanded relative to the first circuit pattern 311, causing an error. At this time, the correction step 24 will remove at least one correction pattern from the second circuit pattern 312 to smooth out the overlap error caused by the process expansion of the second circuit pattern 312. Conversely, when shrinking, the second circuit pattern 312 will shift to the left relative to the first circuit pattern 311 at the bottom layer, and the leftward shift of the rightmost overlap error is the smallest (i.e. the negative value is the smallest). Therefore, the overlap error at the rightmost end minus the overlap error at the leftmost end is taken as a positive value, indicating that the overlap error of the circuit pattern is caused by shrinkage. At this time, the correction step 24 will decide to insert at least one correction pattern from the second circuit pattern 312 to make up for the overlap error of the second circuit pattern 312 caused by process shrinkage.

[0064] Preferably, the correction step 24 involves removing or inserting multiple correction patterns from different positions of the first line pattern 311 or the second line pattern 312 of the at least one line pattern unit 31, or removing or inserting multiple correction patterns from different positions of the first line pattern 311 and the second line pattern 312 respectively, so as to perform superposition correction on the first line pattern 311 and the second line pattern 312.

[0065] More specifically, taking the correction step 24, which involves selecting the second circuit pattern 312 for overlay error correction, as an example, the correction pattern is removed or inserted from the second circuit pattern 312 to cause the selected second circuit pattern 312 to have an offset correction amount relative to the first circuit pattern 311, and the offset correction amount is equivalent to the overlay error offset value. In this embodiment, the overlay error offset value is equivalent to the offset of the overall overlay center position of the first circuit pattern 311 and the second circuit pattern 312, and the offset correction amount is the sum of the dimensions of the number of inserted or removed correction patterns. Therefore, it is necessary to control the offset correction amount to be equivalent to the overlay error offset value to ensure the correction result.

[0066] Preferably, the correction step 24 involves selecting to remove or insert the at least one correction pattern into the second circuit pattern 312 formed in a subsequent process.

[0067] The comparison step 25 compares the difference in overlap error between the first circuit pattern 311 and the second circuit pattern 312 after removing or inserting the at least one correction pattern. By comparing the difference between the first circuit pattern 311 and the second circuit pattern 312 before and after correction, the correction result can be evaluated, and the detailed parameters of the correction step 24 can be further fine-tuned. Taking the aforementioned correction step 24 as an example of correcting the overlap error of the second circuit pattern 312, the comparison step 25 compares the difference in overlap error between the second circuit pattern 312 before and after removing or inserting the at least one correction pattern to evaluate the correction result.

[0068] It should be noted that the comparison step 25 may be omitted if necessary.

[0069] See also Figure 4, in some embodiments, the correcting step 24 may further divide the circuit pattern unit 31 along a first direction X (equivalent to the extending direction of the circuit pattern unit 31) into m equally divided correction regions 313, and in the correcting step 24, the at least one correction pattern is removed from or inserted into the at least one correction region 313, where |(m×n×p)-E|<np, m×n×p is the product of the three, E is the difference between the overlay errors at the two different positions or the preset value, that is: (m-1)×nP<E<(m+1)×nP, P is the electron beam resolution or the predetermined value of the unit pixel size, and nP is the product of the two. Preferably, in the correcting step 24, at least one correction pattern is removed from or inserted into each of the correction regions 313. Since the calculated correction dimension value is extremely small (approximately between 1 nm and 4 nm), by correcting the circuit pattern of each correction region 313 (in this embodiment, the correction of the second circuit pattern 312 is taken as an example for illustration), the second circuit pattern 312 can be gradually shifted, so as to obtain a better overlay error correction result.

[0070] In some embodiments, in the correcting step 24, the at least one circuit pattern unit 31 is divided into m equally divided correction regions, and m≧2, or at least two correction patterns are inserted.

[0071] With further reference to Figure 4 , in some embodiments, the selected region 30 has a plurality of circuit pattern units 31, and in the correcting step 24, a correction baseline 33 extending along a second direction Y perpendicular to the first direction X and passing through the circuit pattern unit 31 is defined, and from the region of the circuit pattern unit 31 through which the correction baseline 33 passes, the correction pattern is removed from or inserted into the first circuit pattern 311 or the second circuit pattern 312 to be corrected.

[0072] Specifically, taking the correction of the second circuit pattern 312 in each correction region 313 by using the correction baseline 33 as an example for illustration, when the passing region of the correction baseline 33 passing through each correction region 313 simultaneously includes any second circuit pattern 312 and the non-circuit region 32 adjacent to the second circuit pattern 312, the correction pattern to be inserted or removed has the same property as the second circuit pattern 312 (that is, the correction pattern is a circuit); when the regions through which the correction baseline 33 passes are respectively the second circuit pattern 312 or the non-circuit region 32 between two adjacent second circuit patterns 312, the correction pattern has the same property as the region through which the correction baseline 33 passes, for example: when the region through which the correction baseline 33 passes is the non-circuit region 32, the correction pattern to be inserted or removed is a non-circuit.

[0073] When one side of the correction baseline 33 is located at the boundary between the second circuit pattern 312 and the non-circuit area 32 adjacent to the second circuit pattern 312, a correction pattern with the same properties as either the second circuit pattern 312 or the non-circuit area 32 can be inserted or removed. However, correction patterns inserted or removed within the same correction area 313 will have the same properties. For example, such as Figure 4 As shown, the correction baseline 33 passes through three line pattern units 31 in the same correction area 313. In two of the line pattern units 31, one side of the correction baseline 33 is located at the boundary between its second line pattern 312 and the non-line area 32. At this time, a correction pattern with the same nature as the second line pattern 312 can be inserted or removed. However, the nature of the correction patterns inserted or removed in the two line pattern units 31 will be the same.

[0074] Preferably, when one side of the correction baseline 33 is located at the boundary between the second circuit pattern 312 and the non-circuit area 32 adjacent to the second circuit pattern 312, a correction pattern having the same nature as the second circuit pattern 312 is selected to be inserted or removed.

[0075] The size adjustment step 26 is performed after the correction step 24 to adjust the size of the corrected first circuit pattern 311 or the second circuit pattern 312.

[0076] Since the dimensions of the first circuit pattern 311 or the second circuit pattern 312 at the position where the correction pattern is inserted or removed will change after the correction step 24, and differ from the dimensions of other unadjusted first circuit patterns 311 or second circuit patterns 312, the size adjustment step 26 can be performed after the correction step 24 to compensate the dimensions of the first circuit pattern 311 or the second circuit pattern 312 where the correction pattern is inserted or removed, so that the dimensions of the first circuit pattern 311 or the second circuit pattern 312 before and after the correction step 24 can remain consistent.

[0077] Specifically, please refer to the following: Figure 5 The first line pattern 311 is the line located in the front layer. Figure 5 (represented by L), the second circuit pattern 312 is a perforation located in the current layer ( Figure 5 Taking V as an example, the correction step 24 involves reducing the width W of the perforation V (second circuit pattern 312) and the non-circuit area within the predetermined area 100 by the same size as the correction pattern 101. 101The position of the perforation V is shifted to correct the overlap between the line L (first line pattern 311) and the perforation V (second line pattern 312). Because after the pattern is shifted to correct the overlap, in addition to the second line pattern 312 being shifted, the predetermined area 100 originally containing the second line pattern 312 will also change size synchronously due to a reduction in size similar to that of the correction pattern 101. Figure 5 (represented by 100'), therefore, the size adjustment step 26 is to independently reduce the size of the perforation located within the predetermined area 100', corresponding to the width of the deleted correction pattern 101, which results in a reduction in size. Figure 5 The corresponding dimensional compensation and expansion (represented by V') is performed to compensate for the reduced width W by adjusting the perforation V' of the corrected width. 101 Restore the perforation V to its original width, and resize the predetermined area 100' that has dimensional errors due to the correction of the second line pattern 312 (2W). 101 Adjustments are made to ensure that the predetermined areas 100 and 100' containing the front and rear layer patterns are of the same size (e.g., ...). Figure 5 The reduced width (2W) is compensated for by taking the predetermined region 100' whose size has changed, without affecting the size and overlap of the predetermined region 100' and the perforation V located at the boundary of the predetermined region 100'. 101 (and restore to the original size), thus maintaining the dimensional consistency of the predetermined area 100 and the dimensional consistency of the perforation V inside and outside the predetermined area 100 without affecting the stacking position. Conversely, when the correction step 24 is to insert the correction pattern 101 from the second line pattern 312 in the predetermined area 100, the size adjustment step 26 is to reduce the size of the perforation V' that is increased due to the insertion of the correction pattern, and adjust the size of the predetermined area 100 and the predetermined area 100' to maintain the dimensional consistency of the predetermined area 100 and the dimensional consistency of the perforation V inside and outside the predetermined area 100.

[0078] In other words, the principle of the size adjustment step 26 is to keep the center of the pattern after the correction step 24 unchanged, and only adjust the size of the pattern that has changed in size during the correction process, so as to maintain the size consistency of all patterns before and after correction.

[0079] Preferably, the size adjustment step 26 is based on the principle of keeping the center of the pattern after the correction step 24 unchanged, and only performing left-right symmetrical size adjustment on the pattern whose size has changed during the correction process, so as to maintain the size consistency of all patterns before and after correction.

[0080] It is worth mentioning that after the overlapping error of the circuit pattern unit 31 is corrected using the aforementioned embodiment of the micro-lithography pattern overlay correction method, a corrected circuit pattern can be generated from the circuit pattern unit 31 after the overlapping error correction. Then, a photomask pattern can be drawn based on the corrected circuit pattern to complete the photomask fabrication with the corrected pattern.

[0081] See Figure 6 , 7 In detail, the photomask pattern generation method in this case is performed by a photomask pattern generation system 400, which is largely the same as the lithography pattern overlay correction system 200, except that the photomask pattern generation system 400 also includes an image data generation unit 45 and a photomask drawing unit 46.

[0082] The method for generating the photomask pattern first uses steps 21 to 24 of the aforementioned embodiment of the lithography pattern overlay correction method to correct the overlay error of the first line pattern 311 or the second line pattern 312. Then, the image data generation unit 45 performs a photomask pattern generation step 27 to digitize the at least one line pattern unit 31 after overlay correction, generating a GDS file suitable for the Graphic Data System (GDS) or a corrected line pattern suitable for the MEBES photomask pattern format. Next, the photomask drawing unit 46 performs a photomask drawing step 28 to draw the photomask pattern based on the corrected line pattern using the image data system or the MEBES, thereby generating a photomask with the corrected pattern, which can be used in subsequent lithography processes. When using the photomask with the corrected pattern in subsequent lithography processes, the overlay error caused by the same process can be compensated. The photomask drawing unit 46 is an electron beam writing system.

[0083] In summary, the present invention utilizes an image file system to calculate a correction dimension value between two overlap errors or preset values ​​between the first circuit pattern 311 or the second circuit pattern 312 generated in the semiconductor pre- and post-processing stages. This correction dimension value is then used to perform overlap correction on the first circuit pattern 311 or the second circuit pattern 312. Therefore, it is not limited by the alignment limits of the alignment machine's measurement compensation, thus improving the accuracy of the overlap correction. Furthermore, the correction circuit pattern after overlap correction can be used to draw a photomask pattern, thereby generating a photomask with the corrected pattern. Therefore, when the photomask is used for subsequent lithography processes, the overlap error caused by the same process can be compensated, thus achieving the objective of the present invention.

Claims

1. A method for correcting the overlay of lithography patterns, characterized in that: comprising: a selecting step: selecting at least one selected region on a semiconductor substrate, wherein the at least one selected region comprises at least one circuit pattern unit, and the at least one circuit pattern unit has a plurality of first circuit patterns and a plurality of second circuit patterns respectively formed by patterning processes on a front layer and a rear layer; an overlay error obtaining step: obtaining overlay errors at two different positions of the first circuit patterns and the second circuit patterns; a calculating step: calculating a corrected dimension value through the overlay errors at the two different positions or a preset value; and a correcting step: removing or inserting at least one correction pattern having the same dimension as the corrected dimension value from or into the at least one circuit pattern unit, so as to perform overlay correction on the at least one circuit pattern unit.

2. The method for correcting overlay of lithography patterns according to claim 1, characterized in that: The overlay errors at the two different positions in the overlay error obtaining step are respectively obtained from the overlay errors of the first circuit patterns and the second circuit patterns located at two ends of the at least one circuit pattern unit.

3. The method for correcting overlay of lithography patterns according to claim 1, characterized in that: The first circuit patterns and the second circuit patterns are each spaced apart by a non-circuit region, and the correcting step is to select one of the first circuit patterns and the second circuit patterns to remove or insert the at least one correction pattern.

4. The method for correcting overlay of lithography patterns according to claim 1, characterized in that: The corrected dimension value is obtained by dividing the difference between the overlay errors at the two different positions or the preset value by nP, where n is a positive integer, and P is a predetermined value of electron beam resolution or unit pixel size. The correcting step further comprises dividing the at least one circuit pattern unit into m equal correction regions along the extending direction of the at least one circuit pattern unit, where |(m×n×P)-E|<nP, E is the difference between the overlay errors at the two different positions or the preset value, and the correcting step is to remove or insert the at least one correction pattern from or into at least one of the correction regions.

5. The method for correcting overlay of lithography patterns according to claim 1, characterized in that: The at least one selected region has a plurality of circuit pattern units, and the correcting step is to define a correction baseline extending along a second direction perpendicular to the extending direction of one of the circuit pattern units, wherein the correction baseline passes through at least one of the circuit pattern units, and the correction pattern is removed from or inserted into at least one of the circuit pattern units through which the correction baseline passes.

6. The method for correcting overlay of lithography patterns according to claim 5, characterized in that: The first circuit patterns and the second circuit patterns in at least one of the circuit pattern units are spaced apart from each other by non-circuit regions, and when the region through which the correction baseline passes is one of the circuit patterns or a non-circuit region between the circuit patterns, the correction pattern has the same property as the region through which the correction baseline passes.

7. The method for correcting overlay of lithography patterns according to claim 5, characterized in that: When the region through which the correction baseline passes includes both any one of the circuit patterns and a non-circuit region adjacent to said any circuit pattern, or one side edge of the correction baseline is located at the junction between said any circuit pattern and the adjacent non-circuit region, the correction pattern may be selected to have the same property as one of said any circuit pattern and the non-circuit region.

8. The method for correcting overlay of lithography patterns according to claim 3, characterized in that: The lithographic pattern overlay correction method further comprises a comparing step performed after the correcting step, for comparing the difference in overlay error of the first circuit patterns or the second circuit patterns after the at least one correction pattern is removed or inserted.

9. The method for correcting overlay of lithography patterns according to claim 4, characterized in that: The correction step involves dividing the at least one line pattern unit into m equal parts, where m ≥ 2, and inserting at least two correction patterns into the at least one correction area.

10. A method for generating a photomask pattern, characterized in that: Include: The selection step involves selecting at least one selected area on a semiconductor substrate. The at least one selected area includes at least one circuit pattern unit, which has multiple first circuit patterns and multiple second circuit patterns formed in patterning processes of the front layer and the back layer, respectively. The step of obtaining the overlap error involves obtaining the overlap error at two different positions of the first circuit pattern and the second circuit pattern. The calculation step involves calculating the corrected dimension value using the overlap error or preset value at the two different positions. The correction step involves removing or inserting at least one correction pattern with the same size as the correction dimension value from or into the at least one circuit pattern unit to perform overlap correction on the at least one circuit pattern unit; and The photomask pattern generation step involves digitizing the at least one line pattern unit after overlay correction to generate a corrected line pattern.

11. The method for generating a photomask pattern according to claim 10, characterized in that: It also includes a photomask drawing step, in which the photomask is drawn using an electron beam drawing system based on the correction circuit pattern.

12. A lithography pattern overlay correction system, characterized in that: Include: The data selection unit extracts at least one selected area from a semiconductor substrate, the at least one selected area including at least one circuit pattern unit, the at least one circuit pattern unit having a plurality of first circuit patterns and a plurality of second circuit patterns formed in the patterning processes of the front layer and the back layer respectively. A calculation unit is configured to obtain the overlap error at two different positions of the first and second line patterns in the at least one selected area, and to obtain a correction dimension value based on the overlap error at the two different positions or a preset value; and The correction unit removes or inserts at least one correction pattern having the same size as the correction dimension value from the at least one line pattern unit to perform overlap correction on the at least one line pattern unit.

13. The lithography pattern overlay correction system according to claim 12, characterized in that: The lithography pattern overlay correction system also includes an image data generation unit for generating a corrected line pattern from the at least one line pattern unit after overlay correction.

14. The lithography pattern overlay correction system according to claim 13, characterized in that: The lithography pattern overlay correction system also includes a photomask drawing unit, which can draw a photomask pattern according to the correction circuit diagram to generate a photomask.

15. The lithography pattern overlay correction system according to claim 12, characterized in that: The lithography pattern overlay correction system also includes a comparison unit that compares the differences between the first line pattern or the second line pattern before and after overlay correction.

16. A method for correcting the overlay of lithography patterns, characterized in that: Include: The step of obtaining the superposition error involves obtaining at least one line pattern unit on the semiconductor device before and after the expected process imaging from the pattern design system, and performing process simulation using process parameters to obtain the error values ​​of two different positions of multiple first line patterns or multiple second line patterns before and after the process simulation. The line pattern unit includes the first line pattern and the second line pattern. The calculation step involves calculating the corrected dimension value using the error value or preset value at the two different positions. and The correction step involves removing or inserting at least one correction pattern with the same size as the correction dimension value from the at least one line pattern unit to perform overlap correction on the at least one line pattern unit.

17. The method for correcting overlay of lithography patterns according to any one of claims 1 or 16, characterized in that: The lithography pattern overlay correction method further includes a size adjustment step performed after the correction step to compensate the size of the at least one line pattern unit into which the correction pattern is inserted or removed.

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