Display device

Abstract

Disclosed are display devices. The display device includes a display panel, a drive controller, a gate driver, an emission driver, and a data driver. The display panel includes a pixel including a drive switching element and a light emitting element. The drive controller is configured to determine a drive frequency that is changed according to input image data or a drive mode. The gate driver is configured to output a gate signal and a bias control signal to the pixel. The emission driver is configured to output an emission signal to the pixel. The data driver is configured to output a data voltage to the pixel. The bias control signal to which a bias voltage is applied to the drive switching element has a first width in a write frame and a second width different from the first width in a hold frame.

Description

Technical Field

[0001] Embodiments of the present invention generally relate to display devices and methods for driving display devices. More specifically, embodiments of the present invention relate to a display device and a method for driving the display device that remove the difference between the brightness in a write frame and the brightness in a hold frame caused by the bias difference between the write frame and the hold frame in a variable frequency driving method. Background Technology

[0002] Typically, a display device includes a display panel and a display panel driver. The display panel includes multiple gate lines, multiple data lines, multiple emitter lines, and multiple pixels. The display panel driver includes a gate driver, a data driver, an emitter driver, and a drive controller. The gate driver outputs gate signals to the gate lines. The data driver outputs data voltages to the data lines. The emitter driver outputs emitter signals to the emitter lines. The drive controller controls the gate driver, data driver, and emitter driver.

[0003] To realistically represent game and movie images, high-resolution driving methods and high-frequency driving methods can be used. Furthermore, when supporting game and movie images, high-frequency driving methods and variable-frequency driving methods are used to reduce power consumption. In the variable-frequency driving method, the display panel can have a write frame when data voltage is written to a pixel, and a hold frame when maintaining the data voltage written to the pixel without writing the data voltage to the pixel.

[0004] In this paper, the offset of the write frame and the offset of the hold frame may differ from each other, so that the brightness of the image in the write frame and the brightness of the image in the hold frame may differ from each other. The display quality of the display panel may be degraded due to the difference in brightness.

[0005] The information disclosed in this background section is only for understanding the background of the concept of the present invention, and therefore may contain information that does not constitute prior art. Summary of the Invention

[0006] Embodiments of the present invention provide a display device that can remove the difference between the brightness in the written frame and the brightness in the held frame in a variable frequency driving method, thereby enhancing the display quality of the display panel.

[0007] Additional features of the inventive concept will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the inventive concept.

[0008] Embodiments of the present invention also provide a method for driving a display device.

[0009] In an embodiment of the display device according to the concept of the present invention, the display device includes a display panel, a drive controller, a gate driver, an emitter driver, and a data driver. The display panel includes pixels comprising drive switching elements (e.g., first pixel switching elements) and light-emitting elements. The drive controller is configured to determine a drive frequency that changes according to input image data or a drive mode. The gate driver is configured to output a gate signal and a bias control signal to the pixels. The emitter driver is configured to output an emitter signal to the pixels. The data driver is configured to output a data voltage to the pixels. The bias control signal for applying a bias voltage to the drive switching elements has a first width in a write frame and a second width different from the first width in a hold frame.

[0010] In an implementation, the second width may be greater than the first width.

[0011] In this implementation, when the driving frequency is at a normal frequency, the display panel may only have write frames. When the driving frequency is a low driving frequency, which is lower than the normal frequency, the display panel may have both write frames and hold frames.

[0012] In an implementation, a pixel may include a first pixel switching element, a second pixel switching element, a third pixel switching element, a fourth pixel switching element, a fifth pixel switching element, a sixth pixel switching element, a seventh pixel switching element, an eighth pixel switching element, a ninth pixel switching element, a light-emitting element, a first capacitor, and a second capacitor. The first pixel switching element includes a control electrode connected to a first node, an input electrode connected to a second node, and an output electrode connected to a third node. The second pixel switching element includes a control electrode, an input electrode configured to receive a data voltage, and an output electrode connected to a fourth node. The third pixel switching element includes a control electrode, an input electrode connected to the first node, and an output electrode connected to the third node. The fourth pixel switching element includes a control electrode, an input electrode configured to receive an initialization voltage, and an output electrode connected to the first node. The fifth pixel switching element includes a control electrode configured to receive a base voltage. The sixth pixel switching element includes a control electrode, an input electrode connected to the third node, and an output electrode connected to the anode of the light-emitting element. The seventh pixel switching element includes a control electrode, an input electrode configured to receive an initialization voltage, and an output electrode connected to the anode of the light-emitting element. The eighth pixel switching element includes a control electrode, an input electrode configured to receive a bias voltage, and an output electrode connected to the second node. The ninth pixel switching element includes a control electrode, an input electrode configured to receive a high power supply voltage, and an output electrode connected to the second node. The light-emitting element includes an anode connected to the output electrode of the seventh pixel switching element and a cathode configured to receive a low power supply voltage. The first capacitor includes a first electrode configured to receive a high power supply voltage and a second electrode connected to the fourth node. The second capacitor includes a first electrode connected to the fourth node and a second electrode connected to the first node.

[0013] In one implementation, a bias control signal may be applied to the control electrode of the eighth pixel switching element.

[0014] In this implementation, a bias control signal may be applied to the control electrode of the seventh pixel switching element.

[0015] In one implementation, the first gate signal may be applied to the control electrode of the second pixel switching element.

[0016] In one implementation, a second gate signal may be applied to the control electrode of the fourth pixel switching element. A third gate signal may be applied to the control electrodes of the third pixel switching element and the fifth pixel switching element.

[0017] In one implementation, a first transmission signal may be applied to the control electrode of the ninth pixel switching element. A second transmission signal may be applied to the control electrode of the sixth pixel switching element.

[0018] In an embodiment, the display device may further include a power supply voltage generator configured to generate a high power supply voltage, a low power supply voltage, an initialization voltage, a reference voltage, and a bias voltage, and to output the high power supply voltage, the low power supply voltage, the initialization voltage, the reference voltage, and the bias voltage to the pixels.

[0019] In this implementation, the bias voltage of the hold frame can be greater than the bias voltage of the write frame.

[0020] In an implementation, a pixel may include a first pixel switching element, a second pixel switching element, a third pixel switching element, a fourth pixel switching element, a fifth pixel switching element, a sixth pixel switching element, a seventh pixel switching element, an eighth pixel switching element, a light-emitting element, a first capacitor, and a second capacitor. The first pixel switching element includes a control electrode connected to a first node, an input electrode connected to a second node, and an output electrode connected to a third node. The second pixel switching element includes a control electrode, an input electrode configured to receive a data voltage, and an output electrode connected to a fourth node. The third pixel switching element includes a control electrode, an input electrode connected to the first node, and an output electrode connected to the third node. The fourth pixel switching element includes a control electrode, an input electrode configured to receive a reference voltage, and an output electrode connected to the fourth node. The fifth pixel switching element... The switching element includes a control electrode, an input electrode configured to receive a high power supply voltage, and an output electrode connected to the second node. The sixth pixel switching element includes a control electrode, an input electrode connected to the third node, and an output electrode connected to the anode of the light-emitting element. The seventh pixel switching element includes a control electrode, an input electrode configured to receive an initialization voltage, and an output electrode connected to the anode of the light-emitting element. The eighth pixel switching element includes a control electrode, an input electrode configured to receive a bias voltage, and an output electrode connected to the second node. The light-emitting element includes an anode connected to the output electrode of the seventh pixel switching element and a cathode configured to receive a low power supply voltage. The first capacitor includes a first electrode configured to receive a high power supply voltage and a second electrode connected to the first node. The second capacitor includes a first electrode connected to the third node and a second electrode connected to the fourth node.

[0021] In one implementation, a bias control signal may be applied to the control electrode of the eighth pixel switching element.

[0022] In one implementation, a first gate signal may be applied to the control electrode of a second pixel switching element. A second gate signal may be applied to the control electrode of a third pixel switching element.

[0023] In one implementation, the third gate signal may be applied to the control electrode of the fourth pixel switching element. The fourth gate signal may be applied to the control electrode of the seventh pixel switching element. The fourth gate signal may be the same as the third gate signal applied to the next horizontal line.

[0024] In an embodiment of the display device according to the concept of the present invention, the display device includes a display panel, a drive controller, a gate driver, an emitter driver, a data driver, and a power supply voltage generator. The display panel includes pixels comprising driving switching elements and light-emitting elements. The drive controller is configured to determine a drive frequency that changes according to input image data or a drive mode. The gate driver is configured to output a gate signal and a bias control signal to the pixels. The emitter driver is configured to output an emitter signal to the pixels. The data driver is configured to output a data voltage to the pixels. The power supply voltage generator is configured to generate a bias voltage. The bias voltage for writing frames is different from the bias voltage for holding frames.

[0025] In this implementation, when the driving frequency is at a normal frequency, the display panel may only have write frames. When the driving frequency is a low driving frequency, which is lower than the normal frequency, the display panel may have both write frames and hold frames.

[0026] In this implementation, the bias voltage for writing the frame may be less than the bias voltage for holding the frame.

[0027] In one implementation, the width of the bias control signal in the written frame for applying a bias voltage to the driving switching element can be equal to the width of the bias control signal in the holding frame.

[0028] In an embodiment of the method for driving a display device according to the concept of the present invention, the method includes determining a driving frequency that varies according to input image data or a driving mode, outputting a gate signal and a bias control signal to a pixel including a driving switching element and a light-emitting element, outputting an emission signal to the pixel, and outputting a data voltage to the pixel. The bias control signal for applying a bias voltage to the driving switching element has a first width in a write frame and a second width different from the first width in a hold frame.

[0029] According to the display device and the method of driving the display device, the width of the bias control signal of the write frame and the width of the bias control signal of the hold frame can be set differently in the variable frequency driving method, or the bias voltage of the write frame and the bias voltage of the hold frame can be set differently in the variable frequency driving method, so that the difference between the bias degree of the write frame and the bias degree of the hold frame can be removed in the variable frequency driving method.

[0030] Therefore, the difference between the brightness in the written frame and the brightness in the held frame can be removed in the variable frequency driving method, thereby enhancing the display quality of the display panel.

[0031] Furthermore, a variable frequency driving method is operable within a range that does not cause degradation of display quality, thereby reducing the power consumption of the display device.

[0032] It should be understood that both the foregoing general description and the following detailed description are exemplary and explanatory, and are intended to provide further explanation of the claimed invention. Attached Figure Description

[0033] The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the invention and, together with the description, serve to explain the concepts of the invention.

[0034] Figure 1 A block diagram illustrating a display device according to an embodiment of the concept of the present invention;

[0035] Figure 2 To show Figure 1 The circuit diagram of the pixels of the display panel;

[0036] Figure 3 To show the application to Figure 2 Timing diagram of the input signals of pixels and the signals of nodes;

[0037] Figure 4 To show Figure 2 The circuit diagram of the operation of the pixel during the first duration;

[0038] Figure 5 To show Figure 2 The circuit diagram of the operation of the pixel during the second duration;

[0039] Figure 6 To show Figure 2 Circuit diagram of the operation of the pixels in the third and fifth durations;

[0040] Figure 7 To show Figure 2 Circuit diagram of the operation of the pixels in the fourth and sixth durations;

[0041] Figure 8 To show Figure 2 The circuit diagram of the operation of the pixel during the seventh duration;

[0042] Figure 9 To show Figure 2 The circuit diagram of the operation of the pixel during the eighth duration;

[0043] Figure 10 To show Figure 2 The circuit diagram of the operation of the pixel during the ninth duration;

[0044] Figure 11 To illustrate the application of in the write frame Figure 2 Timing diagram of the input signal of the pixel;

[0045] Figure 12 To illustrate the application of in the holding frame Figure 2 Timing diagram of the input signal of the pixel;

[0046] Figure 13 To show Figure 1 Timing diagram of the operations of the display device in the write frame and hold frame;

[0047] Figure 14 A timing diagram illustrating the operation of a display device according to an embodiment of the concept of the present invention in a write frame and a hold frame;

[0048] Figure 15 A timing diagram illustrating the operation of a display device according to an embodiment of the concept of the present invention in a write frame and a hold frame;

[0049] Figure 16 A circuit diagram illustrating the pixels of a display panel of a display device according to an embodiment of the concept of the present invention;

[0050] Figure 17 To show the application to Figure 16 Timing diagram of the input signals of pixels and the signals of nodes;

[0051] Figure 18 To illustrate the application of in the write frame Figure 16 The timing diagram of the input signal of the pixel; and

[0052] Figure 19 To illustrate the application of in the holding frame Figure 16 The timing diagram of the input signal of the pixel. Detailed Implementation

[0053] In the following description, numerous specific details are set forth for purposes of explanation to provide a thorough understanding of various exemplary embodiments or implementations of the invention. As used herein, “implementation” and “method” are interchangeable terms and are non-limiting examples of devices or methods employing one or more of the inventive concepts disclosed herein. However, it will be apparent that various exemplary embodiments may be practiced without these specific details or in one or more equivalent arrangements. In other instances, well-known structures and devices are shown in block diagram form to avoid unnecessarily obscuring the various exemplary embodiments. Furthermore, the various exemplary embodiments may be different, but not necessarily exclusive. For example, the specific shapes, configurations, and characteristics of exemplary embodiments may be used or implemented in another exemplary embodiment without departing from the inventive concept.

[0054] Unless otherwise stated, the exemplary embodiments shown should be understood as exemplary features providing details of variations in some ways in which the inventive concept can be implemented in practice. Therefore, unless otherwise stated, features, components, modules, layers, films, panels, areas and / or aspects of various embodiments (hereinafter individually or collectively referred to as “elements”) may be combined, separated, interchanged and / or rearranged in other ways without departing from the inventive concept.

[0055] Crosshairs and / or shading are typically provided in the accompanying drawings to clarify the boundaries between adjacent elements. Thus, unless otherwise stated, the presence or absence of crosshairs or shading does not convey or indicate any preference or requirement for particular materials, material properties, dimensions, proportions, commonalities between illustrated elements, and / or any other characteristics, properties, performance, etc., of the elements. Additionally, in the drawings, the size and relative size of elements may be exaggerated for clarity and / or descriptive purposes. When exemplary embodiments can be implemented in different ways, the specific process sequence may be performed differently than the sequence described. For example, two consecutively described processes may be performed substantially simultaneously or in the reverse order of their description. Furthermore, similar reference numerals denote similar elements.

[0056] When an element (such as a layer) is referred to as being “on,” “connected to,” or “attached to” another element or layer, the element (such as a layer) may be directly on, directly connected to, or directly attached to the other element or layer, or an intermediary element or layer may be present. However, when an element or layer is referred to as being “directly” on, directly connected to, or directly attached to another element or layer, an intermediary element or layer is not present. Therefore, the term “connected” can refer to a physical, electrical, and / or fluid connection, with or without an intermediary element. Furthermore, the D1-axis, D2-axis, and D3-axis are not limited to the three axes of a Cartesian coordinate system (such as the x-axis, y-axis, and z-axis) and can be interpreted in a broader sense. For example, the D1-axis, D2-axis, and D3-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0057] Although the terms “first,” “second,” etc., may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Therefore, without departing from the teachings of this disclosure, the first element discussed below can be referred to as the second element.

[0058] Spatial relative terms such as “beneath,” “below,” “under,” “lower,” “above,” “upper,” “over,” “higher,” and “side” (e.g., as in “sidewall”) may be used herein for descriptive purposes and, therefore, to describe the relationship between one element and another as shown in the accompanying drawings. In addition to the orientations depicted in the figures, spatial relative terms are also intended to cover different orientations of the device in use, operation, and / or manufacture. For example, if the device in the figures is flipped, an element described as “below” or “under” other elements or features will subsequently be oriented “above” other elements or features. Thus, the exemplary term “below” can cover both above and below orientations. Furthermore, the device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and thereby the spatial relative descriptive terms used herein are interpreted accordingly.

[0059] The technical terms used herein are for the purpose of describing particular embodiments and are not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” as used herein are intended to include the plural forms as well. Furthermore, when the terms “comprises,” “comprising,” “includes,” and / or “including” are used in this specification, they indicate the presence of stated features, integers, steps, operations, elements, components, and / or clusters thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or clusters thereof. It should also be noted that, as used herein, the terms “substantially,” “about,” and other similar terms are used as approximations rather than terms of degree, and are thus utilized to account for inherent biases in measurements, calculations, and / or provided values ​​that would be recognized by those skilled in the art.

[0060] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Unless expressly defined herein, terms, such as those defined in common dictionaries, shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art and shall not be interpreted in an idealized or overly formal sense.

[0061] Figure 1 A block diagram illustrating a display device according to an embodiment of the concept of the present invention.

[0062] Reference Figure 1 The display device includes a display panel 100 and a display panel driver. The display panel driver includes a drive controller 200, a gate driver 300, a gamma reference voltage generator 400, a data driver 500, and a transmit driver 600. The display panel driver may also include a power supply voltage generator 700.

[0063] The display panel 100 has a display area displaying an image and a peripheral area adjacent to the display area.

[0064] The display panel 100 includes multiple gate lines GWL, GIL, and GCL, multiple bias lines EBL, multiple data lines DL, multiple emitter lines EL1 and EL2, and multiple pixels electrically connected to the gate lines GWL, GIL, and GCL, the bias lines EBL, the data lines DL, and the emitter lines EL1 and EL2. The gate lines GWL, GIL, and GCL and the bias line EBL extend in a first direction D1, the data lines DL extend in a second direction D2 intersecting the first direction D1, and the emitter lines EL1 and EL2 extend in the first direction D1.

[0065] The drive controller 200 receives input image data IMG and input control signals CONT from an external device. For example, the input image data IMG may include red image data, green image data, and blue image data. The input image data IMG may also include white image data. The input image data IMG may also include magenta image data, cyan image data, and yellow image data. The input control signal CONT may include a master clock signal and a data enable signal. The input control signal CONT may also include a vertical synchronization signal and a horizontal synchronization signal.

[0066] The drive controller 200 generates a first control signal CONT1, a second control signal CONT2, a third control signal CONT3, a fourth control signal CONT4, and a data signal DATA based on the input image data IMG and the input control signal CONT.

[0067] The drive controller 200 generates a first control signal CONT1 for controlling the operation of the gate driver 300 based on the input control signal CONT, and outputs the first control signal CONT1 to the gate driver 300. The first control signal CONT1 may include a vertical start signal and a gate clock signal.

[0068] The drive controller 200 generates a second control signal CONT2 based on the input control signal CONT for controlling the operation of the data driver 500, and outputs the second control signal CONT2 to the data driver 500. The second control signal CONT2 may include a horizontal start signal and a load signal.

[0069] The drive controller 200 generates a data signal DATA based on the input image data IMG. The drive controller 200 outputs the data signal DATA to the data driver 500.

[0070] The drive controller 200 generates a third control signal CONT3 based on the input control signal CONT for controlling the operation of the gamma reference voltage generator 400, and outputs the third control signal CONT3 to the gamma reference voltage generator 400.

[0071] The drive controller 200 generates a fourth control signal CONT4 for controlling the operation of the transmitter driver 600 based on the input control signal CONT, and outputs the fourth control signal CONT4 to the transmitter driver 600.

[0072] In this embodiment, the drive controller 200 can determine the drive frequency that changes based on the input image data IMG or the drive mode. For example, when the input image data IMG represents a static image, the drive frequency can be relatively low. For example, when the drive mode is a game mode, the drive controller 200 can determine the drive frequency of the input image data IMG to be variable.

[0073] For example, when the driving frequency is at the normal frequency, the display panel 100 may have write frames. For example, the normal frequency may be substantially the same as the input frequency of the input image data IMG.

[0074] For example, when the driving frequency is a low driving frequency, which is less than the normal frequency, the display panel 100 may have a write frame and a hold frame. In the write frame, data voltage can be written to the pixels of the display panel 100. In the hold frame, data voltage may not be written to the pixels of the display panel 100, but the data voltage written to the pixels can be maintained.

[0075] The gate driver 300 generates gate signals for driving gate lines GWL, GIL, and GCL in response to a first control signal CONT1 received from the drive controller 200. The gate driver 300 can output the gate signals to the gate lines GWL, GIL, and GCL. For example, the gate driver 300 can be mounted on the peripheral area of ​​the display panel 100. Alternatively, the gate driver 300 can be integrated into the peripheral area of ​​the display panel 100.

[0076] In this embodiment, the gate driver 300 generates a bias signal to drive the bias line EBL in response to a first control signal CONT1 received from the drive controller 200. The gate driver 300 can output the bias signal to the bias line EBL.

[0077] The gamma reference voltage generator 400 generates a gamma reference voltage VGREF in response to a third control signal CONT3 received from the drive controller 200. The gamma reference voltage generator 400 provides the gamma reference voltage VGREF to the data driver 500. The gamma reference voltage VGREF has a value corresponding to the level of the data signal DATA.

[0078] In one implementation, the gamma reference voltage generator 400 may be located in the drive controller 200 or the data driver 500.

[0079] The data driver 500 receives a second control signal CONT2 and a data signal DATA from the drive controller 200, and receives a gamma reference voltage VGREF from the gamma reference voltage generator 400. The data driver 500 uses the gamma reference voltage VGREF to convert the data signal DATA into a data voltage of analog type. The data driver 500 outputs the data voltage to the data line DL.

[0080] The transmitter driver 600 generates a transmit signal to drive the transmit lines EL1 and EL2 in response to a fourth control signal CONT4 received from the drive controller 200. The transmitter driver 600 can output the transmit signal to the transmit lines EL1 and EL2.

[0081] The power supply voltage generator 700 generates a high power supply voltage ELVDD, a low power supply voltage ELVSS, an initialization voltage VINT, a reference voltage VREF, and a bias voltage VBIAS. The power supply voltage generator 700 outputs the high power supply voltage ELVDD, the low power supply voltage ELVSS, the initialization voltage VINT, the reference voltage VREF, and the bias voltage VBIAS to the pixels of the display panel 100.

[0082] Figure 2 To show Figure 1 Circuit diagram of a display panel with 100 pixels. Figure 3 To show the application to Figure 2 Timing diagram of the input signals of pixels and node signals.

[0083] Reference Figures 1 to 3 The display panel 100 includes multiple pixels. Each pixel includes a driving switching element T1 and a light-emitting element EE.

[0084] A pixel may include a first pixel switching element (which may be referred to as a driving switching element) T1, a second pixel switching element T2, a third pixel switching element T3, a fourth pixel switching element T4, a fifth pixel switching element T5, a sixth pixel switching element T6, a seventh pixel switching element T7, an eighth pixel switching element T8, a ninth pixel switching element T9, a light-emitting element EE, a first capacitor CST, and a second capacitor CPR. The first pixel switching element T1 includes a control electrode connected to a first node G, an input electrode connected to a second node S, and an output electrode connected to a third node D. The second pixel switching element T2 includes a control electrode, an input electrode receiving a data voltage VDATA, and an output electrode connected to a fourth node A. The third pixel switching element T3 includes a control electrode, an input electrode connected to the first node G, and an output electrode connected to the third node D. The fourth pixel switching element T4 includes a control electrode, an input electrode receiving an initialization voltage VINT, and an output electrode connected to the first node G. The fifth pixel switching element T5 includes a control electrode... The sixth pixel switching element T6 includes an input electrode receiving a reference voltage VREF and an output electrode connected to the fourth node A. The sixth pixel switching element T6 includes a control electrode, an input electrode connected to the third node D, and an output electrode connected to the anode of the light-emitting element EE. The seventh pixel switching element T7 includes a control electrode, an input electrode receiving an initialization voltage VINT, and an output electrode connected to the anode of the light-emitting element EE. The eighth pixel switching element T8 includes a control electrode, an input electrode receiving a bias voltage VBIAS, and an output electrode connected to the second node S. The ninth pixel switching element T9 includes a control electrode, an input electrode receiving a high power supply voltage ELVDD, and an output electrode connected to the second node S. The light-emitting element EE includes an anode connected to the output electrode of the seventh pixel switching element T7 and a cathode receiving a low power supply voltage ELVSS. The first capacitor CST includes a first electrode receiving a high power supply voltage ELVDD and a second electrode connected to the fourth node A. The second capacitor CPR includes a first electrode connected to the fourth node A and a second electrode connected to the first node G.

[0085] The first gate signal GW can be applied to the control electrode of the second pixel switching element T2. The third gate signal GC can be applied to the control electrode of the third pixel switching element T3. The second gate signal GI can be applied to the control electrode of the fourth pixel switching element T4. The third gate signal GC can be applied to the control electrode of the fifth pixel switching element T5. The second transmit signal EM2 can be applied to the control electrode of the sixth pixel switching element T6. The bias control signal EB can be applied to the control electrode of the seventh pixel switching element T7. The bias control signal EB can be applied to the control electrode of the eighth pixel switching element T8. The first transmit signal EM1 can be applied to the control electrode of the ninth pixel switching element T9.

[0086] For example, the first pixel switching element T1 to the ninth pixel switching element T9 can be a P-type thin-film transistor. The control electrode of the first pixel switching element T1 to the ninth pixel switching element T9 can be a gate electrode. The input electrode of the first pixel switching element T1 to the ninth pixel switching element T9 can be a source electrode. The output electrode of the first pixel switching element T1 to the ninth pixel switching element T9 can be a drain electrode.

[0087] like Figure 3 As shown, during the first duration DR1, the third duration DR3, and the fifth duration DR5, the first transmit signal EM1 may be low, the second transmit signal EM2 may be high, the second gate signal GI may be low, the third gate signal GC may be high, the first gate signal GW may be high, and the bias control signal EB may be high. Furthermore, during the first duration DR1, the third duration DR3, and the fifth duration DR5, the signal T1 GATE at the gate electrode of the first pixel switching element T1 may be low.

[0088] In this article, a low level means an active level, and a high level means an inactive level.

[0089] During the second duration DR2, the fourth duration DR4, and the sixth duration DR6, the first transmit signal EM1 may be low, the second transmit signal EM2 may be high, the second gate signal GI may be high, the third gate signal GC may be low, the first gate signal GW may be high, and the bias control signal EB may be high. Furthermore, during the second duration DR2, the fourth duration DR4, and the sixth duration DR6, the signal T1 GATE at the gate electrode of the first pixel switching element T1 may be high.

[0090] During the seventh duration DR7, the first transmit signal EM1 may be high, the second transmit signal EM2 may be high, the second gate signal GI may be high, the third gate signal GC may be high, the first gate signal GW may be low, and the bias control signal EB may be high. Additionally, during the seventh duration DR7, the signal T1 GATE at the gate electrode of the first pixel switching element T1 may be high.

[0091] During the eighth duration DR8, the first transmit signal EM1 may be high, the second transmit signal EM2 may be high, the second gate signal GI may be high, the third gate signal GC may be high, the first gate signal GW may be high, and the bias control signal EB may be low. Furthermore, during the eighth duration DR8, the signal T1 GATE at the gate electrode of the first pixel switching element T1 may be high.

[0092] During the ninth duration DR9, the first transmit signal EM1 may be low, the second transmit signal EM2 may be low, the second gate signal GI may be high, the third gate signal GC may be high, the first gate signal GW may be high, and the bias control signal EB may be high. Additionally, during the ninth duration DR9, the signal T1 GATE at the gate electrode of the first pixel switching element T1 may be high.

[0093] Figure 4 To show Figure 2 The circuit diagram shows the operation of the pixel during the first duration DR1. Figure 5 To show Figure 2 The circuit diagram shows the operation of the pixel during the second duration DR2. Figure 6 To show Figure 2 Circuit diagram of the operation of pixels in the third duration DR3 and the fifth duration DR5. Figure 7 To show Figure 2 Circuit diagram of the operation of pixels in the fourth duration DR4 and the sixth duration DR6. Figure 8 To show Figure 2 The circuit diagram of the operation of the pixel in the seventh duration DR7. Figure 9 To show Figure 2 The circuit diagram of the operation of the pixel in the eighth duration DR8. Figure 10 To show Figure 2 The circuit diagram of the operation of the pixel in the ninth duration DR9.

[0094] like Figure 4 As shown, during the first duration DR1, the fourth pixel switch element T4 and the ninth pixel switch element T9 are turned on. During the first duration DR1, the fourth node A is in the state where the previous data voltage was written. During the first duration DR1, the initialization voltage VINT is applied to the first node G through the fourth pixel switch element T4. During the first duration DR1, the high supply voltage ELVDD is applied to the second node S through the ninth pixel switch element T9. The initialization voltage VINT is applied to the first node G during the first duration DR1, so that the first duration DR1 can be referred to as the first initialization operation.

[0095] like Figure 5As shown, during the second duration DR2, the third pixel switching element T3, the fifth pixel switching element T5, and the ninth pixel switching element T9 are turned on. During the second duration DR2, the reference voltage VREF is applied to the fourth node A through the fifth pixel switching element T5. Therefore, the voltage at the fourth node A can be changed from the previous data voltage to the reference voltage VREF. During the second duration DR2, ELVDD-Vth is applied to the first node G through the path formed by the ninth pixel switching element T9, the first pixel switching element T1, and the third pixel switching element T3. In this paper, Vth is the threshold voltage of the first pixel switching element T1. During the second duration DR2, the high supply voltage ELVDD is applied to the second node S through the ninth pixel switching element T9. ELVDD-Vth is applied to the first node G during the second duration DR2, so that the second duration DR2 can be referred to as a first threshold compensation operation. However, in this operation, the voltage change at the fourth node A can affect the compensation of the threshold voltage Vth of the first node G, so that the second duration DR2 can also be referred to as an incomplete threshold compensation operation.

[0096] like Figure 6 As shown, during the third duration DR3 and the fifth duration DR5, the fourth pixel switching element T4 and the ninth pixel switching element T9 are turned on. During the third duration DR3 and the fifth duration DR5, the fourth node A is in a state where the reference voltage VREF has been written. During the third duration DR3 and the fifth duration DR5, the initialization voltage VINT is applied to the first node G through the fourth pixel switching element T4. During the third duration DR3 and the fifth duration DR5, the high supply voltage ELVDD is applied to the second node S through the ninth pixel switching element T9. The initialization voltage VINT is applied to the first node G during the third duration DR3 and the fifth duration DR5, so that the third duration DR3 and the fifth duration DR5 can be referred to as the second initialization operation and the third initialization operation, respectively.

[0097] like Figure 7As shown, during the fourth duration DR4 and the sixth duration DR6, the third pixel switching element T3, the fifth pixel switching element T5, and the ninth pixel switching element T9 are turned on. During the fourth duration DR4 and the sixth duration DR6, the reference voltage VREF is applied to the fourth node A through the fifth pixel switching element T5. During the fourth duration DR4 and the sixth duration DR6, ELVDD-Vth is applied to the first node G through the path formed by the ninth pixel switching element T9, the first pixel switching element T1, and the third pixel switching element T3. Here, Vth is the threshold voltage of the first pixel switching element T1. During the fourth duration DR4 and the sixth duration DR6, the high supply voltage ELVDD is applied to the second node S through the ninth pixel switching element T9. ELVDD-Vth is applied to the first node G during the fourth duration DR4 and the sixth duration DR6, such that the fourth duration DR4 and the sixth duration DR6 can be referred to as the second threshold compensation operation and the third threshold compensation operation, respectively. The fourth node A is in a stable state due to the reference voltage VREF, so that the voltage at the fourth node A does not affect the compensation of the threshold voltage Vth of the first node G during this operation, so that the fourth duration DR4 and the sixth duration DR6 can also be referred to as the complete threshold compensation operation.

[0098] Although in this embodiment the initialization operation is performed three times (DR1, DR3, and DR5) and the threshold compensation operation is performed three times (DR2, DR4, and DR6), the invention is not limited thereto. The initialization operation may be performed more or less than three times, and the threshold compensation operation may be performed more or less than three times.

[0099] like Figure 8 As shown, during the seventh duration DR7, the second pixel switching element T2 is turned on. During the seventh duration DR7, the data voltage VDATA is applied to the fourth node A through the second pixel switching element T2. ELVDD-Vth+VDATA-VREF can be applied to the first node G through the coupling of the second capacitor CPR. ELVDD-Vth+VDATA-VREF is applied to the first node G during the seventh duration DR7, so that the seventh duration DR7 can be referred to as a data write operation.

[0100] like Figure 9As shown, during the eighth duration DR8, the seventh pixel switch element T7 and the eighth pixel switch element T8 are turned on. During the eighth duration DR8, the fourth node A is in a state where the data voltage VDATA is written. During the eighth duration DR8, the first node G is in a state where the data voltage ELVDD-Vth+VDATA-VREF is written through the coupling of the second capacitor CPR. During the eighth duration DR8, the bias voltage VBIAS is applied to the second node S through the eighth pixel switch element T8. In addition, the anode of the light-emitting element EE is initialized by the initialization voltage VINT through the seventh pixel switch element T7. The bias voltage VBIAS is applied to the input electrode of the first pixel switch element T1 through the eighth pixel switch element T8 during the eighth duration DR8, so that the eighth duration DR8 can be referred to as the bias operation.

[0101] like Figure 10 As shown, during the ninth duration DR9, the first pixel switching element T1, the sixth pixel switching element T6, and the ninth pixel switching element T9 are turned on. During the ninth duration DR9, the fourth node A is in a state where the data voltage VDATA is written. During the ninth duration DR9, the first node G is in a state where the coupling ELVDD-Vth+VDATA-VREF is written through the second capacitor CPR. During the ninth duration DR9, the high supply voltage ELVDD is applied to the second node S through the ninth pixel switching element T9. During the ninth duration DR9, the light-emitting element EE emits light along the path formed by the first pixel switching element T1, the sixth pixel switching element T6, and the ninth pixel switching element T9, so that the ninth duration DR9 can be referred to as the emission operation. In this paper, the drain-source current I of the first pixel switching element T1 can be expressed as the following Equation 1.

[0102] [Equation 1]

[0103]

[0104] In Equation 1, μ is the mobility of the first pixel switching element T1. Cox is the capacitance per unit area of ​​the first pixel switching element T1. W / L is the aspect ratio of the first pixel switching element T1.

[0105] Figure 11 To illustrate the application of in the write frame Figure 2 The timing diagram of the input signal of the pixel. Figure 12 To illustrate the application of in the holding frame Figure 2 The timing diagram of the input signal of the pixel.

[0106] Reference Figures 1 to 12 ,like Figure 11 As shown, in the write frame, pixels can be referenced Figures 4 to 10 During the interpretation process, light is emitted. For example, in a write frame, the first gate signal GW, the second gate signal GI, and the third gate signal GC are each active, so that the pixel can sequentially perform initialization, threshold compensation, data write, bias, and emission operations.

[0107] On the contrary, such as Figure 12 As shown, the reference can be omitted in the holding frame. Figures 4 to 10 The explanation covers initialization, threshold compensation, and data writing operations during the process. (Refer to...) Figures 4 to 10 The bias and transmit operations during the interpretation process can be performed sequentially within the hold frame.

[0108] During the initialization operation in the write frame, an initialization voltage VINT is applied to the first node G and a high power supply voltage ELVDD is applied to the second node S, enabling the first bias operation of the first pixel switching element T1. Additionally, during the bias operation in the write frame, the second bias operation of the first pixel switching element T1 can be operated using the bias voltage VBIAS through the eighth pixel switching element T8.

[0109] Conversely, in the hold frame, the initialization operation is omitted so that the first bias operation of the first pixel switching element T1 can be omitted, and instead, the second bias operation of the first pixel switching element T1 can be operated only by using the bias voltage VBIAS through the eighth pixel switching element T8 in the bias operation.

[0110] Due to the difference in the offset between the write frame and the hold frame, the brightness of the image in the write frame and the brightness of the image in the hold frame may differ from each other. Therefore, the display quality of the display panel 100 may be degraded due to the difference in brightness.

[0111] In this embodiment, the bias control signal EB used to apply the bias voltage VBIAS to the drive switching element T1 may have a first width WW in the write frame and a second width WH different from the first width WW in the hold frame. In the hold frame, the second width WH (e.g., Figure 12 The 3H in the first width WW can be set to be greater than the first width (e.g., Figure 11 (1H in the middle) so that the insufficient bias can be increased in the hold frame.

[0112] Furthermore, in this embodiment, the bias voltage VBIAS in the write frame can be equal to the bias voltage VBIAS in the hold frame. In this embodiment, the power supply voltage generator 700 can generate a bias voltage VBIAS with a constant level, regardless of the write frame and the hold frame.

[0113] Figure 13 It is shown Figure 1 Timing diagram of the operations of the display device in the write frame and hold frame.

[0114] Reference Figures 1 to 13 ,exist Figure 13 In this process, the first frame can have a frame rate of 240Hz. 240Hz can be the normal frequency. When the driving frequency is the normal frequency, the display panel 100 can only have write frames.

[0115] The first frame is a write frame, which allows the first bias operation of the first pixel switching element T1 to be operated using the initialization voltage VINT and the high power supply voltage ELVDD during the initialization operation, and the second bias operation of the first pixel switching element T1 to be performed using the bias voltage VBIAS through the eighth pixel switching element T8 during the bias operation.

[0116] The second through fifth frames can have a frame rate of 60Hz. 60Hz can be a low drive frequency, which is lower than the normal frequency.

[0117] The second frame is a write frame, and frames three through five are hold frames. The second frame is a write frame so that the first bias operation of the first pixel switching element T1 can be operated using the initialization voltage VINT and the high supply voltage ELVDD during the initialization operation, and the second bias operation of the first pixel switching element T1 can be performed using the bias voltage VBIAS through the eighth pixel switching element T8 during the bias operation. Conversely, frames three through five are hold frames so that the initialization operation is omitted, and the second bias operation of the first pixel switching element T1 can be performed only using the bias voltage VBIAS through the eighth pixel switching element T8 during the bias operation.

[0118] The bias control signal EB used to apply the bias voltage VBIAS to the drive switching element T1 may have a first width WW in the write frame and a second width WH greater than the first width WW in the hold frame, so as to compensate for insufficient bias in the hold frame.

[0119] The sixth frame can have a frame rate of 240Hz. 240Hz is a normal frequency.

[0120] According to this embodiment, the width of the bias control signal EB for the write frame and the width of the bias control signal EB for the hold frame can be set differently in the variable frequency driving method, or the bias voltage of the write frame and the bias voltage of the hold frame can be set differently in the variable frequency driving method, so that the difference between the bias degree of the write frame and the bias degree of the hold frame can be eliminated in the variable frequency driving method.

[0121] Therefore, the difference between the brightness in the written frame and the brightness in the held frame can be removed in the variable frequency driving method, thereby enhancing the display quality of the display panel 100.

[0122] Furthermore, a variable frequency driving method is operable within a range that does not cause degradation of display quality, thereby reducing the power consumption of the display device.

[0123] Figure 14 A timing diagram illustrating the operation of a display device in a write frame and a hold frame according to an embodiment of the concept of the present invention.

[0124] Aside from the method for compensating for insufficient bias, the display device and the method for driving the display device according to this embodiment are similar to those described in the reference. Figures 1 to 13 The display device and the method of driving the display device explained in the previous embodiment are essentially the same. Therefore, the same reference numerals will be used to refer to the same... Figures 1 to 13 The parts described in the previous embodiment are the same as or similar to those described above, and any repeated explanations of the above elements will be omitted.

[0125] Reference Figure 14 In this embodiment, the bias control signal EB used to apply bias voltages VBIAS1 and VBIAS2 to the drive switching element T1 may have a first width WW in the write frame and a second width WW equal to the first width WW in the hold frame. Alternatively, the bias voltage VBIAS2 of the hold frame may be set to be greater than the bias voltage VBIAS1 of the write frame, so that insufficient bias can be increased in the hold frame.

[0126] exist Figure 14 In the middle, the first frame can be Figure 14 The display panel 100 has a frame rate of 240Hz. 240Hz is a normal frequency. When the drive frequency is normal, the display panel 100 may only have write frames.

[0127] The second through fifth frames can have a frame rate of 60Hz. 60Hz can be a low drive frequency, which is lower than the normal frequency.

[0128] The second frame is a write frame, and frames three through five are hold frames. The second frame is a write frame so that the first bias operation of the first pixel switching element T1 can be operated using the initialization voltage VINT and the high supply voltage ELVDD during the initialization operation, and the second bias operation of the first pixel switching element T1 can be performed using the bias voltage VBIAS1 via the eighth pixel switching element T8 during the bias operation. Conversely, frames three through five are hold frames so that the initialization operation is omitted, and the second bias operation of the first pixel switching element T1 can be operated only using the bias voltage VBIAS2 via the eighth pixel switching element T8 during the bias operation.

[0129] The bias control signal EB, used to apply bias voltages VBIAS1 and VBIAS2 to the drive switching element T1, may have a first width WW in the write frame and a first width WW in the hold frame. The bias voltage VBIAS2 of the hold frame may be set to be greater than the bias voltage VBIAS1 of the write frame.

[0130] The sixth frame can have a frame rate of 240Hz. 240Hz is a normal frequency.

[0131] According to this embodiment, the width of the bias control signal EB for the write frame and the width of the bias control signal EB for the hold frame can be set differently in the variable frequency driving method, or the bias voltage of the write frame and the bias voltage of the hold frame can be set differently in the variable frequency driving method, so that the difference between the bias degree of the write frame and the bias degree of the hold frame can be eliminated in the variable frequency driving method.

[0132] Therefore, the difference between the brightness in the written frame and the brightness in the held frame can be removed in the variable frequency driving method, thereby enhancing the display quality of the display panel 100.

[0133] Furthermore, a variable frequency driving method is operable within a range that does not cause degradation of display quality, thereby reducing the power consumption of the display device.

[0134] Figure 15 A timing diagram illustrating the operation of a display device in a write frame and a hold frame according to an embodiment of the concept of the present invention.

[0135] Aside from the method for compensating for insufficient bias, the display device and the method for driving the display device according to this embodiment are similar to those described in the reference. Figures 1 to 13 The display device and the method of driving the display device explained in the previous embodiment are essentially the same. Therefore, the same reference numerals will be used to refer to the same... Figures 1 to 13 The parts described in the previous embodiment are the same as or similar to those described above, and any repeated explanations of the above elements will be omitted.

[0136] Reference Figure 15 In this embodiment, the bias control signal EB used to apply bias voltages VBIAS1 and VBIAS2 to the drive switching element T1 may have a first width WW in the write frame and a second width WH different from the first width WW in the hold frame. The second width WH may be set to be greater than the first width WW so that insufficient bias can be increased in the hold frame.

[0137] In addition, the bias voltage VBIAS2 of the hold frame can be set to be greater than the bias voltage VBIAS1 of the write frame to increase the degree of insufficient bias in the hold frame.

[0138] exist Figure 15 In the middle, the first frame can be Figure 15 The display panel 100 has a frame rate of 240Hz. 240Hz is a normal frequency. When the drive frequency is normal, the display panel 100 may only have write frames.

[0139] The second through fifth frames can have a frame rate of 60Hz. 60Hz can be a low drive frequency, which is lower than the normal frequency.

[0140] The second frame is a write frame, and frames three through five are hold frames. The second frame is a write frame so that the first bias operation of the first pixel switching element T1 can be operated using the initialization voltage VINT and the high supply voltage ELVDD during the initialization operation, and the second bias operation of the first pixel switching element T1 can be operated using the bias voltage VBIAS1 via the eighth pixel switching element T8 during the bias operation. Conversely, frames three through five are hold frames so that the initialization operation is omitted, and the second bias operation of the first pixel switching element T1 can be operated only using the bias voltage VBIAS1 via the eighth pixel switching element T8 during the bias operation.

[0141] The bias control signal EB, used to apply bias voltages VBIAS1 and VBIAS2 to the drive switching element T1, may have a first width WW in the write frame and a second width WH greater than the first width WW in the hold frame, so as to compensate for insufficient bias in the hold frame.

[0142] In addition, the bias voltage VBIAS2 for holding frames can be set to be greater than the bias voltage VBIAS1 for writing frames.

[0143] The sixth frame can have a frame rate of 240Hz. 240Hz is a normal frequency.

[0144] According to this embodiment, the width of the bias control signal EB for the write frame and the width of the bias control signal EB for the hold frame can be set differently in the variable frequency driving method, or the bias voltage of the write frame and the bias voltage of the hold frame can be set differently in the variable frequency driving method, so that the difference between the bias degree of the write frame and the bias degree of the hold frame can be eliminated in the variable frequency driving method.

[0145] Therefore, the difference between the brightness in the written frame and the brightness in the held frame can be removed in the variable frequency driving method, thereby enhancing the display quality of the display panel 100.

[0146] Furthermore, a variable frequency driving method is operable within a range that does not cause degradation of display quality, thereby reducing the power consumption of the display device.

[0147] Figure 16A circuit diagram illustrating the pixels of a display panel of a display device according to an embodiment of the concept of the present invention. Figure 17 To show the application to Figure 16 Timing diagram of the input signals of pixels and node signals. Figure 18 To illustrate the application of in the write frame Figure 16 The timing diagram of the input signal of the pixel. Figure 19 To illustrate the application of in the holding frame Figure 16 The timing diagram of the input signal of the pixel.

[0148] Apart from the pixel structure of the display panel, the display device and the method for driving the display device according to this embodiment are similar to those described in the reference. Figures 1 to 13 The display device and the method of driving the display device explained in the previous embodiment are essentially the same. Therefore, the same reference numerals will be used to refer to the same... Figures 1 to 13 The parts described in the previous embodiment are the same as or similar to those described above, and any repeated explanations of the above elements will be omitted.

[0149] Reference Figures 16 to 19Each pixel may include a first pixel switching element T1, a second pixel switching element T2, a third pixel switching element T3, a fourth pixel switching element T4, a fifth pixel switching element T5, a sixth pixel switching element T6, a seventh pixel switching element T7, an eighth pixel switching element T8, a light-emitting element EE, a first capacitor CST, and a second capacitor CPR. The first pixel switching element T1 includes a control electrode connected to a first node G, an input electrode connected to a second node S, and an output electrode connected to a third node D. The second pixel switching element T2 includes a control electrode, an input electrode receiving a data voltage VDATA, and an output electrode connected to a fourth node N4. The third pixel switching element T3 includes a control electrode, an input electrode connected to the first node G, and an output electrode connected to the third node D. The fourth pixel switching element T4 includes a control electrode, an input electrode receiving a reference voltage VREF, and an output electrode connected to the fourth node N4. The fifth pixel switching element T8... The switching element T5 includes a control electrode, an input electrode that receives a high power supply voltage ELVDD, and an output electrode connected to the second node S. The sixth pixel switching element T6 includes a control electrode, an input electrode connected to the third node D, and an output electrode connected to the anode of the light-emitting element EE. The seventh pixel switching element T7 includes a control electrode, an input electrode that receives an initialization voltage VINT, and an output electrode connected to the anode of the light-emitting element EE. The eighth pixel switching element T8 includes a control electrode, an input electrode that receives a bias voltage VBIAS, and an output electrode connected to the second node S. The light-emitting element EE includes an anode connected to the output electrode of the seventh pixel switching element T7 and a cathode that receives a low power supply voltage ELVSS. The first capacitor CST includes a first electrode that receives a high power supply voltage ELVDD and a second electrode connected to the first node G. The second capacitor CPR includes a first electrode connected to the third node D and a second electrode connected to the fourth node N4.

[0150] For example, the bias control signal EB2(N) (for example, Figure 17 EB2) can be applied to the control electrode of the eighth pixel switching element T8. For example, the first gate signal GW(N) (e.g., Figure 17 The GW signal can be applied to the control electrode of the second pixel switching element T2. For example, the second gate signal GC(N) (e.g., Figure 17 The GC signal in the third pixel switching element T3 can be applied to the control electrode of the third pixel switching element T3. For example, the third gate signal EB1(N) (e.g., Figure 17 The fourth gate signal EB1(N+1) can be applied to the control electrode of the fourth pixel switching element T4. For example, the fourth gate signal EB1(N+1) can be applied to the control electrode of the seventh pixel switching element T7. In this paper, the fourth gate signal EB1(N+1) can be the same as the third gate signal EB1(N) applied to the next horizontal line.

[0151] like Figure 17 As shown, the pixel can perform initialization and data write operations during the first duration DRA. During the first duration DRA, the data voltage VDATA can be written to the pixel.

[0152] The pixel can be biased during the second duration DRB. During the second duration DRB, the bias voltage VBIAS can be written to the pixel.

[0153] The pixel can emit light during the third duration DRC. During the third duration DRC, the light-emitting element EE can emit light corresponding to the data voltage VDATA.

[0154] like Figure 18 and Figure 19 As shown, in this embodiment, the bias control signal EB2, which applies the bias voltage VBIAS to the drive switching element T1, can have a first width WW in the write frame and a second width WH, which is different from the first width WW, in the hold frame. In the hold frame, the second width WH can be set to be greater than the first width WW so that insufficient bias can be increased in the hold frame.

[0155] Furthermore, in this embodiment, the bias voltage VBIAS in the write frame can be equal to the bias voltage VBIAS in the hold frame. In this embodiment, the power supply voltage generator 700 can generate a bias voltage VBIAS with a constant level, regardless of the write frame and the hold frame.

[0156] According to this embodiment, the width of the bias control signal EB2 for the write frame and the width of the bias control signal EB2 for the hold frame can be set differently in the variable frequency driving method, or the bias voltage of the write frame and the bias voltage of the hold frame can be set differently in the variable frequency driving method, so that the difference between the bias degree of the write frame and the bias degree of the hold frame can be removed in the variable frequency driving method.

[0157] Therefore, the difference between the brightness in the written frame and the brightness in the held frame can be removed in the variable frequency driving method, thereby enhancing the display quality of the display panel 100.

[0158] Furthermore, a variable frequency driving method is operable within a range that does not cause degradation of display quality, thereby reducing the power consumption of the display device.

[0159] According to the concept of the present invention as described above, the difference between the brightness in the written frame and the brightness in the held frame can be removed in the variable frequency driving method, thereby enhancing the display quality of the display panel.

[0160] The foregoing is illustrative of the concept of the invention and should not be construed as limiting it. Although some embodiments of the concept of the invention have been described, those skilled in the art will readily appreciate that many modifications can be made to the embodiments without substantially departing from the novelty and advantages of the concept of the invention. Accordingly, all such modifications are intended to be included within the scope of the concept of the invention as defined in the claims. In the claims, the clauses specifying means plus function are intended to cover structures described herein as performing said function, and not only structural equivalents but also equivalent structures. Therefore, it should be understood that the foregoing is illustrative of the concept of the invention and should not be construed as limiting it to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims. The concept of the invention is defined by the appended claims, and the equivalents of the claims are included therein.

[0161] While certain implementations and methods have been described herein, other implementations and variations will become apparent from this description. Accordingly, it will be apparent to those skilled in the art that the inventive concept is not limited to these implementations, but rather to the broader scope of the appended claims and various apparent variations and equivalents.

Claims

1. A display device, comprising: The display panel has pixels including a first pixel switching element and a light-emitting element; A drive controller configured to determine a drive frequency that changes based on input image data or a drive mode; A gate driver configured to output a gate signal and a bias control signal to the pixel; A transmitter driver configured to output a transmitter signal to the pixel; as well as A data driver configured to output a data voltage to the pixel. The bias control signal that applies the bias voltage to the first pixel switching element has a first width in the write frame and a second width different from the first width in the hold frame. The pixels include: The first pixel switching element includes a control electrode connected to a first node, an input electrode connected to a second node, and an output electrode connected to a third node; The second pixel switching element includes a control electrode, an input electrode configured to receive the data voltage, and an output electrode connected to the fourth node; A third pixel switching element, the third pixel switching element including a control electrode, an input electrode connected to the first node, and an output electrode connected to the third node; A fourth pixel switching element, the fourth pixel switching element including a control electrode, an input electrode configured to receive an initialization voltage, and an output electrode connected to the first node; A fifth pixel switching element, the fifth pixel switching element including a control electrode, an input electrode configured to receive a reference voltage, and an output electrode connected to the fourth node; A sixth pixel switching element, the sixth pixel switching element including a control electrode, an input electrode connected to the third node, and an output electrode connected to the anode of the light-emitting element; A seventh pixel switching element, the seventh pixel switching element including a control electrode, an input electrode configured to receive the initialization voltage, and an output electrode connected to the anode of the light-emitting element; An eighth pixel switching element, the eighth pixel switching element including a control electrode, an input electrode configured to receive the bias voltage, and an output electrode connected to the second node; A ninth pixel switching element, the ninth pixel switching element including a control electrode, an input electrode configured to receive a high power supply voltage, and an output electrode connected to the second node; The light-emitting element includes an anode connected to the output electrode of the seventh pixel switching element and a cathode configured to receive a low power supply voltage; A first capacitor, the first capacitor including a first electrode configured to receive the high power supply voltage and a second electrode connected to the fourth node; and The second capacitor includes a first electrode connected to the fourth node and a second electrode connected to the first node.

2. The display device according to claim 1, wherein, The second width is greater than the first width.

3. The display device according to claim 1, wherein, When the driving frequency is at a normal frequency, the display panel only has the write frame, and When the driving frequency is a low driving frequency that is less than the normal frequency, the display panel has the write frame and the hold frame.

4. The display device according to claim 1, wherein, The bias control signal is applied to the control electrode of the eighth pixel switching element.

5. The display device according to claim 4, wherein, The bias control signal is applied to the control electrode of the seventh pixel switching element.

6. The display device according to claim 1, wherein, A first gate signal is applied to the control electrode of the second pixel switching element.

7. The display device according to claim 6, wherein, The second gate signal is applied to the control electrode of the fourth pixel switching element. The third gate signal is applied to the control electrode of the third pixel switching element and the control electrode of the fifth pixel switching element.

8. The display device according to claim 1, wherein, A first transmission signal is applied to the control electrode of the ninth pixel switching element, and The second transmission signal is applied to the control electrode of the sixth pixel switching element.

9. The display device according to claim 1, further comprising: A power supply voltage generator is configured to generate a high power supply voltage, a low power supply voltage, an initialization voltage, a reference voltage, and a bias voltage, and to output the high power supply voltage, the low power supply voltage, the initialization voltage, the reference voltage, and the bias voltage to the pixel.

10. The display device according to claim 9, wherein, The bias voltage of the hold frame is greater than the bias voltage of the write frame.

11. A display device, comprising: The display panel has pixels including a first pixel switching element and a light-emitting element; A drive controller configured to determine a drive frequency that changes based on input image data or a drive mode; A gate driver configured to output a gate signal and a bias control signal to the pixel; A transmitter driver configured to output a transmitter signal to the pixel; as well as A data driver configured to output a data voltage to the pixel. The bias control signal that applies the bias voltage to the first pixel switching element has a first width in the write frame and a second width different from the first width in the hold frame. The pixels include: The first pixel switching element includes a control electrode connected to a first node, an input electrode connected to a second node, and an output electrode connected to a third node; The second pixel switching element includes a control electrode, an input electrode configured to receive the data voltage, and an output electrode connected to the fourth node; A third pixel switching element, the third pixel switching element including a control electrode, an input electrode connected to the first node, and an output electrode connected to the third node; A fourth pixel switching element, the fourth pixel switching element including a control electrode, an input electrode configured to receive a reference voltage, and an output electrode connected to the fourth node; A fifth pixel switching element, the fifth pixel switching element including a control electrode, an input electrode configured to receive a high power supply voltage, and an output electrode connected to the second node; A sixth pixel switching element, the sixth pixel switching element including a control electrode, an input electrode connected to the third node, and an output electrode connected to the anode of the light-emitting element; A seventh pixel switching element, the seventh pixel switching element including a control electrode, an input electrode configured to receive an initialization voltage, and an output electrode connected to the anode of the light-emitting element; An eighth pixel switching element, the eighth pixel switching element including a control electrode, an input electrode configured to receive the bias voltage, and an output electrode connected to the second node; The light-emitting element includes an anode connected to the output electrode of the seventh pixel switching element and a cathode configured to receive a low power supply voltage; A first capacitor, the first capacitor including a first electrode configured to receive the high power supply voltage and a second electrode connected to the first node; and The second capacitor includes a first electrode connected to the third node and a second electrode connected to the fourth node.

12. The display device according to claim 11, wherein, The bias control signal is applied to the control electrode of the eighth pixel switching element.

13. The display device according to claim 12, wherein, A first gate signal is applied to the control electrode of the second pixel switching element, and The second gate signal is applied to the control electrode of the third pixel switching element.

14. The display device according to claim 13, wherein, A third gate signal is applied to the control electrode of the fourth pixel switching element. The fourth gate signal is applied to the control electrode of the seventh pixel switching element, and The fourth gate signal is the same as the third gate signal applied to the next horizontal line.

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