Memory system and method of programming the same

Abstract

The present application provides a memory system and a programming method. Each word line of the memory is connected to a plurality of memory cells, the plurality of memory cells including first memory cells and second memory cells other than the first memory cells, and the programming method includes: performing a first-stage programming to program threshold voltages of the first memory cells to be greater than or equal to a final verify voltage of the first memory cells and to program threshold voltages of the second memory cells to be greater than or equal to a first-stage intermediate verify voltage, wherein the first-stage intermediate verify voltage of the memory cells is less than the final verify voltage, the threshold voltage of the first memory cells is greater than the threshold voltage of the second memory cells; and performing an Nth-stage programming to configure the threshold voltages of the plurality of second memory cells to be greater than or equal to the final verify voltage, wherein N≥2.

Description

[0001] This application is a divisional application of application number 202110671777.0 filed on June 17, 2021, entitled "Memory System and Programming Method Thereof". Technical Field

[0002] This application relates to the field of memory, and more particularly to a non-volatile memory system and a method for setting the programming voltage thereon. Background Technology

[0003] Flash memory devices are characterized by their reprogrammability, high storage density, low power consumption, large capacity, fast read and write speeds, and suitability for storing large amounts of data. They have demonstrated strong market competitiveness in the non-volatile storage field and are being used more and more widely. For example, flash memory devices are already widely used in smartphones, cloud storage, and computer solid-state drives.

[0004] Flash memory widely uses NAND flash memory chips to process data. Existing NAND flash memory chips typically employ a multi-level programming method to reduce coupling interference between word lines of memory cells and improve the accuracy of data access. The multi-level programming method uses Incremental Step Pulse Programming (ISPP) to program the memory cells of the flash memory device by gradually increasing the programming voltage. During the programming process, multiple programming pulses are applied to the memory cells. After each programming operation, a verification operation is performed. If the threshold voltage of the memory cell is greater than or equal to a predetermined verification voltage, the verification is successful, and the programming operation ends. Conversely, if the threshold voltage of the memory cell is less than the verification voltage, the verification fails, and the programming voltage applied to the memory cell needs to be increased until the verification is successful, at which point the programming ends.

[0005] When storing large amounts of data in flash memory devices, extensive verification processing is required, which consumes a significant amount of time and reduces the read and write speed of the memory. Therefore, improving the read and write speed of memory cells while ensuring the accuracy of data storage is a problem that needs to be solved at present. Summary of the Invention

[0006] In view of the above or other at least some shortcomings of the prior art, this application provides a memory system and a method for setting the programming voltage thereon.

[0007] According to one aspect of this application, a method for programming a memory is provided, wherein each word line of the memory connects to a plurality of memory cells, characterized in that the plurality of memory cells includes a first memory cell and second memory cells other than the first memory cell, the method comprising: performing a first-level programming to set a threshold voltage of the first memory cell to be greater than or equal to a final verification voltage of the first memory cell; programming a threshold voltage of the second memory cell to be greater than or equal to a first-level intermediate verification voltage, wherein the first-level intermediate verification voltage of the memory cell is less than the final verification voltage, and the threshold voltage of the first memory cell is greater than the threshold voltage of the second memory cell; and performing an Nth-level programming to configure the threshold voltages of the plurality of second memory cells to be greater than or equal to the final verification voltage, wherein N≥2.

[0008] According to another aspect of this application, a memory system is provided, which may include a memory array, a voltage supply circuit, and a controller. The memory array includes a plurality of word lines, each connected to a plurality of memory cells. The voltage supply circuit is coupled to the memory array. The controller is configured to control the voltage supply circuit to apply a programming voltage and a verification voltage to each word line to program a plurality of memory cells connected to the same word line. The plurality of memory cells connected to the same word line includes a first memory cell and second memory cells other than the first memory cell. In a first-level programming stage, a threshold voltage of the first memory cell is configured to be greater than or equal to a final verification voltage of the first memory cell, and threshold voltages of the plurality of second memory cells are configured to be greater than or equal to a first-level intermediate verification voltage, wherein the first-level intermediate verification voltage of the memory cell is less than the final verification voltage, and the threshold voltage of the first memory cell is greater than the threshold voltage of the second memory cell; and in an N-level programming stage, the threshold voltages of the plurality of second memory cells are configured to be greater than or equal to the final verification voltage, where N ≥ 2.

[0009] In one implementation, during each programming stage from the first to the Nth stage, the verification voltage and final verification voltage of the plurality of second memory cells may be configured to be less than the final verification voltage of the first memory cell.

[0010] In one embodiment, the first-level programming may include: applying a first programming voltage to the plurality of second memory cells; verifying whether the threshold voltage of the plurality of second memory cells is greater than or equal to the first-level intermediate verification voltage; in response to the threshold voltage of the plurality of second memory cells being less than the first-level intermediate verification voltage, increasing the first programming voltage by a step length, and reapplying the increased first programming voltage to the plurality of second memory cells; and continuing to perform the verification step and the reapplication step until the threshold voltage of the plurality of second memory cells is greater than or equal to the first-level intermediate verification voltage.

[0011] In one embodiment, the first-level programming may further include: applying an Nth programming voltage to the first memory cell, such that the threshold voltage of the first memory cell is greater than or equal to the final verification voltage, wherein the final verification voltage is the verification voltage of the first memory cell in the Nth-level programming.

[0012] In one implementation, the Nth level programming may include: applying an Nth programming voltage to the plurality of second memory cells; verifying whether the threshold voltage of the second memory cells in different memory states after being subjected to the Nth programming voltage is greater than or equal to the final verification voltage; in response to the threshold voltage of the second memory cells in different memory states being less than the final verification voltage, increasing the Nth programming voltage by an Nth step and reapplying the Nth programming voltage after the increase in step size to the second memory cells; and continuing to perform the verification step and the reapplication step until the threshold voltage of the plurality of second memory cells is greater than or equal to the final verification voltage.

[0013] In one implementation, the Nth step length may be smaller than the first step length.

[0014] In one implementation, before performing the Nth level of the multi-level programming, the first level programming may be performed sequentially on the memory cells connected to the plurality of word lines of the memory.

[0015] In one embodiment, the memory array may include any one of a single-level cell (SLC) flash memory array, a multi-level cell (MLC) flash memory array, a three-level cell (TLC) flash memory array, a four-level cell (QLC) flash memory array, and a five-level cell (PLC) flash memory array.

[0016] According to the memory system and programming voltage setting method of some embodiments of this application, the threshold voltage verification is only performed on the memory cell in the highest storage state during the first level of programming, reducing the threshold voltage verification time in subsequent multi-level programming and thus reducing the memory programming time to a certain extent. Furthermore, according to some of the above embodiments, multi-level programming of the memory cell using programming pulses of different durations can reduce programming interference between word lines containing the memory cell, achieving a denser threshold voltage distribution and improving the accuracy of data storage to a certain extent. Attached Figure Description

[0017] Figure 1 A memory system according to an embodiment of this application;

[0018] Figure 2 This is a schematic diagram of a portion of the storage cell array according to an embodiment of this application;

[0019] Figure 3 This is a flowchart illustrating a multi-level programming method according to an embodiment of this application;

[0020] Figure 4 This is a schematic diagram illustrating the specific process of step S201 for performing first-level programming on a memory cell according to an embodiment of this application;

[0021] Figure 5 This is a schematic diagram of the threshold voltage distribution after the first stage of programming of the QLC memory storage cell according to an embodiment of this application;

[0022] Figure 6A A schematic diagram of memory programming pulses according to an embodiment of this application;

[0023] Figure 6B This is a schematic diagram of the memory programming process according to an embodiment of this application;

[0024] Figure 7 A schematic diagram illustrating the specific process of performing the Nth level programming step S202 of the storage unit according to the embodiments of this application; and

[0025] Figure 8 This is a schematic diagram of the threshold voltage distribution after the Nth level programming of the QLC memory storage cell according to an embodiment of this application. Detailed Implementation

[0026] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this application and are not intended to limit the scope of this application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0027] In the accompanying drawings, the size, dimensions, and shapes of the elements have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not strictly to scale. As used herein, the terms “approximately,” “about,” and similar terms are used to indicate approximation, not degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art. Furthermore, the order in which the steps are described in this application does not necessarily indicate the order in which these steps occur in actual operation, unless otherwise expressly defined or deduced from the context.

[0028] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to examples or illustrations.

[0029] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0030] It should be noted that, where there is no conflict, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0031] Figure 1 This is a memory system 100 according to an embodiment of this application. For example... Figure 1 As shown, the memory system 100 may include a memory cell array 10, a voltage supply circuit 20, and a controller 30.

[0032] The memory cell array 10 may include a plurality of memory blocks, each memory block including a plurality of word lines WL connected to a plurality of memory cells 101 respectively, and each memory cell 101 may realize a plurality of memory states, wherein a lower memory state corresponds to a lower threshold voltage and a higher memory state corresponds to a higher threshold voltage. Figure 2 This is a schematic diagram of a portion of a storage cell array according to an embodiment of this application. Figure 2As shown, the memory cells in the memory cell array 10 can be connected to word lines WL and bit lines BL. The memory cell array 10 can also be connected to other select lines, such as serial select line SSL, ground select line GSL, common source line CSL, etc. The number of memory cells, word lines WL, and bit lines BL are illustrative and not limited thereto. The memory cell array 10 can be connected to the voltage supply circuit 20 via word lines WL and bit lines BL. The memory cell array 10 can refer to an array formed by arranging memory cells, or it can refer to an array formed by arranging all the memory cells constituting the entire memory. According to embodiments of this application, the memory cell array 10 can include any one of a single-level cell (SLC) flash memory cell array, a multi-level cell (MLC) flash memory cell array, a three-level cell (TLC) flash memory cell array, a four-level cell (QLC) flash memory cell array, and a five-level cell (PLC) flash memory cell array. Embodiments of this application do not specifically limit the type of memory cell array 10; any suitable memory cell array is permitted without departing from the present invention.

[0033] Each storage cell in the storage cell array 10 can store one or more bits. For example, a single-level cell (SLC) flash memory cell can store one bit, a multi-level cell (MLC) flash memory cell can store two bits, a triple-level cell (TLC) flash memory cell can store three bits, a quad-level cell (QLC) flash memory cell can store four bits, a penta-level cell (PLC) flash memory cell can store five bits, and so on. A multi-level storage cell can implement multiple storage states, thereby writing data bits into the storage cell by programming it to one of multiple storage states. For example, an MLC has four storage states, each determined by two bits; a TLC has eight storage states, each determined by three bits; a QLC has sixteen storage states, each determined by four bits; and a PLC has thirty-two storage states, each determined by five bits.

[0034] Back Figure 1 ,like Figure 1As shown, voltage supply circuit 20 is coupled to memory cell array 10 and configured to apply programming voltage and verification voltage to predetermined word lines. Voltage supply circuit 20 can generate various voltages for performing operations such as erasing, programming, reading, writing, and verification on memory cell array 10 in response to control signals from controller 30. Specifically, voltage supply circuit 20 may include page caches, word line drive circuitry, etc., and is used to provide word line voltages and bit line voltages. The generated word line voltages and bit line voltages may, for example, include programming voltage, programming suppression voltage, read voltage, and verification voltage.

[0035] The controller 30 is coupled to the memory cell array 10 and the voltage supply circuit 20, and is configured to control the voltage supply circuit to generate and apply different programming voltages to the memory cell array 10. The controller 30 selects bit lines and word lines to apply specific programming voltages to the memory cells in the memory cell array 10 by sending programming signals, thereby placing the memory cells in different storage states. For example, during a programming operation, a programming voltage and a verification voltage can be applied to the word line containing the selected programmed memory cell, and a programming suppression voltage can be applied to the bit line containing the unselected programmed memory cell. During a read operation, a read voltage can be applied to the word line containing the selected programmed memory cell, and a read suppression voltage can be applied to the bit line containing the memory cell that is prohibited from reading.

[0036] In one embodiment of this application, the controller 30 is configured to control the voltage supply circuit 20 to apply a programming voltage to each word line for multi-level programming of multiple memory cells connected to the same word line. In multi-level programming, the multiple memory cells connected to the same word line include a first memory cell and a second memory cell other than the first memory cell.

[0037] Figure 3 This is a flowchart illustrating a multi-level programming method 200 according to an embodiment of this application. Figure 3As shown, the memory programming voltage method 200 includes steps S201 and S202. In step S201, under the control of the controller 30, the first level of multi-level programming (first programming) is performed such that the threshold voltage of the first memory cell is greater than or equal to the final verification voltage (verification voltage of the first memory state) of the first memory cell, that is, the threshold voltage of the first memory cell is in the final threshold voltage distribution of the first memory state, and the threshold voltages of a plurality of second memory cells are configured to be greater than or equal to the first level intermediate verification voltage (intermediate verification voltage of the second memory state), that is, the threshold voltage of the second memory cells is in the intermediate threshold voltage distribution of the second memory state, wherein the first level intermediate verification voltage (intermediate verification voltage of the second memory state) of the memory cell is less than the final verification voltage (final verification voltage of the second memory state) of the second memory cell, and the threshold voltage of the first memory cell is greater than the threshold voltage of the second memory cell. In step S202, the Nth level of multi-level programming (second programming) is performed, such that the threshold voltages of the plurality of second memory cells are configured to be greater than or equal to the final verification voltage of the second memory cells (the final verification voltage of the second memory state), that is, the threshold voltages of the second memory cells are in the final threshold voltage distribution of the second memory state, where N≥2. Moreover, in any programming process, the verification voltages of the plurality of second memory cells are configured to be less than the verification voltage of the first memory cell.

[0038] According to the programming method of the embodiments of this application, by performing multi-level programming on the second storage unit and programming the first storage unit once, the programming time of the storage unit is improved to a certain extent, thereby increasing the storage speed of the memory.

[0039] Figure 4 This is a schematic diagram illustrating the specific process of step S201 for performing first-level programming of a memory cell according to an embodiment of this application. For example... Figure 4 As shown, step S201 of the first-level programming may include:

[0040] Step S2011: Apply a first programming voltage to the plurality of second memory cells;

[0041] Step S2012: Verify whether the threshold voltage of multiple second memory cells is greater than or equal to the first-level intermediate verification voltage; the first-level intermediate verification voltage is a preset voltage used to verify the memory cells in the first-level programming, and the magnitude of the preset voltage can be preset differently according to the specific memory cells.

[0042] Step S2013: In response to the threshold voltage of the plurality of second memory cells being less than the first-stage intermediate verification voltage, the first programming voltage is increased by the length of the first step, and the increased first programming voltage is reapplied to the plurality of second memory cells;

[0043] Step S2014: Continue performing the verification step and the reapplication step until the threshold voltage of the multiple second memory cells is greater than or equal to the first-level intermediate verification voltage.

[0044] In the first-level programming, the Nth programming voltage is applied to the first memory cell so that the threshold voltage of the first memory cell is greater than or equal to the final verification voltage of the first memory cell, where the final verification voltage is the verification voltage corresponding to the first memory cell in the Nth-level programming.

[0045] According to the method for performing first-level programming of the memory cell according to the embodiments of this application, a first programming voltage is applied to the word line connected to the memory cell, and the voltage of the bit line where the memory cell is located is controlled to make the memory cell be in different storage states for preliminary programming.

[0046] Figure 5 This is a schematic diagram of the threshold voltage distribution after the first stage of programming of the QLC memory storage cell according to an embodiment of this application. Figure 5 As shown, the horizontal axis represents the threshold voltage of the memory cell, the vertical axis represents the number of memory cells, and the curve represents the normal distribution of the number of memory cells under different threshold voltages. A single memory cell in a QLC flash memory can store 4 bits of data, meaning each cell can have 16 different storage states, represented by storage state 1 P0', storage state 2 P1', storage state 3 P2'... storage state 16 P15'. For ease of description, memory cells in storage states P0'-P14' are referred to as second memory cells, and memory cells in the highest storage state P15' are referred to as first memory cells. Each storage state from P0' to P14' corresponds to a threshold voltage range (i.e., an intermediate threshold voltage distribution), and each storage state includes a first-level intermediate verification voltage; that is, the intermediate verification voltage of storage state 2 P1' is PV1', the intermediate verification voltage of storage state 3 P2' is PV2'... but the intermediate verification voltage of storage state 16 P15' is PV15', which is the final verification voltage.

[0047] Figure 6A This is a schematic diagram of the memory programming pulse according to an embodiment of this application. Figure 6B This is a schematic diagram of the memory programming process according to an embodiment of this application. Currently, the commonly used memory programming method is incremental pulse programming. Taking voltage programming signals as an example, combined with... Figure 6A and Figure 6B Explain the programming process.

[0048] like Figure 6A As shown, the horizontal axis represents time, and the vertical axis represents the programming voltage of the memory cell. Figure 6BThe horizontal axis represents time, and the vertical axis represents the threshold voltage of the memory cell. Taking Level 1 programming as an example, firstly, a programming pulse 510 (first programming voltage) is applied to the memory cell. Then, the verification stage 520 is entered to verify whether the threshold voltage of the second memory cell is greater than or equal to the first intermediate verification voltage. For example, the threshold voltage of the second memory cell in the P1' storage state is compared with the first intermediate verification voltage PV1' of the P1' storage state. If the threshold voltage of some second memory cells in the P1' storage state is greater than or equal to the first intermediate verification voltage PV1', and the threshold voltage of other second memory cells in the P1' storage state is less than the first intermediate verification voltage PV1', then a programming pulse 530 (second programming voltage) is applied to the second memory cells with a threshold voltage less than the first intermediate verification voltage. The voltage corresponding to the programming pulse 530 is ΔVpp greater than the voltage corresponding to the programming pulse 510. At this time, the threshold voltage of the second memory cell with a threshold voltage less than the first intermediate verification voltage PV1' is increased, for example, by ΔVth. Then, the verification stage 540 is entered to verify whether the threshold voltage of the memory cell with a threshold voltage less than the first intermediate verification voltage PV1' after increasing the threshold voltage by ΔVth is greater than or equal to the first intermediate verification voltage PV1'. The programming voltage is applied in increments of the first step length, i.e., ΔVpp. The threshold voltage of the memory cell that has not reached the first-level intermediate verification voltage increases with the increase of the programming voltage. This process is repeated until the threshold voltage of the second memory cell is greater than or equal to the first-level intermediate verification voltage. The Nth-level programming voltage is directly applied to the first memory cell in the highest storage state P15', making the threshold voltage of the first memory cell greater than or equal to the final verification voltage of the first memory cell. As those skilled in the art will know, Figure 6A The examples shown are for illustrative purposes only and are not intended to limit the number of first programming pulses or the pulse amplitude.

[0049] In one embodiment of the programming method of this application, before performing the Nth level programming of the multi-level programming, the first level programming is performed sequentially on the memory cells connected by multiple word lines of the memory.

[0050] Figure 7 This is a schematic diagram illustrating the specific process of performing the Nth level programming step S202 of the storage unit according to an embodiment of this application. For example... Figure 7 As shown, the steps for programming the Nth level of the memory cell are as follows:

[0051] Step S2021: Apply the Nth programming voltage (fifth programming voltage) to the plurality of second memory cells;

[0052] Step S2022: Verify whether the threshold voltage of the second memory cell, which is in a different memory state after being subjected to the Nth programming voltage, is greater than or equal to the final verification voltage;

[0053] Step S2023: In response to the threshold voltage of the second memory cell in a different memory state being less than the final verification voltage, the Nth programming voltage is increased by the Nth step, and the Nth programming voltage (sixth programming voltage) after the increase is reapplied to the second memory cell;

[0054] Step S2024: Continue performing the verification step and reapplying the step until the threshold voltage of the multiple second memory cells is greater than or equal to the final verification voltage.

[0055] According to the method for performing Nth-level programming on the second memory cell according to the embodiments of this application, the second memory cell in different storage states is further programmed so that the threshold voltage distribution of the second memory cell in different storage states meets the final requirements.

[0056] Figure 8 This is a schematic diagram of the threshold voltage distribution after the Nth level programming of a QLC memory storage cell according to an embodiment of this application. Figure 8 As shown, the horizontal axis represents the threshold voltage of the memory cell, and the vertical axis represents the number of memory cells. The curve represents the normal distribution of the number of memory cells under different threshold voltages. The memory cells are then programmed in the Nth stage using a progressively increasing pulse programming method. The Nth programming voltage is applied to multiple second memory cells (excluding the first memory cell). For example, memory states P0', P1', P2'…P14' are programmed in the Nth stage, while memory state P15' is not. Each memory state from P0 to P14 corresponds to a threshold voltage range (i.e., the final threshold voltage distribution). The Nth stage programming process is similar to the first stage programming and will not be elaborated further. After the Nth stage programming, each memory state from P0 to P14 is represented as memory state P0 (1st stage), memory state P1 (2nd stage), memory state P2 (3rd stage),…memory state P14 (15th stage). It is worth noting that the voltage applied in the Nth stage programming increases in Nth step increments, where the Nth step increment is smaller than the first step increment.

[0057] According to the programming method of this application embodiment, during the first-level programming, using programming pulses with a large step size can effectively reduce programming time. However, the threshold voltage distribution range of the memory cells is large, and the threshold voltage distribution ranges of adjacent states may overlap. Even small changes in the threshold voltage of the memory cells can cause misreading, resulting in severe programming interference. Therefore, during the N-level programming, using programming pulses with a smaller step size can effectively reduce the distribution range of the threshold voltage of memory cells in the same memory state, reduce programming interference, and improve programming accuracy.

[0058] In addition, during the Nth-level programming, the threshold voltages of the second memory cells in different storage states are verified and compared with the final verification voltage of the second memory cells. After the Nth-level programming, the threshold voltages of multiple second memory cells are greater than or equal to the final verification voltage of the second memory cells. The final verification voltages of the second memory cells in the Nth-level programming are PV1, PV2…PV15 respectively, where PV15 is equal to PV15’, that is, the final verification voltage of the first memory cell. Since the Nth step size is small and the final verification voltages corresponding to the second memory cells during the Nth-level programming are large, for example, PV1’ < PV1, PV2’ < PV2, … PV14’ < PV;4. Therefore, the threshold voltage distribution interval (final threshold voltage distribution) of the second memory cells in the same state becomes smaller compared with the threshold voltage distribution interval (intermediate threshold voltage distribution) of the second memory cells after the first-level programming. The non-overlapping part between the threshold voltage distributions of adjacent states is called the read window. The smaller the threshold voltage distribution interval is, the larger the read window is, and during the data reading process, the probability of misjudgment is lower. During the Nth-level programming, the threshold distribution interval of the memory cells in the storage state P14 has become smaller, the read window between the storage state P15’ has become larger, and the storage state P15’ is already the highest storage state. Therefore, in this embodiment, the storage state P15’ is only programmed once, which reduces the programming time of the memory cells to a certain extent and improves the programming speed.

[0059] In another embodiment of the present application, the first memory cell performs threshold voltage verification during the Nth-level programming. After performing an operation such as a write operation on the memory, charges are injected into the charge storage layer of the floating gate structure. The more charges in the charge storage layer of the memory cell, the larger the threshold of the memory cell. By determining the magnitude of the threshold voltage of the memory cell, the storage state of the memory cell can be obtained, and thus the stored content can be obtained. However, as time goes by, the charges stored in the floating gate layer of some memory cells will gradually leak, resulting in a decrease in the amount of charges stored in the floating gate structure of the memory cell, which will cause an instantaneous threshold voltage shift (Instant voltage shift, abbreviated as IVS). This means that the threshold voltage increased by the programming operation may drop within a short time after the operation, resulting in a broadening of the threshold voltage distribution of the memory cell. In this way, the storage state may be misjudged during data reading, resulting in misreading. Therefore, in order to improve the errors that may be caused by the instantaneous threshold voltage shift, the first memory cell performs threshold voltage verification during the Nth-level programming, that is, the threshold voltage of the first memory cell is verified with the final verification voltage of the first memory cell.

[0060] According to a programming method of one embodiment of this application, since the first memory cell is programmed only once, the programming time of the memory cell is reduced to a certain extent, and the programming speed is improved. In the Nth level programming, verification is performed on the first memory cell, which to a certain extent mitigates errors that may be caused by instantaneous threshold voltage drift and improves the read accuracy of the memory.

[0061] In the programming method of this application embodiment, multi-level programming of a four-level cell (QLC) flash memory is used as an example to illustrate the memory programming method of this application. However, those skilled in the art will understand that the memory of this application may include all flash memories applicable to the programming method of this application.

[0062] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the invention. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for programming a memory, wherein each word line of the memory connects to multiple memory cells, characterized in that, The plurality of storage units includes a first storage unit and a second storage unit, wherein the first storage unit is the storage unit whose target storage state is the highest storage state; the method includes: Perform Level 1 programming to program the first memory cell to a threshold voltage greater than or equal to the final verification voltage of the first memory cell, and to program the second memory cell to a threshold voltage greater than or equal to the Level 1 intermediate verification voltage, wherein the Level 1 intermediate verification voltage is less than the final verification voltage of the second memory cell, and the threshold voltage of the first memory cell is greater than the threshold voltage of the second memory cell; and Perform level N programming to configure the threshold voltage of the second memory cell to be greater than or equal to the final verification voltage of the second memory cell, where N≥2.

2. The method according to claim 1, characterized in that, The final verification voltage of the first memory cell is greater than the final verification voltage of the second memory cell and the first-stage intermediate verification voltage.

3. The method according to claim 1, characterized in that, The Level 1 programming includes: A first programming voltage is applied to the second memory cell; Verify whether the threshold voltage of the second memory cell is greater than or equal to the first-stage intermediate verification voltage; In response to the threshold voltage of the second memory cell being less than the first-stage intermediate verification voltage, the first programming voltage, increased by the first step length, is reapplied to the second memory cell; and Continue performing the verification steps and the reapplied steps until the threshold voltage of the second memory cell is greater than or equal to the first-level intermediate verification voltage.

4. The method according to claim 3, characterized in that, The Nth level programming includes: A programming suppression voltage is applied to the first memory cell; Apply the Nth programming voltage to the second memory cell after the first stage of programming; Verify whether the threshold voltage of the second memory cell to which the Nth programming voltage has been applied is greater than or equal to the final verification voltage of the second memory cell; In response to the threshold voltage of the second memory cell being less than the final verification voltage of the second memory cell, the Nth programming voltage, increased by the Nth step, is reapplied to the second memory cell; and Continue performing the verification steps and reapplying steps until the threshold voltage of the second memory cell is greater than or equal to the final verification voltage of the second memory cell.

5. The method according to claim 4, characterized in that, The length of the Nth step is less than the length of the first step.

6. The method according to any one of claims 1 to 5, characterized in that, Before performing the Nth level programming, the first level programming is performed sequentially on the memory cells connected to each of the plurality of word lines of the memory.

7. A memory system, characterized in that, include: A memory cell array, comprising multiple word lines that are connected to multiple memory cells respectively; A voltage supply circuit is coupled to the memory cell array; as well as The controller is configured to control the voltage supply circuitry to apply a programming voltage and a verification voltage to each word line for multi-level programming of multiple memory cells connected to the same word line. Among them, the plurality of storage units connected by the same word line include a first storage unit and a second storage unit, wherein the first storage unit is the storage unit whose target storage state is the highest storage state; In Level 1 programming, the threshold voltage of the first memory cell is configured to be greater than or equal to the final verification voltage of the first memory cell, and the threshold voltage of the second memory cell is configured to be greater than or equal to the first-level intermediate verification voltage, wherein the first-level intermediate verification voltage of the memory cell is less than the final verification voltage of the second memory cell, and the threshold voltage of the first memory cell is greater than the threshold voltage of the second memory cell; and In the Nth level programming, the threshold voltage of the second memory cell is configured to be greater than or equal to the final verification voltage of the second memory cell, where N≥2.

8. The memory system according to claim 7, characterized in that, The final verification voltage of the first memory cell is greater than the final verification voltage of the second memory cell and the first-stage intermediate verification voltage.

9. The memory system according to claim 7, characterized in that, The Level 1 programming includes: A first programming voltage is applied to the second memory cell; Verify whether the threshold voltage of the second memory cell is greater than or equal to the first-stage intermediate verification voltage; In response to the threshold voltage of the second memory cell being less than the first-stage intermediate verification voltage, the first programming voltage, increased by the first step length, is reapplied to the second memory cell; and Continue performing the verification and reapplication steps until the threshold voltage of the second memory cell is greater than or equal to the first-stage intermediate verification voltage.

10. The memory system according to claim 9, characterized in that, The Nth level programming includes: A programming suppression voltage is applied to the first memory cell; Apply the Nth programming voltage to the second memory cell; Verify whether the threshold voltage of the second memory cell, which is in a different memory state after being subjected to the Nth programming voltage, is greater than or equal to the final verification voltage of the second memory cell; In response to the threshold voltage of the second memory cell in a different memory state being less than the final verification voltage of the second memory cell, the Nth programming voltage, increased by the Nth step, is reapplied to the second memory cell; and Continue performing the verification and reapplication steps until the threshold voltage of the second memory cell is greater than or equal to the final verification voltage of the corresponding second memory cell.

11. The memory system according to claim 10, characterized in that, The length of the Nth step is less than the length of the first step.

12. The memory system according to claim 7, characterized in that, The storage unit array includes any one of the following: single-level cell SLC flash memory storage unit array, multi-level cell MLC flash memory storage unit array, three-level cell TLC flash memory storage unit array, four-level cell QLC flash memory storage unit array, and five-level cell PLC flash memory storage unit array.

13. A method for programming a memory, characterized in that, The method includes: Multi-level programming is performed on the target storage cells connected by the select word line to make the target storage cells be in a corresponding target storage state; wherein, the target storage state includes a first storage state and a second storage state, the first storage state is the target storage state of the first storage cell in the target storage cells, and the second storage state is the target storage state of the second storage cell in the target storage cells; the first storage state and the second storage state are different; the first storage cell is the storage cell whose target storage state is the highest storage state; The execution of multi-level programming includes: Execute the first programming in the multi-level programming to make the threshold voltage of the first memory cell be in the final threshold voltage distribution of the first memory state; and make the threshold voltage of the second memory cell be in the intermediate threshold voltage distribution of the second memory state. Perform the second programming in the multi-level programming to make the threshold voltage of the second memory cell be in the final threshold voltage distribution of the second memory state.

14. The memory programming method according to claim 13, characterized in that, The verification voltage of the first storage state is greater than the verification voltage of the second storage state.

15. The memory programming method according to claim 14, characterized in that, Each of the storage units is configured to have 2 N One of the storage states stores N bits of data; N is greater than or equal to 1. The target storage state includes 2 N There are two storage states, the first storage state being the 2nd storage state. N The highest storage state among the storage states; the second storage state is the 2nd storage state. N Other storage states besides the highest storage state among the storage states.

16. The memory programming method according to claim 13, characterized in that, The range of the final threshold voltage distribution of the second storage state is narrower than the range of the intermediate threshold voltage distribution of the second storage state.

17. The memory programming method according to claim 14, characterized in that, The verification voltage of the second storage state includes an intermediate verification voltage and a final verification voltage; the final verification voltage of the second storage state is greater than the intermediate verification voltage of the second storage state; wherein, the intermediate verification voltage of the second storage state is the verification voltage of the second storage state in the first programming operation, and the final verification voltage of the second storage state is the verification voltage of the second storage state in the second programming operation.

18. The memory programming method according to claim 17, characterized in that, The execution of the first program in the multi-level programming includes: A first programming voltage is applied to the word line of the second memory cell; The second memory cell after the first programming voltage is applied is verified using the intermediate verification voltage of the second memory state. In response to the threshold voltage of the second memory cell being less than the intermediate verification voltage of the second memory state, a second programming voltage greater than the first programming voltage is applied to the word line of the second memory cell. The second memory cell after the second programming voltage is applied is verified using the intermediate verification voltage of the second memory state. Repeat the steps of applying programming voltage and verification operation until the threshold voltage of the second memory cell is greater than or equal to the intermediate verification voltage of the second memory state.

19. The memory programming method according to claim 18, characterized in that, The execution of the second programming step in the multi-level programming includes: A programming suppression voltage is applied to the first memory cell; A fifth programming voltage is applied to the word line of the second memory cell; The second memory cell after the fifth programming voltage is applied is verified using the final verification voltage of the second memory state. In response to the threshold voltage of the second memory cell being less than the final verification voltage of the second memory state, a sixth programming voltage greater than the fifth programming voltage is applied to the word line of the second memory cell. The second memory cell after the sixth programming voltage is applied is verified using the final verification voltage of the second memory state. Repeat the above steps until the threshold voltage of the second storage cell is greater than or equal to the final verification voltage of the second storage state.

20. The memory programming method according to claim 19, characterized in that, The difference between the sixth programming voltage and the fifth programming voltage is less than the difference between the second programming voltage and the first programming voltage.

21. The memory programming method according to claim 13, characterized in that, After the first programming step in the multi-level programming is executed, the second programming step in the multi-level programming is executed.

22. A memory system, characterized in that, include: A memory cell array, comprising multiple word lines that are connected to multiple memory cells respectively; A voltage supply circuit is coupled to the memory cell array; as well as A controller is configured to: control the voltage supply circuit to apply a programming voltage and a verification voltage to each word line to perform multi-level programming on the target memory cell connected to the selected word line, so that the target memory cell is in a corresponding target memory state; wherein the target memory state includes a first memory state and a second memory state, the first memory state being the target memory state of a first memory cell in the target memory cells, and the second memory state being the target memory state of a second memory cell in the target memory cells; the first memory state and the second memory state are different; the first memory cell is the memory cell whose target memory state is the highest memory state; The controller is specifically configured as follows: Execute the first programming in the multi-level programming to make the threshold voltage of the first memory cell be in the final threshold voltage distribution of the first memory state; and make the threshold voltage of the second memory cell be in the intermediate threshold voltage distribution of the second memory state. Perform the second programming in the multi-level programming to make the threshold voltage of the second memory cell be in the final threshold voltage distribution of the second memory state.

23. The memory system according to claim 22, characterized in that, The verification voltage of the first storage state is greater than the verification voltage of the second storage state.

24. The memory system according to claim 23, characterized in that, Each of the storage units is configured to have 2 N One of the storage states stores N bits of data; N is greater than or equal to 1. The target storage state includes 2 N There are two storage states, the first storage state being the 2nd storage state. N The highest storage state among the storage states; the second storage state is the 2nd storage state. N Other storage states besides the highest storage state among the storage states.

25. The memory system according to claim 23, characterized in that, Performing the first programming step in the multi-level programming includes: A first programming voltage is applied to the word line of the second memory cell; The second memory cell after the first programming voltage is applied is verified using the intermediate verification voltage of the second memory state. In response to the threshold voltage of the second memory cell being less than the intermediate verification voltage of the second memory state, a second programming voltage greater than the first programming voltage is applied to the word line of the second memory cell. The second memory cell after the second programming voltage is applied is verified using the intermediate verification voltage of the second memory state. Repeat the steps of applying programming voltage and verification operation until the threshold voltage of the second memory cell is greater than or equal to the intermediate verification voltage of the second memory state.

26. The memory system according to claim 25, characterized in that, Performing the second programming step in the multi-level programming includes: A programming suppression voltage is applied to the first memory cell; A fifth programming voltage is applied to the word line of the second memory cell; The second memory cell after the fifth programming voltage is applied is verified using the final verification voltage of the second memory state. In response to the threshold voltage of the second memory cell being less than the final verification voltage of the second memory state, a sixth programming voltage greater than the fifth programming voltage is applied to the second memory cell. The second memory cell after the sixth programming voltage is applied is verified using the final verification voltage of the second memory state. Repeat the above steps until the threshold voltage of the second storage cell is greater than or equal to the final verification voltage of the second storage state.

27. The memory system according to claim 26, characterized in that, The difference between the sixth programming voltage and the fifth programming voltage is less than the difference between the second programming voltage and the first programming voltage.

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