An antifuse address decode circuit, method of operation, and memory

Abstract

The embodiments of the present disclosure disclose an anti-fuse address decoding circuit, an operation method and a memory. The anti-fuse address decoding circuit comprises: a pre-decoding module configured to decode a programming address of an anti-fuse memory array and output a programming address pre-decoding signal; a level shifting module coupled to the pre-decoding module and configured to boost the programming address pre-decoding signal and output a boosted signal; and a programming address decoding module configured to receive the boosted signal, decode the boosted signal and output a programming address signal.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and in particular to an antifuse address decoding circuit, an operating method, and a memory. Background Technology

[0002] Anti-fuse-based programmable devices are widely used in various chips. For example, in DRAM chips, anti-fuse programmable memory can store the address information of defective memory cells, thereby enabling redundancy replacement (including row and column replacement). Furthermore, by programming the anti-fuse programmable memory, precise adjustments can be made to various internal parameters of the chip (such as voltage, current, and frequency). When the chip powers on, the information stored in the anti-fuse programmable memory is transmitted and latched in the required locations via built-in transmission circuitry.

[0003] However, current antifuse devices suffer from problems such as large chip area and high cost. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide an antifuse address decoding circuit, an operation method, and a memory.

[0005] According to a first aspect of the present disclosure, an antifuse address decoding circuit is provided, the antifuse address decoding circuit comprising:

[0006] The pre-decoding module is used to decode the programming address of the antifuse memory array and output the programming address pre-decoding signal;

[0007] A level shifting module, coupled to the pre-decoding module, is used to boost the programming address pre-decoding signal and output the boosted signal;

[0008] The programming address decoding module receives the boost signal, decodes the boost signal, and outputs the programming address signal.

[0009] In some embodiments, the level shifting module includes a first level shifting module and a second level shifting module;

[0010] The first level shifting module is coupled to the pre-decoding module and is used to boost the programming address pre-decoding signal and output a first boosted signal;

[0011] The second level shifting module is coupled to the first level shifting module and is used to boost the first boost signal and output a second boost signal.

[0012] In some embodiments, the voltage level of the first boost signal includes a logic low value and a logic high value, and the voltage level of the second boost signal includes a logic low value and a logic high value;

[0013] The logic low value of the first boost signal is less than the logic low value of the second boost signal; the logic high value of the first boost signal is less than the logic high value of the second boost signal.

[0014] In some embodiments, the voltage level of the programming address pre-decoding signal includes a logic low value and a logic high value;

[0015] The logic low and logic high values ​​of the voltage level of the programming address pre-decoding signal are 0V and 1.2V, respectively.

[0016] The logic low and logic high values ​​of the voltage level of the first boost signal are 0V and 3V, respectively;

[0017] The voltage level of the second boost signal has a logic low value range of 2.5V to 3V and a logic high value range of 5V to 6V.

[0018] In some embodiments, the programming address decoding module includes:

[0019] The word line address decoding module is coupled to the first level shifting module and is used to output the word line address signal according to the first boost signal;

[0020] The programming line address decoding module is coupled to the second level shifting module and is used to output the programming line address signal according to the second boost signal.

[0021] In some embodiments, the programming address includes row address information and subarray address information;

[0022] The first boost signal includes a first row address boost signal and a first subarray address boost signal; the second boost signal includes a second row address boost signal and a second subarray address boost signal.

[0023] In some embodiments, the word line address decoding module includes: a first NAND gate and a first inverter;

[0024] The input of the first NAND gate is connected to the first row address boost signal and the first subarray address boost signal, and the output is connected to the first inverter;

[0025] The first inverter outputs a word line address signal.

[0026] In some embodiments, the programming line address decoding module includes: a second NAND gate and a second inverter;

[0027] The input of the second NAND gate is connected to the second row address boost signal and the second subarray address boost signal, and the output is connected to the second inverter;

[0028] The output of the second inverter outputs the programming line address signal.

[0029] In some embodiments, the first NAND gate includes a first P-type transistor, a second P-type transistor, a first N-type transistor, and a second N-type transistor; the first inverter includes a third P-type transistor and a third N-type transistor;

[0030] The control terminals of the first P-type transistor and the first N-type transistor are controlled by the first subarray address boost signal, and the control terminals of the second P-type transistor and the second N-type transistor are controlled by the first row address boost signal.

[0031] The first P-type transistor, the second P-type transistor, and the first N-type transistor are connected to the first node. The control terminals of the third P-type transistor and the third N-type transistor intersect and are connected to the first node. The first terminals of the third P-type transistor and the third N-type transistor are connected and output a word line address signal.

[0032] The second terminals of the second N-type transistor and the third N-type transistor are connected to a first voltage signal; the second terminals of the first P-type transistor, the second P-type transistor, and the third P-type transistor are connected to a second voltage signal; wherein the first voltage signal is less than the second voltage signal.

[0033] In some embodiments, the voltage value of the first voltage signal is 0V, and the voltage value of the second voltage signal is 2.5V.

[0034] In some embodiments, the second NAND gate includes a fourth P-type transistor, a fifth P-type transistor, a fourth N-type transistor, and a fifth N-type transistor; the second inverter includes a sixth P-type transistor and a sixth N-type transistor;

[0035] The control terminals of the fourth P-type transistor and the fourth N-type transistor are controlled by the second subarray address boost signal, and the control terminals of the fifth P-type transistor and the fifth N-type transistor are controlled by the second row address boost signal;

[0036] The first terminals of the fourth P-type transistor, the fifth P-type transistor, and the fourth N-type transistor are connected to the second node. The control terminals of the sixth P-type transistor and the sixth N-type transistor intersect and are connected to the second node. The first terminals of the sixth P-type transistor and the sixth N-type transistor are connected and output a programming line address signal.

[0037] The second terminals of the fifth N-type transistor and the sixth N-type transistor are connected to a third voltage signal; the second terminals of the fourth P-type transistor, the fifth P-type transistor, and the sixth P-type transistor are connected to a fourth voltage signal; the third voltage signal is less than the fourth voltage signal.

[0038] In some embodiments, the voltage value of the third voltage signal ranges from 2.5V to 3V; the voltage value of the fourth voltage signal ranges from 5V to 6V.

[0039] According to a second aspect of the present disclosure, a memory is provided, including an antifuse address decoding circuit as described in any of the above embodiments.

[0040] According to a third aspect of the present disclosure, a method for operating an antifuse address decoding circuit is provided, comprising:

[0041] The pre-decoding module decodes the programming address of the input antifuse memory array and outputs a programming address pre-decoding signal;

[0042] The level shifting module boosts the programming address pre-decoding signal and outputs the boosted signal;

[0043] The programming address decoding module decodes the boost signal and outputs the programming address signal.

[0044] In some embodiments, the level shifting module boosts the programming address pre-decoding signal and outputs a boosted signal; including:

[0045] The first level shifting module boosts the programming address pre-decoding signal and outputs a first boosted signal;

[0046] The second level shifting module boosts the first boost signal and outputs a second boost signal.

[0047] In some embodiments,

[0048] The word line address decoding module in the programming address decoding module outputs a word line address signal according to the input first boost signal;

[0049] The programming line address decoding module in the programming address decoding module outputs the programming line address signal according to the input second boost signal.

[0050] In this embodiment of the disclosure, by first pre-decoding the antifuse address decoding circuit, then boosting it through a level shifting module, and then decoding it to obtain the address signal, the number of level shifting modules is reduced, thereby reducing the chip area and lowering the cost. Attached Figure Description

[0051] To more clearly illustrate the technical solutions in the embodiments of this disclosure or in the conventional art, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0052] Figure 1 This is a schematic diagram of the antifuse address decoding circuit provided in an embodiment of the present disclosure;

[0053] Figure 2 This is a schematic diagram of the structure of the antifuse memory provided in an embodiment of the present disclosure;

[0054] Figure 3a and Figure 3b A schematic diagram of the structure of a subarray of an antifuse memory array provided for embodiments of this disclosure;

[0055] Figure 3c The circuit diagram for a subarray;

[0056] Figure 4a A circuit diagram of the antifuse address decoding circuit provided in an embodiment of this disclosure;

[0057] Figure 4b This is a schematic diagram of the structure of the programming address decoding module provided in an embodiment of the present disclosure;

[0058] Figure 5a and Figure 5b A circuit diagram of a word line address decoding module provided in an embodiment of this disclosure;

[0059] Figure 6a and Figure 6b Circuit diagram of the programming line address decoding module provided in the embodiments of this disclosure;

[0060] Figure 7 A timing diagram of the antifuse address decoding circuit provided in an embodiment of this disclosure;

[0061] Figure 8 A flowchart illustrating the operation method of the antifuse address decoding circuit provided in this embodiment of the disclosure.

[0062] Explanation of reference numerals in the attached figures:

[0063] 10 - Pre-decoding module;

[0064] 21-First level shifting module; 22-Second level shifting module;

[0065] 30 - Programming row address decoding module; 31 - Second NAND gate; 32 - Second inverter; 311 - Fourth P-type transistor; 312 - Fifth P-type transistor; 313 - Fourth N-type transistor; 314 - Fifth N-type transistor; 321 - Sixth P-type transistor; 322 - Sixth N-type transistor;

[0066] 40 - Word line address decoding module; 41 - First NAND gate; 42 - First inverter; 411 - First P-type transistor; 412 - Second P-type transistor; 413 - First N-type transistor; 414 - Second N-type transistor; 421 - Third P-type transistor; 422 - Third N-type transistor;

[0067] 50 - Antifuse memory cell; 501 - First antifuse memory transistor; 502 - First transistor; 503 - Second transistor; 504 - Second antifuse memory transistor. Detailed Implementation

[0068] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0069] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0070] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0071] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0072] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0073] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0074] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0075] In some embodiments, in an antifuse memory array, because there are multiple word line address signals and multiple programming line address signals, if pre-decoding is not performed, then after decoding, multiple level shifting modules are needed to level-shift the word line address signals and programming line address signals. For example, if there are 256 word line address signals, a 16-to-256 decoder is needed, and the decoded 256-bit signal needs to be level-shifted by 256 level shifting modules. Thus, the large number of level shifting modules increases the chip area and cost.

[0076] Based on this, the present disclosure provides an antifuse address decoding circuit. Figure 1 This is a schematic diagram of the antifuse address decoding circuit provided in an embodiment of the present disclosure.

[0077] See Figure 1 The antifuse address decoding circuit includes: a pre-decoding module 10, used to decode the programming address of the antifuse memory array and output a programming address pre-decoding signal; a level shifting module, coupled to the pre-decoding module 10, used to boost the programming address pre-decoding signal and output a boosted signal; and a programming address decoding module, which receives the boosted signal, used to decode the boosted signal and output a programming address signal.

[0078] In this embodiment of the disclosure, by first pre-decoding the antifuse address decoding circuit, then boosting it through a level shifting module, and then decoding it to obtain the address signal, the number of level shifting modules is reduced, thereby reducing the chip area and lowering the cost.

[0079] Figure 2 This is a schematic diagram of the structure of the antifuse memory provided in an embodiment of the present disclosure.

[0080] like Figure 2 As shown, the antifuse memory includes an antifuse memory array (Cell Array), a row address latch and decoder module (XADD Latch & Decoder), a column address latch and decoder module (YADD Latch & Decoder), a high-voltage circuit module (Pump Circuit), a gating and amplifying module (Y-Gating & Sensing), and a logic control module (ControlLogic).

[0081] Specifically, the row address latching and decoding module is used to latch and decode the row address information of the antifuse memory array; the column address latching and decoding module is used to latch and decode the column address information of the antifuse memory array.

[0082] The high-voltage circuit module is used to generate high voltage to program the antifuse memory cells in the antifuse memory array. For example, in antifuse applications, high voltage is used to apply high voltage to the gate oxide layer of the antifuse memory cell to achieve programming.

[0083] The gating and amplification module is used to detect and judge the information stored in the antifuse memory cell in read mode. For example, the detection result of a programmed antifuse memory cell is "1", and the detection result of an unprogrammed antifuse memory cell is "0".

[0084] The logic control module is used to coordinate and control various operations, such as switching control between different modes, addressing control of antifuse memory cells, reading control of fuse status of antifuse memory cells, and enabling control of high-voltage circuits.

[0085] In one embodiment, the level shifting module includes a first level shifting module 21 and a second level shifting module 22; the first level shifting module 21 is coupled to the pre-decoding module 10 and is used to boost the programming address pre-decoding signal and output a first boosted signal; the second level shifting module 22 is coupled to the first level shifting module 21 and is used to boost the first boosted signal and output a second boosted signal.

[0086] In this embodiment of the disclosure, multiple word line address signals and programming line address signals can be obtained by only two level shifts after pre-decoding, reducing the number of level shifting modules and thus reducing the chip area.

[0087] In one embodiment, the voltage level of the first boost signal includes a logic low value and a logic high value, and the voltage level of the second boost signal includes a logic low value and a logic high value; the logic low value of the first boost signal is less than the logic low value of the second boost signal; and the logic high value of the first boost signal is less than the logic high value of the second boost signal.

[0088] In one embodiment, the voltage level of the programming address pre-decoding signal includes a logic low value and a logic high value; the logic low value and logic high value of the programming address pre-decoding signal are 0V and 1.2V, respectively; the logic low value and logic high value of the first boost signal are 0V and 3V, respectively; the logic low value of the second boost signal ranges from 2.5V to 3V, and the logic high value ranges from 5V to 6V.

[0089] The first level shifting module 21, coupled to the pre-decoding module 10, is used to boost the programming address pre-decoding signal and output a first boosted signal. This includes shifting the logic high value of the voltage level of the programming address pre-decoding signal to the logic high value of the voltage level of the first boosted signal. Specifically, the logic high value of the programming address pre-decoding signal (1.2V) is boosted to 3V, forming the logic high value of the voltage level of the first boosted signal, while the logic low value of the voltage level of the first boosted signal remains consistent with the logic low value of the programming address pre-decoding signal, which is 0V.

[0090] The second level shifting module 22, coupled to the first level shifting module 21, is used to boost the first boost signal and output a second boost signal. This includes shifting the logic low value of the voltage level of the first boost signal to the logic low value of the voltage level of the second boost signal, and shifting the logic high value of the voltage level of the first boost signal to the logic high value of the voltage level of the second boost signal. Specifically, the logic low value (0V) of the first boost signal is boosted to a range of 2.5V to 3V to form the logic low value of the voltage level of the second boost signal; the logic high value (3V) of the first boost signal is boosted to a range of 5V to 6V to form the logic high value of the voltage level of the second boost signal.

[0091] In one embodiment, the antifuse address decoding circuit includes a programming address decoding module comprising: a word line address decoding module 40, coupled to the first level shifting module 21, for outputting a word line address signal according to the first boost signal; and a programming line address decoding module 30, coupled to the second level shifting module 22, for outputting a programming line address signal according to the second boost signal.

[0092] In one embodiment, the programming address includes row address information and subarray address information;

[0093] The first boost signal includes a first row address boost signal and a first subarray address boost signal; the second boost signal includes a second row address boost signal and a second subarray address boost signal.

[0094] Specifically, Figure 3a and Figure 3b A schematic diagram of the structure of a subarray of an antifuse memory array provided for an embodiment of this disclosure.

[0095] In some embodiments, in addition to row addresses (XADD) and column addresses (YADD), the address information of the antifuse memory array may also include subarray addresses, such as YSEG, XSEG, and ZADD; wherein, as Figure 3aAs shown, YSEG information is used to distinguish different subarrays sharing the same word line (WL); such as Figure 3b As shown, XSEG information is used to distinguish different subarrays sharing the same bit line (BL); antifuse memory arrays can be divided into different parts as needed, for example, the cell size of different parts may be different, and ZADD can be used to distinguish the different parts.

[0096] Figure 3c The circuit diagram for a subarray is as follows: Figure 3c As shown, taking XSEG0 as an example, the subarray includes multiple antifuse memory cells 50. Each antifuse memory cell 50 includes a first antifuse memory transistor 501, a first transistor 502, a second transistor 503, and a second antifuse memory transistor 504. The first transistor 502 and the second transistor 503 are controlled by two adjacent word lines WLm (where m is the sequence number of the corresponding word line). The first antifuse memory transistor 501 and the second antifuse memory transistor 504 are controlled by two programming wires PGm (where m is the sequence number of the corresponding word line). The first terminal of the first antifuse memory transistor 501 is connected to the first terminal of the first transistor 502. The first terminal of the second antifuse memory transistor 504 is connected to the first terminal of the second transistor 503. The second terminal of the first transistor 502 is connected to the second terminal of the second transistor 503, and the second terminals of the first transistor 502 and the second transistor 503 are connected to the bit lines.

[0097] Specifically, in combination Figure 3c The subarray is a 16*16 antifuse memory array, meaning it includes 16 bit lines (BL) and 16 word lines (WL). Therefore, in Figure 3c In the embodiment shown, a total of 8 antifuse memory cells 50 are connected to each bit line.

[0098] It should be explained that the row address information is decoded and output as a programming row address pre-decoding signal. The programming row address pre-decoding signal is boosted for the first time to become a first row address boost signal. The first row address boost signal is boosted for the second time to become a second row address boost signal. Similarly, the subarray address information is decoded and output as a programming subarray address pre-decoding signal. The programming subarray address pre-decoding signal is boosted for the first time to become a first subarray address boost signal. The first subarray address boost signal is boosted for the second time to become a second subarray address boost signal.

[0099] Figure 4a A circuit diagram of the antifuse address decoding circuit provided in the embodiments of this disclosure is shown below. Figure 4aAs shown, the pre-decoding module 10 pre-decodes the 4-bit row address information (4-bit XADD) and the 4-bit subarray address information (4-bit XSEG). The pre-decoding module 10 is a 4-to-16 bit decoder. After pre-decoding, a 16-bit programming address pre-decoding signal is obtained, which is the programming row address pre-decoding signal (XADD<15:0>) and the programming subarray address pre-decoding signal (XSEG<15:0>). The first level shifting module 21 (Level The programmable address pre-decoding module 40 (XDEC_WL) boosts the programming address pre-decoding signal to obtain the first boosted signal, which is the first row address boosted signal (XADD_VPP<15:0>) and the first subarray address boosted signal (XSEG_VPP<15:0>). Then, the word line address decoding module 40 (XDEC_WL) can output the word line address signal (WL<255:0>) according to the first row address boosted signal and the first subarray address boosted signal. The second level shift module 22 (Levelshift2) can boost the first row address boosted signal and the first subarray address boosted signal to obtain the second row address boosted signal (XADD_VPG<15:0>) and the second subarray address boosted signal (XSEG_VPPG<15:0>). The programming row address decoding module 30 (XDEC_PG) can output the programming row address signal (PG<255:0>) according to the second row address boosted signal and the second subarray address boosted signal.

[0100] Figure 5a and Figure 5b The circuit diagram of the word line address decoding module provided in the embodiments of this disclosure is as follows: Figure 5a As shown, the word line address decoding module 40 includes: a first NAND gate 41 and a first inverter 42; the input of the first NAND gate 41 is connected to the first row address boost signal and the first subarray address boost signal, and the output is connected to the first inverter 42; the output of the first inverter 42 outputs the word line address signal. Specifically, for example, as... Figure 5a As shown, based on the 16-bit first row address boost signal (XADD_VPP<15:0>) and the 1-bit first subarray address boost signal (XSEG_VPP)... <0> This will give you a 16-bit word line address signal (WL<15:0>).

[0101] like Figure 5b As shown, the first NAND gate 41 includes a first P-type transistor 411, a second P-type transistor 412, a first N-type transistor 413, and a second N-type transistor 414; the first inverter 42 includes a third P-type transistor 421 and a third N-type transistor 422.

[0102] The control terminals of the first P-type transistor 411 and the first N-type transistor 413 are boosted by the first subarray address signal (XSEG_VPP). <n>The control terminals of the second P-type transistor 412 and the second N-type transistor 414 are controlled by the first row address boost signal (XADD_VPP). <n>)control;

[0103] The first terminals of the first P-type transistor 411, the second P-type transistor 412, and the first N-type transistor 413 are connected to the first node N1. The control terminals of the third P-type transistor 421 and the third N-type transistor 422 intersect and are connected to the first node N1. Furthermore, the first terminals of the third P-type transistor 421 and the third N-type transistor 422 are connected and output a word line address signal (WL). <n>);

[0104] The second terminal of the second N-type transistor 414 and the third N-type transistor 422 are connected to the first voltage signal VSS; the second terminal of the first P-type transistor 411, the second P-type transistor 412 and the third P-type transistor 421 are connected to the second voltage signal VFSWL; wherein, the first voltage signal VSS is less than the second voltage signal VFSWL.

[0105] See Figure 4b The word line address decoding module XDEC_WL can decode the 16-bit first row address boost signal (XADD_VPP<15:0>) and the 16-bit first subarray address boost signal (XSEG_VPP<15:0>) to obtain a 256-bit word line address signal (WL<256:0>). Specifically, taking one of the first subarray address boost signals as an example, for instance, a 16-bit first row address boost signal (XADD_VPP<15:0>) and a 1-bit first subarray address boost signal (XSEG_VPP<15:0>). <0> This will give you a 16-bit word line address signal (WL<15:0>).

[0106] In one embodiment, the voltage value of the first voltage signal VSS is 0V, and the voltage value of the second voltage signal VFSWL is 2.5V.

[0107] Figure 6a and Figure 6b The circuit diagram of the programming line address decoding module provided in the embodiments of this disclosure is as follows: Figure 6a As shown, the programming row address decoding module 30 includes: a second NAND gate 31 and a second inverter 32; the input of the second NAND gate 31 is connected to the second row address boost signal and the second subarray address boost signal, and the output is connected to the second inverter 32; the output of the second inverter 32 outputs the programming row address signal. Specifically, for example, as... Figure 6a As shown, based on the 16-bit second row address boost signal (XADD_VPG<15:0>) and the 1-bit second subarray address boost signal (XSEG_VPG)... <0> This will give you a 16-bit programming line address signal (PG<15:0>).

[0108] like Figure 6b As shown, the second NAND gate 31 includes a fourth P-type transistor 311, a fifth P-type transistor 312, a fourth N-type transistor 313, and a fifth N-type transistor 314; the second inverter 32 includes a sixth P-type transistor 321 and a sixth N-type transistor 322.

[0109] The control terminals of the fourth P-type transistor 311 and the fourth N-type transistor 313 are boosted by the second subarray address signal (XSEG_VPG). <n>The control terminals of the fifth P-type transistor 312 and the fifth N-type transistor 314 are controlled by the second row address boost signal XADD_VPG. <n>control;

[0110] The first terminals of the fourth P-type transistor 311, the fifth P-type transistor 312, and the fourth N-type transistor 313 are connected to the second node N2. The control terminals of the sixth P-type transistor 321 and the sixth N-type transistor 322 intersect and are connected to the second node N2. The first terminals of the sixth P-type transistor 321 and the sixth N-type transistor 322 are connected and output a programming line address signal (PG). <n>);

[0111] The second terminals of the fifth N-type transistor 314 and the sixth N-type transistor 322 are connected to the third voltage signal VPGL; the second terminals of the fourth P-type transistor 311, the fifth P-type transistor 312 and the sixth P-type transistor 321 are connected to the fourth voltage signal VPGH; the third voltage signal VPGL is less than the fourth voltage signal VPGH.

[0112] See Figure 4b The programming row address decoding module XDEC_PG can decode the 16-bit second row address boost signal (XADD_VPG<15:0>) and the 16-bit second subarray address boost signal (XSEG_VPG<15:0>) to obtain a 256-bit programming row address signal (PG<256:0>). Specifically, taking one of the second subarray address boost signals as an example, for instance, a 16-bit second row address boost signal (XADD_VPG<15:0>) and a 1-bit second subarray address boost signal (XSEG_VPG). <0> This will give you a 16-bit programming line address signal (PG<15:0>).

[0113] In one embodiment, the voltage value of the third voltage signal VPGL is in the range of 2.5V to 3V; and the voltage value of the fourth voltage signal VPGH is in the range of 5V to 6V.

[0114] The fourth voltage signal VPGH has a voltage range of 5V to 6V, and the third voltage signal VPGL has a voltage range of 2.5V to 3.0V. To avoid damage to the device from the high voltage of VPGH, VPGH should be powered on only after the VPGL voltage has stabilized. Figure 7 As shown, after VPGL stabilizes and the programming start (Blown_En) signal becomes valid, VPGH is powered on. This can prevent the devices in the XDEC_PG module from being damaged by high voltage.

[0115] Because device withstand voltage is relative to voltage, if the difference between the high and low voltages of a circuit does not exceed a safe value, the device will not break down. In the embodiments of this disclosure, if the third voltage signal VPGL is activated after the fourth voltage signal VPGH, and VPGL is activated relative to the 6.0V VPGH, then the maximum voltage difference in the circuit will reach 6.0V, causing the circuit to break down and fail. If VPGL is activated first, and then VPGH is activated later, then even if the VPGH voltage is very high, the voltage difference between it and VPGL is only 3.0V, and the device will not break down and fail.

[0116] This disclosure also provides an operation method for an antifuse address decoding circuit; please refer to the appendix for details. Figure 8 As shown in the figure, the method includes the following steps:

[0117] Step 801: The pre-decoding module decodes the programming address of the input antifuse memory array and outputs the programming address pre-decoding signal;

[0118] Step 802: The level shifting module boosts the programming address pre-decoding signal and outputs the boosted signal;

[0119] Step 803: The programming address decoding module decodes the boost signal and outputs the programming address signal.

[0120] The operation method of the antifuse address decoding circuit provided in this disclosure will be further described in detail below with reference to specific embodiments.

[0121] See Figure 1 First, step 801 is executed, where the pre-decoding module 10 decodes the programming address of the input antifuse memory array and outputs the programming address pre-decoding signal.

[0122] Next, step 802 is executed, whereby the level shifting module boosts the programming address pre-decoding signal and outputs the boosted signal.

[0123] In one embodiment, the level shifting module boosts the programming address pre-decoding signal and outputs a boosted signal; this includes: a first level shifting module 21 boosting the programming address pre-decoding signal and outputting a first boosted signal; and a second level shifting module 22 boosting the first boosted signal and outputting a second boosted signal.

[0124] In this embodiment, multiple word line address signals and programming line address signals can be obtained through only two level shifts after pre-decoding, reducing the number of level shifting modules and thus reducing the chip area.

[0125] In one embodiment, the voltage level of the first boost signal includes a logic low value and a logic high value, and the voltage level of the second boost signal includes a logic low value and a logic high value; the logic low value of the first boost signal is less than the logic low value of the second boost signal; and the logic high value of the first boost signal is less than the logic high value of the second boost signal.

[0126] In one embodiment, the voltage level of the programming address pre-decoding signal includes a logic low value and a logic high value; the logic low value and logic high value of the programming address pre-decoding signal are 0V and 1.2V, respectively; the logic low value and logic high value of the first boost signal are 0V and 3V, respectively; the logic low value of the second boost signal ranges from 2.5V to 3V, and the logic high value ranges from 5V to 6V.

[0127] The first level shifting module 21 boosts the programming address pre-decoding signal and outputs a first boosted signal, including shifting the logic high value of the voltage level of the programming address pre-decoding signal to the logic high value of the voltage level of the first boosted signal. Specifically, the logic high value of the programming address pre-decoding signal (1.2V) is boosted to 3V, forming the logic high value of the voltage level of the first boosted signal, while the logic low value of the voltage level of the first boosted signal remains consistent with the logic low value of the programming address pre-decoding signal, which is 0V.

[0128] The second level shifting module 22 boosts the first boost signal and outputs a second boost signal, including: shifting the logic low value of the voltage level of the first boost signal to the logic low value of the voltage level of the second boost signal, and shifting the logic high value of the voltage level of the first boost signal to the logic high value of the voltage level of the second boost signal. Specifically, the logic low value of the first boost signal (0V) is boosted to a range of 2.5V to 3V to form the logic low value of the voltage level of the second boost signal; the logic high value of the first boost signal (3V) is boosted to a range of 5V to 6V to form the logic high value of the voltage level of the second boost signal.

[0129] Next, step 803 is executed, where the programming address decoding module decodes the boost signal and outputs the programming address signal.

[0130] In one embodiment, the word line address decoding module 40 in the programming address decoding module outputs a word line address signal according to the input first boost signal;

[0131] The programming line address decoding module 30 in the programming address decoding module outputs the programming line address signal according to the input second boost signal.

[0132] In one embodiment, the specific operation process of the antifuse address decoding circuit is as follows: Figure 4a As shown, the pre-decoding module 10 pre-decodes the 4-bit row address information (4-bit XADD) and the 4-bit subarray address information (4-bit XSEG). The pre-decoding module 10 is a 4-to-16 bit decoder. After pre-decoding, a 16-bit programming address pre-decoding signal is obtained, which is the programming row address pre-decoding signal (XADD<15:0>) and the programming subarray address pre-decoding signal (XSEG<15:0>). The first level shifting module 21 (Level The programming address pre-decoding module 40 (XDEC_WL) boosts the signal to obtain the first boosted signal, which is the first row address boosted signal (XADD_VPP<15:0>) and the first subarray address boosted signal (XSEG_VPP<15:0>). Then, the word line address decoding module 40 (XDEC_WL) outputs the word line address signal (WL<255:0>) based on the first row address boosted signal and the first subarray address boosted signal. The second level shift module 22 (Level shift2) boosts the first row address boosted signal and the first subarray address boosted signal to obtain the second row address boosted signal (XADD_VPG<15:0>) and the second subarray address boosted signal (XSEG_VPPG<15:0>). The programming row address decoding module 30 (XDEC_PG) outputs the programming row address signal (PG<255:0>) based on the second row address boosted signal and the second subarray address boosted signal.

[0133] This disclosure also provides a memory including an antifuse address decoding circuit as described in any of the above embodiments.

[0134] The above description is merely a preferred embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.< / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. An antifuse address decoding circuit, characterized in that, The antifuse address decoding circuit includes: The pre-decoding module is used to decode the programming address of the antifuse memory array and output the programming address pre-decoding signal; A level shifting module, coupled to the pre-decoding module, is used to boost the programming address pre-decoding signal and output the boosted signal; The programming address decoding module receives the boost signal, decodes the boost signal, and outputs the programming address signal. The level shifting module includes a first level shifting module and a second level shifting module; The first level shifting module is coupled to the pre-decoding module and is used to boost the programming address pre-decoding signal and output a first boosted signal; The second level shift module is coupled to the first level shift module and is used to boost the first boost signal and output a second boost signal; The programming address decoding module includes: The word line address decoding module is coupled to the first level shifting module and is used to output the word line address signal according to the first boost signal; The programming line address decoding module is coupled to the second level shifting module and is used to output the programming line address signal according to the second boost signal.

2. The circuit according to claim 1, characterized in that, The voltage level of the first boost signal includes a logic low value and a logic high value, and the voltage level of the second boost signal includes a logic low value and a logic high value; The logic low value of the first boost signal is less than the logic low value of the second boost signal; the logic high value of the first boost signal is less than the logic high value of the second boost signal.

3. The circuit according to claim 2, characterized in that, The voltage levels of the programming address pre-decoding signal include logic low and logic high values; The logic low and logic high values ​​of the voltage level of the programming address pre-decoding signal are 0V and 1.2V, respectively. The logic low and logic high values ​​of the voltage level of the first boost signal are 0V and 3V, respectively; The logic low value of the second boost signal ranges from 2.5V to 3V, and the logic high value ranges from 5V to 6V.

4. The circuit according to claim 1, characterized in that, The programming address includes row address information and subarray address information; The first boost signal includes a first row address boost signal and a first subarray address boost signal; the second boost signal includes a second row address boost signal and a second subarray address boost signal.

5. The circuit according to claim 4, characterized in that, The word line address decoding module includes: a first NAND gate and a first inverter; The input of the first NAND gate is connected to the first row address boost signal and the first subarray address boost signal, and the output is connected to the first inverter; The first inverter outputs a word line address signal.

6. The circuit according to claim 4, characterized in that, The programming line address decoding module includes: a second NAND gate and a second inverter; The input of the second NAND gate is connected to the second row address boost signal and the second subarray address boost signal, and the output is connected to the second inverter; The output of the second inverter outputs the programming line address signal.

7. The circuit according to claim 5, characterized in that, The first NAND gate includes a first P-type transistor, a second P-type transistor, a first N-type transistor, and a second N-type transistor; the first inverter includes a third P-type transistor and a third N-type transistor. The control terminals of the first P-type transistor and the first N-type transistor are controlled by the first subarray address boost signal, and the control terminals of the second P-type transistor and the second N-type transistor are controlled by the first row address boost signal. The first P-type transistor, the second P-type transistor, and the first N-type transistor are connected to the first node. The control terminals of the third P-type transistor and the third N-type transistor intersect and are connected to the first node. The first terminals of the third P-type transistor and the third N-type transistor are connected and output a word line address signal. The second terminals of the second N-type transistor and the third N-type transistor are connected to a first voltage signal; the second terminals of the first P-type transistor, the second P-type transistor, and the third P-type transistor are connected to a second voltage signal; wherein the first voltage signal is less than the second voltage signal.

8. The circuit according to claim 7, characterized in that, The voltage value of the first voltage signal is 0V, and the voltage value of the second voltage signal is 2.5V.

9. The circuit according to claim 6, characterized in that, The second NAND gate includes a fourth P-type transistor, a fifth P-type transistor, a fourth N-type transistor, and a fifth N-type transistor; the second inverter includes a sixth P-type transistor and a sixth N-type transistor; The control terminals of the fourth P-type transistor and the fourth N-type transistor are controlled by the second subarray address boost signal, and the control terminals of the fifth P-type transistor and the fifth N-type transistor are controlled by the second row address boost signal; The first terminals of the fourth P-type transistor, the fifth P-type transistor, and the fourth N-type transistor are connected to the second node. The control terminals of the sixth P-type transistor and the sixth N-type transistor intersect and are connected to the second node. The first terminals of the sixth P-type transistor and the sixth N-type transistor are connected and output a programming line address signal. The second terminals of the fifth N-type transistor and the sixth N-type transistor are connected to a third voltage signal; the second terminals of the fourth P-type transistor, the fifth P-type transistor, and the sixth P-type transistor are connected to a fourth voltage signal; the third voltage signal is less than the fourth voltage signal.

10. The circuit according to claim 9, characterized in that, The voltage value of the third voltage signal ranges from 2.5V to 3V; the voltage value of the fourth voltage signal ranges from 5V to 6V.

11. A memory, characterized in that, Includes the antifuse address decoding circuit as described in any one of claims 1-10.

12. An operation method for an antifuse address decoding circuit, characterized in that, include: The pre-decoding module decodes the programming address of the input antifuse memory array and outputs a programming address pre-decoding signal; The level shifting module boosts the programming address pre-decoding signal and outputs the boosted signal; The programming address decoding module decodes the boost signal and outputs the programming address signal; The level shifting module boosts the programming address pre-decoding signal and outputs a boosted signal; including: The first level shifting module boosts the programming address pre-decoding signal and outputs a first boosted signal; The second level shifting module boosts the first boost signal and outputs a second boost signal; The word line address decoding module in the programming address decoding module outputs a word line address signal according to the input first boost signal; The programming line address decoding module in the programming address decoding module outputs the programming line address signal according to the input second boost signal.

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