Method for manufacturing a semiconductor structure and semiconductor structure

Abstract

The present disclosure provides a semiconductor structure manufacturing method and a semiconductor structure, and relates to the technical field of semiconductors. The semiconductor structure manufacturing method comprises the following steps: providing a substrate, the substrate is provided with a plurality of discrete bit line structures, an initial contact layer is arranged between adjacent bit line structures, and the initial contact layer has a gap; removing part of the initial contact layer to open the gap, the remaining initial contact layer forms a contact layer, and the remaining gap forms a first gap; and forming a filling layer, the filling layer fills the first gap and covers the top surface of the contact layer. The present disclosure fills the first gap with the filling layer, eliminates the gap in the contact layer, thereby effectively improving the resistance of the contact layer and improving the electrical properties and yield of the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a method for fabricating a semiconductor structure and the semiconductor structure itself. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory that allows for high-speed, random writing and reading of data, and is widely used in data storage devices. DRAM consists of multiple repeatedly arranged memory cells, each including a transistor and a capacitor. The capacitor is connected to the source and drain of the transistor via a capacitor contact area or capacitor contact structure.

[0003] As DRAM manufacturing technology continues to advance, the transistors and capacitors in the arrayed memory cells of DRAM are becoming increasingly dense. This makes the manufacturing of contact holes used to form contact structures more and more difficult, resulting in gaps forming inside the contact structures (such as capacitor contact structures) during the formation process. These gaps increase the resistance of the contact structure, reducing the electrical properties and yield of the semiconductor structure. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0005] This disclosure provides a method for fabricating a semiconductor structure and the semiconductor structure itself.

[0006] The first aspect of this disclosure provides a method for fabricating a semiconductor structure, the method comprising:

[0007] A substrate is provided, on which a plurality of discretely arranged bit line structures are provided, and an initial contact layer is provided between adjacent bit line structures, and a gap is provided in the initial contact layer;

[0008] A portion of the initial contact layer is removed to open the gap, the remaining initial contact layer forms a contact layer, and the remaining gap forms a first gap;

[0009] A filling layer is formed, which fills the first gap and covers the top surface of the contact layer.

[0010] According to some embodiments of this disclosure, a filling layer is formed that fills the first gap and covers the top surface of the contact layer, including:

[0011] A first intermediate filling layer is formed in the first gap, and the top surface of the first intermediate filling layer is flush with the top surface of the contact layer.

[0012] The first intermediate filling layer is processed to form the first filling layer;

[0013] A second initial fill layer is formed on the first fill layer. The second initial fill layer includes a first segment and a second segment that are alternately connected in sequence. The first segment covers the top surface of the contact layer, and the second segment wraps the bit line structure.

[0014] The first segment is processed and the second segment is removed. The processed first segment forms a second filling layer, and the first filling layer and the second filling layer form the filling layer.

[0015] According to some embodiments of this disclosure, the material of the first filling layer and the material of the second filling layer are the same.

[0016] According to some embodiments of this disclosure, a first intermediate filling layer is formed within the first gap, including:

[0017] A first initial filling layer is formed within the first gap, the first initial filling layer extends outside the first gap, the first initial filling layer covers the top surface of the contact layer and wraps the bit line structure;

[0018] The first initial fill layer that wraps around the bit line structure and covers the top surface of the contact layer is removed, and the remaining first initial fill layer forms the first intermediate fill layer.

[0019] According to some embodiments of this disclosure, the thickness of the first initial filling layer is less than 5 nm.

[0020] According to some embodiments of this disclosure, removing the first initial filler layer that encloses the bit line structure and covers the top surface of the contact layer includes:

[0021] A first dielectric layer is formed on the first initial fill layer;

[0022] Remove the first dielectric layer, the first initial fill layer that encloses the bit line structure, and the first initial fill layer that covers the top surface of the contact layer.

[0023] According to some embodiments of this disclosure, the first intermediate filling layer is processed to form the first filling layer, including:

[0024] The first intermediate filler layer is subjected to high-temperature tempering to form the first filler layer;

[0025] The first segment is processed to form a second filling layer, including:

[0026] The first segment is subjected to high-temperature tempering to form the second filler layer.

[0027] According to some embodiments of this disclosure, a filling layer is formed that fills the first gap and covers the top surface of the contact layer, including:

[0028] An initial fill layer is formed on the contact layer, the initial fill layer filling the first gap and covering the top surface of the contact layer;

[0029] The initial fill layer is processed to form the fill layer.

[0030] According to some embodiments of this disclosure, a substrate is provided, on which a plurality of discretely arranged bit line structures are provided, and an initial contact layer is provided between adjacent bit line structures, the initial contact layer having a gap, including:

[0031] A plurality of spaced bit lines are formed on the substrate;

[0032] An isolation sidewall is formed to enclose the outer peripheral surface of the bit line, and a contact hole is formed between adjacent isolation sidewalls;

[0033] An initial contact layer is formed within the contact hole, and the top surface of the initial contact layer is flush with the top surface of the isolation sidewall.

[0034] According to some embodiments of this disclosure, a plurality of spaced bit lines are formed on the substrate, including:

[0035] An initial bit line contact layer, an initial conductive layer, and a second initial dielectric layer are sequentially formed on the substrate.

[0036] A mask layer with a mask pattern is formed on the second initial dielectric layer. A portion of the second initial dielectric layer, a portion of the initial conductive layer, and a portion of the initial bit line contact layer are removed according to the mask pattern. The remaining second initial dielectric layer forms a second dielectric layer, the remaining initial conductive layer forms a conductive layer, and the remaining initial bit line contact layer forms a bit line contact layer.

[0037] The bit line is formed by the second dielectric layer, the conductive layer, and the bit line contact layer.

[0038] According to some embodiments of this disclosure, forming an isolation sidewall that encloses the outer peripheral surface of the bit line includes:

[0039] A first sidewall layer, a second sidewall layer, and a third sidewall layer are sequentially formed on the outer periphery of the position line.

[0040] A second aspect of this disclosure provides a semiconductor structure, comprising:

[0041] A substrate having a plurality of discretely arranged bitline structures;

[0042] A contact structure comprising a contact layer and a filler layer, the contact layer being located between adjacent bit line structures, wherein the contact layer has a first gap, the opening of the first gap being exposed to the outside, and the filler layer filling the first gap and covering the top surface of the contact layer.

[0043] According to some embodiments of this disclosure, the filling layer includes a first filling layer and a second filling layer, the first filling layer being located within the first gap, and the second filling layer covering the top surface of the contact layer and the first filling layer.

[0044] According to some embodiments of this disclosure, the first filler layer and the second filler layer are made of the same material.

[0045] According to some embodiments of this disclosure, the aspect ratio between adjacent bitline structures is greater than 2.

[0046] According to some embodiments of this disclosure, the bit line structure includes bit lines and isolation sidewalls;

[0047] There are multiple bit lines, and the multiple bit lines are spaced apart on the substrate;

[0048] The isolation sidewall encloses the outer periphery of the bit line.

[0049] According to some embodiments of this disclosure, the bit line includes a bit line contact layer, a conductive layer, and a second dielectric layer stacked together, wherein the bit line contact layer is connected to the substrate.

[0050] According to some embodiments of this disclosure, the isolation sidewall includes a first sidewall layer, a second sidewall layer, and a third sidewall layer stacked together, wherein the first sidewall layer wraps around the outer peripheral surface of the bit line.

[0051] In the semiconductor structure fabrication method and semiconductor structure provided in this disclosure, there are gaps in the formed initial contact layer. After removing part of the initial contact layer, the gaps are opened, and the retained initial contact layer forms a contact layer, while the retained gaps form a first gap. Then, the entire first gap is filled with a filling layer to eliminate the gaps in the contact layer, thereby effectively improving the resistance of the contact layer and improving the electrical properties and yield of the semiconductor structure.

[0052] After reading and understanding the accompanying diagrams and detailed descriptions, other aspects can be understood. Attached Figure Description

[0053] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of these embodiments. In these drawings, similar reference numerals are used to denote similar elements. The drawings described below are some embodiments of the present disclosure, but not all embodiments. Other drawings will be readily available to those skilled in the art based on these drawings without inventive effort.

[0054] Figure 1 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0055] Figure 2 This is a schematic diagram illustrating the formation of a mask layer in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0056] Figure 3 This is a schematic diagram illustrating the formation of bit lines in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0057] Figure 4 This is a schematic diagram illustrating the formation of an isolation sidewall in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0058] Figure 5 This is a schematic diagram illustrating the formation of an initial contact layer in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0059] Figure 6 This is a schematic diagram illustrating the formation of a contact layer in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0060] Figure 7 This is a schematic diagram illustrating the formation of a first initial filling layer in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0061] Figure 8 This is a schematic diagram illustrating the formation of a first dielectric layer in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0062] Figure 9 This is a schematic diagram illustrating the removal of a portion of the first initial filler layer in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0063] Figure 10 This is a schematic diagram illustrating the formation of a first intermediate filling layer in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0064] Figure 11 This is a schematic diagram illustrating the formation of a second initial filling layer in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0065] Figure 12 This is a schematic diagram illustrating the formation of a filling layer in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0066] Figure label:

[0067] 10. Substrate; 20. Bitline structure;

[0068] 21. Position line; 22. Isolation sidewall;

[0069] 23. Groove; 24. Mask layer;

[0070] 30. Contact hole; 40. Contact layer;

[0071] 41. Initial contact layer; 50. Gap;

[0072] 51. First gap; 60. Filling layer;

[0073] 61. First filler layer; 62. First intermediate filler layer;

[0074] 63. First initial fill layer; 64. Second initial fill layer;

[0075] 65. Second filler layer; 70. Contact structure;

[0076] 80. First dielectric layer; 211. Bit line contact layer;

[0077] 212. Conductive layer; 213. Second dielectric layer;

[0078] 221. First side wall layer; 222. Second side wall layer;

[0079] 223. Third side wall layer; 641. First section;

[0080] 624, Second segment; 211a, Initial bit line contact layer;

[0081] 212a, initial conductive layer; 213a, second initial dielectric layer. Detailed Implementation

[0082] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions in the disclosed embodiments will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0083] Dynamic Random Access Memory (DRAM) is a semiconductor memory that allows for high-speed, random writing and reading of data, and is widely used in data storage devices. DRAM consists of multiple repeatedly arranged memory cells, each including a transistor and a capacitor. The capacitor is connected to the source and drain of the transistor via a capacitor contact area or capacitor contact structure.

[0084] As DRAM manufacturing technology continues to advance, the transistors and capacitors in the arrayed memory cells of DRAM are becoming increasingly dense. This makes the manufacturing of contact holes used to form contact structures more and more difficult, and the large depth-to-width ratio of the contact holes causes gaps to form inside the contact structures (such as capacitor contact structures) when forming contact structures within the contact holes. These gaps increase the resistance of the contact structure, reducing the electrical properties and yield of the semiconductor structure.

[0085] To eliminate the aforementioned gaps, one approach in related technologies is to reduce the boron doping concentration; however, this method has limited effectiveness in improving the resistance of the contact structure. Another approach involves depositing silicon nitride or similar materials within the gaps and forming silicides on the contact structure. This, combined with the silicon nitride, reduces the resistance of the contact structure. However, in this method, the silicon nitride cannot completely fill the gap, thus leaving gaps in the contact structure and reducing the electrical properties and yield of the semiconductor structure.

[0086] To address one of the aforementioned technical problems, this disclosure provides a method for fabricating a semiconductor structure in exemplary embodiments, which will be described below in conjunction with... Figures 1-11 The methods for fabricating semiconductor structures are introduced.

[0087] This embodiment does not limit the semiconductor structure. The following description will take the capacitor contact in dynamic random access memory (DRAM) as an example of the semiconductor structure, but this embodiment is not limited to this.

[0088] like Figure 1 As shown, an exemplary embodiment of this disclosure provides a method for fabricating a semiconductor structure, comprising the following steps:

[0089] Step S100: Provide a substrate, on which a plurality of discrete bit line structures are provided, with an initial contact layer between adjacent bit line structures, and a gap within the initial contact layer.

[0090] Step S200: Remove part of the initial contact layer to open the gap, the remaining initial contact layer forms the contact layer, and the remaining gap forms the first gap.

[0091] Step S300: Form a filling layer that fills the first gap and covers the top surface of the contact layer.

[0092] Reference Figure 2 As shown, in step S100, the substrate 10 serves as a support component for dynamic random access memory (DRAM), supporting other components disposed thereon. The substrate 10 can be made of a semiconductor material, which can be one or more of silicon, germanium, silicon-germanium compounds, and silicon-carbide compounds. In this embodiment, silicon is used as the substrate 10. The use of silicon as the substrate 10 in this embodiment is for the convenience of those skilled in the art in understanding the subsequent formation method and does not constitute a limitation. In practical applications, a suitable substrate material can be selected according to requirements.

[0093] Reference Figure 4 As shown, multiple discrete bit line structures 20 are provided on the substrate 10, and contact holes 30 are formed between adjacent bit line structures 20. Due to the continuous miniaturization of the manufacturing process, in the direction perpendicular to the top surface of the substrate 10, with the height of the bit line structure 20 remaining unchanged, the distance between adjacent bit line structures 20 becomes smaller, that is, the lateral dimension of the contact hole 30 decreases, resulting in an increase in the aspect ratio of the contact hole 30. This causes a gap 50 to be formed within the initial contact layer 41 when the initial contact layer 41 is deposited within the contact hole 30 (see reference). Figure 5 ).

[0094] like Figure 6 As shown, in step S200, an etching process can be used to remove part of the initial contact layer 41 to open the gap 50, exposing the internal space of the gap 50. The retained initial contact layer 41 forms the contact layer 40, and the retained gap 50 forms the first gap 51. In one example, using... Figure 6 Based on the orientation shown in the figure, when opening the gap 50, the initial contact layer 41 forming the upper half of the gap 50 can be removed to expose the lower half of the gap 50, forming the first gap 51.

[0095] like Figure 12 As shown, in step S300, a filling layer 60 can be formed in the first gap 51 using a deposition process. The filling layer 60 fills the entire first gap 51 and covers the top surface of the contact layer 40. After the filling layer 60 is formed, the filling layer 60 and the contact layer 40 form a contact structure 70.

[0096] The contact structure 70 can be disposed on at least one of the source / drain regions and the gate structure of the active region within the substrate 10, serving as an electrode lead-out structure to apply operating voltage and lead out operating current. For example, when the contact structure 70 is disposed on the source region, it serves as a capacitor contact structure connected to a capacitor structure; or, when the contact structure 70 is disposed on the drain region, it serves as a bit line contact structure connected to a bit line; or, when the contact structure 70 is disposed on the gate structure, it is used for connection between the gate structure and structures such as chip pads, facilitating external voltage application to the chip.

[0097] In this embodiment, the first gap is filled by a filling layer to eliminate the gap in the contact layer, thereby effectively improving the resistance of the contact layer and improving the electrical properties and yield of the semiconductor structure.

[0098] According to an exemplary embodiment, this embodiment is a further explanation of step S100 above.

[0099] In forming multiple discrete bitline structures on a substrate, the following methods can be used:

[0100] like Figure 3 As shown, multiple spaced bit lines 21 are formed on the substrate 10 using atomic layer deposition, physical vapor deposition, or chemical vapor deposition processes, and grooves 23 are formed between adjacent bit lines 21.

[0101] Then, as Figure 4 As shown, isolation sidewalls 22 are formed on the sidewalls of the groove 23 and the top surface of the bit line 21 using atomic layer deposition, physical vapor deposition, or chemical vapor deposition processes. After formation, the isolation sidewalls 22 cover the sidewalls and top surface of the bit line 21, i.e., the isolation sidewalls 22 enclose the outer periphery of the bit line 21. Contact holes 30 are formed between the isolation sidewalls 22 on the inner walls of both sides of the groove 23.

[0102] Continue to refer to Figure 5 As shown, an initial contact layer 41 is formed within the contact hole 30 using atomic layer deposition, physical vapor deposition, chemical vapor deposition, or other deposition processes. The top surface of the initial contact layer 41 is flush with the top surface of the isolation sidewall 22. The material of the initial contact layer 41 may include, but is not limited to, polycrystalline silicon, tungsten metal, or titanium nitride.

[0103] As manufacturing processes continue to shrink, the distance between adjacent bit line structures 20 tends to decrease in the direction perpendicular to the top surface of the substrate 10, while the height of the bit line structure 20 remains constant. This leads to an increase in the aspect ratio of the contact hole 30. For example, when the aspect ratio of the contact hole 30 is greater than 2:1, the top of the initial contact layer 41 will be sealed prematurely when depositing the initial contact layer 41 within the contact hole 30. Therefore, a gap 50 will appear within the formed initial contact layer 41, and the top surface of the gap 50 will be lower than the top surface of the bit line structure 20. In the semiconductor structure manufacturing process, the presence of the gap 50 is detrimental to improving the conductivity of the semiconductor structure. Therefore, the gap 50 can be removed in subsequent processes.

[0104] In this embodiment, the method for forming the bitline structure is simple and easy to control. Furthermore, the isolation sidewalls provide good protection and isolation for the bitline, effectively ensuring the performance of the bitline structure.

[0105] In some embodiments, such as Figure 2 and Figure 3 As shown, the following methods can be used to form multiple spaced bit lines on the substrate:

[0106] An initial bit line contact layer 211a, an initial conductive layer 212a, and a second initial dielectric layer 213a are formed on a substrate 10 using atomic layer deposition, physical vapor deposition, or chemical vapor deposition.

[0107] A mask layer 24 with a mask pattern is formed on the second initial dielectric layer 213a. Along a direction perpendicular to the top surface of the substrate 10, a portion of the second initial dielectric layer 213a, a portion of the initial conductive layer 212a, and a portion of the initial bit line contact layer 211a are removed using an etching process according to the mask pattern. The retained second initial dielectric layer 213a forms the second dielectric layer 213, the retained initial conductive layer 212a forms the conductive layer 212, and the retained initial bit line contact layer 211a forms the bit line contact layer 211.

[0108] The second dielectric layer 213, the conductive layer 212, and the bit line contact layer 211 form the bit line 21.

[0109] In this embodiment, the bit line is formed by using the mask pattern of the mask layer, which can improve the formation accuracy of each structural layer of the bit line contact layer, conductive layer and second dielectric layer, and improve the formation quality of the bit line. The method is simple and easy to control.

[0110] In some embodiments, such as Figure 4 As shown, the process of forming the isolation sidewall on the outer periphery of the enclosure line can be carried out using the following methods:

[0111] A first sidewall layer 221, a second sidewall layer 222, and a third sidewall layer 223 are sequentially formed on the outer peripheral surface of the site line 21 using atomic layer deposition, physical vapor deposition, or chemical vapor deposition.

[0112] The materials of the first sidewall layer 221, the second sidewall layer 222, and the third sidewall layer 223 can be the same or different. In one example, the materials of the first sidewall layer 221, the second sidewall layer 222, and the third sidewall layer 223 can all include insulating materials such as silicon dioxide and borosilicate glass to isolate the alignment line 21 and subsequent contact structures. In another example, the first sidewall layer 221, the second sidewall layer 222, and the third sidewall layer 223 can include silicon nitride or silicon oxide, thereby forming a "NON" structure, such as a silicon nitride layer, a silicon oxide layer, and a silicon nitride layer, where "O" represents silicon oxide and "N" represents silicon nitride. Since the stress directions generated by the silicon oxide layer and the silicon nitride layer are different, using a "NON" structure helps to reduce stress, improve the isolation performance of the isolation sidewall 22, and facilitate selective etching in subsequent structures, thereby ensuring and improving the performance of the semiconductor structure.

[0113] It should be noted that in some embodiments, the isolation sidewall 22 may also be a single-layer structure. When the isolation sidewall 22 is a single-layer structure, the material of the isolation sidewall 22 may include, but is not limited to, isolation materials such as silicon dioxide, borosilicate glass, silicon nitride, or silicon oxynitride.

[0114] According to an exemplary embodiment, this embodiment is a further explanation of step S300 above.

[0115] In some embodiments, the filling layer can be formed using the following methods:

[0116] A first intermediate filling layer 62 is formed within the first gap 51 using atomic layer deposition, chemical vapor deposition, or physical vapor deposition. The top surface of the first intermediate filling layer 62 is flush with the top surface of the contact layer 40.

[0117] Among them, reference Figure 7 As shown, during the formation of the first intermediate filling layer 62, a first initial filling layer 63 can be formed within the first gap 51 using atomic layer deposition, chemical vapor deposition, or physical vapor deposition. The first initial filling layer 63 extends beyond the first gap 51, covering the top surface of the contact layer 40 and enclosing the bit line structure 20. The material of the first initial filling layer 63 can be, but is not limited to, cobalt, nickel, or titanium.

[0118] In one example, an initial filling layer 63 is formed within the first gap 51 using atomic layer deposition (ALD). ALD is characterized by a slow deposition rate, high film density, and good step coverage. As process technology continues to miniaturize, the aspect ratio of the contact holes 30 used to form the contact structure 70 increases. During the formation of the contact structure 70, the size of the gap 50 formed within the contact structure 70 varies depending on the deposition material and deposition parameters. Therefore, even if the top opening size of the first gap 51 is 1 nm, the initial filling layer 63 formed using ALD can completely fill the first gap 51, ensuring its complete elimination and facilitating the filling or formation of subsequent structural layers.

[0119] Reference Figure 8 and Figure 9 As shown, the first initial filler layer 63 of the wrapping bit line structure 20 is removed by an etching process, and the first initial filler layer 63 covering the top surface of the contact layer 40 is also removed, while the first initial filler layer 63 located in the first gap 51 is retained. The retained first initial filler layer 63 forms the first intermediate filler layer 62.

[0120] Reference Figure 8 As shown, in some embodiments, during the removal of the first initial filler layer 63 covering the top surface of the bit line structure 20 and the contact layer 40, a first dielectric layer 80 can be formed on the first initial filler layer 63 using atomic layer deposition, chemical vapor deposition, or physical vapor deposition. The material of the first dielectric layer 80 may include, but is not limited to, silicon nitride.

[0121] In the process of setting the first dielectric layer 80, the first dielectric layer 80 needs to be removed first by etching process, and then the first initial fill layer 63 covering the bit line structure 20 and the first initial fill layer 63 covering the top surface of the contact layer 40 need to be removed.

[0122] In some embodiments, refer to Figure 7 As shown, the thickness of the first initial filling layer 63 is less than 5nm, that is, the deposition thickness of the first initial filling layer 63 is less than 5nm, so that the first initial filling layer can better fill the entire first gap, ensure that the first gap is completely eliminated, improve the resistance of the contact structure, and improve the electrical properties and yield of the semiconductor structure.

[0123] In this embodiment, by setting a first dielectric layer, the quality of the first intermediate filling layer can be ensured during the removal of part of the first initial filling layer. Simultaneously, it protects the contact layer, preventing damage to the contact layer and the first intermediate filling layer within the first gap during the etching process of the first initial filling layer. Taking a polysilicon contact layer and silicon nitride as an example, after the contact layer fills between adjacent bit line structures and is etched to a preset height (e.g., along a direction perpendicular to the top surface of the substrate, at any position after removing part of the gap), the etching process of the contact layer is completed. Then, silicon nitride is used to protect the polysilicon layer from consumption by subsequent processes. Without the protection of silicon nitride, during subsequent deposition of semiconductor structures such as oxides, the oxides will neutralize the doping elements in the polysilicon layer and consume part of the polysilicon layer, thus forming an etching termination layer for subsequent processes. This could cause the contact layer to come into contact with subsequent semiconductor structures (such as pads), reducing the electrical properties and yield of the semiconductor structure.

[0124] After the first intermediate filling layer 62 is formed, refer to Figure 10 As shown, the first intermediate filler layer 62 is processed to form the first filler layer 61. Specifically, the first intermediate filler layer 62 can be subjected to high-temperature tempering to form the first filler layer 61. Taking cobalt metal as an example, through high-temperature tempering, the cobalt metal reacts to form cobalt silicide, which better fills the entire first gap 51 and eliminates the influence of the first gap 51 on the resistance of the contact structure 70.

[0125] Then, after the first filling layer 61 is formed, refer to Figure 11 As shown, a second initial filling layer 64 is formed on the first filling layer 61 using atomic layer deposition, physical vapor deposition, or chemical vapor deposition. The second initial filling layer 64 includes a first segment 641 and a second segment 642 connected alternately in sequence, wherein the first segment 641 covers the top surface of the contact layer 40, and the second segment 642 wraps around the bit line structure 20. The material of the second initial filling layer 64 may include, but is not limited to, cobalt, nickel, or titanium.

[0126] Then, refer to Figure 11 As shown, the first segment 641 undergoes high-temperature tempering treatment, causing the first segment 641 to form a second filler layer 65. The first filler layer 61 and the second filler layer 65 form a filler layer 60. In some embodiments, refer to... Figure 12As shown, the materials of the first filling layer 61 and the second filling layer 65 are the same. For example, both the first filling layer 61 and the second filling layer 65 can be made of cobalt metal, which forms cobalt silicide in the subsequent high-temperature tempering process. Using the same materials for the first and second filling layers allows for deposition using the same deposition parameters, reducing the process difficulty of the filling layer 60 and saving on the manufacturing cost of the semiconductor structure. Furthermore, it effectively ensures a good connection between the first and second filling layers, improving the conductivity between the filling layer and the contact layer.

[0127] The untreated second segment 642 is removed using an etching process. In one example, the first filler layer 61 and the first segment 641 can be processed in the same high-temperature tempering step to form the filler layer 60, thereby reducing the process cost of forming the filler layer 60.

[0128] In another embodiment, only the first intermediate filler layer 62 may be formed, which fills the entire first gap 51, and then the first intermediate filler layer 62 may be subjected to high-temperature tempering to form the first filler layer 61.

[0129] In this embodiment, the first filling layer is used to fill the entire first gap, and the top surface of the first filling layer and the contact layer is covered by the second filling layer. The first filling layer and the second filling layer form a filling layer. That is, the filling layer is formed by filling twice, which can more thoroughly fill the entire first gap, completely eliminate the gap in the contact layer, reduce the damage to the contact layer in subsequent processes, improve the resistance of the semiconductor structure, and improve the electrical properties and yield of the semiconductor structure.

[0130] In some embodiments, the filling layer can also be formed using the following methods:

[0131] An initial fill layer (not shown in the figure) is formed on the contact layer 40 using atomic layer deposition, physical vapor deposition, or chemical vapor deposition. The initial fill layer fills the first gap 51 and covers the top surface of the contact layer 40. The material of the initial fill layer may include, but is not limited to, cobalt, nickel, or titanium.

[0132] Then, the initial filler layer is subjected to high-temperature tempering treatment to form silicides (such as cobalt silicide, nickel silicide, or titanium silicide) to form filler layer 60.

[0133] In this embodiment, the filling layer is formed in one step. On the one hand, this can reduce the manufacturing process cost of the semiconductor structure; on the other hand, the filling layer can completely eliminate the first gap, improve the resistance of the contact structure, and thus improve the electrical properties and yield of the semiconductor structure.

[0134] like Figure 12As shown, an exemplary embodiment of this disclosure provides a semiconductor structure. The semiconductor structure includes a substrate 10 and a contact structure 70.

[0135] Multiple discrete bit line structures 20 are provided on the top surface of the substrate 10, and contact holes 30 are formed between adjacent bit line structures.

[0136] The contact structure 70 includes a contact layer 40 and a filler layer 60. The contact layer 40 is disposed within the contact hole 30, that is, the contact layer 40 is located between adjacent bit line structures 20. The contact layer 40 has a first gap 51 (see reference). Figure 6 As shown, the opening of the first gap 51 is exposed to the outside, and the filling layer 60 fills the first gap 51 and covers the top surface of the contact layer 40.

[0137] In this embodiment, the first gap is filled by a filling layer to eliminate the gap in the contact layer, thereby effectively improving the resistance of the contact layer and improving the electrical properties and yield of the semiconductor structure.

[0138] In some embodiments, such as Figure 12 As shown, the filling layer 60 includes a first filling layer 61 and a second filling layer 65. The first filling layer 61 is located within the first gap 51 and fills the entire first gap 51. The second filling layer 65 covers the top surface of the contact layer 40 and the top surface of the first filling layer 61, and the second filling layer 65 is connected to the first filling layer 61.

[0139] In this embodiment, the first filling layer is used to fill the entire first gap, and the top surface of the first filling layer and the contact layer is covered by the second filling layer. The first filling layer and the second filling layer form a filling layer. That is, the filling layer is formed by filling twice, which can more thoroughly fill the entire first gap, completely eliminate the gap in the contact layer, reduce the damage to the contact layer in subsequent processes, improve the resistance of the semiconductor structure, and improve the electrical properties and yield of the semiconductor structure.

[0140] In some embodiments, such as Figure 12 As shown, the first filler layer 61 and the second filler layer 65 are made of the same material. For example, both the first filler layer 61 and the second filler layer 65 can be made of cobalt metal, which forms cobalt silicide in the subsequent high-temperature tempering process. Using the same material for the first and second filler layers allows for deposition using the same deposition parameters, reducing the process difficulty of the filler layer 60 and saving on the process cost of the semiconductor structure. Furthermore, it effectively ensures a good connection between the first and second filler layers, improving the conductivity between the filler layer and the contact layer.

[0141] In some embodiments, such as Figure 12As shown, the aspect ratio between adjacent bit line structures 20 is greater than 2, that is, the aspect ratio of the contact hole 30 is greater than 2, and the depth of the contact hole 30 is more than twice its width. (Refer to...) Figure 5 As shown, during the formation of the initial contact layer 41, since the top of the contact hole 30 is sealed in advance, a gap 50 will appear within the formed initial contact layer 30. The top surface of the gap 50 will be lower than the top surface of the bit line structure 20. In the semiconductor structure manufacturing process, the presence of the gap 50 is detrimental to improving the conductivity of the semiconductor structure. Therefore, the gap 50 can be removed in subsequent processes to ensure and improve the performance and yield of the semiconductor structure.

[0142] In some embodiments, such as Figure 12 As shown, the bit line structure 20 includes bit line 21 and isolation sidewall 22.

[0143] There are multiple bit lines 21, which are spaced apart on the substrate 10. Each bit line 21 includes a bit line contact layer 211, a conductive layer 212, and a second dielectric layer 213 stacked together. The bit line contact layer 211 is connected to the substrate 10.

[0144] The isolation sidewall 22 includes a first sidewall layer 221, a second sidewall layer 222, and a third sidewall layer 223 stacked together, wherein the first sidewall layer 221 covers the outer periphery of the positioning line 21. The materials of the first sidewall layer 221, the second sidewall layer 222, and the third sidewall layer 223 may be the same or different.

[0145] In this embodiment, the isolation sidewall can improve the isolation performance of the alignment line, which is beneficial for selective etching in subsequent structures, thereby ensuring and improving the performance of the semiconductor structure.

[0146] In the description of this disclosure, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this disclosure.

[0147] It is understood that the terms "first," "second," etc., as used in this disclosure may be used to describe various structures, but these structures are not limited by these terms. These terms are only used to distinguish one structure from another.

[0148] In one or more accompanying drawings, the same elements are represented by similar reference numerals. For clarity, many parts in the drawings are not drawn to scale. Furthermore, certain well-known parts may not be shown. For simplicity, a structure obtained after several steps may be depicted in a single drawing. Many specific details of this disclosure, such as the structure, materials, dimensions, processing methods, and techniques of the devices, are described below to provide a clearer understanding of the disclosure. However, as those skilled in the art will understand, this disclosure may be implemented without adhering to these specific details.

[0149] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, The method includes: A substrate is provided, on which a plurality of discretely arranged bit line structures are provided, and an initial contact layer is provided between adjacent bit line structures, and a gap is provided in the initial contact layer; A portion of the initial contact layer is removed to open the gap, the remaining initial contact layer forms a contact layer, and the remaining gap forms a first gap; A filling layer is formed, which fills the first gap and covers the top surface of the contact layer; Forming a filling layer that fills the first gap and covers the top surface of the contact layer, comprising: A first intermediate filling layer is formed in the first gap, and the top surface of the first intermediate filling layer is flush with the top surface of the contact layer. The first intermediate filling layer is processed to form the first filling layer; A second initial fill layer is formed on the first fill layer. The second initial fill layer includes a first segment and a second segment that are alternately connected in sequence. The first segment covers the top surface of the contact layer, and the second segment wraps the bit line structure. The first segment is processed and the second segment is removed. The processed first segment forms a second filling layer, and the first filling layer and the second filling layer form the filling layer.

2. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The material of the first filler layer is the same as the material of the second filler layer.

3. The method for fabricating a semiconductor structure according to claim 1, characterized in that, A first intermediate filling layer is formed within the first gap, comprising: A first initial filling layer is formed within the first gap, the first initial filling layer extends outside the first gap, the first initial filling layer covers the top surface of the contact layer and wraps the bit line structure; The first initial fill layer that wraps around the bit line structure and covers the top surface of the contact layer is removed, and the remaining first initial fill layer forms the first intermediate fill layer.

4. The method for fabricating a semiconductor structure according to claim 3, characterized in that, The thickness of the first initial filling layer is less than 5 nm.

5. The method for fabricating a semiconductor structure according to claim 3, characterized in that, Removing the first initial filler layer that encloses the bit line structure and covers the top surface of the contact layer includes: A first dielectric layer is formed on the first initial filling layer; Remove the first dielectric layer, the first initial fill layer that encloses the bit line structure, and the first initial fill layer that covers the top surface of the contact layer.

6. The method for fabricating a semiconductor structure according to claim 3, characterized in that, Processing the first intermediate filler layer to form the first filler layer includes: The first intermediate filler layer is subjected to high-temperature tempering to form the first filler layer; The first segment is processed to form a second filling layer, including: The first segment is subjected to high-temperature tempering to form the second filler layer.

7. The method for fabricating a semiconductor structure according to claim 1, characterized in that, Forming a filling layer that fills the first gap and covers the top surface of the contact layer, comprising: An initial fill layer is formed on the contact layer, the initial fill layer filling the first gap and covering the top surface of the contact layer; The initial fill layer is processed to form the fill layer.

8. The method for fabricating a semiconductor structure according to claim 1, characterized in that, A substrate is provided, on which a plurality of discretely arranged bitline structures are provided, and an initial contact layer is provided between adjacent bitline structures, the initial contact layer having a gap, including: A plurality of spaced bit lines are formed on the substrate; An isolation sidewall is formed to enclose the outer peripheral surface of the bit line, and a contact hole is formed between adjacent isolation sidewalls; An initial contact layer is formed within the contact hole, and the top surface of the initial contact layer is flush with the top surface of the isolation sidewall.

9. The method for fabricating a semiconductor structure according to claim 8, characterized in that, A plurality of spaced bit lines are formed on the substrate, including: An initial bit line contact layer, an initial conductive layer, and a second initial dielectric layer are sequentially formed on the substrate. A mask layer with a mask pattern is formed on the second initial dielectric layer. A portion of the second initial dielectric layer, a portion of the initial conductive layer, and a portion of the initial bit line contact layer are removed according to the mask pattern. The remaining second initial dielectric layer forms a second dielectric layer, the remaining initial conductive layer forms a conductive layer, and the remaining initial bit line contact layer forms a bit line contact layer. The bit line is formed by the second dielectric layer, the conductive layer, and the bit line contact layer.

10. The method for fabricating a semiconductor structure according to claim 9, characterized in that, An isolation sidewall forming an enclosure around the outer periphery of the bit line includes: A first sidewall layer, a second sidewall layer, and a third sidewall layer are sequentially formed on the outer periphery of the position line.

11. A semiconductor structure, characterized in that, include: A substrate having a plurality of discretely arranged bitline structures; A contact structure comprising a contact layer and a filler layer, the contact layer being located between adjacent bit line structures, wherein the contact layer has a first gap, the opening of the first gap being exposed to the outside, and the filler layer filling the first gap and covering the top surface of the contact layer; The filling layer includes a first filling layer and a second filling layer, the first filling layer being located within the first gap, and the second filling layer covering the top surface of the contact layer and the first filling layer.

12. The semiconductor structure according to claim 11, characterized in that, The first filler layer and the second filler layer are made of the same material.

13. The semiconductor structure according to claim 11, characterized in that, The aspect ratio between adjacent bitline structures is greater than 2.

14. The semiconductor structure according to claim 11, characterized in that, The bit line structure includes bit lines and isolation sidewalls; There are multiple bit lines, and the multiple bit lines are spaced apart on the substrate; The isolation sidewall encloses the outer periphery of the bit line.

15. The semiconductor structure according to claim 14, characterized in that, The bit line includes a bit line contact layer, a conductive layer, and a second dielectric layer stacked together, and the bit line contact layer is connected to the substrate.

16. The semiconductor structure according to claim 14, characterized in that, The isolation sidewall includes a first sidewall layer, a second sidewall layer, and a third sidewall layer stacked together, with the first sidewall layer covering the outer periphery of the bit line.

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