Epitaxial silicon in horizontal access devices in vertical three-dimensional (3D) memory

Abstract

This application relates to epitaxial silicon within horizontal access devices in vertical three-dimensional (3D) memory. Systems, methods, and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and storage nodes. The horizontally oriented access devices have first and second source / drain regions separated by a channel region that is epitaxially grown. A gate opposite the channel region forms a full-enclosure of each surface of the channel region as a gate-all-around (GAA) structure separated from the channel region by a gate dielectric. The memory cells have horizontally oriented storage nodes coupled to the second source / drain regions and digit lines coupled to the first source / drain regions.

Description

Technical Field

[0001] This disclosure generally relates to memory devices, and more specifically, to epitaxial silicon within horizontal access devices in vertical three-dimensional (3D) memory. Background Technology

[0002] Memory is commonly implemented in electronic systems such as computers, cell phones, and handheld devices. Many different types of memory exist, including volatile and non-volatile memory. Volatile memory may require power to maintain its data and can include random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), and synchronous dynamic random access memory (SDRAM). Non-volatile memory provides persistent data by retaining the stored data when no power is supplied and can include NAND flash memory, NOR flash memory, nitride read-only memory (NROM), phase-change memory (e.g., phase-change random access memory), resistive memory (e.g., resistive random access memory), crosspoint memory, ferroelectric random access memory (FeRAM), etc.

[0003] As design rules shrink, the semiconductor space available for manufacturing memories containing DRAM arrays is decreasing. A corresponding memory cell for DRAM may include access means, such as transistors, having first and second source / drain regions separated by an epitaxially grown channel region. A gate may be opposite to and separated from the channel region by a gate dielectric. Access lines, such as word lines, are electrically connected to the gate of the DRAM cell. A DRAM cell may include memory nodes, such as capacitor cells, coupled to digital lines via access means. Access means may be activated (e.g., to select a cell) via access lines coupled to access transistors. Capacitors may store charge corresponding to the data value (e.g., logic "1" or "0") of the corresponding cell. Summary of the Invention

[0004] In one aspect, this application provides a method for forming a vertically stacked memory cell array having horizontally oriented access devices and memory nodes, the method comprising: epitaxially forming alternating layers of silicon-germanium (SiGe) and silicon (Si) materials from a substrate to form a vertical stack; forming a plurality of first vertical openings having a first horizontal direction and a second horizontal direction through the vertical stack, the first vertical openings extending primarily in the second horizontal direction to form an elongated column of vertical pillars having first vertical sidewalls in the stack; filling the plurality of first vertical openings with a first dielectric material; and selectively removing the first dielectric material from the plurality of first vertical openings. A portion of the material is used to expose the sidewalls of a first region adjacent to an epitaxially grown silicon-germanium (SiGe) material, forming a plurality of spaced-apart second vertical openings through the vertical stack; the epitaxially grown silicon-germanium (SiGe) material is isotropically selectively etched to form a plurality of first horizontal openings; a second dielectric material is conformally deposited on the exposed surfaces in the plurality of first horizontal openings; the first dielectric material is deposited to fill the plurality of first horizontal openings; a third vertical opening is formed, the third vertical opening extending through the vertical stack and primarily in the first horizontal direction to expose the sidewalls of the second region adjacent to the epitaxially grown silicon-germanium (SiGe); the epitaxially grown silicon-germanium (SiGe) material is selectively etched to form a plurality of second horizontal openings extending a first distance (DIST 1) from the third vertical opening; the second dielectric material is selectively etched from the third vertical opening to a second distance (DIST 2); and a gate dielectric material is formed on the exposed surfaces of the epitaxially grown Si material to form a horizontal access device.

[0005] On the other hand, this application provides a method for forming a vertically stacked memory cell array having horizontally oriented access devices and memory nodes. The method includes: epitaxially forming alternating layers of silicon-germanium (SiGe) and silicon (Si) materials from a substrate to form a vertical stack; forming a plurality of first vertical openings having a first horizontal direction and a second horizontal direction through the vertical stack, the first vertical openings extending primarily in the second horizontal direction to form an elongated vertical column having first vertical sidewalls in the stack; filling the plurality of first vertical openings with a first dielectric material; and exposing the second vertical sidewalls of a first region of epitaxially grown silicon-germanium (SiGe) by patterning and selectively removing the first dielectric material from the plurality of first vertical openings (in the first horizontal direction) to expose the second vertical sidewalls of the first region of the epitaxially grown silicon-germanium (SiGe) through the vertical stack. The epitaxially grown silicon germanium (SiGe) is stacked vertically to form a plurality of spaced-apart second vertical openings; the epitaxially grown silicon germanium (SiGe) is selectively etched isotropically to form a plurality of first horizontal openings in the first region to separate layers of the Si material; a second dielectric material is conformally deposited on the exposed surfaces in the plurality of first horizontal openings to a first thickness (t1); the first dielectric material is deposited through the plurality of spaced-apart second vertical openings to fill the plurality of first horizontal openings; a third vertical opening is formed, the third vertical opening extending through the vertical stack and primarily in the first horizontal direction to expose a third vertical sidewall adjacent to the second region of the epitaxially grown silicon germanium (SiGe); and the epitaxially grown silicon germanium (SiGe) is selectively etched to form a plurality of second horizontal openings in the second region at a distance (up to a first distance (DIST 1)) from the third vertical opening, and the second dielectric material terminates thereon.

[0006] On the other hand, this application provides a memory device for forming a vertically stacked memory cell array, the vertically stacked memory cell array having a horizontally oriented access device and a memory node, the memory device comprising: a vertically stacked memory cell array having a horizontally oriented access device and a memory node, the memory node comprising: a horizontally oriented access device having a first source / drain region and a second source / drain region separated by an epitaxially grown channel region, and a gate opposite to the channel region formed on each surface of the gate dielectric material completely surrounding the channel region as a gate all-around (GAA) structure; and a horizontally oriented memory node electrically coupled to the second source / drain region of the horizontally oriented access device. Attached Figure Description

[0007] Figure 1A This is a schematic diagram of a horizontal access device in a vertical three-dimensional (3D) memory according to several embodiments of the present disclosure.

[0008] Figure 1B This is a perspective view showing a portion of a horizontal access device in a vertical three-dimensional (3D) memory according to various embodiments of the present disclosure.

[0009] Figure 2A This is a schematic diagram of a horizontal access device in a vertical three-dimensional (3D) memory according to several embodiments of the present disclosure.

[0010] Figure 2B This is a perspective view showing a portion of a horizontal access device in a vertical three-dimensional (3D) memory according to various embodiments of the present disclosure.

[0011] Figures 3A-3B A portion of a horizontal access device in a vertical three-dimensional (3D) memory according to several embodiments of the present disclosure is shown.

[0012] Figure 4 This is a cross-sectional view of epitaxial silicon formed within a horizontal access device in a vertical three-dimensional (3D) memory according to several embodiments of the present disclosure.

[0013] Figures 5A to 5B An example method is shown for one stage of a semiconductor manufacturing process for forming epitaxial silicon within a horizontal access device in a vertical three-dimensional (3D) memory according to several embodiments of the present disclosure.

[0014] Figures 6A to 6E An example method is shown for another stage of a semiconductor manufacturing process for forming epitaxial silicon within a horizontal access device in a vertical three-dimensional (3D) memory according to several embodiments of the present disclosure.

[0015] Figures 7A to 7E An example method is shown for another stage of a semiconductor manufacturing process for forming epitaxial silicon within a horizontal access device in a vertical three-dimensional (3D) memory according to several embodiments of the present disclosure.

[0016] Figures 8A to 8E An example method is shown for another stage of a semiconductor manufacturing process for forming epitaxial silicon within a horizontal access device in a vertical three-dimensional (3D) memory according to several embodiments of the present disclosure.

[0017] Figures 9A to 9E An example method is shown for another stage of a semiconductor manufacturing process for forming epitaxial silicon within a horizontal access device in a vertical three-dimensional (3D) memory according to several embodiments of the present disclosure.

[0018] Figures 10A to 10E An example method is shown for another stage of a semiconductor manufacturing process for forming epitaxial silicon within a horizontal access device in a vertical three-dimensional (3D) memory according to several embodiments of the present disclosure.

[0019] Figures 11A to 11E An example method is shown for another stage of a semiconductor manufacturing process for forming epitaxial silicon within a horizontal access device in a vertical three-dimensional (3D) memory according to several embodiments of the present disclosure.

[0020] Figures 12A to 12E An example method is shown for another stage of a semiconductor manufacturing process for forming epitaxial silicon within a horizontal access device in a vertical three-dimensional (3D) memory according to several embodiments of the present disclosure.

[0021] Figures 13A to 13E An example method is shown for another stage of a semiconductor manufacturing process for forming epitaxial silicon within a horizontal access device in a vertical three-dimensional (3D) memory according to several embodiments of the present disclosure.

[0022] Figures 14A to 14E An example method is shown for another stage of a semiconductor manufacturing process for forming epitaxial silicon within a horizontal access device in a vertical three-dimensional (3D) memory according to several embodiments of the present disclosure.

[0023] Figures 15A to 15E An example method is shown for another stage of a semiconductor manufacturing process for forming epitaxial silicon within a horizontal access device in a vertical three-dimensional (3D) memory according to several embodiments of the present disclosure.

[0024] Figures 16A to 16E An example method is shown for another stage of a semiconductor manufacturing process for forming epitaxial silicon within a horizontal access device in a vertical three-dimensional (3D) memory according to several embodiments of the present disclosure.

[0025] Figures 17A to 17E Examples of methods for forming epitaxial silicon within a horizontal access device in a vertical three-dimensional (3D) memory are shown at another stage of the semiconductor manufacturing process and according to several embodiments of the present disclosure.

[0026] Figures 18A to 18E Examples of methods for forming epitaxial silicon within a horizontal access device in a vertical three-dimensional (3D) memory are shown at another stage of the semiconductor manufacturing process and according to several embodiments of the present disclosure.

[0027] Figures 19A to 19E An example method is shown for another stage of a semiconductor manufacturing process for forming epitaxial silicon within a horizontal access device in a vertical three-dimensional (3D) memory according to several embodiments of the present disclosure.

[0028] Figures 20A to 20E An example method is shown for another stage of a semiconductor manufacturing process for forming epitaxial silicon within a horizontal access device in a vertical three-dimensional (3D) memory according to several embodiments of the present disclosure.

[0029] Figures 21A to 21B A cross-sectional view of an example horizontally oriented access device coupled to a horizontally oriented access line according to several embodiments of the present disclosure is shown, having vertical digital lines for a semiconductor device.

[0030] Figures 22A to 22B An example method is shown for another stage of a semiconductor manufacturing process for forming epitaxial silicon within a horizontal access device in a vertical three-dimensional (3D) memory according to several embodiments of the present disclosure.

[0031] Figures 23A to 23B A top view of an example horizontally oriented access device coupled to horizontally oriented access lines according to several embodiments of the present disclosure is shown, having vertical digital lines for a semiconductor device.

[0032] Figure 24 This is a block diagram of a device in the form of a computing system including a memory device, according to several embodiments of the present disclosure. Detailed Implementation

[0033] Embodiments of this disclosure describe the formation of epitaxial silicon within horizontal access devices in a vertical three-dimensional (3D) memory. Vertically oriented digital lines are formed together with the horizontally oriented access devices and access lines in a vertically stacked memory cell array. The horizontally oriented access devices are integrated with the horizontally oriented access lines, which have a first source / drain region and a second source / drain region separated by an epitaxially grown channel region and are integrated with the vertically oriented digital lines. In vertically stacked memory array structures (e.g., transistor structures), polysilicon (also known as polysilicon) can leak, causing current to leak through the polysilicon structure, making the transistor less efficient. Monocrystalline silicon is not easily leaky; however, monocrystalline silicon cannot be grown on amorphous dielectric materials (e.g., oxides or nitrides), which are common materials for forming transistors.

[0034] However, as disclosed in the embodiments of this disclosure, it is possible to use a silicon wafer that can serve as a substrate for transistors during the high-temperature processes required for the formation of single-crystal silicon. In such embodiments, a silicon-germanium layer can be grown on a silicon substrate. Subsequently, single-crystal silicon can be grown on the silicon-germanium.

[0035] This can be achieved, for example, by providing a thin monocrystalline silicon-germanium layer as a seed layer, and then heating the layer to grow the monocrystalline silicon-germanium layer to a thicker thickness through epitaxial growth. Once the desired layer thickness is achieved, a silicon layer can be formed on the surface of the silicon-germanium layer. Similar to the silicon-germanium layer, this can be achieved, for example, by providing a thin monocrystalline silicon layer as a seed layer, and then heating the layer to grow the thin monocrystalline silicon layer to a thicker monocrystalline silicon layer through epitaxial growth.

[0036] Depending on the silicon-germanium concentration, if silicon is amount x and germanium is amount y, and if y is less than x, then the silicon / silicon-germanium lattice has a smaller lattice mismatch relative to the single-crystal silicon lattice. This allows silicon to grow on top of silicon-germanium with a single-crystal structure. If a thin layer of single-crystal silicon is applied to the surface of silicon-germanium, the entire silicon layer acts as a seed for the growth of the single-crystal silicon layer. Such layering can be carried out alternately (e.g., SiGe / Si / SiGe / Si, etc.) to produce a superlattice structure in a vertically stacked form, such as... Figure 4 As shown.

[0037] For example, a silicon-germanium seed layer can be formed with a thickness (height) of 100 angstroms and can be grown to, for example, 1000 angstroms. A thin silicon seed layer can be formed on the surface of the silicon-germanium layer with a thickness of, for example, 50 angstroms and can be grown to, for example, 300 angstroms. Unless expressly stated in a particular claim, these thicknesses are provided as examples only and should not be considered limiting.

[0038] The transistor device disclosed herein exhibits superior performance in terms of I-on, improved I-off, driveability, and / or leakage current because there are no grain boundaries, and therefore current does not leak through the grain boundaries, which are common sites of leakage in polycrystalline silicon. In some embodiments, the device may have, for example, three orders of magnitude lower I-off (leakage).

[0039] The advantages of the structures and processes described herein may include lower cutoff current (Ioff) for the access device compared to silicon-based (Si-based) access devices (e.g., transistors), better DRAM refresh requirements, and / or reduced gate / drain induced leakage (GIDL) of the access device. This disclosure describes a channel region formed from epitaxially grown material. Incorporating a gate-all-around (GAA) structure into the channel region of the semiconductor material provides better electrostatic control of the channel, better subthreshold slope, and a more cost-effective process.

[0040] The figures in this document follow a numbering convention, where the first one or more numbers correspond to the figure number, and the remaining numbers identify the elements or components in the figure. Similar elements or components between different figures can be identified by using similar numbers. For example, reference numeral 104 could refer to... Figure 1A-1B Component "04" in the text, and similar components in Figure 2A and 2B The symbol 204 can be used to represent multiple similar elements within a drawing. A reference numeral followed by a hyphen and another number or letter can be used to represent multiple similar elements within a drawing. For example, 302-1 can refer to... Figure 3A and 3BComponent 302-1 and 302-2 can refer to component 302-2, which can be similar to component 302-1. Such similar components can typically be referenced without hyphens and additional numbers or letters. For example, components 302-1 and 302-2, or other similar components, can be represented collectively as 302.

[0041] Figure 1A This is a block diagram of an apparatus according to several embodiments of the present disclosure. Figure 1A A circuit diagram showing a cell array of a three-dimensional (3D) semiconductor memory device according to an embodiment of the present disclosure is provided. Figure 1A The diagram shows that the cell array may have multiple sub-cell arrays 101-1, 101-2, ..., 101-N. Sub-cell arrays 101-1, 101-2, ..., 101-N may be arranged along a second direction (D2) 105. Each of the sub-cell arrays, such as sub-cell array 101-2, may contain multiple access lines 107-1, 107-2, ..., 107-Q (also referred to as word lines). Additionally, each of the sub-cell arrays, such as sub-cell array 101-2, may contain multiple digital lines 103-1, 103-2, ..., 103-Q (also referred to as bit lines, data lines, or sensing lines). Figure 1A In the diagram, access lines 107-1, 107-2, ..., 107-Q are shown extending in a first direction (D1) 109, and digital lines 103-1, 103-2, ..., 103-Q are shown extending in a third direction (D3) 111. According to an embodiment, the first direction (D1) 109 and the second direction (D2) 105 can be considered in a horizontal (“XY”) plane. The third direction (D3) 111 can be considered to be in a vertical (“Z”) plane. Therefore, according to the embodiment described herein, digital lines 103-1, 103-2, ..., 103-Q extend in a vertical direction, for example, in the third direction (D3) 111.

[0042] A memory cell (e.g., 110) may include access means (e.g., access transistors) and a memory node located at the intersection of each access line 107-1, 107-2, ..., 107-Q and each digital line 103-1, 103-2, ..., 103-Q. The memory cell can be written to or read from using the access lines 107-1, 107-2, ..., 107-Q and the digital lines 103-1, 103-2, ..., 103-Q. The access lines 107-1, 107-2, ..., 107-Q are conductively interconnected along the horizontal rows of each sub-cell array 101-1, 101-2, ..., 101-N, and the digital lines 103-1, 103-2, ..., 103-Q are conductively interconnected along the vertical columns of each sub-cell array 101-1, 101-2, ..., 101-N. A memory cell (e.g., 110) may be located between an access line (e.g., 107-2) and a digital line (e.g., 103-2). Each memory cell can be uniquely addressed by a combination of access lines 107-1, 107-2, ..., 107-Q and digital lines 103-1, 103-2, ..., 103-Q.

[0043] Access lines 107-1, 107-2, ..., 107-P may be or include conductive patterns (e.g., metal lines) disposed on and spaced apart from the substrate. Access lines 107-1, 107-2, ..., 107-Q may extend in a first direction (D1) 109. Access lines 107-1, 107-2, ..., 107-Q in a sub-cell array (e.g., 101-2) may be spaced apart from each other in a vertical direction (e.g., in a third direction (D3) 111).

[0044] Digital lines 103-1, 103-2, ..., 103-Q may be or include conductive patterns (e.g., metal lines) extending in a vertical direction (e.g., on a third direction (D3) 111) relative to the substrate. Digital lines in a sub-cell array (e.g., 101-2) may be spaced apart from each other in a first direction (D1) 109.

[0045] The gate of a memory cell (e.g., memory cell 110) may be connected to an access line (e.g., 107-2), and the first conductive node (e.g., a first source / drain region) of the access means (e.g., a transistor) of memory cell 110 may be connected to a digital line (e.g., 103-2). Each of the memory cells (e.g., memory cell 110) may be connected to a storage node, such as a capacitor. The second conductive node (e.g., a second source / drain region) of the access means (e.g., a transistor) of memory cell 110 may be connected to a storage node, such as a capacitor. Although the references to first and second source / drain regions are used herein to designate two separate and distinct source / drain regions, it is not intended that the source / drain regions referred to as “first” and / or “second” have a particular meaning. It is only desirable that one of the source / drain regions is connected to a digital line, such as 103-2, and the other may be connected to a storage node.

[0046] Figure 1B A perspective view is shown illustrating a three-dimensional (3D) semiconductor memory device according to some embodiments of the present disclosure, such as a vertically oriented memory cell stack in an array. Figure 1A A portion of the sub-cell array 101-2 shown.

[0047] like Figure 1B As shown, a bonding can be formed on the substrate 100. Figure 1A One of the described array of sub-cells, such as 101-2. For example, substrate 100 may be or comprise a silicon substrate, a germanium substrate, or a silicon-germanium substrate, etc. However, the embodiments are not limited to these examples.

[0048] like Figure 1B As shown in the example embodiments, substrate 100 may be fabricated thereon with vertically oriented memory cells extending in a vertical direction (e.g., third direction (D3) 111). Figure 1A The memory cells 110 in the memory cell stack are stacked. According to some embodiments, the vertically oriented memory cell stack can be manufactured such that each memory cell (e.g., memory cells 110) is ... Figure 1A The memory cells 110 are formed on multiple vertical levels, such as a first level (L1), a second level (L2), and a third level (L3). Repeating vertical levels L1, L2, and L3 can be arranged (e.g., "stacked") in the vertical direction, for example... Figure 1AOn the third direction (D3) 111 shown, and separable from the substrate 100 by an insulating material 120. Each of the repeating vertical levels L1, L2, and L3 may contain multiple discrete components (e.g., regions) of a horizontally oriented access device 130 (e.g., transistor) and a memory node (e.g., a capacitor) containing access lines 107-1, 107-2, ..., 107-Q connections and digital lines 103-1, 103-2, ..., 103-Q connections. (See below for further details.) Figure 4 In more detail, multiple discrete components of the horizontally oriented access device 130 (e.g., transistors) can be formed in multiple iterations of a vertically repeating layer within each level, and can be formed in a second direction (D2) 105 (similar to...). Figure 1A It extends horizontally in the second direction (D2)105 shown.

[0049] Multiple discrete components of the lateral access device 130 (e.g., a transistor) may include a first source / drain region 121 and a second source / drain region 123 separated by a channel region 125, extending laterally in a second direction (D2) 105 and formed within the body of the access device. In some embodiments, the channel region 125 may comprise silicon, germanium, silicon-germanium, and / or indium gallium zinc oxide (IGZO). In some embodiments, the first source / drain region 121 and the second source / drain region 123 may comprise an n-type dopant region formed within the p-type doped body of the access device to form an n-type conductive transistor. In some embodiments, the first source / drain region 121 and the second source / drain region 123 may comprise a p-type dopant formed within the n-type doped body of the access device to form a p-type conductive transistor. By way of example, but not limitation, the n-type dopant may comprise phosphorus (P) atoms, and the p-type dopant may comprise boron (B) atoms formed in the opposite doped body region of a polycrystalline silicon semiconductor material. However, the embodiments are not limited to these examples.

[0050] Storage node 127 (e.g., a capacitor) can be connected to a corresponding terminal of the access device. For example... Figure 1B As shown, storage node 127 (e.g., a capacitor) may be connected to the second source / drain region 123 of the access device. A storage node may be or contain a memory element capable of storing data. Each of the storage nodes may be a memory element using one of a capacitor, a magnetic tunnel junction pattern, and / or a variable resistor body containing a phase change material, etc. However, embodiments are not limited to these examples. In some embodiments, with unit cells (e.g., Figure 1A The memory node associated with each access device of the memory cell 110) can be similarly located in the second direction (D2) 105 (similar to Figure 1A It extends in the second direction (D2) 105 shown.

[0051] like Figure 1B As shown, multiple horizontally oriented access lines 107-1, 107-2, ..., 107-Q are in the first direction (D1) 109 (similar to...). Figure 1A Extending along the first direction (D1) 109). Multiple horizontally oriented access lines 107-1, 107-2, ..., 107-Q can be similar to... Figure 1A The access lines 107-1, 107-2, ..., 107-Q are shown. Multiple horizontally oriented access lines 107-1, 107-2, ..., 107-Q may be arranged (e.g., "stacked") along a third direction (D3) 111. The multiple horizontally oriented access lines 107-1, 107-2, ..., 107-Q may contain a conductive material. For example, the conductive material may contain one or more of the following: doped semiconductors (e.g., doped silicon, doped germanium, etc.), conductive metal nitrides (e.g., titanium nitride, tantalum nitride, etc.), metals (e.g., tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), cobalt (Co), molybdenum (Mo), etc.), and / or metal semiconductor compounds (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.). However, the embodiments are not limited to these examples.

[0052] In each of the vertical hierarchies (L1)113-1, (L2)113-2, and (L3)113-P, the horizontally oriented memory cell (e.g., Figure 1A The memory cells 110 in the device may be horizontally spaced apart from each other in the first direction (D1) 109. However, a plurality of discrete components of the horizontally oriented access device 130 extending laterally in the second direction (D2) 105 (e.g., the first source / drain region 121 and the second source / drain region 123 separated by the channel region 125) and a plurality of horizontally oriented access lines 107-1, 107-2, ..., 107-Q extending laterally in the first direction (D1) 109 may be formed in different vertical layers within each level. For example, a plurality of horizontally oriented access lines 107-1, 107-2, ..., 107-Q extending in the first direction (D1) 109 may be formed on the top surface of the channel region opposite to and electrically coupled to the channel region 125, separated from it by the gate dielectric, and orthogonal to the horizontally oriented access device 130 extending laterally in the second direction (D2) 105 (e.g., transistors). In some embodiments, a plurality of horizontally oriented access lines 107-1, 107-2, ..., 107-Q extending in the first direction (D1) 109 are formed in a vertical layer, higher than the layer that forms the discrete components of the horizontally oriented access device (e.g., the first source / drain region 121 and the second source / drain region 123 separated by the channel region 125), away from the substrate 100.

[0053] like Figure 1BAs shown in the example embodiments, digital lines 103-1, 103-2, ..., 103-Q extend vertically relative to substrate 100 (e.g., on a third direction (D3) 111). Furthermore, as... Figure 1B As shown, a sub-cell array (e.g., Figure 1A The digital lines 103-1, 103-2, ..., 103-Q in the sub-cell array 101-2 can be spaced apart from each other in the first direction (D1) 109. The digital lines 103-1, 103-2, ..., 103-Q can be configured to extend vertically in the third direction (D3) 111 relative to the substrate 100 in a vertical alignment with the source / drain region to serve as the first source / drain region 121, or as shown, vertically adjacent to the first source / drain region 121 extending laterally in the second direction (D2) 105 of each of the horizontally oriented access devices 130 (e.g., transistors), but adjacent to each other in the first direction (D1) 109 at a certain level (e.g., the first level (L1)). Each of the digital lines 103-1, 103-2, ..., 103-Q may extend vertically in a third direction (D3) on the sidewall of the corresponding of a plurality of vertically stacked horizontally oriented access devices 130 (e.g., transistors). In some embodiments, the plurality of vertically oriented digital lines 103-1, 103-2, ..., 103-Q extending in the third direction (D3) 111 may be directly and / or connected to the side surface of the first source / drain region 121 via additional contacts comprising metal silicide.

[0054] For example, the first vertically extending digital line (e.g., 103-1) may be adjacent to the sidewall of the first source / drain region 121 of the first horizontally oriented access device 130 (e.g., a transistor) in the first level (L1) 113-1, the sidewall of the first source / drain region 121 of the first horizontally oriented access device 130 (e.g., a transistor) in the second level (L2) 113-2, and the sidewall of the first source / drain region 121 of the first horizontally oriented access device 130 (e.g., a transistor) in the third level (L3) 113-P, etc. Similarly, the second vertically extending digital line (e.g., 103-2) may be adjacent to the sidewall of the first source / drain region 121 of the second horizontally oriented access device 130 (e.g., transistor) in the first level (L1) 113-1, and spaced apart from the first horizontally oriented access device 130 (e.g., transistor) in the first direction (D1) 109. Furthermore, the second vertically extending digital line (e.g., 103-2) may be adjacent to the sidewall of the first source / drain region 121 of the second laterally oriented access device 130 (e.g., transistor) in the second level (L2) 113-2, and the sidewall of the first source / drain region 121 of the second horizontally oriented access device 130 (e.g., transistor) in the third level (L3) 113-P, etc. The embodiments are not limited to a specific number of levels.

[0055] The vertically extending digital lines 103-1, 103-2, ..., 103-Q may contain conductive materials, such as doped semiconductor materials, conductive metal nitrides, metals, and / or metal-semiconductor compounds. The digital lines 103-1, 103-2, ..., 103-Q may correspond to... Figure 1A The described digital line (DL).

[0056] like Figure 1B As shown in the example embodiment, conductive body contacts can be formed in each layer (L1) 113-1, (L2) 113-2, and (L3) 113-P above the substrate 100, extending along the end surface of the horizontally oriented access device 130 (e.g., a transistor) in a first direction (D1) 109. The body contacts can be connected to each memory cell (e.g., Figure 1A The body of the horizontally oriented access device 130 (e.g., a transistor) in the memory cell 110 (as in the memory cell 110) Figure 3A and 3B (as shown in 336) (e.g., the body region). The body contact may contain a conductive material, such as a doped semiconductor material, a conductive metal nitride, a metal, and / or a metal-semiconductor compound.

[0057] although Figure 1BNot shown, but insulating material may fill other spaces in the vertically stacked memory cell array. For example, the insulating material may comprise one or more of silicon oxide, silicon nitride, and / or silicon oxynitride. However, the embodiments are not limited to these examples.

[0058] Figure 2A This is a block diagram of an apparatus according to several embodiments of the present disclosure. Figure 2A A circuit diagram showing a cell array of a three-dimensional (3D) semiconductor memory device according to an embodiment of the present disclosure is provided. Figure 2A The diagram shows that the cell array may have multiple sub-cell arrays 201-1, 201-2, ..., 201-N. The sub-cell arrays 201-1, 201-2, ..., 201-N may be arranged along a second direction (D2) 205. Each of the sub-cell arrays (e.g., sub-cell array 201-2) may contain multiple access lines 203-1, 203-2, ..., 203-Q (also referred to as word lines). Additionally, each of the sub-cell arrays (e.g., sub-cell array 201-2) may contain multiple digital lines 207-1, 207-2, ..., 207-Q (which may also be referred to as bit lines, data lines, or sensing lines). Figure 2A In the diagram, digital lines 203-1, 203-2, ..., 203-Q are shown extending in the first direction (D1) 209, and access lines 207-1, 207-2, ..., 207-Q are shown extending in the third direction (D3) 211.

[0059] The first direction (D1) 209 and the second direction (D2) 205 can be considered to be in a horizontal (“XY”) plane. The third direction (D3) 211 can be considered to be in a vertical (“Z”) direction (e.g., transverse to the XY plane). Therefore, according to the embodiments described herein, access lines 203-1, 203-2, ..., 203-Q extend in a vertical direction (e.g., the third direction (D3) 211).

[0060] A memory cell (e.g., 210) may include access means (e.g., access transistors) and a memory node located at the intersection of each access line 203-1, 203-2, ..., 203-Q and each digital line 207-1, 207-2, ..., 207-Q. The memory cell can be written to or read from using the access lines 203-1, 203-2, ..., 203-Q and the digital lines 207-1, 207-2, ..., 207-Q. The digital lines 207-1, 207-2, ..., 207-Q are conductively interconnected along the horizontal columns of each sub-cell array 201-1, 201-2, ..., 201-N, and the access lines 203-1, 203-2, ..., 203-Q are conductively interconnected along the vertical rows of each sub-cell array 201-1, 201-2, ..., 201-N. A memory cell (e.g., 210) may be located between an access line (e.g., 203-2) and a digital line (e.g., 207-2). Each memory cell can be uniquely addressed by a combination of access lines 203-1, 203-2, ..., 203-Q and digital lines 207-1, 207-2, ..., 207-Q.

[0061] Digital lines 207-1, 207-2, ..., 207-Q may be or include conductive patterns (e.g., metal lines) disposed on and spaced apart from the substrate. Digital lines 207-1, 207-2, ..., 207-Q may extend in a first direction (D1) 209. Digital lines 207-1, 207-2, ..., 207-Q in a sub-cell array (e.g., 201-2) may be spaced apart from each other in a vertical direction (e.g., in a third direction (D3) 211).

[0062] Access lines 203-1, 203-2, ..., 203-Q may be or include conductive patterns (e.g., metal lines) extending in a vertical direction (e.g., on a third direction (D3) 211) relative to the substrate. Access lines in a sub-cell array (e.g., 201-2) may be spaced apart from each other in a first direction (D1) 209.

[0063] The gate of a memory cell (e.g., memory cell 210) may be connected to an access line (e.g., 203-2), and the first conductive node (e.g., a first source / drain region) of the access means (e.g., a transistor) of memory cell 210 may be connected to a digital line (e.g., 207-2). Each of the memory cells (e.g., memory cell 210) may be connected to a storage node (e.g., a capacitor). The second conductive node (e.g., a second source / drain region) of the access means (e.g., a transistor) of memory cell 210 may be connected to a storage node (e.g., a capacitor). The storage node (e.g., a capacitor) may be formed of a ferroelectric material and / or a dielectric material, such as zirconium oxide (ZrO2), hafnium oxide (HfO2), lanthanum oxide (La2O3), lead zirconate titanate (PZT, Pb[Zr(x)Ti(1-x)]O3), barium titanate (BaTiO3), aluminum oxide (e.g., Al2O3), combinations of these with or without dopants, or other suitable materials.

[0064] Although this paper uses first and second source / drain region references to denote two separate and distinct source / drain regions, it is not intended that the source / drain regions referred to as "first" and / or "second" have a single meaning. It is only desirable that one of the source / drain regions is connected to a digital line (e.g., 207-2), and the other is connected to a memory node.

[0065] Figure 2B A perspective view is shown illustrating a three-dimensional (3D) semiconductor memory device (e.g., as a stack of vertically oriented memory cells in an array) according to some embodiments of the present disclosure. Figure 2A (A portion of the sub-cell array 201-2 shown). Figure 2B As shown, a bonding can be formed on the substrate 200. Figure 2A One of the described array of sub-cells (e.g., 201-2). For example, substrate 200 may be or comprise a silicon substrate, a germanium substrate, or a silicon-germanium substrate, etc. However, the embodiments are not limited to these examples.

[0066] like Figure 2B As shown in the example embodiment, substrate 200 may be fabricated thereon with vertically oriented memory cells extending in a vertical direction (e.g., third direction (D3) 211). Figure 2A The memory cells 210 in the memory cell stack are stacked. According to some embodiments, the vertically oriented memory cell stack can be manufactured such that each memory cell (e.g., memory cells 210) is ... Figure 2A The memory cells 210 are formed on multiple vertical levels (e.g., a first level (L1), a second level (L2), and a third level (L3)). Repeating vertical levels L1, L2, and L3 can be arranged (e.g., "stacked") in the vertical direction (e.g., ...). Figure 2AThe third direction (D3) 211 shown is on the substrate 200 and can be separated from the substrate 200 by an insulating material 220. Each of the repeating vertical levels L1, L2, and L3 may contain multiple discrete components (e.g., regions) of a laterally oriented access device 230 (e.g., transistor) and a memory node (e.g., a capacitor) containing access lines 203-1, 203-2, ..., 203-Q connections and digital lines 207-1, 207-2, ..., 207-Q connections. (See the following text for further details.) Figure 4 In more detail, multiple discrete components of the lateral orientation access device 230 (e.g., transistors) can be formed in multiple iterations of a vertically repeating layer within each level, and can be formed in a second direction (D2) 205 (similar to...). Figure 2A It extends horizontally in the second direction (D2)205 shown.

[0067] Multiple discrete components of a lateral access device 230 (e.g., a transistor) may include a first source / drain region 221 and a second source / drain region 223 separated by a channel region 225, extending laterally in a second direction (D2) 205 and formed within the body of the access device. In some embodiments, the channel region 225 may comprise silicon, germanium, silicon-germanium, and / or indium gallium zinc oxide (IGZO). In some embodiments, the first source / drain region 221 and the second source / drain region 223 may comprise an n-type dopant region formed within a p-type doped body of the access device to form an n-type conductive transistor. In some embodiments, the first source / drain region 221 and the second source / drain region 223 may comprise a p-type dopant formed within an n-type doped body of the access device to form a p-type conductive transistor. By way of example, but not limitation, the n-type dopant may comprise phosphorus (P) atoms, and the p-type dopant may comprise boron (B) atoms formed in a relative doped body region of a polycrystalline silicon semiconductor material. However, the embodiments are not limited to these examples.

[0068] Storage node 227 (e.g., a capacitor) can be connected to a corresponding terminal of the access device. For example... Figure 2B As shown, storage node 227 (e.g., a capacitor) may be connected to the second source / drain region 223 of the access device. A storage node may be or contain a memory element capable of storing data. Each of the storage nodes may be a memory element using one of a capacitor, a magnetic tunnel junction pattern, and / or a variable resistor body containing a phase change material, etc. However, embodiments are not limited to these examples. In some embodiments, with unit cells (e.g., Figure 2A The memory node associated with each access device of the memory cell 210 in the second direction (D2) 205 (similar to Figure 2A It extends in the second direction (D2) 205 shown.

[0069] like Figure 2B As shown, multiple horizontally oriented digital lines 207-1, 207-2, ..., 207-Q are in the first direction (D1) 209 (similar to...). Figure 2A Extending along the first direction (D1) 209). Multiple horizontally oriented digital lines 207-1, 207-2, ..., 207-Q can be similar to... Figure 2A The digital lines 207-1, 207-2, ..., 207-Q are shown. Multiple horizontally oriented digital lines 207-1, 207-2, ..., 207-Q may be arranged (e.g., "stacked") along a third direction (D3) 211. The multiple horizontally oriented digital lines 207-1, 207-2, ..., 207-Q may contain a conductive material. For example, the conductive material may contain one or more of the following: doped semiconductors (e.g., doped silicon, doped germanium, etc.), conductive metal nitrides (e.g., titanium nitride, tantalum nitride, etc.), metals (e.g., tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), cobalt (Co), molybdenum (Mo), etc.), and / or metal semiconductor compounds (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.). However, the embodiments are not limited to these examples.

[0070] In each of the vertical hierarchies (L1)213-1, (L2)213-2, and (L3)213-P, the horizontally oriented memory cell (e.g., Figure 2A The memory cells 210 in the memory may be horizontally spaced apart from each other in the first direction (D1) 209. However, as described below... Figure 4As described in more detail, a plurality of discrete components of the laterally oriented access device 230 extending laterally in the second direction (D2) 205 (e.g., the first source / drain region 221 and the second source / drain region 223 separated by the channel region 225) and a plurality of horizontally oriented digital lines 207-1, 207-2, ..., 207-Q extending laterally in the first direction (D1) 209 may be formed in different vertical layers within each level. For example, the plurality of horizontally oriented digital lines 207-1, 207-2, ..., 207-Q extending laterally in the first direction (D1) 209 may be disposed on and electrically contacted with the top surface of the first source / drain region 221 and orthogonal to the laterally oriented access device 230 extending laterally in the second direction (D2) 205 (e.g., transistors). In some embodiments, a plurality of horizontally oriented digital lines 207-1, 207-2, ..., 207-Q extending in the first direction (D1) 209 are formed in a vertical layer, higher than the layer forming the discrete components of the lateral access device (e.g., the first source / drain region 221 and the second source / drain region 223 separated by the channel region 225), away from the substrate 200. In some embodiments, the plurality of horizontally oriented digital lines 207-1, 207-2, ..., 207-Q extending in the first direction (D1) 209 may be directly and / or connected to the top surface of the first source / drain region 221 via additional contacts comprising metal silicide.

[0071] like Figure 2B As shown in the example embodiments, access lines 203-1, 203-2, ..., 203-Q extend vertically relative to substrate 200 (e.g., on third-direction (D3) 211). Furthermore, as... Figure 2B As shown, a sub-cell array (e.g., Figure 2A Access lines 203-1, 203-2, ..., 203-Q in the sub-cell array 201-2 can be spaced apart from each other in a first direction (D1) 209. Access lines 203-1, 203-2, ..., 203-Q can be configured to extend vertically between a pair of laterally oriented access devices 230 (e.g., transistors) extending laterally along a second direction (D2) 205 in a third direction (D3) 211 relative to the substrate 200, but adjacent to each other in a certain level (e.g., a first level (L1)) in the first direction (D1) 209. Each of access lines 203-1, 203-2, ..., 203-Q can extend vertically in a third direction (D3) on the sidewall of the corresponding of a plurality of vertically stacked laterally oriented access devices 230 (e.g., transistors).

[0072] For example, and such Figure 3A and 3BAs shown in more detail, the first of the vertically extending access lines (e.g., 203-1) may be adjacent to the sidewall of the channel region 225 of the first lateral access device 230 (e.g., transistor) in the first level (L1) 213-1, the sidewall of the channel region 225 of the first lateral access device 230 (e.g., transistor) in the second level (L2) 213-2, and the sidewall of the channel region 225 of the first lateral access device 230 (e.g., transistor) in the third level (L3) 213-P, etc. Similarly, the second vertically extending access line (e.g., 203-2) may be adjacent to the sidewall of the channel region 225 of the second laterally oriented access device 230 (e.g., transistor) in the first level (L1) 213-1, and spaced apart from the first laterally oriented access device 230 (e.g., transistor) in the first direction (D1) 209. Furthermore, the second vertically extending access line (e.g., 203-2) may be adjacent to the sidewall of the channel region 225 of the second laterally oriented access device 230 (e.g., transistor) in the second level (L2) 213-2, and the sidewall of the channel region 225 of the second laterally oriented access device 230 (e.g., transistor) in the third level (L3) 213-P, etc. The embodiments are not limited to a specific number of levels.

[0073] The vertically extending access lines 203-1, 203-2, ..., 203-Q may contain conductive materials, such as doped semiconductor materials, conductive metal nitrides, metals, and / or metal-semiconductor compounds. Access lines 203-1, 203-2, ..., 203-Q may correspond to... Figure 2A The word line (WL) of the description.

[0074] like Figure 2B As shown in the example embodiment, conductive body contacts 295 may be formed on the end surface of the laterally oriented access device 230 (e.g., a transistor) extending in a first direction (D1) 209 in each layer (L1) 213-1, (L2) 213-2, and (L3) 213-P above the substrate 200. The body contacts 295 may be connected to each memory cell (e.g., Figure 2A The body of the lateral access device 230 (e.g., a transistor) in the memory cell 210) (as in the memory cell 210) Figure 3A and 3B (as shown in 336) (e.g., the body region). Body contact 295 may contain a conductive material, such as a doped semiconductor material, a conductive metal nitride, a metal, and / or a metal-semiconductor compound.

[0075] although Figure 2BNot shown, but insulating material may fill other spaces in the vertically stacked memory cell array. For example, the insulating material may comprise one or more of silicon oxide, silicon nitride, and / or silicon oxynitride. However, the embodiments are not limited to these examples.

[0076] Figure 3A A vertically stacked memory cell array according to some embodiments of the present disclosure is shown in more detail (e.g., Figure 1A and 1B The unit cells (e.g., within the sub-unit array 101-2) in the sub-unit array 101-2 Figure 1A and 1B (Memory unit 110 in the middle). For example Figure 3A As shown, the first source / drain region 321 and the second source / drain region 323 can be impurity-doped regions of the lateral access device 330 (e.g., a transistor). The first source / drain region 321 and the second source / drain region 323 can be similar to... Figure 2A and 2B The first source / drain region 221 and the second source / drain region 223 are shown. The first and second source / drain regions may be separated by a channel 325 formed in a body (e.g., a body region) of the semiconductor material of the horizontally oriented access device 330 (e.g., a transistor). The first source / drain region 321 and the second source / drain region 323 may be formed by an n-type or p-type dopant doped in the body region. Embodiments are not limited thereto.

[0077] For example, in an n-type conductive transistor configuration, the body region of the lateral access device 330 (e.g., a transistor) can be formed of a lightly doped p-type (p-) semiconductor material. In one embodiment, the body region and the channel 325 separating the first source / drain region 321 and the second source / drain region 323 may comprise a lightly doped p-type (e.g., low dopant concentration (p-)) polysilicon (Si) material composed of boron (B) atoms as impurity dopants for polysilicon. The first source / drain region 321 and the second source / drain region 323 may also comprise metals and / or metal composite materials formed using atomic layer deposition processes, etc., containing at least one of the following: ruthenium (Ru), molybdenum (Mo), nickel (Ni), titanium (Ti), copper (Cu), a highly doped degenerate semiconductor material, and / or indium oxide (In₂O₃) or indium tin oxide (In₂-xSnxO₃). However, the embodiments are not limited to these examples. As used herein, degenerate semiconductors refer to semiconductor materials, such as polycrystalline silicon, that contain high levels of doping that utilize significant interactions between dopants such as phosphorus (P), boron (B), etc. In contrast, non-degenerate semiconductors contain moderate levels of doping, where dopant atoms are well separated from each other in the semiconductor host lattice with negligible interactions.

[0078] In this example, the first source / drain region 321 and the second source / drain region 321 may contain highly doped n-type conductive impurities (e.g., highly doped (n+)) doped into the first source / drain region 321 and the second source / drain region 323. In some embodiments, the highly doped n-type conductive first drain region 321 and the second drain region 323 may contain a high concentration of phosphorus (P) atoms deposited therein. However, the embodiments are not limited to this example. In other embodiments, the horizontally oriented access device 330 (e.g., a transistor) may have a p-type conductive configuration, in which case the conductivity type of the impurity (e.g., the dopant) will be reversed.

[0079] like Figure 3A As shown in the example embodiment, the first source / drain region 321 may occupy the upper portion of the body of the lateral access device 330 (e.g., a transistor). For example, the first source / drain region 321 may have a bottom surface within the body of the lateral access device 330 that is vertically higher in the third direction (D3) 311 compared to the bottom surface of the body of the lateral access device 330. Thus, the lateral transistor 330 may have a body portion located below the first source / drain region 321 and in electrical contact with the body contacts. Furthermore, as Figure 3A As shown in the example implementation, similar to Figure 2A and 2B Access lines 207-1, 207-2, ..., 207-Q and Figure 1A and 1B The access lines 107-1, 107-2, ..., 107-Q (e.g., 307-1) shown may be disposed opposite to and coupled to the top surface of the channel region 325, separated from it by the gate dielectric 304. The gate dielectric material 304 may comprise, for example, a high-k dielectric material, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. Embodiments are not limited thereto. For example, in the high-k dielectric material example, the gate dielectric material 304 may comprise one or more of the following: hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, etc.

[0080] like Figure 3A As shown in the example embodiment, in the body of a horizontally oriented access device 330 (e.g., a transistor) that is horizontally conductive between the first source / drain region 321 and the second source / drain region 323 along the second direction (D2) 305, similar to Figure 2A and 2B The digital lines 203-1, 203-2, ..., 203-Q and Figure 1A and 1BThe digital lines 103-1, 103-2, ..., 103-Q (e.g., 303-1) may extend vertically in a third direction (D3) 311 adjacent to the sidewall of the first source / drain region 321. In this embodiment, the vertically oriented digital line 303-1 is asymmetrically formed adjacent to the first source / drain region 321 in electrical contact. The digital line 303-1 may be asymmetrically formed to reserve space for the body contact in the channel region 325.

[0081] Figure 3B A vertically stacked memory cell array according to some embodiments of the present disclosure is shown in more detail (e.g., Figure 1A and 1B The unit cells (e.g., within the sub-unit array 101-2) in the sub-unit array 101-2 Figure 1A-1B (Memory unit 110 in the middle). For example Figure 3B As shown, the first source / drain region 321 and the second source / drain region 323 can be impurity-doped regions of the lateral access device 330 (e.g., a transistor). The first source / drain region 321 and the second source / drain region 323 can be similar to... Figure 2A and 2B The first source / drain region 221 and the second source / drain region 223 shown are as follows: Figure 3A The first source / drain region 321 and the second source / drain region 323 are shown. The first and second source / drain regions may be separated by a channel 325 formed in a body (e.g., a body region) of the semiconductor material of the horizontally oriented access device 330 (e.g., a transistor). The first source / drain region 321 and the second source / drain region 323 may be formed by an n-type or p-type dopant doped in the body region. Embodiments are not limited thereto.

[0082] like Figure 3B As shown in the example embodiment, in the body of a horizontally oriented access device 330 (e.g., a transistor) that is horizontally conductive between the first source / drain region 321 and the second source / drain region 323 along the second direction (D2) 305, similar to Figure 2A and 2B The digital lines 203-1, 203-2, ..., 203-Q and Figure 1A and 1B The digital lines 103-1, 103-2, ..., 103-Q (e.g., 303-1) may extend vertically in a third direction (D3) 311 adjacent to the sidewall of the first source / drain region 321. In this embodiment, the vertically oriented digital lines 303-1 are symmetrically formed in a vertically aligned manner to make electrical contact with the first source / drain region 321. The digital lines 303-1 may be formed in contact with an insulating material, such that there are no body contacts within the channel 325.

[0083] like Figure 3BAs shown in the example embodiment, digital line 303-1 can be symmetrically formed within a first source / drain region 321, such that the first source / drain region 321 surrounds the digital line 303-1. The first source / drain region 321 can occupy the upper portion of the body of the lateral orientation access device 330 (e.g., a transistor). For example, the first source / drain region 321 can have a bottom surface within the body of the lateral orientation access device 330, which is vertically higher in a third direction (D3) 311 compared to the bottom surface of the body of the lateral orientation access device 330. Thus, the lateral orientation transistor 330 can have a body portion located below the first source / drain region 321 and in contact with the body contacts. An insulating material can fill the body contacts so that the first source / drain region 321 is not electrically in contact with the channel 325. Furthermore, as Figure 3B As shown in the example implementation, similar to Figure 2A and 2B Access lines 207-1, 207-2, ..., 207-Q and Figure 1A and 1B The access lines (e.g., 307-1) shown as 107-1, 107-2, ..., 107-Q can be disposed around and coupled to the channel region 325, and separated from it by the gate dielectric 304.

[0084] Figure 4 It is used in, for example Figure 1A-3B A cross-sectional view of a stage of a semiconductor manufacturing process for forming epitaxial silicon within a horizontal access device in a vertical three-dimensional (3D) memory shown and according to several embodiments of the present disclosure.

[0085] exist Figure 4 In the example embodiments shown, the method includes epitaxially forming alternating layers of silicon germanium (SiGe) materials 430-1, 430-2, ..., 430-N (collectively referred to as epitaxially grown silicon germanium (SiGe) 430) and silicon (Si) materials 432-1, 432-2, ..., 432-N (collectively referred to as epitaxially grown single-crystal silicon (Si) material 432) on the working surface of a semiconductor substrate 400 to form a vertical stack 401. In one embodiment, the epitaxially grown silicon germanium (SiGe) 430 may be deposited to have a thickness (e.g., vertical height) in the third direction (D3) ranging from thirty (30) nanometers (nm). In one embodiment, silicon 432 may be deposited to have a thickness (t2) (e.g., vertical height) ranging from five (5) nm to thirty (30) nm. However, the embodiments are not limited to these examples. Figure 4 As shown, vertical direction 411 is shown as... Figure 1A-3BThe third direction (D3) shown in the first, second and third directions is similar to the third direction (D3) in the xyz coordinate system, such as the z direction.

[0086] In some embodiments, the epitaxially grown silicon-germanium (SiGe) 430-1, 430-2, ..., 430-N may be a mixture of epitaxially grown silicon and germanium. By way of example and not limitation, the epitaxially grown silicon-germanium (SiGe) 430 may be grown on substrate material 400. Embodiments are not limited to these examples. In some embodiments, the epitaxially grown single-crystal silicon (Si) materials 432-1, 432-2, ..., 432-N may include polycrystalline silicon and / or amorphous silicon (Si) materials. The epitaxially grown single-crystal silicon (Si) materials 432-1, 432-2, ..., 432-N may be lightly doped, p-type (p-) epitaxially grown single-crystal silicon (Si) materials. Silicon materials 432-1, 432-2, ..., 432-N may also be formed by epitaxial growth on epitaxially grown silicon-germanium (SiGe) 430. After forming the epitaxially grown silicon-germanium (SiGe) 430, the seed crystal is converted into pure silicon. However, the embodiments are not limited to these examples.

[0087] Alternating layers of epitaxially grown silicon germanium (SiGe) 430-1, 430-2, ..., 430-N and epitaxially grown single-crystal silicon (Si) material 432-1, 432-2, ..., 432-N can be deposited according to a semiconductor manufacturing process (e.g., chemical vapor deposition (CVD) in a semiconductor manufacturing apparatus). However, the embodiments are not limited to this example, and other suitable semiconductor manufacturing techniques can be used to deposit alternating layers of epitaxially grown silicon germanium (SiGe) and epitaxially grown single-crystal silicon (Si) material in repeated iterations to form a vertical stack 401.

[0088] These layers may appear in a vertically repeating iterative manner. Figure 4 In the example, three layers of repeated iterations are shown, numbered 1, 2, and 3. For example, in another repeated iteration, the stack may include: a first epitaxially grown silicon-germanium (SiGe) 430-1, a first epitaxially grown single-crystal silicon (Si) material 432-1, a second epitaxially grown silicon-germanium (SiGe) 430-2, a second epitaxially grown single-crystal silicon (Si) material 432-2, a third SiGe material 430-3, and a third epitaxially grown single-crystal silicon (Si) material 432-3. However, the embodiments are not limited to this example and may include more or fewer repeated iterations.

[0089] Figure 5A Showing for use in, for example Figure 1A-3BAn example method of a stage of a semiconductor manufacturing process for forming epitaxial silicon within a horizontal access device in a vertical three-dimensional (3D) memory, as shown and according to several embodiments of the present disclosure. Figure 5A A top view of a semiconductor structure at a specific point in time during a semiconductor manufacturing process according to one or more embodiments is shown. Figure 5A In the example embodiment shown, the method includes forming a plurality of first vertical openings 515 through a vertical stack to a substrate using an etchant process, having a first horizontal direction (D1) 509 and a second horizontal direction (D2) 505. In one example, as Figure 5A As shown, a plurality of first vertical openings 515 extend primarily in the second horizontal direction (D2) 505 and can be formed in a vertical stack of elongated vertical columns 513-1, 513-2, ..., 513-M (collectively and / or individually referred to as 513) having sidewalls 514. The plurality of first vertical openings 500 can be formed by patterning a photomask 535 (e.g., forming a hard mask (HM)) on the vertical stack using photolithography prior to etching the plurality of first vertical openings 515. Similar semiconductor process techniques can be used at other points in the semiconductor manufacturing process described herein.

[0090] The opening 515 can be filled with a dielectric material 539. In one example, the opening 515 can be filled using a spin dielectric process. In one embodiment, the dielectric material 539 can be an oxide material. However, the embodiments are not limited thereto.

[0091] Figure 5B It is along Figure 5A The cross-sectional view taken by the cutting line A-A' in the figure shows another view of the semiconductor structure at a specific time in the semiconductor manufacturing process. Figure 5B The cross-sectional view shown illustrates repeated iterations of alternating layers of epitaxially grown silicon germanium (SiGe) 530 and epitaxially grown single-crystal silicon (Si) material 532 on a semiconductor substrate 500 to form a vertical stack (e.g., Figure 4 401 shown).

[0092] like Figure 5BAs shown, multiple first vertical openings can be formed through layers within the vertically stacked memory cells to expose the vertical sidewalls in the vertical stack and form elongated vertical columns 513, which are then filled with a first dielectric material 539. The first vertical openings can be formed through repeated iterations of epitaxially grown silicon-germanium (SiGe) 530 and epitaxially grown single-crystal silicon (Si) material 532. Therefore, the first vertical openings can be formed through the first epitaxially grown silicon-germanium (SiGe) 530-1, the first epitaxially grown single-crystal silicon (Si) material 532-1, the second epitaxially grown silicon-germanium (SiGe) 530-2, the second epitaxially grown single-crystal silicon (Si) material 532-2, the third SiGe material 530-3, and the third epitaxially grown single-crystal silicon (Si) material 532-3. However, the embodiments are not limited to these examples. Figure 5B The vertical opening is shown. Multiple vertical openings can be formed through the material layer. A first vertical opening can be formed to expose the vertical sidewalls in the vertical stack. The first vertical opening can extend in the second horizontal direction (D2) 505 to form an elongated column of vertical columns with the first vertical sidewalls in the vertical stack, and then be filled with a third dielectric 539.

[0093] like Figure 5B As shown, a first dielectric material 539, such as an oxide or other suitable spin dielectric (SOD), can be deposited in the first vertical opening using a process such as CVD to fill the first vertical opening. The first dielectric material 539 may also be formed from silicon nitride (Si3N4) material. In another example, the first dielectric material 539 may comprise silicon oxynitride (SiO2). x N y (and / or combinations thereof.) Embodiments are not limited to these examples. Multiple first vertical openings can be formed by patterning a photolithographic mask 535 (e.g., forming a hard mask (HM)) on a vertical stack using photolithography techniques prior to etching the multiple first vertical openings. In one embodiment, the hard mask 535 can be deposited on epitaxially grown silicon germanium (SiGe) 530. Similar semiconductor process techniques can be used at other points in the semiconductor manufacturing process described herein.

[0094] Figure 6A An example method is shown for another stage of a semiconductor manufacturing process for forming epitaxial silicon within a horizontal access device in a vertical three-dimensional (3D) memory according to several embodiments of the present disclosure. Figure 6A A top view of a semiconductor structure at a specific point in time during a semiconductor manufacturing process according to one or more embodiments is shown. Figure 6AIn the example embodiment shown, the method includes using an etchant process to pattern and selectively remove a first dielectric material 639 from a plurality of first vertical openings to expose second vertical sidewalls adjacent to a first region of epitaxially grown silicon-germanium (SiGe), forming a plurality of spaced-apart second vertical openings 631 through a vertical stack. The plurality of second vertical openings 631 can be formed through a material layer. In one example, such as Figure 6A As shown, the spaced-apart second vertical openings 631 extend primarily in the first horizontal direction (D2) 609 and can form short vertical squares within a plurality of adjacent vertically stacked first vertical openings 615. The second vertical openings 631 can be formed by patterning the first dielectric material 639 using photolithography to form openings within the vertical stack prior to etching the plurality of first vertical openings 615.

[0095] Figure 6B It is along Figure 6A The cross-sectional view taken by the cutting line A-A' in the figure shows another view of the semiconductor structure at a specific time in the semiconductor manufacturing process. Figure 6B The cross-sectional view shown illustrates repeated iterations of alternating layers of silicon-germanium (SiGe) 630 and silicon material 632 epitaxially grown on semiconductor substrate 600 to form a vertical stack (e.g., Figure 4 401 shown).

[0096] like Figure 6B As shown, multiple first vertical openings can be formed through layers within a vertically stacked memory cell to expose the vertical sidewalls in the vertical stack. First vertical openings 615 can be formed through repeated iterations of epitaxially grown silicon-germanium (SiGe) 630 and epitaxially grown single-crystal silicon (Si) material 632. Therefore, first vertical openings 615 can be formed through the first epitaxially grown silicon-germanium (SiGe) 630-1, the first epitaxially grown single-crystal silicon (Si) material 632-1, the second epitaxially grown silicon-germanium (SiGe) 630-2, the second epitaxially grown single-crystal silicon (Si) material 632-2, the third epitaxially grown silicon-germanium (SiGe) 630-3, and the third epitaxially grown single-crystal silicon (Si) material 632-3. However, the embodiments are not limited to these examples. Figure 6B The vertical opening shown. Multiple vertical openings can be formed through the material layer. A first vertical opening can be formed to expose the vertical sidewalls in the vertical stack. The first vertical opening can extend in the second horizontal direction (D2)605 to form an elongated vertical column with the first vertical sidewalls in the vertical stack.

[0097] like Figure 6BAs shown, a first dielectric material 639, such as an oxide or other suitable spin dielectric (SOD), can be deposited in the first vertical opening using a process such as CVD to fill the first vertical opening. A photolithographic material 635 (e.g., a hard mask) can be deposited on the vertical stack using CVD and planarized using chemical mechanical planarization (CMP). Similar semiconductor process techniques can be used at other points in the semiconductor manufacturing process described herein.

[0098] Figure 6C It is along Figure 6A The cross-sectional view taken by the cutting line B-B' in the figure shows the method used to form, for example Figure 1A-3B Another view of the semiconductor structure at this particular point in a semiconductor manufacturing process, showing an example of a vertical digital line of a semiconductor device having a horizontally oriented access device and a horizontally oriented access line according to several embodiments of the present disclosure.

[0099] like Figure 6C As shown, a vertical stack may include repeated iterations of epitaxially grown silicon germanium (SiGe) 630 and epitaxially grown silicon (Si) material 632. Therefore, a vertical stack can be formed using a first epitaxially grown silicon germanium (SiGe) 630-1, a first epitaxially grown single-crystal silicon (Si) material 632-1, a second epitaxially grown silicon germanium (SiGe) 630-2, a second epitaxially grown single-crystal silicon (Si) material 632-2, a third epitaxially grown silicon germanium (SiGe) 630-3, and a third epitaxially grown single-crystal silicon (Si) material 632-3. A CVD-deposited photolithography material 635 (e.g., a hard mask) and planarization using chemical mechanical planarization (CMP) can be used to cover the vertical stack. Similar semiconductor process techniques can be used at other points in the semiconductor manufacturing process described herein.

[0100] Figure 6D Show along Figure 6A The cross-sectional view taken by the cutting line C-C' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 6D The cross-sectional diagram shown extends in the second horizontal direction (D2) 605 outside the area of ​​the horizontally oriented access device and the horizontally oriented storage node.

[0101] exist Figure 6DIn the first vertical opening, a first dielectric material 639, such as oxide or other suitable spin dielectric (SOD), can be deposited using a process such as CVD. The first dielectric material 639 is shown spaced along a first direction (D1) extending into and from the drawing plane of the three-dimensional array of vertically oriented memory cells. The first dielectric material 639 can be seen along the repeating iterative axis of alternating layers of epitaxially grown silicon germanium (SiGe) 630 and epitaxially grown single-crystal silicon (Si) material 632. A hard mask 635, which can be deposited using CVD and planarized using chemical mechanical planarization (CMP), can be seen on the vertical stack. Specific areas can be patterned and exposed on the vertical stack using photolithography. Similar semiconductor process techniques can be used at other points in the semiconductor manufacturing process described herein. Using such techniques, a portion of the first dielectric material 639 can be patterned and exposed to etch a portion of the first dielectric material in a vertical direction, thereby selectively removing a portion of the first dielectric material 639 in a plurality of first vertical openings 631 to expose the sidewalls of a first region adjacent to the epitaxially grown silicon germanium (SiGe) 630.

[0102] Figure 6E Show along Figure 6A The cross-sectional view taken by the cutting line D-D' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 6E The cross-sectional diagram shown is an extension of the repeating iterative axis along the first direction (D1) 609 from right to left in the drawing plane, along the alternating layers of epitaxially grown silicon germanium (SiGe) 630 and epitaxially grown single-crystal silicon (Si) material 632.

[0103] In this cross-sectional view, a second vertical opening 631 can be seen through repeated iterations of alternating layers of epitaxially grown silicon-germanium (SiGe) 630 and epitaxially grown single-crystal silicon (Si) material 632, allowing etching to pass through these alternating layers. Figure 6E In this embodiment, a second vertical opening 631 can be formed by repeated iterations of epitaxially grown silicon-germanium (SiGe) 630 and epitaxially grown single-crystal silicon (Si) material 632. Therefore, the second vertical opening 631 can be formed by passing through the first epitaxially grown silicon-germanium (SiGe) 630-1, the first epitaxially grown single-crystal silicon (Si) material 632-1, the second epitaxially grown silicon-germanium (SiGe) 630-2, the second epitaxially grown single-crystal silicon (Si) material 632-2, the third epitaxially grown silicon-germanium (SiGe) 630-3, and the third epitaxially grown single-crystal silicon (Si) material 632-3. However, the embodiment is not limited to this. Figure 6EThe vertical opening shown can be formed by passing through the material layer.

[0104] Figure 7A Showing for use in, for example Figure 1A-3B This is an example method of another stage of a semiconductor manufacturing process for forming epitaxial silicon within a horizontal access device in a vertical three-dimensional (3D) memory, as shown in and according to several embodiments of the present disclosure. Figure 7A A top view of a semiconductor structure at a specific point in time during a semiconductor manufacturing process according to one or more embodiments is shown. Figure 7A In the illustrated embodiment, the method includes extending second vertical openings 731 by selectively etching a first dielectric material 739 filled in a plurality of first vertical openings 715 having a first horizontal direction (D1) 709 and a second horizontal direction (D2) 705, a portion of epitaxially grown silicon-germanium (SiGe) 730 through a vertically stacked structure, and a portion of a hard mask surface 735 connecting the plurality of first vertical openings 715 using an etchant process. The plurality of second vertical openings 731 can be formed through the material layers. The plurality of first vertical openings 715 can be observed within the hard mask 735 covering the working surface of the vertical semiconductor stack.

[0105] Figure 7B It is along Figure 7A The cross-sectional view taken by the cutting line A-A' in the figure shows another view of the semiconductor structure at a specific time in the semiconductor manufacturing process. Figure 7B The cross-sectional view shown illustrates the repeated iterations of alternating layers of silicon germanium (SiGe) 730 epitaxially grown on semiconductor substrate 715 and epitaxially grown single-crystal silicon (Si) material 732.

[0106] like Figure 7B As shown, multiple first vertical openings can be formed through layers within a vertically stacked memory cell to expose the vertical sidewalls in the vertical stack. The first vertical openings can be formed through repeated iterations of epitaxially grown silicon-germanium (SiGe) 730 and epitaxially grown single-crystal silicon (Si) material 732. Therefore, the first vertical openings can be formed through the first epitaxially grown silicon-germanium (SiGe) 730-1, the first epitaxially grown single-crystal silicon (Si) material 732-1, the second epitaxially grown silicon-germanium (SiGe) 730-2, the second epitaxially grown single-crystal silicon (Si) material 732-2, the third epitaxially grown silicon-germanium (SiGe) 730-3, and the third epitaxially grown single-crystal silicon (Si) material 732-3. However, the embodiments are not limited to these examples. Figure 7B The vertical opening shown. Multiple vertical openings can be formed through the material layer. A first vertical opening can be formed to expose the vertical sidewalls in the vertical stack. The first vertical opening can extend in the first horizontal direction (D1) 709 to form an elongated vertical column with the first vertical sidewalls in the vertical stack.

[0107] like Figure 7B As shown, a first dielectric material 739, such as an oxide or other suitable spin dielectric (SOD), filling the first vertical opening can be observed. A hard mask 735 can be deposited on the vertical stack. Similar semiconductor process techniques can be used at other points in the semiconductor manufacturing process described herein.

[0108] Figure 7C It is along Figure 7A A cross-sectional view taken by the cutting line B-B' in the figure, showing the use in, for example Figure 1A-3B Another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process in which epitaxial silicon is formed within a horizontal access device in a vertical three-dimensional (3D) memory shown and according to several embodiments of the present disclosure.

[0109] The epitaxially grown silicon-germanium (SiGe) 730 can be selectively etched isotropically to form multiple first horizontal openings 773 in a first region to separate layers of Si material 732. Etching agent can flow into a second vertical opening 731 to selectively etch a portion of the epitaxially grown silicon-germanium (SiGe) 730 within and outside the stack. Therefore, the etchant can target the first epitaxially grown silicon-germanium (SiGe) 730-1, the second epitaxially grown silicon-germanium (SiGe) 730-2, and the third epitaxially grown silicon-germanium (SiGe) 730-3 within the stack. The selective etchant process can etch the epitaxially grown silicon-germanium (SiGe) 730 to form multiple first horizontal openings 773.

[0110] Selective etchant processes may include selectively etching chemicals using phosphoric acid (H3PO4) or hydrogen fluoride (HF) and / or using selective solvents and other possible etch chemicals or solvents to dissolve epitaxially grown silicon germanium (SiGe) 730. Alternatively or additionally, selective etching for removing epitaxially grown silicon germanium (SiGe) 730 may include one or more etch chemicals selected from aqueous etch chemicals, semi-aqueous etch chemicals, vapor etch chemicals, or plasma etch chemicals and other possible selective etch chemicals. For example, dry etch chemicals using oxygen (O2) or O2 and sulfur dioxide (SO2) may be used. As another example, dry etch chemicals using O2 or O2 and nitrogen (N2) may be used to selectively etch epitaxially grown silicon germanium (SiGe) 730.

[0111] Figure 7D Show along Figure 7A The cross-sectional view taken by the cutting line C-C' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 7DThe cross-sectional diagram shown extends in a second horizontal direction (D2) 705 between adjacent areas of the horizontally oriented access device and the horizontally oriented storage node, and in the space separating the adjacent areas.

[0112] exist Figure 7D In the diagram, the first dielectric material 739 is shown filling the space longitudinally along the second direction (D2) 705, but separated from the adjacent access devices and memory nodes of the three-dimensional array of vertically oriented memory cells extending into and from the drawing plane in the first direction (D1). The first dielectric material 739 can be seen along the repeating iterative axis of alternating layers of epitaxially grown silicon germanium (SiGe) 730 and epitaxially grown single-crystal silicon (Si) material 732. A portion of the first dielectric material 739 may be etched in the vertical direction to reflect the second vertical opening 731. Figure 7D The cross-sectional illustration shown is a right-to-left view in the drawing plane, extending along the repeating iterative axis of the alternating layers of epitaxially grown silicon-germanium (SiGe) 730 and epitaxially grown single-crystal silicon (Si) material 732 in a second direction (D2) 705. A hard mask 735 can be seen on the vertical stack, which can be planarized using CVD deposition and chemical mechanical planarization (CMP). Similar semiconductor process techniques can be used at other points in the semiconductor manufacturing process described herein.

[0113] Figure 7E Show along Figure 7A The cross-sectional view taken by the cutting line D-D' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 7E The cross-sectional diagram shown is extended from right to left in the first direction (D1)709 on the drawing plane.

[0114] exist Figure 7E In this view, the epitaxially grown silicon-germanium (SiGe) has been selectively etched isotropically, so that the epitaxially grown silicon-germanium (SiGe) is completely etched. Alternating layers of epitaxially grown single-crystal silicon (Si) material 732 can be observed. An opening formed by the etched second vertical opening 731 can be formed through repeated iterations of the epitaxially grown single-crystal silicon (Si) material 732. Therefore, the first vertical opening 731 can be formed through the first epitaxially grown single-crystal silicon (Si) material 732-1, the second epitaxially grown single-crystal silicon (Si) material 732-2, and the third epitaxially grown single-crystal silicon (Si) material 732-3. However, the embodiments are not limited to this. Figure 7E The vertical opening is shown. Multiple second vertical openings can be formed through the material layer. A hard mask 735 can be deposited using CVD and planarized using chemical mechanical planarization (CMP) to cover the vertical stack. A hard mask 737 covering the vertical stack can be etched through the first vertical opening 731 in the same manner.

[0115] Figure 8A Showing for use in, for example Figure 1A-3B This is an example method of another stage of a semiconductor manufacturing process for forming epitaxial silicon within a horizontal access device in a vertical three-dimensional (3D) memory, as shown in and according to several embodiments of the present disclosure. Figure 8A A top view of a semiconductor structure at a specific point in time during a semiconductor manufacturing process according to one or more embodiments is shown.

[0116] exist Figure 8A In the illustrated embodiment, the method includes depositing a newly deposited second dielectric material 833 through the second vertical opening 831 on the exposed surface of the second vertical opening 831 and on the exposed surface of the epitaxially grown silicon (Si) material 832 within the first horizontal opening 873. Figure 8B A portion of the first dielectric material 839 that has not been etched is visible in the image.

[0117] Figure 8B It is along Figure 8A The cross-sectional view taken by the cutting line A-A' in the figure shows another view of the semiconductor structure at a specific time in the semiconductor manufacturing process. Figure 8B The cross-sectional view shown illustrates the repeated iterations of alternating layers of silicon germanium (SiGe) 830 and epitaxially grown single-crystal silicon (Si) material 832 epitaxially grown on a semiconductor substrate 800.

[0118] like Figure 8B As shown, multiple first vertical openings have been formed through layers within the vertically stacked memory cells to expose the vertical sidewalls of the vertical stack. Figures 6A-6E In the process, the first vertical opening is formed by repeated iterations through epitaxially grown silicon germanium (SiGe) 830 and epitaxially grown single-crystal silicon (Si) material 832.

[0119] like Figure 8B As shown, a first dielectric material 839, such as an oxide or other suitable spin dielectric (SOD), is shown in the first vertical opening 815, used to fill the first vertical opening. A hard mask 835 is shown deposited on a vertical stack. Figure 8B The newly deposited second dielectric material 833 can also be observed on the vertical stack in the cross-sectional view.

[0120] Figure 8C It is along Figure 8A The cross-sectional view taken by the cutting line B-B' in the figure shows the method used to form, for example Figure 1A-3B Another view of the semiconductor structure at this particular point in a semiconductor manufacturing process, showing an example of a vertical digital line of a semiconductor device having a horizontally oriented access device and a horizontally oriented access line according to several embodiments of the present disclosure.

[0121] The epitaxially grown silicon-germanium (SiGe) 830 has been isotropically selectively etched to form a plurality of first horizontal openings 873 in a first region, separating layers of Si material 832. A second dielectric material 833 is conformally deposited around the first horizontal openings 873. The second dielectric material 833 can completely surround the exposed surface deposits in the plurality of first horizontal openings 873. The second dielectric material 833 can be used as a pad around the plurality of first horizontal openings 873. The second dielectric material 833 can be allowed to flow into a second vertical opening 831 to cover the exposed surface of the epitaxially grown silicon (Si) material, wherein the epitaxially grown silicon-germanium (SiGe) is removed to form the plurality of first horizontal openings 873 within the stack.

[0122] In one embodiment, the second dielectric material 833 may comprise a nitride material. In another embodiment, the second dielectric material 833 may comprise a silicon nitride (Si3N4) material (also referred to herein as "SiN"). In another embodiment, the second dielectric material 833 may comprise a silicon dioxide (SiO2) material. In yet another embodiment, the second dielectric material 833 may comprise a silicon oxycarbide (SiOxCy) material and / or a combination thereof. Embodiments are not limited to these examples.

[0123] In one embodiment, the second dielectric material 833 may be conformally deposited around the exposed surface in a plurality of first horizontal openings 873 to have a density of approximately 100 to 300 angstroms. The thickness (t1). However, the embodiments are not limited to these examples.

[0124] Figure 8D Show along Figure 8A The cross-sectional view taken by the cutting line C-C' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 8D The cross-sectional diagram shown extends in the second horizontal direction (D2) 805 outside the area of ​​the horizontally oriented access device and the horizontally oriented storage node.

[0125] exist Figure 8D In the diagram, the first dielectric material 839 is shown as filling the space along the second direction (D2) 805 and separating the access device and storage node area of ​​the three-dimensional array of vertically oriented memory cells extending into and from the drawing plane. Figure 8DThe cross-sectional view shown is an iterative axis extending in the second direction (D2) 805 from right to left in the drawing plane along the alternating layers of epitaxially grown silicon-germanium (SiGe) 830 and epitaxially grown single-crystal silicon (Si) material 832. A portion of the first dielectric material 839 has been etched in the vertical direction within a plurality of first vertical openings 815 to form a second vertical opening 831 to expose the sidewalls of the first region adjacent to the epitaxially grown silicon-germanium (SiGe) 830. Here, a second dielectric material 833 can be deposited into the second vertical opening 831 to cover the sidewalls of the first dielectric material 839 and the exposed surfaces of the epitaxially grown silicon (Si) 830 within and outside the formed first horizontal opening 873. A hard mask 835 can be seen on the vertical stack.

[0126] Figure 8E Show along Figure 8A The cross-sectional view taken by the cutting line D-D' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 8E The cross-sectional diagram shown is an extension of the first direction (D1) 809 along the repeating iterative axis of the epitaxially grown silicon (Si) material 832, which conformally covers and bridges the first horizontal opening 873 with the second dielectric material 833, from right to left in the drawing plane.

[0127] exist Figure 8E In this view, the epitaxially grown silicon-germanium (SiGe) in the first horizontal opening 873 has been selectively etched isotropically, so that the epitaxially grown silicon-germanium (SiGe) is completely etched away. Alternating layers of epitaxially grown single-crystal silicon (Si) material 832 can be seen. A second dielectric material 833 is conformally deposited around the epitaxially grown single-crystal silicon (Si) material 832. Therefore, the second dielectric material 833 can be formed on the surfaces of the first epitaxially grown single-crystal silicon (Si) material 832-1, the second epitaxially grown single-crystal silicon (Si) material 832-2, and the third epitaxially grown single-crystal silicon (Si) material 832-3. The second dielectric material 833 can also be conformally deposited around the hard mask 835 in a manner similar to that of the epitaxially grown single-crystal silicon (Si) material 832 vertically stacked in the access device region in this cross-sectional view. The second dielectric material 833 can also be deposited on the substrate 800.

[0128] Figure 9A Showing for use in, for example Figure 1A-3B This is an example method of another stage of a semiconductor manufacturing process for forming epitaxial silicon within a horizontal access device in a vertical three-dimensional (3D) memory, as shown in and according to several embodiments of the present disclosure. Figure 9A A top view of a semiconductor structure at a specific point in time during a semiconductor manufacturing process according to one or more embodiments is shown.

[0129] exist Figure 9A In the illustrated embodiment, the method includes depositing a first dielectric material 939 to fill a first vertical opening 915. The first vertical opening 915 can be completely filled with the first dielectric material 939.

[0130] Figure 9B It is along Figure 9A The cross-sectional view taken by the cutting line A-A' in the figure shows another view of the semiconductor structure at a specific time in the semiconductor manufacturing process. Figure 9B The cross-sectional view shown illustrates the repeated iterations of alternating layers of silicon germanium (SiGe) 930 and epitaxially grown single-crystal silicon (Si) material 932 epitaxially grown on a semiconductor substrate 900.

[0131] like Figure 9B As shown, multiple first vertical openings 915 are formed through layers within the vertically stacked memory cells to expose the vertical sidewalls in the vertical stack, and are filled with a first dielectric material 939. These first vertical openings are formed through repeated iterations of epitaxially grown silicon-germanium (SiGe) 930 and epitaxially grown single-crystal silicon (Si) material 932. Therefore, Figure 9B A first vertical opening 915 is shown in a memory node region filled with a first dielectric material 939, which passes through a first epitaxially grown silicon-germanium (SiGe) 930-1, a first epitaxially grown single-crystal silicon (Si) material 932-1, a second epitaxially grown silicon-germanium (SiGe) 930-2, a second epitaxially grown single-crystal silicon (Si) material 932-2, a third epitaxially grown silicon-germanium (SiGe) 930-3, and a third epitaxially grown single-crystal silicon (Si) material 932-3. However, the embodiments are not limited to this. Figure 9B The vertical opening shown can be formed by passing through the material layer.

[0132] Figure 9C It is along Figure 9A A cross-sectional view taken by the cutting line B-B' in the figure, showing the use in, for example Figure 1A-3B Another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process in which epitaxial silicon is formed within a horizontal access device in a vertical three-dimensional (3D) memory, as shown in the illustration and according to several embodiments of the present disclosure.

[0133] like Figure 9CAs shown, a first dielectric material 939, such as an oxide or other suitable spin dielectric (SOD), is deposited into a plurality of first horizontal openings 973 on the exposed surface of a second dielectric material 933 to fill the first horizontal openings 973. The first dielectric material 939 can completely fill the plurality of first horizontal openings 973. The first dielectric material 939 can flow into a second vertical opening 931 to fill the second vertical opening and fill the plurality of first horizontal openings 973 within the stack. Thus, the first dielectric material 939 can fill the first horizontal openings 973 within the first epitaxially grown silicon-germanium (SiGe) 930-1, the second epitaxially grown silicon-germanium (SiGe) 930-2, and the third epitaxially grown silicon-germanium (SiGe) 930-3 within the stack, the openings being in Figures 7A-7E Formed and by Figures 8A-8E The second dielectric material 933 is covered in it.

[0134] Figure 9D Show along Figure 9A The cross-sectional view taken by the cutting line C-C' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 9D The cross-sectional diagram shown extends in the second horizontal direction (D2) 905 outside the area of ​​the horizontally oriented access device and the horizontally oriented storage node.

[0135] exist Figure 9D In the diagram, the first dielectric material 939 is shown as filling the space along the second direction (D2) 905, separating the access device and storage node area of ​​the three-dimensional array of vertically oriented memory cells that extend into and from the drawing plane. Figure 9D The cross-sectional view shown is in the drawing plane from right to left, extending in the second direction (D2) 905 along the repeating iterative axis of the alternating layers of epitaxially grown silicon-germanium (SiGe) 930 and epitaxially grown single-crystal silicon (Si) material 932. Using a first dielectric material 939, the first dielectric material 939 can fill the second vertical opening (831, e.g., in the first region adjacent to the epitaxially grown silicon-germanium (SiGe) 930. Figures 8A-8E (As shown). The second hard mask 937 can be deposited on the first dielectric material 939 that fills the second vertical opening and is on the first hard mask 935.

[0136] Figure 9E Show along Figure 9A The cross-sectional view taken by the cutting line D-D' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 9EThe cross-sectional diagram shown is an extension of the repeating iterative axis of the alternating layers of epitaxially grown single-crystal silicon (Si) material 932 from right to left in the drawing plane along the first direction (D1) 909.

[0137] exist Figure 9E In the diagram, a first dielectric material 939 is shown filling the space between epitaxially grown single-crystal silicon (Si) materials 932, the space being located in openings left by etched epitaxially grown silicon-germanium (SiGe). The first dielectric material 939 is also shown in the space between second dielectric materials 933 covering the epitaxially grown single-crystal silicon (Si) materials 932, the single-crystal silicon (Si) materials being spaced apart along a first direction (D1) 909 and vertically stacked in an array extending along a third direction (D3) 911 in a three-dimensional (3D) memory. A hard mask 935 may be covered with the second dielectric material 933. The first dielectric material 939 may also fill the space between the second dielectric materials 933 covering the hard mask 935. A second hard mask 937 may be deposited on the hard mask 935.

[0138] Figure 10A Showing for use in, for example Figure 1A-3B This is an example method of another stage of a semiconductor manufacturing process for forming epitaxial silicon within a horizontal access device in a vertical three-dimensional (3D) memory, as shown in and according to several embodiments of the present disclosure. Figure 10A A top view of a semiconductor structure at a specific point in time during a semiconductor manufacturing process according to one or more embodiments is shown.

[0139] exist Figure 10A In the illustrated embodiment, the method includes forming a third vertical opening 1070 that extends through the vertical stack and primarily in a first horizontal direction to expose the sidewalls of a second region adjacent to the epitaxially grown silicon-germanium (SiGe). The third vertical opening 1070 can be etched through a hard mask 1035. The third vertical opening 1070 can be formed adjacent to a second vertical opening. Furthermore, a plurality of third vertical openings 1070 can be formed through the material layer by patterning the hard mask 1035 and exposing specific regions of the vertical stack using photolithography.

[0140] Figure 10B It is along Figure 10A The cross-sectional view taken by the cutting line A-A' in the figure shows another view of the semiconductor structure at this specific point in the semiconductor manufacturing process. Figure 10B The cross-sectional view shown illustrates the repeated iterations of alternating layers of silicon germanium (SiGe) 1030 and epitaxially grown single-crystal silicon (Si) material 1032 epitaxially grown on a semiconductor substrate 1000.

[0141] like Figure 10BAs shown, multiple first vertical openings are formed through layers within the vertically stacked memory cells to expose the vertical sidewalls in the vertical stack, and are filled with a first dielectric material 1039. The first vertical openings are formed by repeated iterations through epitaxially grown silicon germanium (SiGe) 1030 and epitaxially grown single-crystal silicon (Si) material 1032.

[0142] Figure 10C It is used in, for example Figure 1A-3B Another cross-sectional view of this particular stage of the semiconductor manufacturing process for forming epitaxial silicon within the horizontal access device in a vertical three-dimensional (3D) memory shown and according to several embodiments of the present disclosure. Figure 10C shows along... Figure 10A The cross-sectional view taken by the cutting line B-B' in the figure.

[0143] As mentioned above, Figure 10C The method is illustrated by forming a third vertical opening 1070 that extends through the vertical stack and primarily in the first horizontal direction 1009 to expose the sidewalls of a second region adjacent to the epitaxially grown silicon-germanium (SiGe) 1030. Forming a plurality of patterned third vertical openings 1070 through the vertical stack includes forming a plurality of patterned third vertical openings 1070 vertically aligned with the location of the first source / drain region to serve as the first source / drain region.

[0144] Figure 10D Show along Figure 10A The cross-sectional view taken by the cutting line C-C' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 10D The cross-sectional diagram shown extends in the second horizontal direction (D2)1005 outside the area of ​​the horizontally oriented access device and the horizontally oriented storage node.

[0145] exist Figure 10D In the diagram, the first dielectric material 1039 is shown as a three-dimensional array of access devices and storage node areas of vertically oriented memory cells that fill the space along the second direction (D2) 1005 and extend into and out of the drawing plane. Figure 10D The cross-sectional view shown, from right to left in the drawing plane, extends along the repeating iterative axis of the alternating layers of epitaxially grown silicon-germanium (SiGe) 1030 and epitaxially grown single-crystal silicon (Si) material 1032 in the second horizontal direction (D2) 1005. A third vertical opening 1070, shown as a second region adjacent to the epitaxially grown silicon-germanium (SiGe) 1030, extends primarily in the first horizontal direction 1009 to expose the sidewalls of the vertically stacked layers. A second hard mask 1037 can be seen over the first dielectric material 1039, the vertical stack, and the filled second vertical opening.

[0146] Figure 10E Show along Figure 10A The cross-sectional view taken by the cutting line D-D' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 10E The cross-sectional diagram shown is a right-to-left cross-section extending along a first horizontal direction (D1) 1009 on the drawing plane, along alternating layers of epitaxially grown monocrystalline silicon (Si) material 1032 surrounded by a second dielectric material 1033 and intersecting with multiple first dielectric materials 1039. A hard mask 1035 may be covered by the second dielectric material 1033. The first dielectric materials 1039 may also fill the space between the second dielectric material 1033 and the alternating layers of epitaxially grown monocrystalline silicon (Si) material 1032.

[0147] Figure 11A Showing for use in, for example Figure 1A-3B This is an example method of another stage of a semiconductor manufacturing process for forming epitaxial silicon within a horizontal access device in a vertical three-dimensional (3D) memory, as shown in and according to several embodiments of the present disclosure. Figure 11A A top view of a semiconductor structure at a specific point in time during a semiconductor manufacturing process according to one or more embodiments is shown.

[0148] exist Figure 11A In an example embodiment, the method includes patterning a photomask 1135 using a photolithography process. Figure 11A-11E The method further illustrates the use of one or more etchant processes to selectively etch the SiGe material 1130 to form a plurality of second horizontal openings 1179 at a first distance (DIST 1) from the third vertical opening 1170. Figure 11C (Chinese). For example Figure 11C As can be seen, the second horizontal opening 1179 can be selectively etched into the SiGe material 1130 at a first distance (DIST 1) from the second dielectric material 1133 formed in the second vertical opening 1131. In some embodiments, the second dielectric material 1133 can be used as an etch stop layer during the selective etching of the SiGe material 1130.

[0149] Figure 11B Show along Figure 11A The cross-sectional view taken by the cutting line A-A' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 11B The cross-sectional view shown illustrates the repeated iterations of alternating layers of silicon germanium (SiGe) 1130 and epitaxially grown single-crystal silicon (Si) material 1132 epitaxially grown on semiconductor substrate 1100.

[0150] like Figure 11BAs shown, multiple first vertical openings are formed through layers within the vertically stacked memory cells to expose the vertical sidewalls in the vertical stack. The first vertical openings can be formed through repeated iterations of epitaxially grown silicon germanium (SiGe) 1130 and epitaxially grown single-crystal silicon (Si) material 1132.

[0151] Figure 11C Show along Figure 11A The cross-sectional view taken by the cutting line B-B' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 11C The cross-sectional diagram shown is an illustration of the repeated iteration axis along the second horizontal direction (D2) 1105 extending left and right along the plane of the drawing along the alternating layers of epitaxially grown silicon germanium (SiGe) 1130 and epitaxially grown single-crystal silicon (Si) material 1132.

[0152] exist Figure 11C In an example embodiment, the epitaxially grown silicon-germanium (SiGe) 1130 is selectively etched to form a plurality of second horizontal openings 1179 extending a first distance (DIST 1) 1176 from a third vertical opening 1170. Etching agent can be allowed to flow into the third vertical opening 1170 to selectively etch a portion of the epitaxially grown silicon-germanium (SiGe) 1130. For example, etching agent can be allowed to flow into the third vertical opening 1170 to selectively etch a portion of the epitaxially grown silicon-germanium (SiGe) 1130. The etchant can selectively remove all iterative portions of the stacked epitaxially grown silicon-germanium (SiGe) 1130. Therefore, by using the second dielectric 1133 as an etch stop layer, the etchant can selectively etch the epitaxially grown Si material 1132 and selectively remove the first epitaxially grown silicon germanium (SiGe) 1130-1, the second epitaxially grown silicon germanium (SiGe) 1130-2 and the third epitaxially grown silicon germanium (SiGe) 1130-3, reaching a first distance (DIST 1) 1176 within the stack.

[0153] Selective etchant processes can be performed in multiple steps to protect the structure and stabilize the epitaxially grown single-crystal silicon (Si) material 1132. Selective etchant processes may include one or more etch chemicals selected from aqueous etch chemicals, semi-aqueous etch chemicals, vapor etch chemicals, or plasma etch chemicals, as well as other possible selective etch chemicals. For example, dry etch chemicals using oxygen (O2) or O2 and sulfur dioxide (SO2) may be used. As another example, dry etch chemicals using O2 or O2 and nitrogen (N2) may be used to selectively etch the epitaxially grown silicon germanium (SiGe) 1130. Alternatively or additionally, selective etching for removing the epitaxially grown silicon germanium (SiGe) 1130 may include chemicals that selectively etch phosphoric acid (H3PO4) or hydrogen fluoride (HF) and / or the use of selective solvents and other possible etch chemicals or solvents to dissolve the epitaxially grown silicon germanium (SiGe) 1130.

[0154] A selective etchant process can etch epitaxially grown silicon-germanium (SiGe) 1130 to form a second horizontal opening 1179. The selective etchant process can be performed such that the second horizontal opening 1179 has a length (DIST 1) of a first distance 1176 from a third vertical opening 1170. A second dielectric material 1133 can be used as an etch stop layer to etch the epitaxially grown silicon-germanium (SiGe) 1130 to the first distance (DIST 1) 1176. The first distance (DIST 1) 1176 can be controlled by controlling the time of the reactive gas flowing into the third vertical opening 1170, the composition of the etchant gas, and the etching rate (e.g., rate, concentration, temperature, pressure, and time parameters).

[0155] Therefore, the epitaxially grown silicon-germanium (SiGe) 1130 can be etched from the third vertical opening 1170 to a first distance 1176. Selective etching can be isotropic, but selectively etches the epitaxially grown silicon (Si) material 1132, thereby removing only the epitaxially grown silicon-germanium (SiGe) material 1130 and stopping substantially on the second dielectric material 1133. Thus, in one exemplary embodiment, the selective etchant process can remove substantially all of the epitaxially grown silicon-germanium (SiGe) 1130 until reaching the second dielectric material 1133, thereby horizontally etching from the third vertical opening 1170 to a first distance (DIST 1) 1176 until the location or position of the second dielectric material 1133. However, the embodiments are not limited to this example.

[0156] Figure 11D Show along Figure 11A The cross-sectional view taken by the cutting line C-C' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 11DThe cross-sectional diagram shown is an alternating axis of the alternating layers of epitaxially grown silicon germanium (SiGe) and the remaining epitaxially grown single-crystal silicon (Si) material 1132, which are etched to form the second horizontal opening 1179, extending left and right along the plane of the drawing in the second horizontal direction (D2) 1105.

[0157] The left side of the drawing shows repeated iterations of alternating layers of etched epitaxially grown silicon-germanium (SiGe) and epitaxially grown single-crystal silicon (Si) material 1132 forming the second horizontal opening 1179. A third vertical opening 1170 is shown as a second region adjacent to the second horizontal opening 1179. On the right side of the drawing, the first dielectric material 1139 can be seen, and the second vertical opening 1131 is filled with both the second dielectric material 1133 and the first dielectric material 1139. Dashed lines indicate the presence of the first horizontal opening 1130, which is also filled with both the second dielectric material 1133 and the first dielectric material 1139. Figure 11A The cross-section cut by the cutting line C-C' in the drawing enters the drawing plane.

[0158] Figure 11E Show along Figure 11A The cross-sectional view taken by the cutting line D-D' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 11E The cross-sectional diagram shown is a right-to-left cross-section extending along a first horizontal direction (D1) 1109 of alternating layers of epitaxially grown monocrystalline silicon (Si) material 1132 surrounded by a second dielectric material 1133 and intersecting with multiple first dielectric materials 1139. A hard mask 1135 may be covered by the second dielectric material 1133. The first dielectric materials 1139 may also fill the space between the second dielectric material 1133 and the alternating cross-section of the epitaxially grown monocrystalline silicon (Si) material 1032.

[0159] Figure 12A Showing for use in, for example Figure 1A-3B This is an example method of another stage of a semiconductor manufacturing process for forming epitaxial silicon within a horizontal access device in a vertical three-dimensional (3D) memory, as shown in and according to several embodiments of the present disclosure. Figure 12A A top view of a semiconductor structure at a specific point in time during a semiconductor manufacturing process according to one or more embodiments is shown. Figure 12C As can be seen, a timed selective etching process is performed to selectively etch the second dielectric material 1233 from the third vertical opening 1270 to the second distance (DIST 2).

[0160] Figure 12B Show along Figure 12AThe cross-sectional view taken by the cutting line A-A' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 12B The cross-sectional view shown illustrates the repeated iterations of alternating layers of silicon germanium (SiGe) 1230 and epitaxially grown single-crystal silicon (Si) material 1232 epitaxially grown on semiconductor substrate 1200.

[0161] like Figure 12B As shown, multiple first vertical openings are formed through layers within the vertically stacked memory cells to expose the vertical sidewalls in the vertical stack. The first vertical openings are formed by repeated iterations through epitaxially grown silicon germanium (SiGe) 1230 and epitaxially grown single-crystal silicon (Si) material 1232. Figure 12C Show along Figure 12A The cross-sectional view taken by the cutting line B-B' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 12C The cross-sectional diagram shown illustrates the repetitive iterative axis along the second horizontal direction (D2) 1205, extending left and right along the drawing plane, of the alternating layers of epitaxially grown silicon-germanium (SiGe) 1230 and epitaxially grown single-crystal silicon (Si) material 1232. Figure 12C In some embodiments, the second dielectric material 1233 is selectively etched from the third vertical opening 1270 to a second distance (D2) 1283. In some embodiments, a timed selective etching excitation process can be used to etch the second dielectric material 1233 back to the second distance (DIST 2) 1283. The second distance 1283 is the distance from the third vertical opening 1270 to the remaining unetched portion of the second dielectric material 1233. In some embodiments, the second dielectric material 1233 can be etched back from the third vertical opening 1270 to a second distance (DIST 2) 1283 in the range of approximately twenty-five (25) to seventy-five (75) nanometers (nm). The second dielectric material 1233 can be selectively etched to the epitaxially grown single-crystal silicon (Si) material 1232 and the first dielectric material 1239, thereby keeping the epitaxially grown single-crystal silicon (Si) material 1232 and the first dielectric material intact. Furthermore, as Figure 12DThe diagram further illustrates that, between the access device region and the first horizontal opening 1230, a portion of the first dielectric material 1239 is removed by additional selective etching in a second horizontal opening, which is part of a controlled oxide lateral via through a plurality of first vertical openings 1215, to form a continuous second horizontal opening 1243 extending in the first horizontal direction (D1) 1209. Therefore, in some embodiments, a timing-activated process can be used to etch the second dielectric material 1233. Another selective lateral via can be used to etch the first dielectric material 1239, for example, selectively etching the oxide first dielectric material 1239. In some embodiments, the oxide lateral via can be a more controlled etching process using the second dielectric material 1233 as an etch termination layer, which terminates on the vertical portion of the second dielectric material 1233 formed in the second vertical opening 1231 between epitaxially grown single-crystal silicon (Si) material 1232 separated in the access device region.

[0162] Figure 12D Show along Figure 12A The cross-sectional view taken by the cutting line C-C' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 12D The cross-sectional diagram shown is an illustration of the repeated iteration axis of the alternating layers of etched epitaxially grown silicon germanium (SiGe) and epitaxially grown single-crystal silicon (Si) material 1232 extending left and right along the drawing plane in the second horizontal direction (D2) 1205.

[0163] exist Figure 12D In the drawing, the first dielectric material 1239 is shown filling the space along the second horizontal direction (D2) 1205, separating the access devices and memory node regions of a three-dimensional array of vertically oriented memory cells extending into and from the drawing plane. At the left end of the drawing, repeated iterations of alternating layers of etched epitaxially grown silicon (SiGe) and etched regions are shown, in which the first dielectric material has been removed to form a continuous second horizontal opening 1243 on the first direction (D1) 1209, separating the layers of epitaxially grown single-crystal silicon (Si) material 1232. A third vertical opening 1270 is shown as the region adjacent to the present continuous second horizontal opening 1243. On the right side of the drawing, the first dielectric material 1239, which separates the access devices and memory node regions on the first direction (D1) 1209, can be seen, with the second vertical opening 1231 filled with the second dielectric material 1233 and the first dielectric material 1239. The dashed lines indicate the presence of the remaining portion of the first horizontal opening 1230, which is filled with the second dielectric material 1233 and the first dielectric material 1239, along... Figure 12A The cross-section cut by the cutting line C-C' in the drawing enters the drawing plane.

[0164] For example, in the initially formed first vertical opening 1215 ( Figure 6A A portion of the first dielectric material 1239 has been etched away in the second vertical opening 1231 (615), and the second dielectric material 1233 is filled into the second vertical opening 1231. In some embodiments, the etched portion of the first dielectric material 1239 can be removed using oxide lateral perforation to form the current continuous second horizontal opening 1243.

[0165] Figure 12E Show along Figure 12A The cross-sectional view taken by the cutting line D-D' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 12E The cross-sectional diagram shown is a cross-section extending from right to left in the drawing plane along the alternating layers of epitaxially grown single-crystal silicon (Si) material 1232 and first dielectric material 1239, extending in the first direction (D1) 1209. Figure 12E In this view, the second dielectric material 1233 is no longer shown around the epitaxially grown single-crystal silicon (Si) material 1232. This is because the second dielectric material 1233 is generated by timing excitation of the second dielectric material 1233 in this portion of the cross-sectional view of the access device region, and therefore cannot be seen in this view. Some of the first dielectric material 1239 in the second vertical opening can also be removed from the lateral punch. In this cross-sectional view, the first dielectric material 1239 still remains bridged between layers and vertically distributed between the cross-sectional views of the epitaxially grown single-crystal silicon (Si) material 1232. However, in this cross-sectional view, an open space can be seen adjacent to the bridged epitaxially grown single-crystal silicon (Si) material 1232 and separating the epitaxially grown single-crystal silicon (Si) material 1232 from the first dielectric material 1239.

[0166] Figure 13A Showing for use in, for example Figure 1A-3B This is an example method of another stage of a semiconductor manufacturing process for forming epitaxial silicon within a horizontal access device in a vertical three-dimensional (3D) memory, as shown in and according to several embodiments of the present disclosure. Figure 13A A top view of a semiconductor structure at a specific point in time during a semiconductor manufacturing process according to one or more embodiments is shown. Figure 13C As can be seen, a gate dielectric material can be formed on the exposed surface of the epitaxially formed Si material to form a horizontal access device. In some embodiments, the gate dielectric material may be an oxide material. An oxide material can be deposited on the exposed surface of the epitaxially formed Si material using atomic layer deposition (ALD). Thermal oxidation can be used to densify the oxide material deposited by the ALD.

[0167] Figure 13B Show along Figure 13A The cross-sectional view taken by the cutting line A-A' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 13B The cross-sectional view shown illustrates the repeated iterations of alternating layers of silicon germanium (SiGe) 1330 and epitaxially grown single-crystal silicon (Si) material 1332 epitaxially grown on semiconductor substrate 1300.

[0168] like Figure 13B As shown, multiple first vertical openings are formed through layers within the vertically stacked memory cells to expose the vertical sidewalls in the vertical stack. The first vertical openings are formed by repeated iterations through epitaxially grown silicon germanium (SiGe) 1330 and epitaxially grown single-crystal silicon (Si) material 1332.

[0169] Figure 13C Show along Figure 13A The cross-sectional view taken by the cutting line B-B' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 13C The cross-sectional diagram shown illustrates the repetitive iterative axis along the second horizontal direction (D2) 1305, extending laterally along the drawing plane, of the alternating layers of epitaxially grown silicon-germanium (SiGe) 1330 and epitaxially grown single-crystal silicon (Si) material 1332. Figure 13C In one example embodiment, the epitaxially grown silicon germanium (SiGe) 1330 and the second dielectric material 1333 have been etched back to expose the first dielectric material 1339.

[0170] A gate dielectric material 1342 may be formed on the exposed surface of the epitaxially formed Si material 1332 to form a horizontal access device. In some embodiments, the gate dielectric material may be an oxide material 1342. The gate dielectric material 1342 may be conformally deposited to completely surround each surface of the epitaxially formed Si material 1332 to form a gate-all-around (GAA) gate structure in the channel of the access device region. The gate opposite the channel region provides a subthreshold voltage (sub-Vt) slope in the range of approximately 45 to 100 millivolts (mV / dec). The oxide material 1342 may be deposited on the exposed surface of the epitaxially formed Si material 1332 using atomic layer deposition. In some instances, the oxide material 1342 may be deposited on the exposed surface of the epitaxially grown single-crystal silicon (Si) material 1332 to prevent oxidation of the epitaxially grown single-crystal silicon (Si) material 1332. The deposition of oxide material 1342 can prevent short circuits by protecting the epitaxially grown single-crystal silicon (Si) material 1332 from interacting with the first dielectric material 1339. The oxide material 1342 can be selectively deposited on the exposed surface of the epitaxially grown single-crystal silicon (Si) material 1332 using atomic layer deposition (ALD). The ALD-deposited oxide material 1342 can be densified using a thermal oxidation process. The thermal oxidation process involves forming the oxide material 1342 from a hybrid oxide material. The hybrid oxide material can combine low-temperature oxide materials and high-temperature oxide materials.

[0171] Figure 13D Show along Figure 13A The cross-sectional view taken by the cutting line C-C' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 13D The cross-sectional diagram shown is a repeating iterative axis along the second horizontal direction (D2) 1305 extending left and right along the drawing plane of the alternating layers of etched epitaxially grown silicon germanium (SiGe) and the remaining epitaxially grown single-crystal silicon (Si) material 1332.

[0172] exist Figure 13DIn the diagram, the left side shows repeated iterations of alternating layers of etched epitaxially grown silicon (SiGe) and etched regions, in which a first dielectric material has been removed to form a continuous second horizontal opening 1343 on a first direction (D1) 1209 separating layers of epitaxially grown single-crystal silicon (Si) material 1132. A gate dielectric material 1342 can be formed on the exposed surface of the epitaxially formed Si material 1332. On the right side of the diagram, a first dielectric material 1339 separating the access device and memory node regions on the first direction (D1) 1309 can be seen, and a second vertical opening 1331 is filled with a second dielectric material 1333 and a first dielectric material 1339. A portion of the first dielectric material 1339 has been etched away, while the second dielectric material 1333 serves as an etch stop layer. The second dielectric material 1333 fills the first dielectric material 1339. The etched portion of the first dielectric material 1339 is removed using oxide lateral vias.

[0173] Figure 13E Show along Figure 13A The cross-sectional view taken by the cutting line D-D' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 13E The cross-sectional diagram shown is an illustration of the repeated iterative axis of the epitaxially grown monocrystalline silicon (Si) material 1332 and first dielectric material 1339 extending from right to left in the first direction (D1) 1309 on the drawing plane. Figure 13E In this cross-sectional view, the gate dielectric material 1342 can be shown surrounding the epitaxially grown single-crystal silicon (Si) material 1332. In this cross-sectional view, the first dielectric material 1339 remains bridged between the layers and is vertically distributed between the cross-sectional views of the epitaxially grown single-crystal silicon (Si) material 1332.

[0174] Figure 14A Showing for use in, for example Figure 1A-3B This is an example method of another stage of a semiconductor manufacturing process for forming epitaxial silicon within a horizontal access device in a vertical three-dimensional (3D) memory, as shown in and according to several embodiments of the present disclosure. Figure 14A A top view of a semiconductor structure at a specific point in time during a semiconductor manufacturing process according to one or more embodiments is shown. Figure 14A In an example embodiment, the method includes patterning a photomask 1435 using a photolithography process. A first conductive material 1477 may be deposited over a second vertical opening 1431. The first conductive material 1477 may be deposited in consecutive second horizontal openings to form horizontally oriented access lines opposite to the channel regions of the epitaxially grown single-crystal silicon (Si) material 1432.

[0175] Figure 14B Show along Figure 14A The cross-sectional view taken by the cutting line A-A' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 14B The cross-sectional view shown illustrates the repeated iterations of alternating layers of silicon germanium (SiGe) 1430 and epitaxially grown single-crystal silicon (Si) material 1432 epitaxially grown on semiconductor substrate 1400.

[0176] like Figure 14B As shown, multiple first vertical openings are formed through layers within the vertically stacked memory cells to expose the vertical sidewalls in the vertical stack. The first vertical openings are formed through repeated iterations of epitaxially grown silicon germanium (SiGe) 1430 and epitaxially grown single-crystal silicon (Si) material 1432.

[0177] Figure 14C Show along Figure 14A The cross-sectional view taken by the cutting line B-B' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 14C The cross-sectional diagram shown is an illustration of the repeated iteration axis along the second horizontal direction (D2)1405 extending left and right along the plane of the drawing, which is an alternating layer of epitaxially grown silicon germanium (SiGe) 1430 and epitaxially grown single-crystal silicon (Si) material 1432.

[0178] A first conductive material 1477 can be deposited on the gate dielectric material 1442. The first conductive material 1477 can be deposited surrounding the epitaxially grown single-crystal silicon (Si) material 1432, such that the first conductive material 1477 has a top portion above the epitaxially grown single-crystal silicon (Si) material 1432 and a bottom portion below the epitaxially grown single-crystal silicon (Si) material to form a gate-all-around (GAA) gate structure at the channel of the access device region. The first conductive material 1477 can be conformally deposited into the third vertical opening 1470 and fill the continuous second horizontal opening 1443 until the unetched portions of the oxide material 1442, the first dielectric material 1439, and the second dielectric material 1433 are reached. The first conductive material 1477 can be conformally deposited using chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), or other suitable deposition processes.

[0179] In some embodiments, the first conductive material 1477 may include one or more of the following: doped semiconductors (e.g., doped silicon, doped germanium, etc.), conductive metal nitrides (e.g., titanium nitride, tantalum nitride, etc.), metals (e.g., tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), cobalt (Co), molybdenum (Mo), etc.) and / or metal semiconductor compounds (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.) and / or one or more other combinations thereof. The first conductive material 1477 wound with a gate dielectric material may form a horizontally oriented access line opposite to the channel region of the epitaxially grown single-crystal silicon (Si) material (which may also be referred to as a word line).

[0180] Figure 14D Show along Figure 14A The cross-sectional view taken by the cutting line C-C' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 14D The cross-sectional diagram shown is a repeating iterative axis along the second horizontal direction (D2) 1405 extending left and right along the drawing plane along the alternating layers of continuous second horizontal opening 1443 and epitaxially grown single-crystal silicon (Si) material 1432.

[0181] exist Figure 14D In the drawing, the first dielectric material 1439 is shown as a second horizontal direction (D2) 1405 extending into and from the plane of the drawing along a three-dimensional array of vertically oriented memory cells. At the left end of the drawing, repeated iterations of alternating layers of epitaxially grown single-crystal silicon (Si) material 1432 separated by successive second horizontal openings 1443 along the first direction (D1) 1409 are shown. A first conductive material 1477 is conformally deposited into a third vertical opening 1470 and the second horizontal opening 1443. The first conductive material 1477 is formed on the gate dielectric material 1442. On the right side of the drawing, the first dielectric material 1439, which separates the access device and memory node region along the first direction (D1) 1409, can be seen, and the second horizontal opening 1431 is filled with the second dielectric material 1433 and the first dielectric material 1439.

[0182] Figure 14E Show along Figure 14A The cross-sectional view taken by the cutting line D-D' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 14EThe cross-sectional view shown extends from right to left in the drawing plane along a first direction (D1) 1409, along the repeating iterative axis of alternating layers of epitaxially grown monocrystalline silicon (Si) material 1432 encased by a first dielectric material 1439 and a gate dielectric material 1442. A gate dielectric material 1442 is conformally deposited on each surface of the epitaxially grown monocrystalline silicon (Si) material 1432 to completely surround it, forming a gate-all-around (GAA) gate structure at the channel of the access device region. A first conductive material 1477 fills the space of adjacent bridged epitaxially grown monocrystalline silicon (Si) material 1432. The epitaxially grown monocrystalline silicon (Si) material 1432 can be surrounded by a first conductive material 1477 formed on the gate dielectric material 1442. A first conductive material 1477 is conformally deposited on each surface of the epitaxially grown monocrystalline silicon (Si) material 1432 to completely surround it, forming a gate-all-around (GAA) gate structure at the channel of the access device region. Figure 14E In the diagram, the first conductive material 1477 is shown filling the space left by the etched second dielectric material 1433 in the second horizontal opening 1431.

[0183] Figure 15A Showing for use in, for example Figure 1A-3B This is an example method of another stage of a semiconductor manufacturing process for forming epitaxial silicon within a horizontal access device in a vertical three-dimensional (3D) memory, as shown in and according to several embodiments of the present disclosure. Figure 15A A top view of a semiconductor structure at a specific point in time during a semiconductor manufacturing process according to one or more embodiments is shown. Figure 15A In one example embodiment, the method includes patterning a photomask 1535 using a photolithography process. A first conductive material 1577 may have already been deposited over the second vertical opening 1531 and is now recessed.

[0184] Figure 15B Showing along the storage node area Figure 15A The cross-sectional view taken by the cutting line A-A' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 15B The cross-sectional view shown illustrates the repeated iterations of alternating layers of silicon germanium (SiGe) 1530 and epitaxially grown single-crystal silicon (Si) material 1532 epitaxially grown on the semiconductor substrate 1500 in the memory node region.

[0185] like Figure 15B As shown, multiple first vertical openings can be formed through layers within a vertically stacked memory cell to expose the vertical sidewalls in the vertical stack. The first vertical openings can be formed through repeated iterations of epitaxially grown silicon-germanium (SiGe) 1530 and epitaxially grown single-crystal silicon (Si) material 1532 in the memory node region.

[0186] Figure 15C Show along Figure 15A The cross-sectional view taken by the cutting line B-B' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 15C The cross-sectional diagram shown is an illustration of the repeated iteration axis along the second horizontal direction (D2)1505 extending left and right along the plane of the drawing, which is an alternating layer of epitaxially grown silicon germanium (SiGe) 1530 and epitaxially grown single-crystal silicon (Si) material 1532.

[0187] A first conductive material 1577 is deposited on and surrounds an epitaxially grown monocrystalline silicon (Si) material 1532, and recessed to form a gate all-around (GAA) structure opposite to the channel region of the epitaxially grown monocrystalline silicon (Si) material 1532. The first conductive material 1577 formed on the gate dielectric material 1542 can be recessed and etched away from the third vertical opening 1570. In some embodiments, the first conductive material 1577 can be etched using an atomic layer etching (ALE) process. In some embodiments, the first conductive material 1577 can be etched using an isotropic etching process. The first conductive material 1577 can be selectively etched so that the oxide material 1542 and the first dielectric material 1539 covering the epitaxially grown monocrystalline silicon (Si) material 1532 remain intact. In a successive second horizontal opening, the first conductive material 1577 can be selectively etched back from the third vertical opening 1570 in a second direction for a third distance (DIST 3) in the range of twenty (20) to fifty (50) nanometers (nm). The first conductive material 1577 may surround the epitaxially grown single-crystal silicon (Si) material 1532 and selectively etch back into a continuous second horizontal opening extending in the first horizontal direction.

[0188] Figure 15D Show along Figure 15A The cross-sectional view taken by the cutting line C-C' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 15D The cross-sectional diagram shown is an axis of repeated iteration along the second horizontal direction (D2) 1505 extending left and right along the drawing plane along the alternating layers of the etched first conductive material 1577 and the epitaxially grown single-crystal silicon (Si) material 1532.

[0189] exist Figure 15DIn the diagram, the first dielectric material 1539 is shown as a first horizontal direction (D1) 1509 extending into and from the plane of the drawing along a three-dimensional array of vertically oriented memory cells. At the left end of the drawing, alternating layers of epitaxially grown single-crystal silicon (Si) material 1532 covered by oxide material 1542, separated by consecutive second horizontal openings 1543 along the first direction (D1) 1509, are shown as repeated iterations. The first conductive material 1577 formed on the gate dielectric material 1542 is etched away from the third vertical opening 1570. The first conductive material 1577 formed on the gate dielectric material 1542 is also recessed within the consecutive second horizontal openings 1543 extending along the first horizontal direction 1509. The first conductive material 1577 can be selectively etched, leaving the oxide material 1542 covering the epitaxially grown single-crystal silicon (Si) material 1532 intact. In this view, the unetched first conductive material 1577 can be seen occupying a portion of the space within the continuous second horizontal openings 1543 between the oxide materials 1542. In some embodiments, the first conductive material 1577 may be etched using an atomic layer etching (ALE) process. In some embodiments, the first conductive material 1577 may be etched using an isotropic etching process.

[0190] Figure 15E Showing along the access device area Figure 15A The cross-sectional view taken by the cutting line D-D' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 15E The cross-sectional view shown extends from right to left in the drawing plane along a first direction (D1) 1509, along the repeating iterative axis of alternating layers of epitaxially grown single-crystal silicon (Si) material 1532 encased in first dielectric material 1539 and oxide material 1542. Gate dielectric material 1542 is conformally deposited on each surface of the epitaxially grown single-crystal silicon (Si) material 1532, completely surrounding it, to form a gate-all-around (GAA) gate structure at the channel in the access device region. First conductive material 1577 fills the space of the epitaxially grown single-crystal silicon (Si) material 1532 bridging adjacent to the access device region. The epitaxially grown single-crystal silicon (Si) material 1532 can be surrounded by the first conductive material 1577 formed on the gate dielectric material 1542.

[0191] A first conductive material 1577 is deposited on the gate dielectric material 1542 and formed around the epitaxially grown single-crystal silicon (Si) material 1532 to form a gate all-around (GAA) structure in the access device region opposite to the channel region of the epitaxially grown single-crystal silicon (Si) material 1532. Figure 15EIn the diagram, the first conductive material 1577 is shown filling the space left by the etched second dielectric material 1533 in the second horizontal opening 1531.

[0192] Figure 16A Showing for use in, for example Figure 1A-3B This is an example method of another stage of a semiconductor manufacturing process for forming epitaxial silicon within a horizontal access device in a vertical three-dimensional (3D) memory, as shown in and according to several embodiments of the present disclosure. Figure 16A A top view of a semiconductor structure at a specific point in time during a semiconductor manufacturing process according to one or more embodiments is shown. Figure 16A In an example embodiment, the method includes patterning a photomask 1635 using a photolithography process. Figures 16A-16E The method shown in the paper illustrates that interlayer dielectric (ILD) filling material 1667 can be deposited in the second horizontal opening 1631 to fill the second horizontal opening 1631.

[0193] Figure 16B Showing along the storage node area Figure 16A The cross-sectional view taken by the cutting line A-A' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 16B The cross-sectional view shown illustrates the repeated iterations of alternating layers of silicon germanium (SiGe) 1630 and epitaxially grown single-crystal silicon (Si) material 1632 epitaxially grown on semiconductor substrate 1600.

[0194] like Figure 16B As shown, multiple first vertical openings are formed through layers within the vertically stacked memory cells to expose the vertical sidewalls in the vertical stack.

[0195] Figure 16C Show along Figure 16A The cross-sectional view taken by the cutting line B-B' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 16C The cross-sectional diagram shown is an illustration of the repeated iteration axis along the second horizontal direction (D2)1605 extending left and right along the plane of the drawing, which is an alternating layer of epitaxially grown silicon germanium (SiGe) 1630 and epitaxially grown single-crystal silicon (Si) material 1632.

[0196] ILD filler material 1667 can be deposited into the third vertical opening 1670 and fill the continuous second horizontal openings up to the unetched portions of oxide material 1642, first dielectric material 1639, and first conductive material 1677. ILD filler material 1667 can be conformally deposited using chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), or other suitable deposition processes.

[0197] Figure 16D Show along Figure 16A The cross-sectional view taken by the cutting line C-C' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 16D The cross-sectional diagram shown is an axis of repeated iteration along the second horizontal direction (D2) 1605, extending left and right along the drawing plane, along the alternating layers of the etched first conductive material 1677 and the epitaxially grown single-crystal silicon (Si) material 1632.

[0198] exist Figure 16D In the diagram, the first dielectric material 1639 is shown as a first horizontal direction (D1) 1609 extending into and from the drawing plane along a three-dimensional array of vertically oriented memory cells. At the left end of the drawing, repeated iterations of alternating layers of epitaxially grown single-crystal silicon (Si) material 1632 and etched portions of the first conductive material 1677, covered by the gate dielectric material 1642, are shown. ILD filler material 1667 can be conformally deposited into the third vertical opening 1670 and the second consecutive horizontal opening 1643, up to the unetched portions of the gate dielectric material 1642 and the etched portions of the first conductive material 1677. The first conductive material 1677 is formed on the gate dielectric material 1642.

[0199] Figure 16E Showing along the access device area Figure 16A The cross-sectional view taken by the cutting line D-D' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 16E The cross-sectional view shown is an iterative axis extending from right to left in the drawing plane along a first direction (D1) 1609 along the alternating layers of the first dielectric material 1639 and the epitaxially grown single-crystal silicon (Si) material 1632. The epitaxially grown single-crystal silicon (Si) material 1632 is surrounded by a first conductive material 1677 formed on a gate dielectric material 1642. The first conductive material 1677 may fill the space of the adjacent bridging epitaxially grown single-crystal silicon (Si) material 1632. The first conductive material 1677 is conformally deposited on each surface of the epitaxially grown single-crystal silicon (Si) material 1632 to form a gate-all-around (GAA) gate structure at the channel in the access device region. Figure 16E In the diagram, the first conductive material 1677 is shown filling the space left by the etched second dielectric material 1633 in the second vertical opening.

[0200] Figure 17A Showing for use in, for example Figure 1A-3BThis is an example method of another stage of a semiconductor manufacturing process for forming epitaxial silicon within a horizontal access device in a vertical three-dimensional (3D) memory, as shown in and according to several embodiments of the present disclosure. Figure 17A A top view of a semiconductor structure at a specific point in time during a semiconductor manufacturing process according to one or more embodiments is shown. Figure 17A In an example embodiment, the method includes patterning a photomask 1737 using a photolithography process to form a fourth vertical opening 1751 adjacent to a second region of epitaxially grown single-crystal silicon (Si) material 1732 to expose the stack (e.g., Figure 4 The third vertical sidewall in the stack shown. Figures 17A-17E In the process, epitaxially grown single-crystal silicon (Si) material 1732 is selectively etched in a second horizontal direction to form a plurality of third horizontal openings 1779, wherein memory nodes are formed in a second region (e.g., a memory node region in a vertical array of 3D memory cells). Once the epitaxially grown single-crystal silicon (Si) material 1732 has been removed by selective etching, a second source / drain region (adjacent channel region of a horizontal access device) can be formed in the side surface of the epitaxially grown single-crystal silicon (Si) material 1732 by vapor phase doping from the third horizontal openings 1779.

[0201] Figure 17B Showing along the access node area Figure 17A The cross-sectional view taken by the cutting line A-A' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 17B The cross-sectional view shown is away from multiple individual horizontal access lines 1777 and illustrates repeated iterations of bridging of alternating layers of silicon-germanium (SiGe) 1730 epitaxially grown on semiconductor substrate 1700, bridging openings in a third horizontal opening 1779 to form a vertical stack, where epitaxial silicon material 1732 has been removed to form memory nodes. Figure 17B As shown, vertical direction 1711 is shown as... Figure 1A-3B The third direction (D3) 1711 shown in the first, second, and third directions is similar to the z-direction in the xyz coordinate system. The left-right extending drawing plane lies on the first direction (D1) 1709. Figure 17B In an example embodiment, the material within the vertically stacked alternating layers of epitaxially grown silicon-germanium (SiGe) 1730 extends into and out of the drawing plane in the second direction (D2) and along the orientation axis of the horizontal access device and horizontal storage node of the vertically stacked memory cell array of the three-dimensional (3D) memory.

[0202] Figure 17C Show along Figure 17AThe cross-sectional view taken by the cutting line B-B' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 17C The cross-sectional diagram shown illustrates the repeating iterative axis along the alternating layers of epitaxially grown silicon-germanium (SiGe) 1730, extending laterally along the drawing plane in the second horizontal direction (D2) 1705. Horizontally oriented access devices and horizontally oriented memory nodes (e.g., capacitor cells) can be formed within the layers of epitaxially grown single-crystal silicon (Si) material 1732. Figure 17C As shown, a fourth vertical opening 1751 is formed through vertical stacking, and epitaxially grown single-crystal silicon (Si) material 1732 in the second region 1744 is selectively etched to form a third horizontal opening 1779 in the memory node region, wherein memory nodes, such as horizontally oriented capacitor cells (hereinafter referred to as...) are formed. Figures 18A-18E (As shown in the figure). In one example, atomic layer etching (ALE) is used to selectively etch epitaxially grown single-crystal silicon (Si) material 1732.

[0203] Similarly, Figure 17C As shown, source / drain regions can be formed by vapor-doping a dopant into a side surface portion of an epitaxially grown single-crystal silicon (Si) material 1732. In some embodiments, the source / drain regions may be adjacent to the memory node region and on one side of the channel region (the channel region is connected to the digital lines, such as...). Figure 19A-22B The second source / drain region (as described in the text) is connected to the opposite side of the first source / drain region of the horizontal access device. Figures 18A-18E (As shown). In one example, vapor-phase doping can be used to achieve high isotropy (e.g., non-directional doping) to form a second source / drain region for a horizontally oriented access device. In another example, thermal annealing using a dopant gas (e.g., phosphorus (P)) can be used in conjunction with high-energy plasma-assisted methods to break bonds. However, the embodiments are not limited to these, and other suitable semiconductor fabrication techniques can be used.

[0204] Figure 17D Show along Figure 17A The cross-sectional view taken by the cutting line C-C' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 17DThe cross-sectional diagram shown illustrates a repeating iterative axis along a second horizontal direction (D2) 1705 extending laterally along the drawing plane on the outer side of a certain region, where horizontally oriented access devices and horizontally oriented memory nodes (e.g., capacitor cells) will be formed within the layers of epitaxially grown single-crystal silicon (Si) material 1732. A portion of the first conductive material 1777 and the repeating iterative layer of epitaxially grown single-crystal silicon (Si) material 1732 (covered by oxide material 1742) are shown at the left end of the drawing, where horizontally oriented first conductive material (e.g.,...) can be formed. Figure 1A and 1B Access line 1777 shown, etc. Figure 17D As shown in the cross-sectional view, ILD filling material 1767 is deposited into the third vertical opening 1770 and fills the continuous second horizontal openings 1743 on the gate dielectric material 1742 up to the first conductive material 1777.

[0205] Figure 17E Show along Figure 17A The cross-sectional view taken by the cutting line D-D' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 17E The cross-sectional diagram shown depicts alternating layers of epitaxially grown single-crystal silicon (Si) material 1732, surrounded by a first conductive material 1777 and encased in a gate dielectric material 1742, extending from right to left in the drawing plane along a first direction (D1) 1709. The first conductive material 1777 is conformally deposited on each surface of the epitaxially grown single-crystal silicon (Si) material 1732 to completely surround it, forming a gate-all-around (GAA) gate structure in the channel region of the horizontal access device. Figure 17E In the diagram, the first conductive material 1777 is shown filling the space left by the selective etching that forms the second vertical opening and by the etched second dielectric material 1733.

[0206] Figure 18A Showing for use in, for example Figure 1A-3B This is an example method of another stage of a semiconductor manufacturing process for forming epitaxial silicon within a horizontal access device in a vertical three-dimensional (3D) memory, as shown in and according to several embodiments of the present disclosure. Figure 18A A top view of a semiconductor structure at a specific point in time during a semiconductor manufacturing process according to one or more embodiments is shown. Figure 18AIn one example embodiment, a sacrificial oxide material 1838 replaces the photomask 1837 surrounding the fourth vertical opening 1851. The fourth vertical opening 1851 is formed using a photolithographic etchant process, the vertical opening extending through the vertical stack and primarily in the first horizontal direction (D1) 1809. The fourth vertical opening 1851 is formed by the stack that has passed through the memory node region adjacent to the vertical 3D memory to form a memory node. Figures 18A-18E The method shown in the figure illustrates forming a storage node (e.g., a horizontally oriented capacitor cell) in a third horizontal opening (1779 in Figures 17B and 17C).

[0207] Figure 18B Show along Figure 18A The cross-sectional view taken by the cutting line A-A' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 18B The cross-sectional view shown is away from the multiple individual horizontal access lines 1877 and illustrates the repeated iterations of alternating layers of sacrificial oxide material 1838 separated by the complete formation of the horizontally oriented capacitor cell. The sacrificial oxide material 1838 may be formed of oxide or other suitable spin dielectric (SOD) or inductively coupled liquid dielectric (ILD) filling materials. (The last sentence appears to be incomplete and possibly refers to a different topic.) Figure 18C Further shown and described in this cross-sectional view is a complete horizontally oriented capacitor cell having a first electrode 1861 (e.g., a bottom cell contact electrode), a cell dielectric 1863, and a second electrode 1856 (e.g., a top common node electrode) on a semiconductor substrate 1800 to form a vertical stack. Figure 18B As shown, the vertical direction 1811 is shown as... Figure 1A-3B The third direction (D3) 1811 shown in the first, second, and third directions is similar to the z-direction in the xyz coordinate system. The left-right extending drawing plane lies on the first direction (D1) 1809. Figure 18B In an example embodiment, the first electrode 1861 (e.g., the bottom electrode coupled to the source / drain region of the horizontal access device) and the second electrode 1856 are shown separated by a cell dielectric material 1863 that extends into and out of the drawing plane in a second direction (D2) and along the orientation axis of the horizontal access device and horizontal storage node of the vertically stacked memory cell array of the three-dimensional (3D) memory.

[0208] Figure 18C Show along Figure 18A The cross-sectional view taken by the cutting line B-B' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 18CThe cross-sectional diagram shown is an iterative axis along the second horizontal direction (D2) 1805 extending left and right along the drawing plane along the alternating layers of sacrificial oxide material 1838 and epitaxially grown single-crystal silicon (Si) material 1832, wherein horizontally oriented access devices and horizontally oriented storage nodes (e.g., capacitor cells) can be formed within the layers of epitaxially grown single-crystal silicon (Si) material 1832.

[0209] exist Figure 18C In an example embodiment, a horizontally oriented memory node (e.g., a capacitor cell) is shown to have been formed in this semiconductor manufacturing process, and a first electrode 1861 (e.g., a bottom electrode coupled to the source / drain region of the horizontal access device) and a second electrode 1856 (e.g., a top electrode coupled to a common electrode plane, such as a ground plane) separated by the cell dielectric 1863 are shown. However, the embodiments are not limited to this example. In other embodiments, the first electrode 1861 (e.g., a bottom electrode coupled to the source / drain region of the horizontal access device) and the second electrode 1856 (e.g., a top electrode coupled to a common electrode plane, such as a ground plane) separated by the cell dielectric 1863 may be formed after the first source / drain region, the channel region, and the second source / drain region are formed in a region of epitaxially grown single-crystal silicon (Si) material 1832 for positioning (e.g., placement formation) the horizontally oriented access device, as described below.

[0210] exist Figure 18C In an example embodiment, a horizontally oriented memory node having a first electrode 1861 (e.g., a bottom electrode coupled to the source / drain region of a horizontal access device) and a second electrode 1856 (e.g., a top electrode coupled to a common electrode plane, such as a ground plane) is shown formed in a second horizontal opening, from a fourth vertical opening formed in a vertical stack (e.g., Figure 18B The orientation axis of the horizontal access device and the horizontal storage node of the vertically stacked memory cell array of the three-dimensional (3D) memory extends to the left and right along the drawing plane in the second direction (D2) 1805 to a third distance.

[0211] Figure 18D Show along Figure 18A The cross-sectional view taken by the cutting line C-C' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 18DThe cross-sectional diagram shown illustrates a repeating iterative axis along a second horizontal direction (D2) 1805 extending laterally along the drawing plane on the outer side of a certain region, where horizontally oriented access devices and horizontally oriented memory nodes (e.g., capacitor cells) will be formed within the layers of epitaxially grown single-crystal silicon (Si) material 1832. A portion of the first conductive material 1877 and the repeating iterative layer of epitaxially grown single-crystal silicon (Si) material 1832 (covered by oxide material 1842) are shown at the left end of the drawing, where horizontally oriented first conductive material (e.g.,...) can be formed. Figure 1A and 1B Access line 1877, etc. (as shown).

[0212] Figure 18E Show along Figure 18A The cross-sectional view taken by the cutting line D-D' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 18E The cross-sectional diagram shown is an iterative axis extending in the first direction (D1) 1809 along alternating layers of epitaxially grown single-crystal silicon (Si) material 1832, surrounded by a first dielectric material 1839 and a first conductive material 1877 wrapped with a gate dielectric material, from right to left in the drawing plane. The first conductive material 1877 is conformally deposited on each surface of the epitaxially grown single-crystal silicon (Si) material 1832 to form a gate-all-around (GAA) gate structure at the channel in the access device region. Figure 18E In the diagram, the first conductive material 1877 is shown filling the space left by the second dielectric material etched into the second vertical opening.

[0213] Figure 19A Showing for use in, for example Figure 1A-3B This is an example method of another stage of a semiconductor manufacturing process for forming epitaxial silicon within a horizontal access device in a vertical three-dimensional (3D) memory, as shown in and according to several embodiments of the present disclosure. Figure 19A A top view of a semiconductor structure at a specific point in time during a semiconductor manufacturing process according to one or more embodiments is shown.

[0214] Figure 19AThe method further illustrates the formation of a fourth vertical opening 1951 in the memory node region using one or more etchant processes. This vertical opening extends through the vertical stack and primarily in the first horizontal direction (D1) 1909. The fourth vertical opening 1951 is formed using one or more etchant processes to expose the third sidewall of a second region of the epitaxially grown single-crystal silicon (Si) material adjacent to the vertical stack during repeated iterations of alternating layers of the second electrode 1956 and the sacrificial oxide material 1938.

[0215] Figure 19B Show along Figure 19A The cross-sectional view taken by the cutting line A-A' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 19B The cross-sectional view shown is away from multiple individual horizontal access lines 1977 and illustrates repeated iterations of alternating layers of a second electrode 1956 separated by horizontally oriented capacitor cells having a first electrode 1961 (e.g., a bottom cell contact electrode), a cell dielectric 1963, and a top common node electrode on a semiconductor substrate 1900, to form a vertical stack. Figure 8B As shown, the vertical direction 1911 is shown as... Figure 1A-3B The third direction (D3) 1911 shown in the first, second, and third directions is similar to the z-direction in the xyz coordinate system. The left-right extending drawing plane lies on the first direction (D1) 1909. Figure 19B In an example embodiment, the first electrode 1961 (e.g., the bottom electrode coupled to the source / drain region of the horizontal access device) and the second electrode 1956 are shown separated by a cell dielectric material 1963 that extends into and out of the drawing plane in a second direction (D2) and along the orientation axis of the horizontal access device and horizontal storage node of the vertically stacked memory cell array of the three-dimensional (3D) memory.

[0216] Figure 19C Show along Figure 19A The cross-sectional view taken by the cutting line B-B' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 19C The cross-sectional diagram shown is an iterative axis of alternating layers along the second electrode 1956 extending laterally along the plane of the drawing in the second horizontal direction (D2) 1905, wherein horizontally oriented access devices and horizontally oriented memory nodes (e.g., capacitor cells) can be formed within the layers of epitaxially grown single-crystal silicon (Si) material 1932.

[0217] exist Figure 19CIn an example embodiment, a horizontally oriented memory node (e.g., a capacitor cell) is shown to have been formed in this semiconductor manufacturing process, and a first electrode 1961 (e.g., a bottom electrode coupled to the source / drain region of the horizontal access device) and a second electrode 1956 (e.g., a top electrode coupled to a common electrode plane, such as a ground plane) separated by a cell dielectric 1963 are shown. In this embodiment, a double-sided capacitor is shown as an alternative to a single-sided capacitor. However, the embodiment is not limited to this example. In other embodiments, the first electrode 1961 (e.g., a bottom electrode coupled to the source / drain region of the horizontal access device) and the second electrode 1956 (e.g., a top electrode coupled to a common electrode plane, such as a ground plane) separated by a cell dielectric 1963 may be formed after the first source / drain region, the channel region, and the second source / drain region are formed in a region of epitaxially grown single-crystal silicon (Si) material 1932 for positioning (e.g., placing the horizontally oriented access device), as described below.

[0218] exist Figure 19C In an example embodiment, a horizontally oriented memory node having a first electrode 1961 (e.g., a bottom electrode coupled to the source / drain region of a horizontal access device) and a second electrode 1956 (e.g., a top electrode coupled to a common electrode plane, such as a ground plane) is shown formed in a third horizontal opening, from a vertically stacked (e.g., Figure 4 The vertical opening formed in 401) and the orientation axis of the horizontal access device and horizontal storage node of the vertically stacked memory cell array of the three-dimensional (3D) memory extend to the left and right along the drawing plane in the second direction (D2) 1905 to a third distance. Figure 19C In the diagram, the adjacent horizontal access line 1977 is shown as adjacent to the second dielectric material 1933, wherein a portion of the first conductive material 1977-1 is located above the epitaxially grown single-crystal silicon (Si) material 1932, and a portion of the first conductive material 1977-2 is located below the epitaxially grown single-crystal silicon (Si) material 1932, indicating the position set inward from the drawing plane and orientation.

[0219] The second source / drain region can be formed by the following steps: vapor-doping a dopant in the side surface of an epitaxially grown single-crystal silicon (Si) material 1932 from a third horizontal opening to form a second source / drain region horizontally adjacent to the channel region; and depositing a horizontally oriented capacitor cell having a bottom electrode formed in electrical contact with the second source / drain region. In some embodiments, an ILD filling material 1967 may be deposited into a third vertical opening 1970 and fill the unetched portions of the continuous second horizontal opening 1943 up to the oxide material 1942 and the fourth vertical opening, wherein a second conductive material 1941 is coupled to a metallic material 1971.

[0220] In some embodiments, ILD filler material 1967 may be deposited into the third vertical opening 1970 and fill the unetched portions of the continuous second horizontal openings up to the oxide material 1942 and opening 1955. The fourth vertical opening 1981 may be a location where a second conductive material may subsequently be deposited.

[0221] Figure 19D Show along Figure 19A The cross-sectional view taken by the cutting line C-C' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 19D The cross-sectional view shown extends laterally along the drawing plane in the second horizontal direction (D2) 1905. Repeated iterations of alternating layers of a portion of the first conductive material 1977 are shown at the left end of the drawing. In some embodiments, ILD filler material 1967 may be deposited into the third vertical opening 1970 and fill the unetched portions of the continuous second horizontal openings up to the oxide material 1942 and opening 1955. Opening 1955 may be a location where a second conductive material can subsequently be deposited.

[0222] Figure 19E Show along Figure 19A The cross-sectional view taken by the cutting line D-D' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 19E The cross-sectional diagram shown is an illustration of alternating layers of epitaxially grown single-crystal silicon (Si) material 1932 extending from right to left in the drawing plane along a first direction (D1) 1909, the alternating layers being surrounded on all sides by oxide material 1942 and intersecting across multiple independent horizontal access lines 1977. Figure 19E In the diagram, the first dielectric filling material 1939 is shown as a space separating adjacent horizontally oriented access devices and horizontally oriented storage nodes, which can be formed to extend into and out of the drawing plane, as described in more detail below, and can be spaced along the first direction (D1) 1909 and vertically stacked in the three-dimensional (3D) memory as an array extending in the third direction (D3) 1911.

[0223] Figure 20A Showing for use in, for example Figure 1A-3B This is an example method of another stage of a semiconductor manufacturing process for forming epitaxial silicon within a horizontal access device in a vertical three-dimensional (3D) memory, as shown in and according to several embodiments of the present disclosure. Figure 20A A top view of a semiconductor structure at a specific point in time during a semiconductor manufacturing process according to one or more embodiments is shown.

[0224] Figure 20AThe method further illustrates forming a fourth vertical opening 2051 in the memory node region using one or more etchant processes. This vertical opening extends through the vertical stack and primarily in the first horizontal direction (D1) 2009. The fourth vertical opening 2051 is formed using one or more etchant processes to expose the third sidewall of a second region of epitaxially grown single-crystal silicon (Si) material adjacent to the epitaxially grown single-crystal silicon (Si) material 2032 during repeated iterations of alternating layers. A first conductive material 2077 may be formed above the fourth vertical opening 2051. An ILD filler material 2067 may be formed above the first conductive material 2077.

[0225] In some embodiments, this process is performed after selectively removing the access device regions of epitaxially grown single-crystal silicon (Si) material, wherein a first source / drain region, a channel region, and a second source / drain region of the horizontally oriented access device are formed, such as Figures 10A-10E As shown. According to Figure 20B-20E The illustrated embodiment shows a method comprising selectively etching a second region of epitaxially grown single-crystal silicon (Si) material 2032 to deposit a second source / drain region and a capacitor cell through a second horizontal opening, the second horizontal opening being a second horizontal distance backward from a fourth vertical opening 2051 in the vertical stack. In some embodiments, such as Figure 20B-20E As shown, the method includes forming a capacitor cell as a storage node in a second horizontal opening. By way of example, and not limitation, forming the capacitor includes sequentially depositing a first electrode and a second electrode separated by the cell dielectric in the second horizontal opening using an atomic layer deposition (ALD) process. Other suitable semiconductor manufacturing techniques and / or storage node structures may be used.

[0226] Figure 20B Show along Figure 20A The cross-sectional view taken by the cutting line A-A' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 20B The cross-sectional view shown is away from multiple individual horizontal access lines and illustrates repeated iterations of alternating layers of sacrificial oxide material 2038 separated by horizontally oriented capacitor cells having a first electrode 2061 (e.g., bottom cell contact electrode), a cell dielectric 2063, and a second electrode 2056 (e.g., top common node electrode) on a semiconductor substrate 2000 to form a vertical stack. Figure 20B As shown, the vertical direction 2011 is shown as... Figure 1A-3B The third direction (D3) 2011 shown in the first, second, and third directions is similar to the z-direction in the xyz coordinate system. The left-right extending drawing plane lies on the first direction (D1) 2009. Figure 20BIn an example embodiment, the first electrode 2061 (e.g., the bottom electrode coupled to the source / drain region of the horizontal access device) and the second electrode 2056 are shown separated by a cell dielectric material 2063 that extends into and out of the drawing plane in a second direction (D2) and along the orientation axis of the horizontal access device and horizontal storage node of the vertically stacked memory cell array of the three-dimensional (3D) memory.

[0227] Figure 20C Show along Figure 20A The cross-sectional view taken by the cutting line B-B' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 20C The cross-sectional diagram shown is an axis of repeated iteration along the second horizontal direction (D2) 2005 extending left and right along the drawing plane in a second horizontal direction, where horizontally oriented access devices and horizontally oriented storage nodes (e.g., capacitor cells) can be formed.

[0228] exist Figure 20C In an example embodiment, a horizontally oriented memory node (e.g., a capacitor cell) is shown to have been formed in this semiconductor manufacturing process, and a first electrode 2061 (e.g., a bottom electrode coupled to the source / drain region of the horizontal access device) and a second electrode 2056 (e.g., a top electrode coupled to a common electrode plane, such as a ground plane) separated by the cell dielectric 2063 are shown. However, the embodiments are not limited to this example. In other embodiments, the first electrode 2061 (e.g., a bottom electrode coupled to the source / drain region of the horizontal access device) and the second electrode 2056 (e.g., a top electrode coupled to a common electrode plane, such as a ground plane) separated by the cell dielectric 2063 may be formed after the formation of the first source / drain region, the channel region, and the second source / drain region for positioning (e.g., placing the horizontally oriented access device), as described below.

[0229] exist Figure 20C In an example embodiment, a horizontally oriented memory node having a first electrode 2061 (e.g., a bottom electrode coupled to the source / drain region of a horizontal access device) and a second electrode 2056 (e.g., a top electrode coupled to a common electrode plane, such as a ground plane) is shown formed in a second horizontal opening in a vertically stacked (e.g., Figure 4 The orientation axis of the horizontal access device and the horizontal storage node formed in 401 of the three-dimensional (3D) memory vertical stacked memory cell array extends left and right along the drawing plane in the second direction (D2).

[0230] The second conductive material 2041 can be formed as a vertical digital line adjacent to the first conductive material 2077. The second conductive material 2041 can form a vertically oriented digital line adjacent to the first source / drain region. The first source / drain region can be formed by diffusing an n-type dopant from the n-type polycrystalline silicon (Si) material of the second conductive material 2041 into the silicon material in which the dopant is vapor-doped into the top surface portion of the epitaxially grown single-crystal silicon (Si) material.

[0231] In some embodiments, ILD filling material 2067 may be deposited into the third vertical opening 2070 and fill the continuous second horizontal openings up to the unetched portions of the oxide material 2042 and the second conductive material 2041. In some embodiments, the second conductive material 2041 may be formed of silicide. In some embodiments, the second conductive material 2041 may include titanium material. In some embodiments, the second conductive material 2041 may include titanium nitride (TiN) material. In some embodiments, the second conductive material 2041 may include ruthenium (Ru) material. In some embodiments, the second conductive material 2041 may be tungsten (W).

[0232] In one embodiment, the second conductive material 2041 can be formed by using high-energy (e.g., PECVD) vapor phase doping with a high-energy vapor phase dopant (e.g., phosphorus (P) atoms) as an impurity dopant to form a high concentration of n-type doped (n+) regions within the fourth vertical opening 2081. Polycrystalline silicon (Si) material can be deposited into the fourth vertical opening 2081. For example, highly phosphorus (P)-doped (n+) polycrystalline silicon germanium (SiGe) material can be inserted into the fourth vertical opening 2081 to form the second conductive material 2041.

[0233] The first source / drain region can be formed by diffusing an n-type (n+) dopant outward into epitaxially grown single-crystal silicon (Si) material. In one embodiment, a plurality of patterned fourth vertical openings may be adjacent to the first source / drain region, and a high concentration of n-type dopant may diffuse outward into the epitaxially grown single-crystal silicon (Si) material to form the first source / drain region. The first source / drain region can be formed on the epitaxially grown single-crystal silicon (Si) material.

[0234] Figure 20D Show along Figure 20A The cross-sectional view taken by the cutting line C-C' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 20D The cross-sectional view shown extends horizontally along the second horizontal direction (D2) 2005 on the drawing plane. At the left end of the drawing, repeated iterations of alternating layers of a portion of the first conductive material 2077 are shown.

[0235] Figure 20E Show along Figure 20A The cross-sectional view taken by the cutting line D-D' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 20E The cross-sectional diagram shown is an illustration extending from right to left in the drawing plane along a first direction (D1) 2009 along the repeating iterative axis of alternating layers of grown monocrystalline silicon (Si) material 2032, which are surrounded on all sides by oxide material 2042 and intersect across multiple independent horizontal access lines 2077. Figure 20E In the diagram, the first dielectric filling material 2039 is shown as a space separating adjacent horizontally oriented access devices and horizontally oriented storage nodes. It can be formed to extend into and out of the drawing plane, as described in more detail below, and can be spaced apart along the first direction (D1) 2009 and vertically stacked in the three-dimensional (3D) memory as an array extending in the third direction (D3) 2011.

[0236] Figure 21A Show along Figure 20A The cross-sectional view taken by the cutting line B-B' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 21A The cross-sectional diagram shown is an iterative axis along a second horizontal direction (D2) 2105 extending laterally along the drawing plane, where a sacrificial oxide material 2038 surrounded by alternating layers of capacitor cells having a first electrode 2061 (e.g., a bottom unit contact electrode), a unit dielectric 2063, and separated by a second electrode 2056, can be formed, along which horizontally oriented access devices and horizontally oriented storage nodes (e.g., capacitor cells) can be formed. Figure 21A In an example embodiment, a horizontally oriented memory node (e.g., a capacitor cell) is shown to have been formed in this semiconductor manufacturing process, and a first electrode 2161 (e.g., a bottom electrode coupled to the source / drain region of the horizontal access device) and a second electrode 2156 (e.g., a top electrode coupled to a common electrode plane, such as a ground plane) separated by cell dielectric 2163 are shown. However, the embodiments are not limited to this example. In other embodiments, the first electrode 2161 (e.g., a bottom electrode coupled to the source / drain region of the horizontal access device) and the second electrode 2156 (e.g., a top electrode coupled to a common electrode plane, such as a ground plane) separated by cell dielectric 2163 may be formed after the formation of the first source / drain region 2175, the channel region, and the second source / drain region for positioning (e.g., placement formation) the horizontally oriented access device, as described below.

[0237] exist Figure 21AIn an example embodiment, a horizontally oriented memory node having a first electrode 2161 (e.g., a bottom electrode coupled to the source / drain region of a horizontal access device) and a second electrode 2156 (e.g., a top electrode coupled to a common electrode plane, such as a ground plane) is shown formed in a fourth horizontal opening that is in a vertically stacked (e.g., Figure 4 The orientation axis of the horizontal access device and the horizontal storage node formed in 401 of the three-dimensional (3D) memory vertical stacked memory cell array extends left and right along the drawing plane in the second direction (D2).

[0238] A second conductive material 2141 may be formed within the third vertical opening 2181. The second conductive material 2141 may be formed of a high-concentration n-type dopant. A high-concentration n-type dopant may be formed by depositing polycrystalline silicon material onto the second conductive material 2141. For example, a high-concentration n-type dopant may be formed by depositing highly phosphorus (P)-doped (n+) polycrystalline silicon germanium (SiGe) material onto the second conductive material 2141.

[0239] Metal material 2171 may be deposited in a third vertical opening 2181 within the second conductive material 2141. In some embodiments, metal material 2171 may include one or more of the following: doped semiconductors (e.g., doped silicon, doped germanium, etc.), conductive metal nitrides (e.g., titanium nitride, tantalum nitride, etc.), metals (e.g., tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), cobalt (Co), molybdenum (Mo), etc.) and / or metal semiconductor compounds (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.) and / or one or more other combinations thereof. Metal material 2171 coupled to the second conductive material 2141 may be formed vertically adjacent to the first conductive material 2177.

[0240] Figure 21B Show along Figure 20A The cross-sectional view taken by the cutting line B-B' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 21B The cross-sectional diagram shown is an axis of repeated iterations along a second horizontal direction (D2) 2105 extending laterally along the drawing plane in a second horizontal direction, where horizontally oriented access devices and horizontally oriented storage nodes (e.g., capacitor cells) can be formed. This axis is formed by capacitor cells surrounded by alternating layers of sacrificial oxide material 2138 having a first electrode 2161 (e.g., a bottom unit contact electrode), a unit dielectric 2163, and separated by a second electrode. Figure 21BIn an example embodiment, a horizontally oriented memory node (e.g., a capacitor cell) is shown to have been formed in this semiconductor manufacturing process, and a first electrode 2161 (e.g., a bottom electrode coupled to the source / drain region of the horizontal access device) and a second electrode 2156 (e.g., a top electrode coupled to a common electrode plane, such as a ground plane) separated by the cell dielectric 2163 are shown. However, the embodiments are not limited to this example. In other embodiments, the first electrode 2161 (e.g., a bottom electrode coupled to the source / drain region of the horizontal access device) and the second electrode 2156 (e.g., a top electrode coupled to a common electrode plane, such as a ground plane) separated by the cell dielectric 2163 may be formed after the formation of a second conductive material coupled to the source / drain region and the channel region.

[0241] exist Figure 21B In an example embodiment, a horizontally oriented memory node having a first electrode 2161 (e.g., a bottom electrode coupled to the source / drain region of a horizontal access device) and a second electrode 2156 (e.g., a top electrode coupled to a common electrode plane, such as a ground plane) is shown formed in a second horizontal opening in a vertically stacked (e.g., Figure 4 The orientation axis of the horizontal access device and the horizontal storage node formed in 401 of the three-dimensional (3D) memory vertical stacked memory cell array extends left and right along the drawing plane in the second direction (D2).

[0242] A second conductive material 2141 may be formed within the third vertical opening 2181. The second conductive material 2141 may be formed of a high-concentration n-type dopant. A high-concentration n-type dopant may be formed by depositing polycrystalline silicon material onto the second conductive material 2141. For example, a high-concentration n-type dopant may be formed by depositing highly phosphorus (P)-doped (n+) polycrystalline silicon germanium (SiGe) material onto the second conductive material 2141.

[0243] Metal material 2171 may be deposited in a third vertical opening 2181 within the second conductive material 2141. In some embodiments, metal material 2171 may include one or more of the following: doped semiconductors (e.g., doped silicon, doped germanium, etc.), conductive metal nitrides (e.g., titanium nitride, tantalum nitride, etc.), metals (e.g., tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), cobalt (Co), molybdenum (Mo), etc.) and / or metal semiconductor compounds (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.) and / or one or more other combinations thereof. Metal material 2171 coupled to the second conductive material 2141 may be formed vertically adjacent to the first conductive material 2177.

[0244] Figure 22AAn example method is shown for another stage of a semiconductor manufacturing process for forming epitaxial silicon within a horizontal access device in a vertical three-dimensional (3D) memory according to several embodiments of the present disclosure. Figure 22A A top view of a semiconductor structure at a specific point in time during a semiconductor manufacturing process according to one or more embodiments is shown. In an example embodiment of 22A, the method includes patterning a photomask 2237 using a photolithography process, wherein a second conductive material 2241 is asymmetrical, thereby reserving space for a body contact 2295. Figure 22A The method further illustrates the formation of a vertical opening 2251 in the memory node region 2250 using one or more etchant processes, the vertical opening extending through the vertical stack and primarily in the first horizontal direction (D1) 2209. The vertical opening 2251 is formed by one or more etchant processes to expose a third sidewall of a second region adjacent to the semiconductor material during repeated iterations of alternating layers in the vertical stack.

[0245] According to an example embodiment, the method includes selectively etching a second region of epitaxially grown single-crystal silicon (Si) material 2232 to deposit a second source / drain region and a capacitor cell through a fourth vertical opening. As an example, and not a limitation, forming the capacitor includes sequentially depositing a first electrode 2261 and a second electrode 2256 separated by a cell dielectric 2263 in a second horizontal opening using an atomic layer deposition (ALD) process. Other suitable semiconductor manufacturing techniques and / or memory node structures may be used.

[0246] In other embodiments, the method further includes forming a first source / drain region and a second conductive material 2241 through a third vertical opening 2281. The second conductive material 2241 may be formed vertically through a vertical stack via a plurality of patterned third vertical openings 2281. Vertically oriented digital lines are formed asymmetrically adjacent to the first source / drain region 2275 in electrical contact with it. The second conductive material 2241 may form vertical digital lines adjacent to the first source / drain region 2275. The first source / drain region 2275 may be formed adjacent to the first conductive material 2277 and around a plurality of patterned third vertical openings 2281.

[0247] Figure 22B An example method is shown for another stage of a semiconductor manufacturing process for forming epitaxial silicon within a horizontal access device in a vertical three-dimensional (3D) memory according to several embodiments of the present disclosure. Figure 22B A top view of a semiconductor structure at a specific point in time during a semiconductor manufacturing process according to one or more embodiments is shown. In an example embodiment 22B, the method includes patterning a photomask 2237 using a photolithography process, wherein a second conductive material 2241 is symmetrically deposited. Figure 22BThe method further illustrates forming a vertical opening 2251 in the memory node region 2250 using one or more etchant processes, the vertical opening extending through the vertical stack and primarily in the first horizontal direction (D1) 2209. The vertical opening 2251 is formed by one or more etchant processes to expose the third sidewall of a second region adjacent to the semiconductor material in the vertical stack.

[0248] According to an example embodiment, the method includes selectively etching a second region of epitaxially grown single-crystal silicon (Si) material 2232 to deposit a second source / drain region and a capacitor cell. In some embodiments, the method includes forming a capacitor cell as a storage node in a second horizontal opening. By way of example, and not limitation, forming the capacitor includes sequentially depositing a first electrode 2261 and a second electrode 2256 separated by a cell dielectric 2263 in the second horizontal opening using an atomic layer deposition (ALD) process. Other suitable semiconductor manufacturing techniques and / or storage node structures may be used.

[0249] In other embodiments, the method further includes forming a first source / drain region and a second conductive material 2241 through a third vertical opening 2281. The second conductive material 2241 may be vertically formed through a vertical stack via multiple patterned third vertical openings 2281. The second conductive material 2241 may be symmetrically formed as vertical digital line contacts. The vertically oriented digital lines are symmetrically formed in a vertically aligned manner to make electrical contact with the first source / drain region 2275. The second conductive material 2241 may be formed in contact with an insulating material 2292 such that there are no body contacts within the second vertical opening 2270. The second conductive material 2241 may form vertical digital lines adjacent to the first source / drain region 2275. The first source / drain region 2275 may be formed adjacent to the first conductive material 2277 and around the multiple patterned third vertical openings 2281.

[0250] Figure 23A An alternative top view is shown, illustrating another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process and according to several embodiments of this disclosure. Figure 23A A top view of a semiconductor structure with dual vertical digital lines is shown. Figure 23A As shown, embodiments of this disclosure can be used in structures in which vertically stacked memory cell arrays are electrically coupled in a folded digital line structure. In the folded digital line structure, dual structures can share a single word line 2303. The folded digital line structure is possible when the digital line 2307 has an odd number of word lines 2303. The folded digital line structure is possible when only one word line in a subarray block is active.

[0251] Figure 23BAn alternative top view is shown, illustrating another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process and according to several embodiments of this disclosure. Figure 23B A top view of a semiconductor structure with dual vertical digital lines is shown. Figure 23B As shown, embodiments of this disclosure can be used in structures in which vertically stacked memory cell arrays are electrically coupled in an open digital line architecture. In an open digital line architecture, each digital line structure may have its own word line 2303, such that a dual vertical digital line structure may have two word lines. An open digital line architecture is possible when the digital lines 2307 have an even number of word lines 2303. If two adjacent word lines are connected, only an open digital line architecture is possible; a folded digital line architecture is not possible.

[0252] Figure 24 This is a block diagram of a device in the form of a computing system 2400 including a memory device 2403, according to several embodiments of the present disclosure. As used herein, for example, the memory device 2403, the memory array 2410, and / or the host 2402 may also be individually considered as a "device". According to an embodiment, the memory device 2402 may include at least one memory array 2410 having memory cells formed with digital lines and body contacts.

[0253] In this example, system 2400 includes a host 2402 coupled to memory device 2403 via interface 2404. The computing system 2400 may be a personal laptop, desktop computer, digital camera, mobile phone, memory card reader, or Internet of Things (IoT) enabled device, as well as various other types of systems. Host 2402 may include multiple processing resources (e.g., one or more processors, microprocessors, or other types of control circuitry) capable of accessing memory 2403. System 2400 may include a separate integrated circuit, or both host 2402 and memory device 2403 may be on the same integrated circuit. For example, host 2402 may be a system controller for a memory system including multiple memory devices 2403, wherein system controller 2405 provides access to the respective memory devices 2403 by another processing resource, such as a central processing unit (CPU).

[0254] exist Figure 24In the example shown, host 2402 is responsible for executing an operating system (OS) and / or various applications (e.g., processes) that can be loaded onto it (e.g., loaded from memory device 2403 via controller 2405). The OS and / or various applications can be loaded from memory device 2403 by providing access commands from host 2402 to memory device 2403 to access data including the OS and / or various applications. Host 2402 can also access said data by providing access commands to memory device 2403 to retrieve data used by the OS and / or various applications during execution.

[0255] For clarity, system 2400 has been simplified to focus on features particularly relevant to this disclosure. Memory array 2410 may be a DRAM array comprising at least one memory cell having digital lines and body contacts formed according to the techniques described herein. For example, memory array 2410 may be an unshielded DL 4F2 array, such as a 3D-DRAM memory array. Array 2410 may include memory cells arranged in rows coupled by word lines (which may be referred to herein as access lines or select lines) and columns coupled by digital lines (which may be referred to herein as sense lines or data lines). Although Figure 24 A single array 2410 is shown, but the embodiments are not limited thereto. For example, memory device 2403 may include multiple arrays 2410 (e.g., multiple groups of DRAM cells).

[0256] Memory device 2403 includes address circuitry 2406 for latching address signals provided via interface 2404. The interface may include a physical interface employing, for example, a suitable protocol (e.g., a data bus, address bus, and command bus, or a combination of data / address / command buses). Such a protocol may be custom or proprietary, or interface 2404 may employ a standardized protocol, such as Peripheral Component Interconnect High Speed ​​(PCIe), Gen-Z, CCIX, etc. Address signals are received and decoded by row decoder 2408 and column decoder 2412 to access memory array 2410. Data can be read from memory array 2410 by sensing voltage and / or current changes on a sensing line using sensing circuitry 2411. Sensing circuitry 2411 may include, for example, a sensing amplifier that can read and latch a page (e.g., a row) of data from memory array 2410. I / O circuitry 2407 can be used for bidirectional data communication with host 2402 via interface 2404. The read / write circuitry 2413 is used to write data to or read data from the memory array 2410. For example, the circuitry 2413 may include various drivers, latching circuitry, etc.

[0257] The control circuitry system 2405 decodes signals provided by the host 2402. These signals may be commands provided by the host 2402. These signals may include chip enable signals, write enable signals, and address latch signals for controlling operations performed on the memory array 2410 (including data read operations, data write operations, and data erase operations). In various embodiments, the control circuitry system 2405 is responsible for executing instructions from the host 2402. The control circuitry system 2405 may include a state machine, a sequencer, and / or certain other types of control circuitry systems, which may be implemented in hardware, firmware, or software, or any combination thereof. In some instances, the host 2402 may be a controller external to the memory device 2403. For example, the host 2402 may be a memory controller coupled to the processing resources of a computing device.

[0258] For example, the term semiconductor can refer to a material, wafer, or substrate, and includes any substrate semiconductor structure. "Semiconductor" should be understood to include silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin-film transistor (TFT) technology, doped and undoped semiconductors, epitaxial silicon supported by a substrate semiconductor structure, and other semiconductor structures. Furthermore, when referenced to semiconductor in the foregoing description, prior processing steps may have been used to form regions / junctions in the substrate semiconductor structure, and the term semiconductor may include an underlying material containing these regions / junctions.

[0259] The figures in this document follow a numbering convention, where the first one or more numbers correspond to the figure number, and the remaining numbers identify the elements or components in the figure. Similar (e.g., identical) elements or components between different figures can be identified by using similar numbers. It should be understood that elements shown in the various embodiments herein can be added, interchanged, and / or removed to provide multiple additional embodiments of this disclosure. Furthermore, it should be understood that the scale and relative dimensions of the elements provided in the figures are intended to illustrate embodiments of this disclosure and should not be construed as limiting.

[0260] As used herein, “multiple” or “a number” of something can refer to one or more of such things. For example, multiple or a number of memory cells can refer to one or more memory cells. “Multiple” something means two or more. As used herein, multiple actions performed simultaneously refer to actions that overlap at least partially within a specific time period. As used herein, the term “coupling” can include electrical coupling, direct coupling and / or direct connection (e.g., by direct physical contact) without intermediate elements, or indirect coupling and / or connection with intermediate elements, or wireless coupling. The term coupling can further include two or more elements that cooperate or interact with each other (e.g., as in causality). An element coupled between two elements can be between and coupled to each of the two elements.

[0261] It should be recognized that the term "vertical" refers to variations in verticality due to routine manufacturing, measurement, and / or assembly changes, and those skilled in the art should understand the meaning of the term "vertical." For example, vertical may correspond to the z-direction. As used herein, when a particular element is "adjacent" to another element, the particular element may cover the other element, may be above or laterally to the other element, and / or may be in direct physical contact with the other element. For example, laterally to may refer to a horizontal direction that may be perpendicular to the z-direction (e.g., the y-direction or x-direction).

[0262] While specific embodiments have been shown and described herein, those skilled in the art will understand that arrangements calculated to achieve the same results may replace the specific embodiments shown. This disclosure is intended to cover modifications or variations of various embodiments of this disclosure. It should be understood that the above description has been carried out illustratively and not restrictively. Combinations of the above embodiments and other embodiments not specifically described herein will be apparent to those skilled in the art upon review of the above description. The scope of the various embodiments of this disclosure includes other applications in which the above structures and methods are used. Therefore, the scope of the various embodiments of this disclosure should be determined by reference to the appended claims and the full scope of the equivalents granted therein.

Claims

1. A method for forming a vertically stacked memory cell array, the vertically stacked memory cell array having horizontally oriented access means and memory nodes, the method comprising: Silicon-germanium (SiGe) materials (430, 530, 630, 730, 830, 930, 1030, 1130, 1230, 1) are epitaxially formed from substrates (400, 500, 600, 700, 800, 900, 1000, 1100, 1200, 1300, 1400, 1500, 1600, 1700, 1800, 1900, 2000). Alternating layers of 330, 1430, 1530, 1630, 1730) and silicon (Si) materials (432, 532, 632, 732, 832, 932, 1032, 1132, 1232, 1332, 1432, 1532, 1632, 1732, 1832, 1932, 2032, 2132, 2232) are used to form a vertical stack (401); The vertical stack (401) forms a first horizontal direction (509, 609, 709, 809, 909, 1009, 1109, 1209, 1309, 1409, 1509, 1609, 1709, 1809, 1909, 2009, 2109, 2209) and a second horizontal direction (505, 605, 705, 805, 905, 1005, 1105, 1209). Multiple first vertical openings (515, 615, 715, 815, 915, 1015, 1115, 1215) of 5, 1305, 1405, 1505, 1605, 1705, 1805, 1905, 2005, 2105, 2205), the first vertical openings extending primarily in the second horizontal direction to form an elongated vertical column with first vertical sidewalls in the stack (401); The plurality of first vertical openings are filled with a first dielectric material (539, 639, 739, 839, 939, 1039, 1139, 1239, 1339, 1439, 1539, 1639, 1739, 1839, 1939, 2039); By selectively removing a portion of the first dielectric material (539, 639, 739, 839, 939, 1039, 1139, 1239, 1339, 1439, 1539, 1639, 1739, 1839, 1939, 2039) from the plurality of first vertical openings to expose the sidewalls of the first region of the adjacent epitaxially grown silicon-germanium (SiGe), a plurality of spaced-apart second vertical openings (631, 731, 831, 931, 1031, 1131, 1231, 1331, 1431, 1531) are formed through the vertical stack (401); The epitaxially grown silicon-germanium (SiGe) is selectively etched isotropically to form a plurality of first horizontal openings (773, 873, 973); A second dielectric material (833, 933, 1033, 1133, 1233, 1333, 1433, 1533, 1633, 1733, 1833, 1933, 2033) is conformally deposited on the exposed surfaces in the plurality of first horizontal openings (773, 873, 973); The first dielectric material (539, 639, 739, 839, 939, 1039, 1139, 1239, 1339, 1439, 1539, 1639, 1739, 1839, 1939, 2039) is deposited to fill the plurality of first horizontal openings (773, 873, 973); A third vertical opening (1070, 1170, 1270, 1370, 1470, 1570, 1670, 1770, 1870, 1970, 2070, 2170, 2270) is formed, which extends through the vertical stack (401) and mainly in the first horizontal direction to expose the sidewalls of the second region adjacent to the epitaxially grown silicon germanium (SiGe); Selectively etch the epitaxially grown silicon-germanium (SiGe) to form a plurality of second horizontal openings (1179) extending a first distance (DIST 1) (1176) from the third vertical opening; Selectively etching the second dielectric material from the third vertical opening to a second distance (DIST 2) (1283), wherein selectively etching the epitaxially grown silicon germanium (SiGe) to form the plurality of second horizontal openings extending from the third vertical opening to the first distance (DIST 1) includes using the second dielectric material as an etch stop layer. as well as A gate dielectric material (304, 1342, 1442, 1542, 1642, 1742, 1832, 1932, 2032, 2132, 2232) is formed on the exposed surface of an epitaxially formed silicon (Si) material (432, 532, 632, 732, 832, 932, 1032, 1132, 1232, 1332, 1432, 1532, 1642, 1742, 1842) to form a horizontal access device.

2. The method of claim 1, wherein forming the gate dielectric material comprises: Atomic layer deposition is used to first deposit a layer of oxide material on the exposed surface of the epitaxially formed silicon (Si) material; as well as Thermal oxidation is used to densify the oxide material deposited by ALD.

3. The method according to claim 1, wherein, Selective etching of the second dielectric material includes removing a second distance (DIST 2) (1283) of the second dielectric material in the range of 25 (25) to 75 (75) nanometers (nm) using a timed excitation process; Using an atomic layer etching (ALE) process, the first conductive material (1477, 1577, 1677, 1777, 1877, 1977, 2077, 2177, 2277) and the gate dielectric material are selectively recessed in the second horizontal direction within the third vertical opening, from the third vertical opening back to the third distance (DIST 3) in the range of twenty (20) to fifty (50) nanometers (nm) of the second horizontal opening extending along the first horizontal direction.

4. The method of claim 1, further comprising: Formed from silicon nitride material with a diameter of 100 to 300 angstroms ( The second dielectric material with a conformal thickness (t1) within the range of ) ; The silicon (Si) material is epitaxially grown to have a density of 50 to 300 angstroms. The vertical thickness (t2) within the range of ) 5. The method according to any one of claims 1 to 4, wherein depositing the first conductive material comprises depositing the first conductive material completely surrounding each surface of the silicon (Si) material to form a gate-surrounded all-around (GAA) structure at the channel of the access device region.

6. The method according to any one of claims 1 to 4, further comprising depositing on the gate dielectric material and surrounding the silicon (Si) material to form a first conductive material, and recessing to form a gate-enclosed GAA structure opposite to the channel region of the silicon (Si) material.

7. The method according to any one of claims 1 to 4, wherein the method comprises: A portion of the first dielectric material filling the plurality of first vertical openings between the first horizontal openings is removed to form a continuous second horizontal opening extending in the first horizontal direction; as well as A first conductive material is deposited in the continuous second horizontal opening to form a horizontally oriented access line opposite to the channel region of the silicon (Si) material.

8. The method according to any one of claims 1 to 4, the method further comprising forming a plurality of patterned fourth vertical openings through the vertical stack adjacent to the first source / drain regions (121, 221, 321, 2175, 2275), wherein a second conductive material (2041, 2141, 2241) is deposited to form vertically oriented digital lines.

9. The method of claim 8, further comprising: The vertical stacks passing through the adjacent first source / drain regions deposit doped n-type polycrystalline silicon (Si) material in the plurality of patterned fourth vertical openings to form the vertically oriented digital lines; Annealing is used to diffuse n-type dopant from the n-type polysilicon (Si) material into the epitaxially formed silicon (Si) material to form a first source / drain region adjacent to the channel region in the horizontally oriented access device.

10. The method according to any one of claims 1 to 4, further comprising: A fourth vertical opening (1751, 1851, 1951, 2051) is formed in the second region adjacent to the epitaxially grown single-crystal silicon (Si) material to expose the third vertical sidewall in the vertical stack. The epitaxially grown single-crystal silicon (Si) material is selectively etched in the second horizontal direction to form a plurality of third horizontal openings (1779) in the second region; Vapor dopant is vapor-doped into the side surface of the epitaxially grown single-crystal silicon (Si) material from the third horizontal opening (1779) to form a second source / drain region (123, 223, 323) horizontally adjacent to the channel region; and Deposit horizontally oriented capacitor cells having bottom electrodes (1861, 1961, 2061, 2161) formed in electrical contact with the second source / drain regions (123, 223, 323).

11. The method according to any one of claims 1 to 4, wherein depositing a first conductive material surrounding the silicon (Si) material comprises depositing the first conductive material having a top portion above the silicon (Si) material and a bottom portion below the epitaxially grown single-crystal silicon (Si) material.

12. The method according to any one of claims 1 to 4, wherein depositing a conductive material on the gate dielectric material and recessing in the successive second horizontal openings extending along the first horizontal direction comprises: The gate dielectric and the conductive material are deposited using an atomic layer deposition (ALD) process.

13. The method according to any one of claims 1 to 4, further comprising depositing a ruthenium (Ru) composition as a second conductive material through the vertically stacked plurality of patterned fourth vertical openings to form vertically oriented digital lines.

14. A method for forming a vertically stacked memory cell array, the vertically stacked memory cell array having horizontally oriented access means and memory nodes, the method comprising: Silicon-germanium (SiGe) materials (430, 530, 630, 730, 830, 930, 1030, 1130, 1230, 1) are epitaxially formed from substrates (400, 500, 600, 700, 800, 900, 1000, 1100, 1200, 1300, 1400, 1500, 1600, 1700, 1800, 1900, 2000). Alternating layers of 330, 1430, 1530, 1630, 1730) and silicon (Si) materials (432, 532, 632, 732, 832, 932, 1032, 1132, 1232, 1332, 1432, 1532, 1632, 1732, 1832, 1932, 2032, 2132, 2232) are used to form a vertical stack (401); The vertical stack (401) forms a first horizontal direction (509, 609, 709, 809, 909, 1009, 1109, 1209, 1309, 1409, 1509, 1609, 1709, 1809, 1909, 2009, 2109, 2209) and a second horizontal direction (505, 605, 705, 805, 905, 1005, 1105, 1209). Multiple first vertical openings (515, 615, 715, 815, 915, 1015, 1115, 1215) of 5, 1305, 1405, 1505, 1605, 1705, 1805, 1905, 2005, 2105, 2205), the first vertical openings extending primarily in the second horizontal direction to form an elongated vertical column with first vertical sidewalls in the stack (401); The plurality of first vertical openings are filled with a first dielectric material (539, 639, 739, 839, 939, 1039, 1139, 1239, 1339, 1439, 1539, 1639, 1739, 1839, 1939, 2039); By patterning and selectively removing the first dielectric material from the plurality of first vertical openings (in the first horizontal direction) to expose the second vertical sidewalls of the first region of the epitaxially grown silicon germanium (SiGe), a plurality of spaced second vertical openings (631, 731, 831, 931, 1031, 1131, 1231, 1331, 1431, 1531) are formed through the vertical stack (401); The epitaxially grown silicon-germanium (SiGe) is selectively etched isotropically to form a plurality of first horizontal openings (773, 873, 973) in the first region to separate layers of the silicon (Si) material; A second dielectric material (833, 933, 1033, 1133, 1233, 1333, 1433, 1533, 1633, 1733, 1833, 1933, 2033) is conformally deposited on the exposed surfaces in the plurality of first horizontal openings (773, 873, 973) to a first thickness (t1); The first dielectric material is deposited through the plurality of spaced-apart second vertical openings (631, 731, 831, 931, 1031, 1131, 1231, 1331, 1431, 1531) to fill the plurality of first horizontal openings (773, 873, 973); A third vertical opening (1070, 1170, 1270, 1370, 1470, 1570, 1670, 1770, 1870, 1970, 2070, 2170, 2270) is formed, the third vertical opening extending through the vertical stack (401) and primarily in the first horizontal direction to expose the third vertical sidewall of the second region adjacent to the epitaxially grown silicon-germanium (SiGe); and Selective etching of the epitaxially grown silicon-germanium (SiGe) to form a plurality of second horizontal openings (1179) extending a first distance (DIST 1) (1176) from the third vertical opening (1070, 1170, 1270, 1370, 1470, 1570, 1670, 1770, 1870, 1970, 2070, 2170, 2270) in the second region, and terminating on the second dielectric material (833, 933, 1033, 1133, 1233, 1333, 1433, 1533, 1633, 1733, 1833, 1933, 2033).

15. The method of claim 14, further comprising: A portion of the first dielectric material filling the plurality of first vertical openings between the first horizontal openings is removed to form a continuous second horizontal opening extending in the first horizontal direction; A first conductive material (1477, 1577, 1677, 1777, 1877, 1977, 2077, 2177, 2277) is deposited on and surrounds the silicon (Si) material on a gate dielectric material (304, 1342, 1442, 1542, 1642, 1742, 1842) and recessed in the consecutive second horizontal openings to form a horizontally oriented access line opposite to the channel region of the silicon (Si) material; and The vertical stacks passing through the adjacent first source / drain regions (121, 221, 321, 2175, 2275) form a plurality of patterned fourth vertical openings, in which a second conductive material (2041, 2141, 2241) is deposited to form vertically oriented digital lines.

16. The method of claim 15, wherein a polycrystalline silicon (Si) material having a high concentration of n-type (n+) dopant is deposited in the patterned fourth vertical opening.

17. The method of claim 16, further comprising forming an oxide material having a diameter of 300 to 600 angstroms ( ). The epitaxially grown silicon-germanium (SiGe) with a thickness within the range of ) 18. The method of claim 16, wherein forming the plurality of patterned fourth vertical openings through the vertical stack comprises forming the plurality of patterned fourth vertical openings vertically aligned with the location of the first source / drain region to serve as the first source / drain region.

19. The method of claim 16, wherein forming the plurality of patterned fourth vertical openings through the vertical stack comprises forming the plurality of patterned fourth vertical openings at a location adjacent to the first source / drain region, and diffusing the n-type (n+) dopant outward into the epitaxially grown single-crystal silicon (Si) material to form the first source / drain region.

20. The method of claim 16, wherein the polycrystalline silicon (Si) material deposited in the patterned fourth vertical opening with a high concentration of n-type (n+) dopant comprises highly phosphorus (P) doped (n+) polycrystalline silicon germanium (SiGe) material.

21. A memory device for forming a vertically stacked memory cell array, the vertically stacked memory cell array having horizontally oriented access means and memory nodes, the memory device comprising: A vertically stacked memory cell array, the array having horizontally oriented access devices and memory nodes, including: A horizontally oriented access device having a first source / drain region (121, 221, 321, 2175, 2275) and a second source / drain region (123, 223, 323) separated by an epitaxially grown channel region, and a gate opposite to the channel region formed on each surface of a gate dielectric material (304, 1342, 1442, 1542, 1642, 1742, 1842) as a gate-enclosed all-around (GAA) structure; and A horizontally oriented memory node electrically coupled to the second source / drain region (123, 223, 323) of the horizontally oriented access device; The channel region is a single-crystal silicon channel region, which is formed by alternating epitaxial growth of silicon-germanium (SiGe) material (430, 530, 630, 730, 830, 930, 1030, 1130, 1230, 1330, 1430, 1530, 1630, 1730) and silicon (Si) material (432, 532, 632, 732, 832, 932, 1032, 1132, 1232, 1332, 1432, 1532, 1632, 1732, 1832, 1932, 2032, 2132). It is formed by alternating layers of 2232) and selectively etching the epitaxially grown silicon germanium (SiGe), and a second dielectric material (833, 933, 1033, 1133, 1233, 1333, 1433, 1533, 1633, 1733, 1833, 1933, 2033) is provided between adjacent single-crystal silicon channel regions as an etching termination layer.

22. The memory device of claim 21, comprising: A horizontally oriented access line coupled to the gate and separated from the channel region by the gate dielectric; as well as A vertically oriented digital line is electrically coupled to the first source / drain region of the horizontally oriented access device.

23. The memory device of claim 21, wherein the gate opposite the channel region provides a sub-threshold voltage (sub-Vt) slope in the range of 45 to 100 millivolts (mV / dec).

24. The memory device according to any one of claims 21 to 23, wherein the vertically oriented digital line comprises tungsten (W) material formed on a titanium / titanium nitride (TiN) material, which forms titanium silicide with the first source / drain region of the horizontally oriented access device.

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