Carrier plate for manufacturing a package substrate, package substrate structure and method of manufacturing thereof

Abstract

The application discloses a carrier plate for preparing a packaging substrate, comprising a medium layer, a seed layer in the medium layer, and a copper column layer on the seed layer, the bottom end of the seed layer is higher than the lower surface of the medium layer, the top end of the copper column layer is lower than the upper surface of the medium layer, and the upper and lower surfaces of the medium layer are respectively provided with a first metal layer and a second metal layer. The application also discloses a packaging substrate structure and a manufacturing method of the packaging substrate structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging, and more specifically to a carrier plate for preparing a packaging substrate, a packaging substrate structure, and a method for manufacturing the same. Background Technology

[0002] Existing technology for manufacturing solid copper pillars in the core layer involves blind drilling with a mechanical drill followed by electroplating to fill the holes. This results in residual stubs at the bottom of the mechanically drilled blind holes, which affects the fabrication of the copper pillars and leads to poor conductivity between layers.

[0003] In addition, mechanical blind holes have a large aspect ratio, resulting in poor quality copper pillars after electroplating. Summary of the Invention

[0004] The embodiments of the present invention relate to providing a carrier plate for preparing a packaging substrate, a packaging substrate structure, and a method for manufacturing the same.

[0005] The first aspect of the present invention relates to a carrier plate for preparing a packaging substrate, comprising a dielectric layer, a seed layer within the dielectric layer, and a copper pillar layer on the seed layer, wherein the bottom end of the seed layer is higher than the lower surface of the dielectric layer, the top end of the copper pillar layer is lower than the upper surface of the dielectric layer, and a first metal layer and a second metal layer are respectively disposed on the upper and lower surfaces of the dielectric layer.

[0006] In some embodiments, the dielectric layer includes a first dielectric layer and a second dielectric layer arranged longitudinally, the upper surface of the first dielectric layer and the lower surface of the second dielectric layer are attached together, a seed layer and a copper pillar layer are disposed in the second dielectric layer, the lower surface of the seed layer is flush with the lower surface of the second dielectric layer, the top of the copper pillar layer is lower than the upper surface of the second dielectric layer, a first metal layer is disposed on the lower surface of the first dielectric layer, and a second metal layer is disposed on the upper surface of the second dielectric layer.

[0007] In some embodiments, a first via is provided in the first dielectric layer to expose the seed layer, the first via penetrating the first metal layer, and a second via is provided in the second dielectric layer to expose the top of the copper pillar layer, the second via penetrating the second metal layer.

[0008] In some implementations, the first metal layer and the second metal layer have the same or similar thickness.

[0009] A second aspect of the present invention provides a packaging substrate structure, including a first dielectric layer and a second dielectric layer arranged longitudinally, wherein the upper surface of the first dielectric layer and the lower surface of the second dielectric layer are bonded together, wherein a seed layer, a copper pillar layer on the seed layer and a second conductive pillar layer on the copper pillar layer are disposed within the second dielectric layer, the seed layer is flush with the lower surface of the second dielectric layer, a first conductive pillar layer is disposed within the first dielectric layer and communicates with the seed layer, a first circuit layer is disposed on the lower surface of the first dielectric layer, and a second circuit layer is disposed on the upper surface of the second dielectric layer, wherein the first circuit layer and the second circuit layer are electrically connected through the first conductive pillar layer, the copper pillar layer and the second conductive pillar layer.

[0010] In some implementations, the first dielectric layer and the second dielectric layer may be the same or different.

[0011] In some embodiments, the copper pillar layer includes at least one copper pillar.

[0012] In some embodiments, the system further includes a third dielectric layer on the first circuit layer and a fourth dielectric layer on the second circuit layer. The third dielectric layer contains a third conductive post layer, and a third circuit layer is disposed on the lower surface of the third dielectric layer. The first circuit layer and the third circuit layer are electrically connected through the third conductive post layer. The fourth dielectric layer contains a fourth conductive post layer, and a fourth circuit layer is disposed on the upper surface of the fourth dielectric layer. The second circuit layer and the fourth circuit layer are electrically connected through the fourth conductive post layer.

[0013] In some implementations, the post layer includes at least one post.

[0014] In some embodiments, a first solder mask layer outside the third circuit layer and a second solder mask layer outside the fourth circuit layer are also included, wherein a first solder mask opening and a second solder mask opening are respectively provided in the first solder mask layer and the second solder mask layer.

[0015] A third aspect of the present invention provides a method for manufacturing a packaging substrate structure, comprising the following steps:

[0016] (a) Prepare a first dielectric layer and form a first metal layer on the upper and lower surfaces of the first dielectric layer, respectively;

[0017] (b) A copper pillar layer is prepared on the first metal layer on the upper surface of the first dielectric layer, and the exposed first metal layer on the upper surface of the first dielectric layer is etched to form a seed layer;

[0018] (c) A second dielectric layer is formed on the copper pillar layer, the lower surface of the second dielectric layer is attached to the upper surface of the first dielectric layer, and the top of the copper pillar layer is lower than the upper surface of the second dielectric layer;

[0019] (d) Forming a second metal layer on the upper surface of the second dielectric layer;

[0020] (e) A first via is formed in the first dielectric layer to expose the seed layer and the first via penetrates the first metal layer; a second via is formed in the second dielectric layer to expose the top end of the copper pillar layer and the second via penetrates the second metal layer; the seed layer forms the bottom end of the copper pillar layer; the second via and the first via expose the top end and the bottom end of the copper pillar layer, respectively.

[0021] In some implementation schemes, it also includes:

[0022] (f) After step (e), the first via is electroplated to form a first conductive pillar layer, and the second via is electroplated to form a second conductive pillar layer. The first metal layer and the second metal layer on the lower surface of the first dielectric layer are electrically connected through the first conductive pillar layer, the copper pillar layer and the second conductive pillar layer.

[0023] In some implementation schemes, it also includes:

[0024] (g) After step (f), the first metal layer is processed to form a first circuit layer, and the second metal layer is processed to form a second circuit layer. The first circuit layer and the second circuit layer are connected through the first conductive pillar layer, the copper pillar layer and the second conductive pillar layer.

[0025] In some implementation schemes, it also includes:

[0026] (h) After step (g), a third dielectric layer is formed on the first line layer and a fourth dielectric layer is formed on the second line layer;

[0027] (i) A third metal layer is formed on the third dielectric layer, and a fourth metal layer is formed on the fourth dielectric layer;

[0028] (j) A third conductive pillar layer is formed in the third dielectric layer, and a fourth conductive pillar layer is formed in the fourth dielectric layer. The first circuit layer and the third metal layer are connected through the third conductive pillar layer, and the second circuit layer and the fourth metal layer are connected through the fourth conductive pillar layer.

[0029] (k) Process the third metal layer to form a third circuit layer, process the fourth metal layer to form a fourth circuit layer, the first circuit layer and the third circuit layer are connected through the third conductive post layer, and the second circuit layer and the fourth circuit layer are connected through the fourth conductive post layer;

[0030] (l) A first solder resist layer is formed outside the third circuit layer, a second solder resist layer is formed outside the fourth circuit layer, and a first solder resist window and a second solder resist window are formed in the first solder resist layer and the second solder resist layer, respectively.

[0031] As can be seen from the above, the carrier plate, packaging substrate structure, and manufacturing method for the packaging substrate provided by the present invention pre-fabricate a copper pillar layer within the dielectric layer, and prepare upper and lower conductive pillars respectively connected to the copper pillar layer. This shortens the longitudinal height of the conductive pillars, reduces the aspect ratio of the conductive pillar apertures, and improves the quality of the conductive pillars obtained after through-hole electroplating. As a result, the prepared conductive pillars and copper pillars have good electrical performance and superior reliability. Furthermore, the manufacturing method of this packaging substrate structure can be applied to thick core boards, reducing the warpage defect rate of the substrate. The vias in contact with the circuit can be made smaller, meeting the requirements of fine circuit design in the core layer and improving yield. Attached Figure Description

[0032] To better understand the present invention and to illustrate embodiments thereof, reference is made below purely by way of example to the accompanying drawings.

[0033] When referring specifically to the accompanying drawings, it must be emphasized that the particular illustrations are exemplary and intended only to illustrately discuss preferred embodiments of the invention, and are presented for the purpose of providing illustrations that are considered most useful and readily understood for describing the principles and concepts of the invention. In this regard, no attempt is made to illustrate the structural details of the invention to a degree beyond what is necessary for a basic understanding of the invention; the description with reference to the drawings enables those skilled in the art to recognize how various forms of the invention can be practically embodied. In the drawings:

[0034] Figure 1 This is a schematic diagram of the structure of a mechanical drill in the prior art;

[0035] Figure 2 This is a cross-sectional schematic diagram of a carrier plate 100 for preparing a packaging substrate according to an embodiment of the present invention;

[0036] Figure 3 This is a cross-sectional schematic diagram of a packaging substrate structure 200 according to an embodiment of the present invention;

[0037] Figures 4(a) to 4(j) This diagram shows a cross-sectional view of the intermediate structures of each step in the manufacturing method of a packaging substrate structure 200 according to an embodiment of the present invention. Detailed Implementation

[0038] With the development and advancement of electronic technology, electronic products are evolving towards smaller, thinner, and lighter designs. This has driven the packaging structures of electronic products towards high integration and miniaturization, resulting in increasingly integrated, miniaturized, and multifunctional electronic components and circuit board substrates. This further leads to an increase in the number of layers on the substrate, which serves as the carrier of components, and smaller linewidths, line spacings, and vias / pillars. Simultaneously, the transmission of high-frequency signals and the requirements for signal integrity place increasingly higher demands on interlayer conductivity. The use of solid copper pillars between layers offers excellent electrical performance and superior reliability.

[0039] Existing technology for fabricating solid copper pillars in the core layer involves blind drilling with a mechanical drill followed by hole filling and electroplating. The mechanical drilling structure is as follows: Figure 1 As shown, due to the drill bit's sharp angle, a stub will form at the bottom of the blind hole after blind drilling, affecting the fabrication of the copper pillar and causing poor conductivity between layers. Furthermore, the length of the stub is the length of the working part of the mechanical drill minus the length of the cutting part. In addition, because the aspect ratio of the mechanical blind hole is large, the quality of the copper pillar obtained after filling and electroplating will be substandard.

[0040] To address this problem, the present invention provides a carrier plate for fabricating a packaging substrate, comprising a dielectric layer, a seed layer within the dielectric layer, and a copper pillar layer on the seed layer. The bottom end of the seed layer is higher than the lower surface of the dielectric layer, and the top end of the copper pillar layer is lower than the upper surface of the dielectric layer. A first metal layer is disposed on the lower surface of the dielectric layer, and a second metal layer is disposed on the upper surface of the dielectric layer.

[0041] This invention shortens the longitudinal height of the conductive pillars and reduces the aspect ratio of the conductive pillars by pre-fabricating a copper pillar layer within the dielectric layer and preparing upper and lower conductive pillars that are respectively connected to the copper pillar layer. This improves the quality of the conductive pillars obtained after through-hole electroplating, resulting in conductive pillars and copper pillars with good electrical properties and superior reliability.

[0042] Reference Figure 2 The diagram shows a cross-sectional schematic of a carrier plate 100 used to fabricate a packaging substrate. The carrier plate 100 includes a first dielectric layer 101 and a second dielectric layer 102 arranged longitudinally, which together constitute the dielectric layer of the carrier plate 100.

[0043] The upper surface of the first dielectric layer 101 is attached to the lower surface of the second dielectric layer 102. A seed layer 1021 is disposed in the second dielectric layer 102, and a copper pillar layer 1022 is disposed on the seed layer 1021. The lower surface of the seed layer 1021 is flush with the lower surface of the second dielectric layer 102, and the top of the copper pillar layer 1022 is lower than the upper surface of the second dielectric layer 102. A first metal layer 1011 is disposed on the lower surface of the first dielectric layer 101, and a second metal layer 1023 is disposed on the upper surface of the second dielectric layer 102.

[0044] Typically, the copper pillar layer 1022 may include multiple copper pillars, whose cross-sectional dimensions may be the same or different. Preferably, the copper pillar layer 1022 has uniform dimensions from top to bottom, which is more advantageous for heat dissipation and signal transmission stability in the embedded packaging structure.

[0045] Typically, a first via 1012 exposing the seed layer 1021 may be provided in the first dielectric layer 101, and the first via 1012 penetrates the first metal layer 1011. A second via 1024 exposing the top of the copper pillar layer 1022 may be provided in the second dielectric layer 102, and the second via 1024 penetrates the second metal layer 1023.

[0046] Optionally, the thicknesses of the first metal layer 1011 and the second metal layer 1023 can be the same or similar.

[0047] Reference Figure 3 The diagram shows a cross-sectional view of the packaging substrate structure 200. The packaging substrate structure 200 includes a first dielectric layer 101 and a second dielectric layer 102 arranged longitudinally, with the upper surface of the first dielectric layer 101 and the lower surface of the second dielectric layer 102 bonded together.

[0048] A seed layer 1021 is provided in the second dielectric layer 102, a copper pillar layer 1022 is provided on the seed layer 1021, and a second conductive pillar layer 1025 is provided on the copper pillar layer 1022. The seed layer 1021 is flush with the lower surface of the second dielectric layer 102.

[0049] A first conductive post layer 1013 is disposed within the first dielectric layer 101, and the first conductive post layer 1013 is connected to the seed layer 1021. A first circuit layer 1014 is disposed on the lower surface of the first dielectric layer 101, and a second circuit layer 1026 is disposed on the upper surface of the second dielectric layer 102. The first circuit layer 1014 and the second circuit layer 1026 are electrically connected through the first conductive post layer 1013, the copper post layer 1022, and the second conductive post layer 1025. The first conductive post layer 1013, the copper post layer 1022, and the second conductive post layer 1025 cooperate to electrically connect the first circuit layer 1014 and the second circuit layer 1026, replacing the traditional method of using a single conductive post to connect the circuit layers. This effectively shortens the vertical height of the conductive post, reduces the aspect ratio of the conductive post aperture, and improves the quality of the conductive post.

[0050] Optionally, the first dielectric layer 101 and the second dielectric layer 102 may be the same or different.

[0051] Typically, the copper pillar layer 1022 includes at least one copper pillar; preferably, the copper pillar layer 1022 includes multiple copper pillars, whose cross-sectional dimensions may be the same or different. The copper pillar layer 1022 has uniform dimensions from top to bottom, which is more advantageous for heat dissipation and signal transmission stability in embedded packaging structures.

[0052] Reference Figure 3 The packaging substrate structure 200 also includes a third dielectric layer 103 on the first circuit layer 1014. A third conductive pillar layer 1031 is disposed in the third dielectric layer 103, and a third circuit layer 1032 is disposed on the lower surface of the third dielectric layer. The first circuit layer 1014 and the third circuit layer 1032 are connected through the third conductive pillar layer 1031.

[0053] A fourth dielectric layer 104 is also provided on the second circuit layer 1026. A fourth conductive post layer 1041 is provided inside the fourth dielectric layer 104. A fourth circuit layer 1042 is provided on the upper surface of the fourth dielectric layer 104. The second circuit layer 1026 and the fourth circuit layer 1042 are connected through the fourth conductive post layer 1041.

[0054] Typically, a conductive pillar layer may include at least one conductive pillar, and preferably, a conductive pillar layer may include multiple conductive copper pillars, whose cross-sectional dimensions may be the same or different.

[0055] Reference Figure 3 The packaging substrate structure 200 also includes a first solder resist layer 105 outside the third circuit layer 1032, and a first solder resist opening 1051 is provided in the first solder resist layer 105. A second solder resist layer 106 is provided outside the fourth circuit layer 1042, and a second solder resist opening 1061 is provided in the second solder resist layer 106.

[0056] Reference Figures 4(a) to 4(j) The diagram shows a cross-sectional schematic of the intermediate structure of each step in a method for manufacturing a packaging substrate structure according to an embodiment of the present invention.

[0057] The manufacturing method includes the following steps: preparing a first dielectric layer 101, and forming a first metal layer 1011 on the upper and lower surfaces of the first dielectric layer 101 respectively—step (a), as shown in Figure 4(a).

[0058] Typically, a dielectric layer can be formed by laminating a dielectric material. The dielectric layer can be selected from PP, ABF, or PID, with PP being preferred. The first metal layer 1011 can be formed by applying copper foil to the upper and lower surfaces of the first dielectric layer 101, respectively. The specific method is not limited, but the first metal layer 1011 preferably includes copper.

[0059] Next, a first photoresist layer is applied to the first metal layer 1011 on the upper surface of the first dielectric layer 101, and the first feature pattern is formed by exposure and development. Copper is plated in the first feature pattern to form a copper pillar layer 1022. The first photoresist layer is removed, and the exposed first metal layer 1011 on the upper surface of the first dielectric layer 101 is etched to form a seed layer 1021. The seed layer 1021 corresponds to the bottom end of the copper pillar layer 1022—step (b), as shown in Figure 4(b).

[0060] Then, a second dielectric layer 102 is formed on the copper pillar layer 1022. The lower surface of the second dielectric layer 102 is attached to the upper surface of the first dielectric layer 101. The top of the copper pillar layer 1022 is lower than the upper surface of the second dielectric layer 102. A second metal layer 1023 is formed on the upper surface of the second dielectric layer 102—step (c), as shown in FIG4(c).

[0061] The top of the copper pillar layer 1022 is much lower than the upper surface of the second dielectric layer 102, which can reduce the damage to the copper pillar caused by the lamination of the dielectric layer.

[0062] Typically, the second metal layer 1023 can be formed by applying copper foil, but the specific method is not limited.

[0063] Next, a first via 1012 is formed in the first dielectric layer 101 to expose the seed layer 1021. The first via 1012 penetrates the first metal layer 1011. A second via 1024 is formed in the second dielectric layer 102 to expose the top end of the copper pillar layer 1022. The second via 1024 penetrates the second metal layer 1023. The second via 1024 and the first via 1012 expose the top and bottom ends of the copper pillar layer 1022, respectively—step (d), as shown in Figure 4(d).

[0064] Typically, through holes can be formed by laser drilling.

[0065] Then, the first through hole 1012 is electroplated to form the first through pillar layer 1013, and the second through hole 1024 is electroplated to form the second through pillar layer 1025. The first metal layer 1011 and the second metal layer 1023 on the lower surface of the first dielectric layer 101 are connected through the first through pillar layer 1013, the copper pillar layer 1022 and the second through pillar layer 1025—step (e), as shown in Figure 4(e).

[0066] Next, a second photoresist layer and a third photoresist layer are applied to the first metal layer 1011 and the second metal layer 1023, respectively. They are then exposed and developed to form a second feature pattern and a third feature pattern. The exposed first metal layer 1011 and the second metal layer 1023 are etched into the second feature pattern and the third feature pattern, respectively, to form a first circuit layer 1014 and a second circuit layer 1026. The second photoresist layer and the third photoresist layer are then removed—step (f), as shown in FIG4(f).

[0067] Then, a third dielectric layer 103 is formed on the first circuit layer 1014, a fourth dielectric layer 104 is formed on the second circuit layer 1026, a third metal layer 1033 is formed on the third dielectric layer 103, and a fourth metal layer 1043 is formed on the fourth dielectric layer 104—step (g), as shown in FIG4(g).

[0068] Next, a third via 1034 is formed in the third dielectric layer 103 to expose the first circuit layer 1014, and the third via 1034 penetrates the third metal layer 1033. A fourth via 1044 is formed in the fourth circuit layer 104 to expose the second circuit layer 1026, and the fourth via 1044 penetrates the fourth metal layer 1043. The third via 1034 and the fourth via 1044 are electroplated to form a third conductive pillar layer 1031 and a fourth conductive pillar layer 1041, respectively. The first circuit layer 1014 and the third metal layer 1033 are connected through the third conductive pillar layer 1031, and the second circuit layer 1026 and the fourth metal layer 1043 are connected through the fourth conductive pillar layer 1041—step (h), as shown in Figure 4(h).

[0069] Then, a fourth photoresist layer and a fifth photoresist layer are applied to the third metal layer 1033 and the fourth metal layer 1043, respectively. The fourth feature pattern and the fifth feature pattern are formed by exposure and development. The exposed third metal layer 1033 and the fourth metal layer 1043 are etched in the fourth feature pattern and the fifth feature pattern, respectively, to form the third circuit layer 1032 and the fourth circuit layer 1042. The fourth photoresist layer and the fifth photoresist layer are removed. The first circuit layer 1014 and the third circuit layer 1032 are connected by the third conductive pillar layer 1031. The second circuit layer 1026 and the fourth circuit layer 1042 are connected by the fourth conductive pillar layer 1041. Step (i) is shown in Figure 4(i).

[0070] Finally, a first solder resist layer 105 is formed outside the third circuit layer 1032, and a second solder resist layer 106 is formed outside the fourth circuit layer 1042. A first solder resist window 1051 and a second solder resist window 1061 are formed in the first solder resist layer 105 and the second solder resist layer 106, respectively, to form the packaging substrate structure 200 - step (j), as shown in Figure 4(j).

[0071] Those skilled in the art will recognize that the present invention is not limited to the specific illustrations and descriptions in the context. Furthermore, the scope of the invention is defined by the appended claims, including combinations and sub-combinations of the various technical features described above, as well as variations and modifications thereof, which will be foreseen by those skilled in the art upon reading the foregoing description.

[0072] In the claims, the term "comprising" and its variations, such as "including" or "containing," means that the listed components are included, but generally do not exclude other components.

Claims

1. A carrier board for preparing an encapsulation substrate, comprising a dielectric layer, a seed layer within the dielectric layer, and a copper pillar layer on the seed layer, wherein the bottom end of the seed layer is higher than the lower surface of the dielectric layer, the top end of the copper pillar layer is lower than the upper surface of the dielectric layer, and a first metal layer and a second metal layer are respectively disposed on the upper and lower surfaces of the dielectric layer. The dielectric layer includes a first dielectric layer and a second dielectric layer arranged longitudinally. The upper surface of the first dielectric layer and the lower surface of the second dielectric layer are attached together. A seed layer and a copper pillar layer on the seed layer are disposed in the second dielectric layer. The lower surface of the seed layer is flush with the lower surface of the second dielectric layer. The top of the copper pillar layer is lower than the upper surface of the second dielectric layer. A first metal layer is disposed on the lower surface of the first dielectric layer and a second metal layer is disposed on the upper surface of the second dielectric layer. The first dielectric layer has a first through-hole that exposes the seed layer and penetrates the first metal layer. The second dielectric layer has a second through-hole that exposes the top of the copper pillar layer and penetrates the second metal layer.

2. The carrier plate for preparing a packaging substrate according to claim 1, wherein the first metal layer and the second metal layer have the same or similar thickness.

3. A packaging substrate structure, comprising a first dielectric layer and a second dielectric layer arranged longitudinally, wherein the upper surface of the first dielectric layer and the lower surface of the second dielectric layer are bonded together, wherein a seed layer, a copper pillar layer on the seed layer and a second conductive pillar layer on the copper pillar layer are disposed within the second dielectric layer, the seed layer is flush with the lower surface of the second dielectric layer, a first conductive pillar layer is disposed within the first dielectric layer and communicates with the seed layer, a first circuit layer is disposed on the lower surface of the first dielectric layer, and a second circuit layer is disposed on the upper surface of the second dielectric layer, wherein the first circuit layer and the second circuit layer are electrically connected through the first conductive pillar layer, the copper pillar layer and the second conductive pillar layer; A third dielectric layer is disposed on the first circuit layer and a fourth dielectric layer is disposed on the second circuit layer. A third conductive post layer is disposed within the third dielectric layer, and a third circuit layer is disposed on the lower surface of the third dielectric layer. The first circuit layer and the third circuit layer are electrically connected through the third conductive post layer. A fourth conductive post layer is disposed within the fourth dielectric layer, and a fourth circuit layer is disposed on the upper surface of the fourth dielectric layer. The second circuit layer and the fourth circuit layer are electrically connected through the fourth conductive post layer.

4. The packaging substrate structure according to claim 3, wherein the first dielectric layer and the second dielectric layer are the same or different.

5. The packaging substrate structure according to claim 3, wherein the copper pillar layer comprises at least one copper pillar.

6. The packaging substrate structure according to claim 3, wherein the through-pillar layer includes at least one through-pillar.

7. The packaging substrate structure according to claim 3 further includes a first solder resist layer outside the third circuit layer and a second solder resist layer outside the fourth circuit layer, wherein a first solder resist window and a second solder resist window are respectively provided in the first solder resist layer and the second solder resist layer.

8. A method for fabricating a packaging substrate structure, comprising the following steps: (a) Prepare a first dielectric layer and form a first metal layer on the upper and lower surfaces of the first dielectric layer, respectively; (b) A copper pillar layer is prepared on the first metal layer on the upper surface of the first dielectric layer, and the exposed first metal layer on the upper surface of the first dielectric layer is etched to form a seed layer; (c) A second dielectric layer is formed on the copper pillar layer, the lower surface of the second dielectric layer is attached to the upper surface of the first dielectric layer, and the top of the copper pillar layer is lower than the upper surface of the second dielectric layer; (d) A second metal layer is formed on the upper surface of the second dielectric layer; (e) A first via is formed in the first dielectric layer to expose the seed layer and the first via penetrates the first metal layer; a second via is formed in the second dielectric layer to expose the top end of the copper pillar layer and the second via penetrates the second metal layer; the seed layer forms the bottom end of the copper pillar layer; the second via and the first via expose the top end and the bottom end of the copper pillar layer, respectively.

9. The manufacturing method according to claim 8 further includes: (f) After step (e), the first via is electroplated to form a first conductive pillar layer, and the second via is electroplated to form a second conductive pillar layer. The first metal layer and the second metal layer on the lower surface of the first dielectric layer are electrically connected through the first conductive pillar layer, the copper pillar layer and the second conductive pillar layer.

10. The manufacturing method according to claim 9, further comprising: (g) After step (f), the first metal layer is processed to form a first circuit layer, and the second metal layer is processed to form a second circuit layer. The first circuit layer and the second circuit layer are connected through the first conductive post layer, the copper post layer and the second conductive post layer.

11. The manufacturing method according to claim 10, further comprising: (h) After step (g), a third dielectric layer is formed on the first circuit layer and a fourth dielectric layer is formed on the second circuit layer; (i) A third metal layer is formed on the third dielectric layer, and a fourth metal layer is formed on the fourth dielectric layer; (j) A third conductive pillar layer is formed in the third dielectric layer, and a fourth conductive pillar layer is formed in the fourth dielectric layer. The first circuit layer and the third metal layer are connected through the third conductive pillar layer, and the second circuit layer and the fourth metal layer are connected through the fourth conductive pillar layer. (k) Process the third metal layer to form a third circuit layer, process the fourth metal layer to form a fourth circuit layer, the first circuit layer and the third circuit layer are connected through the third conductive post layer, and the second circuit layer and the fourth circuit layer are connected through the fourth conductive post layer; (l) A first solder resist layer is formed outside the third circuit layer, a second solder resist layer is formed outside the fourth circuit layer, and a first solder resist window and a second solder resist window are formed in the first solder resist layer and the second solder resist layer, respectively.

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