Semiconductor memory device and method of manufacturing semiconductor memory device

Abstract

This application relates to a semiconductor memory device and a method of manufacturing a semiconductor memory device. A semiconductor memory device includes: a first conductive pattern; and a second conductive pattern configured to overlap a first line assembly of the first conductive pattern and expose a first pad assembly of the first conductive pattern. The semiconductor memory device also includes an interlayer insulating layer between the first and second conductive patterns. The semiconductor memory device further includes first conductive contacts and first insulating pillars extending in opposite directions from the first pad assembly of the first conductive pattern.

Description

Technical Field

[0001] Various embodiments of this disclosure may relate to semiconductor memory devices and methods of manufacturing such semiconductor memory devices, and more specifically, to a three-dimensional semiconductor memory device and a method of manufacturing such a three-dimensional semiconductor memory device. Background Technology

[0002] A semiconductor memory device includes a memory cell array and peripheral circuitry connected to the memory cell array. The memory cell array includes multiple memory cells capable of storing data. The peripheral circuitry can supply various operating voltages to the memory cells and control various operations of the memory cells.

[0003] To increase the integration density of semiconductor memory devices, three-dimensional semiconductor memory devices have been proposed. The memory cells of a three-dimensional semiconductor memory device can be arranged in a three-dimensional manner. Therefore, three-dimensional semiconductor memory devices can reduce the two-dimensional area occupied by the memory cells. Summary of the Invention

[0004] Embodiments of this disclosure may provide a semiconductor memory device comprising: a first conductive pattern including a first line assembly and a first pad assembly extending from the first line assembly; a second conductive pattern overlapping the first line assembly of the first conductive pattern and exposing the first pad assembly of the first conductive pattern, the second conductive pattern being spaced apart from the first conductive pattern in a first direction; an interlayer insulating layer between the first conductive pattern and the second conductive pattern; a first conductive contact extending from the first pad assembly of the first conductive pattern in a first direction; and a first insulating post overlapping the first conductive contact and extending from the first pad assembly in a direction opposite to the first direction.

[0005] Embodiments of this disclosure may provide a semiconductor memory device comprising: a first insulating layer including a cell array region and a contact region; a plurality of insulating pillars extending through the first insulating layer in the contact region and extending to different lengths in a first direction; a plurality of conductive patterns, each including pad assemblies surrounding the ends of the insulating pillars at different heights above the first insulating layer; and a plurality of conductive contacts overlapping the insulating pillars and contacting the pad assemblies.

[0006] Embodiments of this disclosure may provide a method for manufacturing a semiconductor memory device, the method comprising the steps of: forming an insulating layer; forming a plurality of insulating pillars having different lengths in a first direction intersecting the surface of the insulating layer; forming a plurality of conductive patterns overlapping the insulating layer and surrounding the ends of the insulating pillars at different heights; and forming a plurality of conductive contacts overlapping the insulating pillars and connected to the conductive patterns.

[0007] Embodiments of this disclosure provide a method for manufacturing a semiconductor memory device, the method comprising the steps of: forming a laminate comprising a plurality of first material layers and a plurality of second material layers alternately stacked in a first direction; forming a plurality of preliminary insulating pillars through the laminate; etching the preliminary insulating pillars to form a plurality of insulating pillars having different lengths in the first direction; etching the first material layers and the second material layers to form a stepped structure having a step formed by the upper surface of the first material layer; forming a pad pattern on the upper surface of the first material layer; forming an upper insulating layer covering the pad pattern and the stepped structure; and forming a plurality of conductive contacts through the upper insulating layer and overlapping the insulating pillars. Attached Figure Description

[0008] Figure 1 This is a block diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0009] Figure 2A and Figure 2B This is a schematic diagram illustrating the arrangement of the peripheral circuit structure, memory cell array, multiple bit lines, and source layer according to an embodiment of the present disclosure.

[0010] Figure 3 This is a circuit diagram illustrating the memory cell array and block selection circuit structure according to an embodiment of the present disclosure.

[0011] Figure 4 This is a perspective view showing a portion of a semiconductor memory device according to an embodiment of the present disclosure.

[0012] Figure 5 This is a perspective view showing a portion of a semiconductor memory device according to an embodiment of the present disclosure.

[0013] Figure 6A and Figure 6B yes Figure 5 The diagram shows a cross-sectional view of a semiconductor memory device.

[0014] Figure 7 yes Figure 5 The diagram shows a plan view of a semiconductor memory device.

[0015] Figure 8 This is a cross-sectional view showing the contact area of ​​a semiconductor memory device according to an embodiment of the present disclosure.

[0016] Figure 9A and Figure 9B This is a cross-sectional view showing a semiconductor memory device according to an embodiment of the present disclosure.

[0017] Figure 10A and Figure 10BThis is a diagram illustrating an example of a process for forming a laminate and a preliminary insulating pillar according to the present disclosure.

[0018] Figure 11A and Figure 11B This is a diagram illustrating an example of the process for forming insulating pillars and stepped structures according to this disclosure.

[0019] Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 15A and Figure 15B This is a diagram illustrating an example of a process for forming pad patterns according to this disclosure.

[0020] Figure 16A and Figure 16B This is a diagram illustrating an example of a process for forming a slit according to the present disclosure.

[0021] Figure 17A , Figure 17B , Figure 18A and Figure 18B This is a diagram illustrating an example of a process for forming conductive patterns according to the present disclosure.

[0022] Figure 19 This is a perspective view illustrating an example of a process for forming a sidewall insulating layer and conductive electrode contacts according to the present disclosure.

[0023] Figure 20 This is a perspective view illustrating an example of a process for forming conductive contacts according to the present disclosure.

[0024] Figure 21 This is a block diagram illustrating the configuration of a memory system according to an embodiment of the present disclosure.

[0025] Figure 22 This is a block diagram illustrating the configuration of a computing system according to an embodiment of the present disclosure. Detailed Implementation

[0026] The specific structural and functional descriptions disclosed herein are merely illustrative in order to describe implementations based on the concepts of this disclosure. Implementations based on the concepts of this disclosure may be carried out in various forms and should not be construed as limited to the specific implementations set forth herein.

[0027] It will be understood that although the terms “first,” “second,” etc., may be used in this document to describe various elements, these elements are not limited by these terms. These terms are used to distinguish one element from another, not to imply the number or order of elements.

[0028] Various embodiments of this disclosure relate to a semiconductor memory device and a method for manufacturing the semiconductor memory device, wherein the method and apparatus can improve the stability of the manufacturing process and increase operational reliability.

[0029] Figure 1 This is a block diagram illustrating a semiconductor memory device 50 according to an embodiment of the present disclosure.

[0030] Reference Figure 1 The semiconductor memory device 50 may include a peripheral circuit structure 40 and a memory cell array 10.

[0031] The peripheral circuit structure 40 can be configured to perform programming operations for storing data in the memory cell array 10, reading operations for outputting data stored in the memory cell array 10, or erasing operations for erasing data stored in the memory cell array 10. In an embodiment, the peripheral circuit structure 40 may include an input / output circuit 21, a control circuit 23, a voltage generation circuit 31, a row decoder 33, a column decoder 35, a page buffer 37, and a source line driver 39.

[0032] The memory cell array 10 may include multiple memory cells for storing data. The memory cells may be arranged in a three-dimensional manner. The memory cell array 10 may be connected to a drain select line DSL, multiple word lines WL, a source select line SSL, multiple bit lines BL, and a common source line CSL.

[0033] Input / output circuit 21 can send commands CMD and addresses ADD received from an external device (e.g., a memory controller) of semiconductor memory device 50 to control circuit 23. Input / output circuit 21 can exchange data DATA with external devices and column decoder 35.

[0034] Control circuit 23 can output operation signal OP_S, row address RADD, source line control signal SL_S, page buffer control signal PB_S and column address CADD in response to command CMD and address ADD.

[0035] The voltage generating circuit 31 can generate various operating voltages Vop for programming, reading and erasing operations in response to the operation signal OP_S.

[0036] The line decoder 33 can transmit the operating voltage Vop to the drain select line DSL, word line WL, and source select line SSL in response to the line address RADD.

[0037] In response to the column address CADD, the column decoder 35 can send data DATA input from the input / output circuit 21 to the page buffer 37, or it can send data DATA stored in the page buffer 37 to the input / output circuit 21. The column decoder 35 can exchange data DATA with the input / output circuit 21 via the column line CL. The column decoder 35 can exchange data DATA with the page buffer 37 via the data line DL.

[0038] In response to the page buffer control signal PB_S, page buffer 37 can temporarily store data DATA received via bit line BL. Page buffer 37 can sense the voltage or current of bit line BL during read operations.

[0039] In response to the source line control signal SL_S, the source line driver 39 can control the voltage applied to the common source line CSL.

[0040] To increase the integration of the semiconductor memory device, the memory cell array 10 may overlap with the peripheral circuit structure 40.

[0041] Figure 2A and Figure 2B This is a schematic diagram illustrating the arrangement of the peripheral circuit structure 40, memory cell array 10, multiple bit lines BL, and source layer SL according to an embodiment of the present disclosure.

[0042] Reference Figure 2A and Figure 2B The peripheral circuit structure 40 can be disposed on a substrate extending in the XY plane. The memory cell array 10, the source layer SL, and the multiple bit lines BL can overlap with the peripheral circuit structure 40. The memory cell array 10 can be disposed between the source layer SL and the multiple bit lines BL.

[0043] The source layer SL and multiple bit lines BL can be connected to the memory cell array 10 via a channel structure. In this embodiment, the source layer SL can be connected via... Figure 1 The common source line CSL shown is connected to the peripheral circuit structure 40. In an embodiment, the source layer SL can be configured as follows: Figure 1 The common source line CSL is shown.

[0044] In the Z-axis direction, the source layer SL, multiple bit lines BL, and memory cell array 10 can be arranged in various ways.

[0045] Reference Figure 2A In this embodiment, the source layer SL can be disposed between the memory cell array 10 and the peripheral circuit structure 40. Multiple bit lines BL can overlap with the source layer SL, and the memory cell array 10 is interposed between them. In other words, the source layer SL and the memory cell array 10 can be disposed between the peripheral circuit structure 40 and the multiple bit lines BL.

[0046] Reference Figure 2B In this embodiment, multiple bit lines BL can be disposed between the memory cell array 10 and the peripheral circuit structure 40. The source layer SL can overlap with the multiple bit lines BL, and the memory cell array 10 is interposed between them. In other words, the multiple bit lines BL and the memory cell array 10 can be disposed between the peripheral circuit structure 40 and the source layer SL.

[0047] return Figure 2A and Figure 2B In one embodiment, processes for forming the source layer SL, multiple bit lines BL, and the memory cell array 10 can be performed on the peripheral circuit structure 40. In another embodiment, the process for forming the memory cell array 10 can be performed separately from the process for forming the peripheral circuit structure 40. Here, the memory cell array 10 and the peripheral circuit structure 40 can be interconnected by conductive bonding patterns.

[0048] Figure 3 This is a circuit diagram illustrating the memory cell array and block selection circuit structure according to an embodiment of the present disclosure.

[0049] Reference Figure 3 The memory cell array may include multiple memory cell strings CS. Each memory cell string CS may include at least one down-select transistor LST, multiple memory cells MC, and at least one up-select transistor UST.

[0050] Multiple memory cells MC can be connected in series between a lower-select transistor LST and an upper-select transistor UST. One of the lower-select transistor LST and the upper-select transistor UST can be used as a source-select transistor, while the other can be used as a drain-select transistor. Multiple memory cells MC can be connected to... Figure 2A and Figure 2B The source layer SL is shown. Multiple memory cells MC can be connected to the source layer via drain selection transistors. Figure 2A and Figure 2B The bit line BL is shown.

[0051] Multiple memory cells MC can be connected to word lines WL. The operation of the multiple memory cells MC can be controlled by a strobe signal applied to word lines WL. A lower select transistor LST can be connected to the lower select line LSL. The operation of the lower select transistor LST can be controlled by a strobe signal applied to the lower select line LSL. An upper select transistor UST can be connected to the upper select line USL. The operation of the upper select transistor UST can be controlled by a strobe signal applied to the upper select line USL. The lower select line LSL, the upper select line USL, and the word lines WL can be implemented by conductive patterns that are spaced apart from each other and stacked simultaneously.

[0052] The lower select line LSL, upper select line USL, and word line WL can be connected to the block select circuit structure BSC. The block select circuit structure BSC can be included in the reference... Figure 1 In the described line decoder 33, in an embodiment, the block select circuit structure BSC may include a pass transistor PT connected to the lower select line LSL, the upper select line USL, and the word line WL, respectively. The gate of the pass transistor PT may be connected to the block select line BSEL. The pass transistor PT may be configured to transmit the voltage applied to the global lines GLSL, GUSL, and GWL to the lower select line LSL, the upper select line USL, and the word line WL in response to a block select signal applied to the block select line BSEL.

[0053] The block select circuit structure (BSC) can be connected to the lower select line (LSL), the upper select line (USL), and the word line (WL) via a gate contact structure (GCT). The gate contact structure (GCT) may include conductive contacts that contact the lower select line (LSL), the upper select line (USL), and the word line (WL).

[0054] Figure 4 This is a perspective view showing a portion of a semiconductor memory device according to an embodiment of the present disclosure.

[0055] Reference Figure 4 The semiconductor memory device may include conductive patterns CP1 and CP2, an interlayer insulating layer IL, conductive contacts CT1 and CT2, and insulating pillars IP1 and IP2.

[0056] Conductive patterns CP1 and CP2 may be stacked while being spaced apart from each other along a first direction D1. Each of the conductive patterns CP1 and CP2 may extend parallel to a plane perpendicular to an axis facing the first direction D1. Hereinafter, the directions facing the axes that intersect each other in the plane are defined as the second direction D2 and the third direction D3.

[0057] Conductive patterns CP1 and CP2 may include the formation of Figure 3 The diagram shows a portion of the lower select line LSL, the upper select line USL, and the word line WL, along with a first conductive pattern CP1 and a second conductive pattern CP2. The second conductive pattern CP2 may be spaced apart from the first conductive pattern CP1 in a first direction D1.

[0058] The first conductive pattern CP1 may have a first line component L1 and a first pad component P1. The first pad component P1 may extend from the first line component L1 in a second direction D2. The first line component L1 and the first pad component P1 may extend parallel to each other. In one embodiment, the first line component L1 and the first pad component P1 may extend in a third direction D3. The first pad component P1 may form an end of the first conductive pattern CP1. In the first direction D1, the thickness of the first pad component P1 may be greater than the thickness of the first line component L1.

[0059] The second conductive pattern CP2 may overlap with the first line component L1 of the first conductive pattern CP1, but may not overlap with the first pad component P1 of the first conductive pattern CP1. Therefore, the first pad component P1 of the first conductive pattern CP1 can be exposed through the second conductive pattern CP2.

[0060] The second conductive pattern CP2 may have a second line component L2 and a second pad component P2. The second line component L2 may overlap with a portion of the first conductive pattern CP1. In one embodiment, the second line component L2 may overlap with a portion of the first line component L1. The second pad component P2 may extend from the second line component L2 and may overlap with an end of the first line component L1. The second pad component P2 may be adjacent to the first pad component P1 of the first conductive pattern CP1. The second pad component P2 may form an end of the second conductive pattern CP2. In the first direction D1, the thickness of the second pad component P2 may be greater than the thickness of the second line component L2.

[0061] An interlayer insulating layer IL may be disposed between a first conductive pattern CP1 and a second conductive pattern CP2. The first conductive pattern CP1 and the second conductive pattern CP2 may be insulated from each other by the interlayer insulating layer IL. A first pad assembly P1 of the first conductive pattern CP1 may extend along a portion of the sidewall of the interlayer insulating layer IL.

[0062] Conductive contacts CT1 and CT2 may include a first conductive contact CT1 and a second conductive contact CT2 respectively connected to a first conductive pattern CP1 and a second conductive pattern CP2. The first conductive contact CT1 may contact a first pad assembly P1 of the first conductive pattern CP1 and may extend from the first pad assembly P1 in a first direction D1. The second conductive contact CT2 may contact a second pad assembly P2 of the second conductive pattern CP2 and may extend from the second pad assembly P2 in the first direction D1. The first conductive contact CT1 and the second conductive contact CT2 may overlap with insulating posts IP1 and IP2 respectively.

[0063] Insulating posts IP1 and IP2 may include a first insulating post IP1 and a second insulating post IP2. The cross-sectional area of ​​each of the first insulating post IP1 and the second insulating post IP2 may be greater than the cross-sectional area of ​​each of the first conductive contact CT1 and the second conductive contact CT2.

[0064] The first insulating post IP1 may overlap with the first conductive contact CT1. The first insulating post IP1 and the first conductive contact CT1 may extend from the first pad assembly P1 of the first conductive pattern CP1 in opposite directions. The first insulating post IP1 may have a first end EP1 inserted into a recess DP of the first pad assembly P1. The first pad assembly P1 may have a bottom BT facing a direction opposite to the first direction D1. The recess DP of the first pad assembly P1 may be defined in the bottom BT of the first pad assembly P1. In the first direction D1, the thickness of the first pad assembly P1 may be greater than the depth of the recess DP.

[0065] The second insulating pillar IP2 may overlap with the second conductive contact CT2. The second insulating pillar IP2 and the second conductive contact CT2 may extend in opposite directions from the second pad assembly P2 of the second conductive pattern CP2. Similar to the first insulating pillar IP1, the second insulating pillar IP2 may have a second end EP2 inserted into a recess in the second pad assembly P2. The second insulating pillar IP2 may have a first penetrating component TP1 extending from the second end EP2 and a second penetrating component TP2 extending from the first penetrating component TP1. The first penetrating component TP1 may be defined as the portion of the second insulating pillar IP2 surrounded by the interlayer insulating layer IL, while the second penetrating component TP2 may be defined as the portion of the second insulating pillar IP2 surrounded by the first line assembly L1 of the first conductive pattern CP1. The second insulating pillar IP2 may protrude further than the first insulating pillar IP1 in a first direction D1.

[0066] According to the embodiments described above in this disclosure, insulating posts IP1 and IP2 can be used to prevent short circuits between conductive patterns CP1 and CP2 disposed at different heights via one of conductive contacts CT1 and CT2. More specifically, the second conductive contact CT2 can be coupled to the second conductive pattern CP2 and can extend to the height at which the first conductive pattern CP1 is disposed during the manufacturing process of the semiconductor memory device. The second insulating post IP2 can overlap with the second conductive contact CT2, thus preventing short circuits from the second conductive contact CT2 to the first conductive pattern CP1.

[0067] Figure 5 This is a perspective view showing a portion of a semiconductor memory device according to an embodiment of the present disclosure.

[0068] Reference Figure 5 The semiconductor memory device may include stacks 100A and 100B. Each of stacks 100A and 100B may include a cell array region AR1 and a contact region AR2. The contact region AR2 may extend from the cell array region AR1. Each of stacks 100A and 100B may form a stepped structure in the contact region AR2.

[0069] Each of the laminates 100A and 100B may include a first insulating layer 101, a conductive pattern 111, an interlayer insulating layer 121, and a second insulating layer 131. The second insulating layer 131 may be spaced apart from the first insulating layer 101 in a first direction D1. The conductive pattern 111 and the interlayer insulating layer 121 may be disposed between the first insulating layer 101 and the second insulating layer 131. Each of the first insulating layer 101, the conductive pattern 111, the interlayer insulating layer 121, and the second insulating layer 131 may extend parallel to a plane perpendicular to an axis facing the first direction D1. In an embodiment, each of the first insulating layer 101, the conductive pattern 111, the interlayer insulating layer 121, and the second insulating layer 131 may extend in a second direction D2 and a third direction D3.

[0070] Conductive pattern 111 may be disposed on the first insulating layer 101. Conductive pattern 111 may be spaced at different distances from the first insulating layer 101 in the first direction D1. Conductive pattern 111 may include a lower conductive pattern 111A, an upper conductive pattern 111B, and a plurality of intermediate conductive patterns 111C. Lower conductive pattern 111A may be defined as the conductive pattern 111 closest to the first insulating layer 101. Lower conductive pattern 111A may be in contact with the first insulating layer 101. Upper conductive pattern 111B may be defined as the conductive pattern furthest from the first insulating layer 101 in the first direction D1. Intermediate conductive patterns 111C may be disposed between the lower conductive pattern 111A and the upper conductive pattern 111B. One of the lower conductive pattern 111A and the upper conductive pattern 111B may be used as... Figure 3 The lower selection line LSL is shown, while another can be used as... Figure 3 The upper selection line USL is shown. The middle conductive pattern 111C can be used as... Figure 3 The character line WL is shown.

[0071] The conductive pattern 111 may overlap with the first insulating layer 101 in the cell array region AR1 and the contact region AR2. The conductive pattern 111 may form a stepped structure in the contact region AR2. In an embodiment, to provide a stepped structure, the conductive pattern 111 may have different lengths in the second direction D2 in the contact region AR2. More specifically, the length of the conductive pattern 111 in the second direction D2 in the contact region AR2 may increase as the conductive pattern 111 gets closer to the first insulating layer 101.

[0072] The conductive pattern 111 may include line assemblies 111L and pad assemblies 111P. Pad assemblies 111P may overlap with the first insulating layer 101 in the contact region AR2. Pad assemblies 111P may be disposed at different heights. Pad assemblies 111P may be configured not to overlap each other. Line assemblies 111L may extend from pad assemblies 111P toward the cell array region AR1 and may overlap with the first insulating layer 101 in the cell array region AR1. In the first direction D1, the thickness T2 of each pad assembly 111P may be greater than the thickness T1 of each line assembly 111L.

[0073] The pad assembly 111P of the upper conductive pattern 111B and the middle conductive pattern 111C can form the ends of the upper conductive pattern 111B and the middle conductive pattern 111C. The pad assembly 111P of the middle conductive pattern 111C may not be covered by the line assembly 111L and the interlayer insulating layer 121.

[0074] The pad assembly 111P of the lower conductive pattern 111A can be defined as the lower pad assembly 111LP, and the line assembly 111L of the lower conductive pattern 111A can be defined as the lower line assembly 111LL. The pad assembly 111P of the upper conductive pattern 111B can be defined as the upper pad assembly 111UP, and the line assembly 111L of the upper conductive pattern 111B can be defined as the upper line assembly 111UL.

[0075] The lower conductive pattern 111A may have a protrusion 111PR extending from the lower pad assembly 111LP in a direction opposite to that of the lower line assembly 111LL. In the first direction D1, the thickness T3 of the protrusion 111PR may be less than the thickness T2 of the lower pad assembly 111LP. In the first direction D1, the thickness T3 of the protrusion 111PR may be less than the thickness T1 of the lower line assembly 111LL. The protrusion 111PR may form the end of the lower conductive pattern 111A. Embodiments of this disclosure are not limited thereto. In embodiments, the protrusion 111PR may be omitted, allowing the lower pad assembly 111LP to form the end of the lower conductive pattern 111A.

[0076] The second insulating layer 131 may be disposed on the upper line assembly 111UL of the upper conductive pattern 111B. The upper pad assembly 111UP of the upper conductive pattern 111B may not be covered by the second insulating layer 131.

[0077] The semiconductor memory device may include a dummy conductive pattern 141 disposed on an edge 131EG of a second insulating layer 131. The dummy conductive pattern 141 may overlap with an upper line assembly 111UL, and the second insulating layer 131 is interposed between them. In the first direction D1, the thickness T4 of the dummy conductive pattern 141 may be less than the thickness T2 of each pad assembly 111P of the conductive pattern 111. In the first direction D1, the thickness T4 of the dummy conductive pattern 141 may be less than the thickness T1 of each line assembly 111L of the conductive pattern 111. Embodiments of this disclosure are not limited thereto. In embodiments, the dummy conductive pattern 141 may be omitted.

[0078] First insulating patterns 151 may be respectively disposed on pad assemblies 111P of conductive patterns 111. First insulating patterns 151A may be spaced apart from interlayer insulating layers 121 in the second direction D2. Each first insulating pattern 151A may protrude further than the adjacent pad assembly 111P in the second direction D2.

[0079] The second insulating pattern 151B may be disposed on the protrusion 111PR. The second insulating pattern 151B may be spaced apart from the lower pad assembly 111LP in the second direction D2. The second insulating pattern 151B may protrude further than the protrusion 111PR in the second direction D2.

[0080] The third insulating pattern 151C may be disposed on the dummy conductive pattern 141. The third insulating pattern 151C may protrude further than the dummy conductive pattern 141 in the second direction D2.

[0081] The first insulating pattern 151A, the second insulating pattern 151B, and the third insulating pattern 151C can be set at different heights and do not need to overlap with each other.

[0082] Each of the laminates 100A and 100B may be covered by an upper insulating layer 161. The upper insulating layer 161 may cover the stepped structure of each of the laminates 100A and 100B. The upper insulating layer 161 may cover a first insulating pattern 151A, a second insulating pattern 151B, and a third insulating pattern 151C. The upper insulating layer 161 may fill the space between the first insulating pattern 151A and the interlayer insulating layer 121. The upper insulating layer 161 may have a substantially flat surface.

[0083] A semiconductor memory device may include a channel structure 173 and a memory layer 171 surrounding the sidewalls of the channel structure 173. The channel structure 173 and the memory layer 171 may extend through each of the stacks 100A and 100B in the cell array region AR1. Although not shown in the figures, the memory layer 171 may include a tunnel insulating layer surrounding the sidewalls of the channel structure 173, a data storage layer surrounding the sidewalls of the tunnel insulating layer, and a barrier insulating layer surrounding the sidewalls of the data storage layer. The tunnel insulating layer, the data storage layer, and the barrier insulating layer may extend in a first direction D1. The data storage layer may include a material capable of storing data altered by Fowler-Nordheim tunneling. In one embodiment, the data storage layer may be formed of a nitride layer capable of trapping charge. The barrier insulating layer may include an oxide capable of blocking charge, and the tunnel insulating layer may include silicon oxide that enables charge tunneling.

[0084] The semiconductor memory device may include a conductive power electrode contact 183 disposed between laminates 100A and 100B. A sidewall insulating layer 181 may be disposed between each of laminates 100A and 100B and the conductive power electrode contact 183.

[0085] The semiconductor memory device may include conductive contacts 185. The conductive contacts 185 may pass through the upper insulating layer 161 overlapping each of the laminates 100A and 100B in the contact area AR2, and may overlap with the pad assembly 111P respectively.

[0086] Figure 6A and Figure 6B yes Figure 5 The diagram shows a cross-sectional view of a semiconductor memory device. Figure 6A It is along the semiconductor memory device Figure 5 A cross-sectional view taken from line I-I'. Figure 6B It is along the semiconductor memory device Figure 5 The cross-sectional view taken from line II-II'.

[0087] Reference Figure 6A and Figure 6B The semiconductor memory device may include an insulating post 135. The insulating post 135 may be located in... Figure 5 The first insulating layer 101 passes through the contact area AR2 shown, and can be accessed through the contact area AR2. Figure 5 The first direction D, as shown, extends to different lengths.

[0088] The ends 135EP of the insulating post 135 can be located at different heights above the first insulating layer 101. The ends 135EP of the insulating post 135 can be spaced apart from the line assemblies 111L of the conductive pattern 111. The ends 135EP of the insulating post 135 can be surrounded by the pad assemblies 111P of the conductive pattern 111.

[0089] Insulating posts 135 may be disposed in the region between the upper line assembly 111UL and the protrusion 111PR. Among the insulating posts 135, the remaining insulating posts, except those overlapping with the lower pad assembly 111LP, may pass through at least one of the interlayer insulation layer 121 and the lower line assembly 111LL. Among the insulating posts 135, the insulating posts overlapping with the upper pad assembly 111UP may pass through the line assembly 111L of the intermediate conductive pattern 111C. Among the insulating posts 135, the insulating posts overlapping with the pad assembly 111P of the intermediate conductive pattern 111C may pass through at least one of the line assembly 111L of the intermediate conductive pattern 111C and the lower line assembly 111LL.

[0090] Conductive contacts 185 may overlap with insulating posts 135. Conductive contacts 185 may be disposed in the region between dummy conductive pattern 141 and protrusion 111PR. Conductive contacts 185 may pass through upper insulating layer 161 and first insulating pattern 151A. Conductive contacts 185 may contact pad assembly 111P.

[0091] The pad assembly 111P can extend between the top surface TS of the insulating post 135 and the bottom surface BS of the conductive contact 185.

[0092] The first insulating pattern 151A may surround the conductive contacts 185 respectively and may extend parallel to the pad assembly 111P.

[0093] The memory layer 171 and the channel structure 173 can pass through the first insulating layer 101, the line assembly 111L of the conductive pattern 111, the interlayer insulating layer 121, the second insulating layer 131 and the upper insulating layer 161.

[0094] The channel structure 173 may include a semiconductor layer SE and a core insulating layer CO. The semiconductor layer SE may include a channel region CH and a doped region DA. The channel region CH may be disposed between the core insulating layer CO and the memory layer 171, and the doped region DA may overlap with the core insulating layer CO. The semiconductor layer SE may include a semiconductor material such as silicon. The doped region DA may include conductive impurities. In this embodiment, the doped region DA may include n-type impurities.

[0095] The conductive electrode contact 183 and the sidewall insulating layer 181 between the laminates 100A and 100B can extend along the sidewall of the upper insulating layer 161.

[0096] Figure 5 , Figure 6A and Figure 6B The structure shown can be applied to Figure 2A or Figure 2B The memory cell array 10 shown. Figure 5 , Figure 6A and Figure 6B The structure shown can be inverted for application. Figure 2A or Figure 2B The memory cell array 10 shown.

[0097] Figure 7 yes Figure 5 The diagram shows a plan view of a semiconductor memory device. Figure 7 It is along the semiconductor memory device Figure 6A The plan view intercepted by line III-III'.

[0098] Reference Figure 7 The conductive pattern 111 can be insulated from the conductive electrode contact 183 through the sidewall insulating layer 181. Figure 7 A plan view of the intermediate conductive pattern 111C is shown.

[0099] An intermediate conductive pattern 111C may surround some insulating posts 135. An insulating post 135P surrounded by the intermediate conductive pattern 111C and adjacent to the sidewall 111SW of the intermediate conductive pattern 111C may be surrounded by the pad assembly 111P of the intermediate conductive pattern 111C.

[0100] An insulating post 135A, which is disposed on one side of the cell array region AR1 relative to an insulating post 135P, can be surrounded by a line assembly 111L of an intermediate conductive pattern 111C. The line assembly 111L can extend to the cell array region AR1 and can surround the channel structure 173, and the memory layer 171 is inserted between the line assembly 111L and the channel structure 173.

[0101] An insulating post 135B, positioned relative to an insulating post 135P and facing in the opposite direction to the cell array region AR1, may be surrounded by at least one of the conductive patterns below the intermediate conductive pattern 111C.

[0102] The cross-sectional area of ​​each insulating post 135 can be larger than the cross-sectional area of ​​each conductive contact 185. Therefore, according to the embodiments of this disclosure, an overlap margin between the conductive contact 185 and the insulating post 135 can be ensured.

[0103] Figure 8 This is a cross-sectional view showing the contact region of a semiconductor memory device according to an embodiment of the present disclosure. Hereinafter, repeated descriptions of the same configuration will be omitted.

[0104] Reference Figure 8The semiconductor memory device may include a stack of conductive patterns 111 and interlayer insulating layers 121. The stack of conductive patterns 111 and interlayer insulating layers 121 may overlap with a first insulating layer 101 in a contact region AR2, and may be formed in a stepped structure in the contact region AR2. A second insulating layer 131 may be disposed on an upper conductive pattern 111B within the conductive patterns 111. The edge 131EG of the second insulating layer 131 may overlap with a dummy conductive pattern 141.

[0105] The first insulating pattern 151A may overlap with the pad assembly 111P of the conductive pattern 111. The second insulating pattern 151B may overlap with the protrusion 111PR of the lower conductive pattern 111A in the conductive pattern 111. The third insulating pattern 151C may overlap with the dummy conductive pattern 141.

[0106] The upper insulating layer 161 may cover the stack of the first insulating layer 101, the conductive pattern 111 and the interlayer insulating layer 121, the second insulating layer 131, the dummy conductive pattern 141, the first insulating pattern 151A, the second insulating pattern 151B and the third insulating pattern 151C.

[0107] The insulating post 135 may overlap with the pad assembly 111P of the conductive pattern 111. The insulating post 135 may have an end 135EP surrounded by the pad assembly 111P. The insulating post 135 may extend from the end 135EP to pass through the first insulating layer 101.

[0108] The semiconductor memory device may include conductive contacts 185' overlapping with insulating pillars 135. The conductive contacts 185' may pass through an upper insulating layer 161 and a first insulating pattern 151A, and further through pad assemblies 111P. In one embodiment, the conductive contacts 185' may extend into the insulating pillars 135. The conductive contacts 185' may have a bottom surface BS' that contacts the insulating pillars 135. According to an embodiment of this disclosure, the sidewalls 185SW of the conductive contacts 185' may contact the pad assemblies 111P.

[0109] Figure 9A and Figure 9B This is a cross-sectional view showing a semiconductor memory device according to an embodiment of the present disclosure. Figure 9A and Figure 9B This is a cross-sectional view of the cell array region of a semiconductor memory device. Figure 9A and Figure 9B Various embodiments of the source layer overlapping the first insulating layer are shown. Repeated descriptions of repetitive configurations will be omitted hereafter.

[0110] Reference Figure 9A and Figure 9BThe semiconductor memory device may include a source layer 201 or 250. A first insulating layer 101, a conductive pattern 111, an interlayer insulating layer 121, a second insulating layer 131, and an upper insulating layer 161 may overlap with the source layer 201 or 250. The semiconductor layer SE of the channel structure 173 may include a channel region CH1 or CH2 connected to the source layer 201 or 250.

[0111] Reference Figure 9A The source layer 201 may include a doped semiconductor material containing conductive impurities. In one embodiment, the source layer 201 may include n-type doped silicon. The channel region CH1 of the semiconductor layer SE may have a bottom surface in contact with the source layer 201. The memory layer 171 may surround the sidewalls of the semiconductor layer SE.

[0112] Reference Figure 9B The source layer 250 may include a first doped semiconductor pattern 251, a channel contact pattern 253, and a second doped semiconductor pattern 255. The channel contact pattern 253 may be disposed between the first insulating layer 101 and the first doped semiconductor pattern 251. The second doped semiconductor pattern 255 may be disposed between the first insulating layer 101 and the channel contact pattern 253. Although not shown in the figure, the second doped semiconductor pattern 255 may be omitted.

[0113] The first doped semiconductor pattern 251 may include at least one of n-type and p-type impurities. The channel contact pattern 253 may include a doped semiconductor layer containing conductive impurities. The second doped semiconductor pattern 255 may include the same conductive impurities as those in the channel contact pattern 253. In an embodiment, each of the channel contact pattern 253 and the second doped semiconductor pattern 255 may include n-type doped silicon.

[0114] The memory layer 171 and the channel structure 173 may extend through the second doped semiconductor pattern 255. The channel structure 173 may extend into the first doped semiconductor pattern 251. The semiconductor layer SE of the channel structure 173 may contact the channel contact pattern 253. In an embodiment, the channel region CH2 of the semiconductor layer SE may have sidewalls that contact the channel contact pattern 253. The channel region CH2 of the semiconductor layer SE may be inserted into a recess in the first doped semiconductor pattern 251. The semiconductor memory device may also include a dummy memory layer 171L disposed between the first doped semiconductor pattern 251 and the channel region CH2 of the semiconductor layer SE.

[0115] Figure 9A and Figure 9B The lower conductive patterns 111A of the semiconductor memory device shown can be used as source select lines.

[0116] The following description focuses on the contact area and describes a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0117] Figure 10A and Figure 10B This is a diagram illustrating an example of the process for forming a laminate and preliminary insulating pillars.

[0118] Reference Figure 10A and Figure 10B A first insulating layer 301 can be formed on a pre-prepared lower structure (not shown). Various lower structures, such as a substrate, a doped semiconductor layer, or a multilayer structure, are possible. Subsequently, a stack 300 can be formed on the first insulating layer 301. The first insulating layer 301 may include an oxide.

[0119] The laminate 300 can be formed by alternately stacking a first material layer 311 and a second material layer 321 in a first direction D1 intersecting the surface of the first insulating layer 301. Each of the first material layer 311 and the second material layer 321 may extend in a second direction D2 and a third direction D3 in a plane parallel to the surface of the first insulating layer 301.

[0120] The first material layer 311 may be formed of a material different from that of the second material layer 321. In embodiments, each first material layer 311 may include a conductive material, and each second material layer 321 may include an insulating material. In embodiments, the first material layer 311 may include an insulating material having etch selectivity relative to the first insulating layer 301 and the second material layer 321. For example, the first material layer 311 may include a nitride such as silicon nitride, and the second material layer 321 may include an oxide such as silicon oxide.

[0121] Subsequently, a second insulating layer 331 may be formed on the laminate 300. The second insulating layer 331 may be formed of a material different from the material of the first material layer 311. In an embodiment, the second insulating layer 331 may include an insulating material that has etch selectivity relative to the first material layer 311. For example, the second insulating layer 331 may include an oxide.

[0122] Subsequently, preliminary insulating pillars 335 may be formed. The preliminary insulating pillars 335 may penetrate the second insulating layer 331, the laminate 300, and the first insulating layer 301. The preliminary insulating pillars 335 may be spaced apart from each other in the second direction D2 and the third direction D3. The preliminary insulating pillars 335 may be formed of a material different from the material of the first material layer 311. In an embodiment, the preliminary insulating pillars 335 may include an insulating material having etch selectivity relative to the first material layer 311. For example, the preliminary insulating pillars 335 may include oxides.

[0123] Figure 11A and Figure 11BThis is a diagram illustrating an example of the process for forming insulating pillars and stepped structures.

[0124] Reference Figure 11A and Figure 11B It can be achieved through etching Figure 10A and Figure 10B The stepped structure 300ST is defined by the second insulating layer 331 and the laminate 300 shown. In this case, it can be defined by etching. Figure 10A and Figure 10B The preliminary insulating post 335 shown defines insulating posts 335A to 335G.

[0125] The insulating posts 335A to 335G may have different lengths in the first direction D1. The upper surfaces 335SU of each of the insulating posts 335A to 335G may be positioned at a lower height than the height at which the second insulating layer 331 is disposed. The upper surfaces 335SU of the insulating posts 335A to 335G may not be covered by the second insulating layer 331, but may be exposed.

[0126] The stepped structure 300ST may include a step formed by the upper surface 311S of the first material layer 311. The upper surface 311S of the first material layer 311 may not be covered by the second insulating layer 331, but may be exposed.

[0127] The upper surface 311S of the first material layer 311 and the upper surface 335SU of the insulating pillars 335A to 335G can provide pad area 340.

[0128] Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 15A and Figure 15B This is a diagram illustrating an example of the process for forming pad patterns.

[0129] Reference Figure 12A and Figure 12B A pad layer 343 can be conformally formed on the stepped structure 300ST to follow the contour of the stepped structure 300ST. The pad layer 343 can extend to cover the first insulating layer 301 and the second insulating layer 331. The pad layer 343 can cover the insulating pillars 335A to 335G. In the above-described structure of the pad layer 343, the pad region 340 can be covered by the pad layer 343.

[0130] The pad layer 343 may be formed of a material different from the materials of the first insulating layer 301, the second material layer 321, and the second insulating layer 331. In one embodiment, the pad layer 343 may include a conductive material. In another embodiment, the pad layer 343 may include an insulating material that has etch selectivity relative to the first insulating layer 301, the second material layer 321, and the second insulating layer 331. For example, the pad layer 343 may include silicon nitride.

[0131] Reference Figure 13A and Figure 13B Insulating patterns 345A, 345B1, and 345C1 can be formed on the pad layer 343. The insulating patterns 345A, 345B1, and 345C1 may comprise a material having etch selectivity relative to the pad layer 343. In one embodiment, the insulating patterns 345A, 345B1, and 345C1 may comprise oxides.

[0132] The insulating patterns 345A, 345B1, and 345C1 may include a plurality of first insulating patterns 345A, second insulating patterns 345B1, and third insulating patterns 345C1. The first insulating patterns 345A, second insulating patterns 345B1, and third insulating patterns 345C1 may be spaced apart from each other.

[0133] The first insulating pattern 345A may overlap with the pad area 340. In other words, the first insulating pattern 345A may overlap with the upper surface 311S of the first material layer 311 and the upper surface 335SU of the insulating pillars 335A to 335G.

[0134] The second insulating pattern 345B1 may overlap with the first insulating layer 301. The second insulating pattern 345B1 may be positioned closer to the first insulating layer 301 in the first direction D1 than each of the first insulating patterns 345A. A portion of the pad layer 343 may be interposed between the first insulating layers 301 and the second insulating patterns 345B1 that are adjacent to each other along the first direction D1. The first insulating layer 301 may extend longer than the first material layer 311 and the second material layer 321 in the second direction D2. The second insulating pattern 345B1 may overlap with the first insulating layer 301 without interposing the first material layer 311 and the second material layer 321.

[0135] The third insulating pattern 345C1 may overlap with the second insulating layer 331. The third insulating pattern 345C1 may be positioned further away from the first insulating layer 301 than each of the first insulating patterns 345A in the first direction D1. A portion of the pad layer 343 may be inserted between the second insulating layer 331 and the third insulating pattern 345C1, which are adjacent to each other along the first direction D1. The first material layer 311 and the second material layer 321 may be inserted between the first insulating layer 301 and the third insulating pattern 345C1, which are adjacent to each other along the first direction D1.

[0136] Reference Figure 14A and Figure 14B A mask pattern 351 can be formed to cover the first insulating pattern 345A. In an embodiment, the mask pattern 351 may be a photoresist pattern defined by a photolithography process. The mask pattern 351 may include... Figure 13A and Figure 13B The overlapping ends of a portion of the second insulating pattern 345B1 shown and with Figure 13A and Figure 13B The overlapping ends of a portion of the third insulating pattern 345C1 shown.

[0137] Subsequently, mask pattern 351 can be used as an etching barrier to remove the material through an etching process. Figure 13A and Figure 13B Some areas of each of the second insulating pattern 345B1 and the third insulating pattern 345C1 shown. Therefore, the narrower widths of the second insulating pattern 345B2 and the third insulating pattern 345C2 can be retained, and a portion of the pad layer 343 can be exposed.

[0138] After that, mask pattern 351 can be removed.

[0139] Reference Figure 15A and Figure 15B The first insulating pattern 345A, the second insulating pattern 345B2, and the third insulating pattern 345C2 can be used as etching barriers to remove the material through the etching process. Figure 14A and Figure 14B This is a portion of the pad layer 343 shown. Here, an etching process can be performed to expose the sidewalls of the second material layer 321. Through the etching process, Figure 14A and Figure 14B The pad layer 343 shown can be separated into pad patterns 343A, 343B and 343C.

[0140] The pad patterns 343A, 343B, and 343C may include multiple first pad patterns 343A, second pad patterns 343B, and third pad patterns 343C. The first pad patterns 343A, second pad patterns 343B, and third pad patterns 343C may be spaced apart from each other. The first pad patterns 343A, second pad patterns 343B, and third pad patterns 343C may be positioned at different heights.

[0141] The first pad pattern 343A can be disposed on the pad area 340. In other words, the first pad pattern 343A can overlap with the upper surface 311S of the first material layer 311 and the upper surface 335SU of the insulating pillars 335A to 335G, respectively.

[0142] The second pad pattern 343B can be disposed between the second insulating pattern 345B2 and the first insulating layer 301. The third pad pattern 343C can be disposed between the third insulating pattern 345C2 and the second insulating layer 331.

[0143] Figure 16A and Figure 16B This is a diagram illustrating an example of the process for forming a slit.

[0144] Reference Figure 16A and Figure 16B An upper insulating layer 353 may be formed on the second insulating layer 331. The upper insulating layer 353 may cover the first insulating pattern 345A, the second insulating pattern 345B2, and the third insulating pattern 345C2. The upper insulating layer 353 may cover the first pad pattern 343A, the second pad pattern 343B, and the third pad pattern 343C. The upper insulating layer 353 may cover the stepped structure 300ST and the first insulating layer 301. The upper insulating layer 353 may fill the space between the first insulating pattern 345A, the second insulating pattern 345B2, and the second material layer 321.

[0145] The upper insulating layer 353 may be formed of a material different from the materials of the first material layer 311, the first pad pattern 343A, the second pad pattern 343B, and the third pad pattern 343C. In embodiments, the upper insulating layer 353 may include an insulating material having etch selectivity relative to the first material layer 311, the first pad pattern 343A, the second pad pattern 343B, and the third pad pattern 343C. For example, the upper insulating layer 353 may include an oxide.

[0146] Subsequently, a slit 355 can be formed by an etching process. The slit 355 can penetrate the upper insulating layer 353, the second insulating layer 331, the first material layer 311, the second material layer 321, and the first insulating layer 301. The slit 355 can extend to penetrate the first insulating pattern 345A, the second insulating pattern 345B2, and the third insulating pattern 345C2. The slit 355 can extend to penetrate the first pad pattern 343A, the second pad pattern 343B, and the third pad pattern 343C.

[0147] Each of the first insulating layer 301, the first material layer 311, the second material layer 321, the upper insulating layer 353, the second insulating layer 331, the first pad pattern 343A, the second pad pattern 343B, the third pad pattern 343C, the first insulating pattern 345A, the second insulating pattern 345B2, and the third insulating pattern 345C2 may be retained on both sides of the slit 355.

[0148] Subsequent processes can be varied.

[0149] In an implementation, when each of the first material layer 311, the first pad pattern 343A, the second pad pattern 343B, and the third pad pattern 343C includes a conductive material, the subsequent steps may be... Figure 19 and Figure 20 The process shown. A first material layer 311 formed of conductive material, a first pad pattern 343A, and a second pad pattern 343B can be used as... Figure 5 and Figure 8 The conductive pattern 111 is shown. The third pad pattern 343C formed of conductive material can be used as... Figure 5 and Figure 8 The dummy conductive pattern 141 shown.

[0150] In an implementation, when each of the first material layer 311, the first pad pattern 343A, the second pad pattern 343B, and the third pad pattern 343C includes an insulating material, a process is performed to replace the first material layer 311, the first pad pattern 343A, the second pad pattern 343B, and the third pad pattern 343C with a conductive pattern, and then the implementation can proceed. Figure 19 and Figure 20 The process shown.

[0151] Figure 17A , Figure 17B , Figure 18A and Figure 18B This is a diagram illustrating an example of a process for forming conductive patterns.

[0152] Reference Figure 17A and Figure 17B The first material layer 311, the first pad pattern 343A, the second pad pattern 343B, and the third pad pattern 343C can be selectively removed through the slit 355. Therefore, openings 359A, 359B, 359C, and 359D can be defined.

[0153] The openings 359A, 359B, 359C, and 359D are spaced apart from each other in the first direction D1 by the second material layer 321 and the second insulating layer 331. The openings 359A, 359B, 359C, and 359D may include a first opening 359A, a second opening 359B, a plurality of third openings 359C, and a fourth opening 359D.

[0154] Hereinafter, insulating posts 335A to 335G are referred to as the first insulating post 335A, the second insulating post 335G, and the third insulating posts 335B to 335F, respectively. Among insulating posts 335A to 335G, the first insulating post 335A may have the shortest length, while among insulating posts 335A to 335G, the second insulating post 335G may have the longest length. The third insulating posts 335B to 335F can be defined as insulating posts other than the first insulating post 335A and the second insulating post 335G among insulating posts 335A to 335G.

[0155] Hereinafter, the second material layer 321 will be referred to as the lowermost second material layer 321B, the intermediate second material layer 321M, and the uppermost second material layer 321T. Among the second material layers 321, the lowermost second material layer 321B may be positioned closest to the first insulating layer 301 in the first direction D1. Among the second material layers 321, the uppermost second material layer 321T may be positioned furthest from the first insulating layer 301 in the first direction D1. The intermediate second material layer 321M may be disposed between the lowermost second material layer 321B and the uppermost second material layer 321T, spaced apart in the first direction D1.

[0156] The first opening 359A may extend from between the first insulating layer 301 and the lowermost second material layer 321B to between the first insulating layer 301 and the first insulating pattern 345A overlapping the first insulating post 335A. Furthermore, the first opening 359A may extend between the first insulating layer 301 and the second insulating pattern 345B2. The end 335EG of the first insulating post 335A may be exposed through the first opening 359A.

[0157] The second opening 359B extends from between the uppermost second material layer 321T and the second insulating layer 331 to between the uppermost second material layer 321T and the first insulating pattern 345A overlapping with the second insulating post 335G. The end 335EG of the second insulating post 335G can be exposed through the second opening 359B.

[0158] The third opening 359C may be defined between adjacent second material layers 321 along the first direction D1. The third opening 359C may extend between the first insulating pattern 345A overlapping with the third insulating pillars 335B to 335F and the intermediate second material layer 321M. The ends 335EG of the third insulating pillars 335B to 335F may be exposed through the third opening 359C, respectively.

[0159] The fourth opening 359D may be defined between the second insulating layer 331 and the third insulating pattern 345C2.

[0160] Reference Figure 18A and Figure 18B Conductive patterns 361A, 361B, 361C, and 361D can be used for filling. Figure 17A and Figure 17B The first opening 359A, the second opening 359B, the third opening 359C, and the fourth opening 359D are shown. Conductive patterns 361A, 361B, 361C, and 361D can be formed by introducing conductive material through slit 355.

[0161] Conductive patterns 361A, 361B, 361C, and 361D are insulated from each other by the second material layer 321 and the second insulating layer 331. Conductive patterns 361A, 361B, 361C, and 361D may surround the ends 335EG of insulating pillars 335A to 335G at different heights. Conductive patterns 361A, 361B, 361C, and 361D may include a lower conductive pattern 361A, an upper conductive pattern 361B, multiple intermediate conductive patterns 361C, and a dummy conductive pattern 361D.

[0162] The lower conductive pattern 361A can be filled Figure 17A and Figure 17B The first opening 359A is shown. The lower conductive pattern 361A may surround the end 335EG of the first insulating post 335A. The lower conductive pattern 361A may extend between the first insulating post 335A and the first insulating pattern 345A that overlaps with the first insulating post 335A.

[0163] 361B conductive pattern can be filled Figure 17A and Figure 17B The second opening 359B is shown. The upper conductive pattern 361B may surround the end 335EG of the second insulating post 335G. The upper conductive pattern 361B may extend between the second insulating post 335G and the first insulating pattern 345A that overlaps with the second insulating post 335G.

[0164] The intermediate conductive pattern 361C can be filled separately. Figure 17A and Figure 17B The third opening 359C is shown. The intermediate conductive pattern 361C may surround the ends 335EG of the third insulating posts 335B to 335F respectively. The intermediate conductive pattern 361C may extend between the third insulating posts 335B to 335F and the first insulating pattern 345A that overlaps with the third insulating posts 335B to 335F.

[0165] Although not shown in the figure, Figure 14A and Figure 14B The mask pattern 351 shown may not be related to Figure 13A and Figure 13BThe third insulating pattern 345C1 and the second insulating pattern 345B1 are shown overlapping. In this case, the second insulating pattern 345B2, the third insulating pattern 345C2 and the dummy conductive pattern 361D may not be retained, and the end of the lower conductive pattern 361A may have a structure similar to the structure of the end of each intermediate conductive pattern 361C.

[0166] Figure 19 This is a perspective view illustrating an example of the process for forming the sidewall insulating layer and the conductive electrode contacts.

[0167] Reference Figure 19 In the implementation method, it is possible to Figure 18A A sidewall insulating layer 371 is formed on the sidewall of the slit 355 shown. Subsequently, a conductive electrode contact 373 extending along the sidewall insulating layer 371 can be formed.

[0168] In the implementation method, when Figure 16B When the individual pad patterns 343A shown are retained as part of the conductive pattern, they can be... Figure 16A A sidewall insulating layer 371 and a conductive electrode contact 373 are formed in the slit 355 shown.

[0169] Figure 20 This is a perspective view illustrating an example of a process for forming conductive contacts.

[0170] Reference Figure 20 Conductive contacts 381 can be formed to pass through the upper insulating layer 353. Conductive contacts 381 can pass through the first insulating pattern 345A. In an embodiment, conductive contacts 381 can interact with... Figure 18B The insulating posts 335A to 335G shown overlap and can be connected to conductive patterns 361A, 361B and 361C.

[0171] Although not shown in the figures, in the implementation, when Figure 16B When the various pad patterns 343A shown are retained as part of the conductive pattern, the conductive contact 381 can be connected to Figure 16B The pad pattern shown is 343A.

[0172] The connection structure of conductive contact 381 and conductive patterns 361A, 361B and 361C can be connected with Figure 6A The connection structure of the conductive contact 185 and the conductive pattern 111 shown is the same, or can be the same as... Figure 8 The conductive contact 185' and the conductive pattern 111 shown have the same connection structure.

[0173] Similar to a reference Figure 7 As described, the cross-sectional area of ​​the conductive contact 381 can be less than... Figure 18B The cross-sectional areas of the insulating pillars 335A to 335G are shown.

[0174] Figure 21 This is a block diagram illustrating the configuration of a memory system 1100 according to an embodiment of the present disclosure.

[0175] Reference Figure 21 The memory system 1100 includes a memory device 1120 and a memory controller 1110.

[0176] The memory device 1120 may be a multi-chip package formed of multiple flash memory chips. The memory device 1120 may include: a first conductive pattern; a second conductive pattern that overlaps with the line components of the first conductive pattern and exposes the pad components of the first conductive pattern; an interlayer insulating layer disposed between the first conductive pattern and the second conductive pattern; and a first conductive contact and a first insulating post that extend in opposite directions from the pad components of the first conductive pattern.

[0177] The storage controller 1110 controls the storage device 1120 and includes a static random access memory (SRAM) 1111, a central processing unit (CPU) 1112, a host interface 1113, an error correction block 1114, and a memory interface 1115. The SRAM 1111 serves as the operating memory for the CPU 1112. The CPU 1112 performs overall control operations for data exchange with the storage controller 1110. A data exchange protocol for a host connected to the storage system 1100 is provided to the host interface 1113. The error correction block 1114 detects errors in data read from the storage device 1120 and corrects the detected errors. The memory interface 1115 interfaces with the storage device 1120. The storage controller 1110 may also include a read-only memory (ROM) for storing code data for interfacing with the host.

[0178] The aforementioned memory system 1100 may be a memory card or solid-state drive (SSD) equipped with a memory device 1120 and a storage controller 1110. For example, when the memory system 1100 is an SSD, the storage controller 1110 may communicate with an external device (e.g., a host) via one of various interface protocols such as Universal Serial Bus (USB), Multimedia Card (MMC), High-Speed ​​Peripheral Component Interconnect (PCI-E), Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), and Integrated Drive Electronic Devices (IDE) protocol.

[0179] Figure 22 This is a block diagram illustrating the configuration of a computing system 1200 according to an embodiment of the present disclosure.

[0180] Reference Figure 22The computing system 1200 may include a CPU 1220, random access memory (RAM) 1230, a user interface 1240, a modem 1250, and a memory system 1210 electrically connected to a system bus 1260. If the computing system 1200 is a mobile device, it may also include a battery for supplying operating voltage to the computing system 1200. It may also include an application chipset, a graphics processor, mobile DRAM, etc.

[0181] The memory system 1210 may include a memory device 1212 and a memory controller 1211.

[0182] The memory device 1212 may include: a first conductive pattern; a second conductive pattern that overlaps with the line assembly of the first conductive pattern and exposes the pad assembly of the first conductive pattern; an interlayer insulating layer disposed between the first conductive pattern and the second conductive pattern; and a first conductive contact and a first insulating post that extend from the pad assembly of the first conductive pattern in opposite directions.

[0183] According to this disclosure, the conductive contacts overlap with the insulating pillars, thus preventing process defects caused by the conductive contacts simultaneously connecting to conductive patterns arranged at different heights. According to this disclosure, the stability of the manufacturing process for semiconductor memory devices can be improved, and the operational reliability of semiconductor memory devices can be increased.

[0184] Cross-references to related applications

[0185] This application claims priority to Korean Patent Application No. 10-2021-0018396, filed with the Korean Intellectual Property Office on February 9, 2021, the full disclosure of which is incorporated herein by reference.

Claims

1. A semiconductor memory device, the semiconductor memory device comprising: A first conductive pattern, the first conductive pattern including a first line assembly and a first pad assembly extending from the first line assembly; A second conductive pattern overlaps with the first line component of the first conductive pattern and exposes the first pad component of the first conductive pattern, the second conductive pattern being spaced apart from the first conductive pattern in a first direction. An interlayer insulating layer is located between the first conductive pattern and the second conductive pattern; A first conductive contact extends from the first pad assembly of the first conductive pattern in the first direction; as well as A first insulating post overlaps with the first conductive contact and extends from the first pad assembly in a direction opposite to the first direction. The first insulating post includes a top surface facing the first conductive contact, and The first pad assembly completely covers the top surface of the first insulating post.

2. The semiconductor memory device according to claim 1, wherein, The cross-sectional area of ​​the first insulating post is greater than the cross-sectional area of ​​the first conductive contact.

3. The semiconductor memory device according to claim 1, in, The bottom of the first pad assembly of the first conductive pattern includes a recess, the bottom facing a direction opposite to the first direction, and The first insulating post includes an end that is inserted into the recess.

4. The semiconductor memory device according to claim 3, wherein, The thickness of the first pad assembly in the first direction is greater than both of the following: The depth of the recess in the first direction; and The thickness of the first line component in the first direction.

5. The semiconductor memory device according to claim 1, wherein, The second conductive pattern includes: A second pad assembly, the second pad assembly being adjacent to the first pad assembly of the first conductive pattern; and The second line component extends from the second pad component.

6. The semiconductor memory device according to claim 5, further comprising: A second conductive contact extends from the second pad assembly of the second conductive pattern in the first direction; as well as The second insulating post overlaps with the second conductive contact and extends from the second pad assembly in the direction opposite to the first direction.

7. The semiconductor memory device according to claim 6, wherein, The second insulating pillar passes through the interlayer insulation layer and the first wire assembly of the first conductive pattern.

8. A semiconductor memory device, the semiconductor memory device comprising: A first insulating layer, the first insulating layer including a unit array region and a contact region; A plurality of insulating posts, the plurality of insulating posts passing through the first insulating layer in the contact area and extending to different lengths in a first direction; Multiple conductive patterns, the multiple conductive patterns including multiple pad assemblies that surround the end of the insulating post at different heights above the first insulating layer; as well as Multiple conductive contacts overlap with the insulating pillar and respectively contact the pad assembly. Each of the plurality of insulating pillars includes a top surface facing the corresponding conductive contact among the plurality of conductive contacts, and Each of the plurality of pad assemblies completely covers the top surface of the corresponding insulating post among the plurality of insulating posts.

9. The semiconductor memory device according to claim 8, wherein, The plurality of conductive patterns each include a line assembly extending from the pad assembly to overlap with the first insulating layer in the cell array region.

10. The semiconductor memory device of claim 9, further comprising: An interlayer insulating layer, the interlayer insulating layer being between the plurality of conductive patterns; A channel structure that passes through the line assembly of the conductive pattern, the interlayer insulating layer, and the first insulating layer in the cell array region; as well as A memory layer that surrounds the sidewalls of the channel structure.

11. The semiconductor memory device according to claim 9, wherein, In the first direction, the thickness of each of the pad assemblies is greater than the thickness of each of the line assemblies.

12. The semiconductor memory device according to claim 9, in, The conductive pattern includes a lower conductive pattern that is in contact with the first insulating layer. The pad assembly of the conductive pattern includes the lower pad assembly of the lower conductive pattern. The conductive pattern's line assembly includes a lower line assembly extending from the lower pad assembly, and The lower conductive pattern has a protrusion extending from the lower pad assembly in a direction opposite to that of the lower line assembly.

13. The semiconductor memory device according to claim 12, wherein, In the first direction, the thickness of the protrusion is less than the thickness of the lower line assembly and the thickness of the lower pad assembly.

14. The semiconductor memory device of claim 9, further comprising: A second insulating layer is provided on the upper wire assembly of the conductive pattern, which is furthest from the first insulating layer. as well as A dummy conductive pattern is provided on the edge of the second insulating layer.

15. The semiconductor memory device according to claim 14, wherein, In the first direction, the thickness of the dummy conductive pattern is less than the thickness of each of the line components of the conductive pattern.

16. The semiconductor memory device according to claim 8, wherein, The cross-sectional area of ​​each of the insulating pillars is greater than the cross-sectional area of ​​each of the conductive contacts.

17. The semiconductor memory device according to claim 8, wherein, The pad assembly of the conductive pattern extends between the top surface of the insulating pillar and the bottom surface of the conductive contact.

18. The semiconductor memory device according to claim 8, wherein, The conductive contact extends into the insulating post.

19. The semiconductor memory device of claim 18, wherein, The pad assembly of the conductive pattern contacts the sidewall of the conductive contact.

20. The semiconductor memory device of claim 18, wherein, The conductive contact includes a bottom surface that contacts the insulating post.

21. A method for manufacturing a semiconductor memory device, the method comprising the following steps: Form an insulating layer; A plurality of insulating pillars are formed that pass through the insulating layer and have different lengths in a first direction intersecting the surface of the insulating layer; Forming a plurality of conductive patterns that overlap with the insulating layer and surround the ends of the insulating pillar at different heights; and Multiple conductive contacts are formed, each overlapping the insulating pillar and connected to the conductive pattern. Each of the plurality of insulating pillars includes a top surface facing the corresponding conductive contact among the plurality of conductive contacts, and Each of the plurality of conductive patterns completely covers the top surface of the corresponding insulating post among the plurality of insulating posts.

22. The method according to claim 21, wherein, The cross-sectional area of ​​each of the conductive contacts is smaller than the cross-sectional area of ​​each of the insulating pillars.

23. A method for manufacturing a semiconductor memory device, the method comprising the following steps: Forming a laminate comprising a plurality of first material layers and a plurality of second material layers alternately stacked in a first direction; Multiple preliminary insulating pillars are formed through the laminate; The plurality of preliminary insulating posts are etched to form a plurality of insulating posts with different lengths in the first direction; Etch the first material layer and the second material layer to form a stepped structure having a step formed by the upper surface of the first material layer; A plurality of pad patterns are formed on the upper surface of the first material layer; Form an upper insulating layer covering the pad pattern and the stepped structure; as well as Multiple conductive contacts are formed that pass through the upper insulating layer and overlap with the insulating pillar. Each of the plurality of insulating pillars includes a top surface facing the corresponding conductive contact among the plurality of conductive contacts. The plurality of pad patterns extend to overlap with the insulating pillars respectively, and Each of the plurality of pad patterns completely covers the top surface of the corresponding insulating pillar among the plurality of insulating pillars.

24. The method according to claim 23, wherein, The etching of the initial insulating pillar is performed simultaneously with the etching of the first material layer and the second material layer.

25. The method according to claim 23, wherein, The first material layer and the pad pattern include a material that has etch selectivity relative to the second material layer.

26. The method of claim 23, further comprising the step of: Remove the first material layer and the pad pattern to define multiple openings that expose the ends of the insulating pillars; as well as Multiple conductive patterns are formed, each filling the opening and surrounding the end of the insulating post.

27. The method according to claim 26, wherein, The plurality of conductive contacts are respectively connected to the conductive pattern.

28. The method according to claim 23, wherein, The step of forming the pad pattern on the upper surface of the first material layer includes the following steps: A pad layer is formed covering the stepped structure and the insulating pillar; A plurality of insulating patterns spaced apart from each other are formed on the pad layer; and The insulating pattern is used as an etching barrier to remove a portion of the pad layer by an etching process to expose the sidewalls of the second material layer.

29. The method according to claim 23, wherein, The cross-sectional area of ​​each of the conductive contacts is smaller than the cross-sectional area of ​​each of the insulating pillars.

Images