Methods of forming electronic devices and related electronic devices, memory devices, and systems

Abstract

The present application relates to methods of forming electronic devices and related electronic devices, memory devices, and systems. The methods of forming electronic devices include forming a stack structure including vertically alternating insulative structures and additional insulative structures; and forming a pillar including a channel material and at least one dielectric material extending vertically through the stack structure. The methods include removing the additional insulative structures to form a cell opening; forming a first conductive material within a portion of the cell opening; and forming a fill material within the cell opening adjacent to the first conductive material. The fill material includes a sacrificial portion. The methods include removing the sacrificial portion of the fill material; and forming a second conductive material within the cell opening in an orientation previously occupied by the sacrificial portion of the fill material.

Description

[0001] Priority requirements

[0002] This application claims the benefit of U.S. Patent Application No. 17 / 171,622, filed February 9, 2021, entitled “METHODS OF FORMING ELECTRONIC DEVICES, AND RELATED ELECTRONIC DEVICES, MEMORY DEVICES, AND SYSTEMS”. Technical Field

[0003] The embodiments disclosed herein relate to the field of microelectronic device design and manufacturing. More specifically, embodiments of this disclosure relate to methods of forming an electronic device comprising a filling material (e.g., a non-conductive material, different conductive materials) within the central portion of individual conductive structures (e.g., access lines, word lines), and related electronic devices, memory devices, and systems. Background Technology

[0004] A persistent goal of the electronics industry is to increase the memory density (e.g., the number of memory cells per memory die) of memory devices, such as non-volatile memory devices (e.g., NAND flash memory devices). One way to increase memory density in non-volatile memory devices is by utilizing vertical memory array (also known as “three-dimensional (3D) memory arrays”) architectures. A conventional vertical memory array comprises vertical memory strings extending through openings in one or more stacked structures that include layers of conductive and insulating structures. Each vertical memory string may contain at least one selection device series-coupled to a series combination of vertically stacked memory cells. Compared to structures with conventional planar (e.g., two-dimensional) transistor arrangements, this configuration allows for a greater number of switching devices (e.g., transistors) to be located in cells (i.e., the length and width of the active surface consumed) of the die region by constructing the array upwards (e.g., vertically) on the die.

[0005] A vertical memory array architecture generally comprises electrical connections between conductive structures of a layer of conductive stacked structure of the memory device and access lines (e.g., word lines), allowing memory cells of the vertical memory array to be uniquely selected for write, read, or erase operations. One method of forming such electrical connections involves forming a so-called “step” (or “staircase”) structure at the edges (e.g., horizontal ends) of the conductive stacked structure of the memory device. The step structure includes individual “steps” defining contact areas of conductive structures, on which conductive contact structures can be positioned to provide electrical access to the conductive structures.

[0006] With the development of vertical memory array technology, additional memory density has been achieved by forming vertical memory arrays as additional layers including conductive structures, and thus including additional step structures and / or additional steps in the associated individual step structures. As the number of conductive layers increases, the processing conditions for forming vertical memory strings extending through the stack become increasingly difficult. Furthermore, as the thickness of each layer decreases to increase the number of layers within a given stack height, the resistivity of the conductive structure can increase, and the conductivity can exhibit a corresponding decrease. However, the decrease in conductivity of the conductive structure can affect the performance of the memory cell strings. Summary of the Invention

[0007] The embodiments described herein include methods for forming an electronic device comprising a filler material within the central portion of an individual conductive structure, and related electronic devices, memory devices, and systems. According to the embodiments described herein, a method of forming an electronic device includes: forming a stacked structure comprising alternating vertical insulating structures and additional insulating structures; forming a pillar comprising a channel material extending vertically through the stacked structure and at least one dielectric material; removing the additional insulating structure to form a cell opening; forming a first conductive material within a portion of the cell opening; forming a filler material adjacent to the first conductive material within the cell opening, the filler material including a sacrificial portion; removing the sacrificial portion of the filler material; and forming a second conductive material within the cell opening in an orientation previously occupied by the sacrificial portion of the filler material.

[0008] According to an additional embodiment described herein, an electronic device includes: a stacked structure comprising alternating layers of conductive and insulating structures; pillars extending vertically through the stacked structure; and a filler material located within the central portion of individual conductive structures of the stacked structure, the filler material being positioned between adjacent pillars and substantially surrounded by the conductive material of the individual conductive structures.

[0009] Furthermore, according to additional embodiments described herein, a memory device includes: a stacked structure comprising alternating conductive and insulating structures arranged in layers, each layer individually including conductive and insulating structures; a barrier material that separates opposing portions of the conductive materials of the conductive structures; a string of memory cells extending vertically through the stacked structure, the string of memory cells including channel material extending vertically through the stacked structure; and conductive rails laterally adjacent to the conductive structures of the stacked structure, each conductive rail being horizontally aligned with the barrier material and the conductive material of its respective conductive structure.

[0010] According to another embodiment described herein, a system includes: a processor operatively coupled to an input device and an output device; and an electronic device operatively coupled to the processor, the electronic device including: a string of memory cells extending vertically through a stacked structure and comprising a vertically alternating sequence of insulating and conductive structures arranged in layers; and a filler material circumferentially surrounding at least some of the string of memory cells, the filler material being situated between opposing portions of conductive material within individual conductive structures. Attached Figure Description

[0011] Figures 1A to 1K This is a simplified cross-sectional view illustrating a method of forming an electronic device according to embodiments of the present disclosure. Figure 1A-1H and 1J-1K) and simplified partial top view ( Figure 1I );

[0012] Figure 2 This is a partial cross-sectional perspective view of an electronic device according to an embodiment of the present disclosure;

[0013] Figure 3 This is a block diagram of an electronic system according to embodiments of the present disclosure; and

[0014] Figure 4 This is a block diagram of a processor-based system according to an embodiment of the present disclosure. Detailed Implementation

[0015] This document describes methods for forming electronic devices (e.g., microelectronic devices, semiconductor devices, memory devices) containing filler materials (e.g., non-conductive materials, different conductive materials) within the central portion of individual conductive structures (e.g., access lines, word lines), as well as related electronic devices, memory devices, and systems. In some embodiments, a method of forming an electronic device includes: forming a stacked structure comprising vertically alternating insulating structures and additional insulating structures; forming pillars extending vertically through the stacked structure; and removing the additional insulating structures to form a cell opening. A first conductive material (e.g., a metal) may be formed within a portion of the cell opening, and a filler material adjacent to the first conductive material may be formed within the cell opening. The material composition of the filler material may differ from that of the first conductive material, and the filler material may be selectively etched relative to the first conductive material. For example, the filler material may comprise one or more of the following: non-conductive materials (e.g., oxide materials, nitride materials, or carbide materials), semiconductor materials (e.g., polysilicon), or conductive materials (e.g., titanium nitride, metals) having a material composition different from that of the first conductive material. The sacrificial portion of the filler material can be removed, and a second conductive material can be formed within the cell opening in the location previously occupied by the sacrificial portion of the filler material. Therefore, the conductive structure (e.g., conductive line, access line, word line) includes filler material within the central portion (e.g., a vertical central portion) of the individual conductive structure in the stacked structure.

[0016] The filler material in the central portion is located between adjacent pillars and is substantially surrounded by conductive material within the individual conductive structures. A second conductive material may be formed within the cell opening near the slot (e.g., replacing the gate slot), but not between adjacent pillars. Alternatively, conductive rails may be formed laterally adjacent to the exposed surfaces of the first and second conductive materials. By using two or more (e.g., three) separate process actions, filler material can be formed within the central portion of the conductive structure, effectively reducing voids in the conductive layer of the layer. Furthermore, the presence of filler material reduces parasitic capacitance between adjacent conductive structures and increases short-circuit margin between vertically adjacent conductive structures without significantly affecting resistance. By reducing parasitic capacitance, electronic devices with filler material in the central portion of the conductive structure according to embodiments of this disclosure can utilize less power and operate at higher speeds compared to conventional electronic devices.

[0017] The following description provides specific details, such as material composition, shape, and size, to provide a sufficient description of embodiments of this disclosure. However, those skilled in the art will understand that embodiments of this disclosure can be practiced without these specific details. In fact, embodiments of this disclosure can be practiced in conjunction with conventional electronic device manufacturing techniques used in the industry. Furthermore, the description provided below does not form a complete process flow for manufacturing electronic devices (e.g., memory devices, such as 3D NAND flash memory devices). The structures described below do not form a complete electronic device. Only those process actions and structures necessary for understanding embodiments of this disclosure are described in detail below. Additional actions to form a complete electronic device from the structures can be performed by conventional manufacturing techniques.

[0018] Unless otherwise indicated, the materials described herein may be formed using conventional techniques including, but not limited to, spin coating, blanket coating, chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma-enhanced ALD, physical vapor deposition (PVD) (including sputtering, evaporation, ionized PVD, and / or plasma-enhanced CVD), or epitaxial growth. Alternatively, the materials may be grown in situ. The technique used for depositing or growing the materials may be selected by those skilled in the art, depending on the specific material to be formed. Unless the context otherwise indicates, material removal may be achieved by any suitable technique including, but not limited to, etching (e.g., dry etching, wet etching, vapor phase etching), ion milling, planarization (e.g., chemical-mechanical planarization), or other known methods.

[0019] The accompanying drawings presented herein are for illustrative purposes only and are not intended to be actual views of any particular material, component, structure, electronic device, or electronic system. The shapes depicted in the drawings are expected to vary due to, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described herein should not be construed as limited to the specific shapes or areas illustrated, but should include, for example, shape variations caused by manufacturing processes. For instance, an area illustrated or described as box-shaped may have rough and / or non-linear characteristics, and an area illustrated or described as circular may include some rough and / or linear characteristics. Furthermore, acute angles shown may be rounded, and vice versa. Therefore, the areas illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shape of the areas and do not limit the scope of the claims. The drawings are not necessarily to scale. Additionally, common elements between figures may retain the same numerical designations.

[0020] As used herein, unless the context clearly indicates otherwise, the singular forms “a / an” and “the” are intended to include the plural forms as well.

[0021] As used herein, “and / or” includes any and all combinations of one or more of the associated listed items.

[0022] As used herein, spatial relative terms such as “below,” “under,” “lower,” “bottom,” “above,” “upper,” “top,” “front,” “rear,” “left,” and “right” are used to conveniently describe the relationship of one element or feature to another, as illustrated in the figures. Unless otherwise specified, spatial relative terms are intended to cover different orientations of material other than those depicted in the figures. For example, if the material in the figures is inverted, then an element described as “below,” “under,” “lower,” or “bottom” of other elements or features will be oriented “above” or “top” of said other elements or features. Thus, the term “below” may encompass both above and below orientations, depending on the context in which the term is used, as will be apparent to those skilled in the art. Material may be oriented in other ways (e.g., rotated 90 degrees, inverted, flipped), and the spatial relative descriptors used herein will be interpreted accordingly.

[0023] As used herein, the terms “vertical,” “longitudinal,” “horizontal,” and “lateral” refer to the principal plane of the structure and are not necessarily defined by the Earth’s gravitational field. A “horizontal” or “lateral” direction is generally parallel to the principal plane of the structure, while a “vertical” or “longitudinal” direction is generally perpendicular to the principal plane of the structure. The principal plane of the structure is defined by structural surfaces that have a relatively large area compared to the other surfaces of the structure.

[0024] As used herein, referring to an element as "on" or "above" another element means and includes that the element is directly on top of the other element, directly adjacent to (e.g., laterally adjacent, vertically adjacent) the other element, directly below the other element, or in direct contact with the other element. It also includes that the element is indirectly on top of the other element, indirectly adjacent to (e.g., indirectly laterally adjacent, indirectly vertically adjacent) the other element, indirectly below the other element, or nearby, with other elements present in between. In contrast, when an element is referred to as "directly on" or "adjacent to" another element, no intermediate elements are present.

[0025] As used herein, spatial relative terms such as “below,” “under,” “lower,” “bottom,” “above,” “upper,” “top,” “front,” “rear,” “left,” and “right” are used to conveniently describe the relationship of one element or feature to another, as illustrated in the figures. Unless otherwise specified, spatial relative terms are intended to cover different orientations of material other than those depicted in the figures. For example, if the material in the figures is inverted, then an element described as “below,” “under,” “lower,” or “bottom” of other elements or features will be oriented “above” or “top” of said other elements or features. Thus, the term “below” may encompass both above and below orientations, depending on the context in which the term is used, as will be apparent to those skilled in the art. Material may be oriented in other ways (e.g., rotated 90 degrees, inverted, flipped), and the spatial relative descriptors used herein will be interpreted accordingly.

[0026] As used herein, the term “configured to” refers to the size, shape, material composition, and arrangement of one or more of at least one structure and at least one device, which in a predetermined manner facilitates the operation of one or more of the structure and device.

[0027] As used herein, features described as “adjacent” to each other (e.g., area, material, structure, device) mean and include features of one or more disclosed identities located closest to each other (e.g., closest to each other). Additional features of one or more disclosed identities that do not match “adjacent” features (e.g., additional area, additional material, additional structure, additional device) may be positioned between “adjacent” features. In other words, “adjacent” features may be positioned directly adjacent to each other such that no other features intervene between “adjacent” features; or “adjacent” features may be positioned indirectly adjacent to each other such that at least one feature having an identifier other than the identifier associated with at least one “adjacent” feature is positioned between “adjacent” features. Thus, features described as “vertically adjacent” to each other mean and include features of one or more disclosed identities located closest to each other (e.g., vertically closest to each other). Furthermore, features described as “horizontally adjacent” to each other mean and include features of one or more disclosed identities located closest to each other (e.g., horizontally closest to each other).

[0028] As used in this article, the term “split” refers to the distance between identical points in two adjacent (i.e., adjacent) features.

[0029] As used herein, the term "generally" refers to and includes the degree to which a given parameter, property, or condition conforms to deviations (such as within acceptable tolerances) as would be understood by one of ordinary skill in the art. By way of example, depending on the specific parameter, property, or condition that is substantially satisfied, it may satisfy at least 90.0%, at least 95.0%, at least 99.0%, at least 99.9%, or even 100.0%.

[0030] As used herein, the term "about" or "approximately" when referring to a value for a particular parameter includes the value, and those skilled in the art will understand that the deviation from the value is within acceptable tolerances for the particular parameter. For example, "about" or "approximately" with respect to a value may include additional values ​​within 90.0% to 108.0% of the value, such as within 95.0% to 105.0%, 97.5% to 102.5%, 99.0% to 101.0%, 99.5% to 100.5%, or 99.9% to 100.1%.

[0031] As used herein, the term "memory device" means and includes, but is not limited to, microelectronic devices that exhibit memory functionality. In other words, and by way of example only, the term "memory device" means and includes not only conventional memory (e.g., conventional volatile memory, such as conventional dynamic random access memory (DRAM); conventional non-volatile memory, such as conventional NAND memory), but also application-specific integrated circuits (ASICs) (e.g., system-on-a-chip (SoC)), electronic devices with combinational logic and memory, or graphics processing units (GPUs) incorporating memory.

[0032] As used herein, the term "electronic device" includes, but is not limited to, memory devices, and semiconductor devices that may or may not incorporate memory, such as logic devices, processor devices, or radio frequency (RF) devices. Furthermore, electronic devices may incorporate memory and other functions, such as a so-called "system-on-a-chip" (SoC) that includes a processor and memory, or an electronic device that includes logic and memory. Electronic devices can be, for example, 3D electronic devices, such as 3D NAND flash memory devices.

[0033] As used herein, the term "conductive material" means and includes electrically conductive material. Conductive material may include one or more of the following: doped polycrystalline silicon, undoped polycrystalline silicon, metals, alloys, conductive metal oxides, conductive metal nitrides, conductive metal silicides, and conductive doped semiconductor materials. By way of example only, conductive material may be formed from one or more of the following and may include one or more of the following: tungsten (W), tungsten nitride (WN). y Nickel (Ni), Tantalum (Ta), Tantalum nitride (TaN) y ), tantalum silicide (TaSi) x Platinum (Pt), Copper (Cu), Silver (Ag), Gold (Au), Aluminum (Al), Molybdenum (Mo), Titanium (Ti), Titanium Nitride (TiN) y Titanium silicide (TiSi) x Titanium silicon nitride (TiSi) x N y ), Titanium aluminum nitride (TiAl) x N y ), molybdenum nitride (MoN) x ), iridium (Ir), iridium oxide (IrO) z ), Ruthenium (Ru), Ruthenium oxide (RuO) z ), n-doped polycrystalline silicon, p-doped polycrystalline silicon, undoped polycrystalline silicon, and conductive doped silicon.

[0034] As used herein, a “conductive structure” means and includes a structure formed of and containing one or more conductive materials. Additional materials (e.g., non-conductive materials) may also be present within the boundaries of the conductive structure (e.g., within the central portion).

[0035] As used herein, “insulating material” means and includes electrically insulating materials, such as at least one dielectric oxide material (e.g., silicon oxide (SiO2)). x Phossilicate glass, borosilicate glass, borosilicate-phosphorus glass, fluorosilicate glass, alumina (AlO) x ), hafnium oxide (HfO) x ), niobium oxide (NbO) x Titanium oxide (TiO) x Zirconium oxide (ZrO) x ), tantalum oxide (TaO) x ) and magnesium oxide (MgO) x One or more of the following), at least one dielectric nitride material (e.g., silicon nitride (SiN) y ()), at least one dielectric oxide nitride material (e.g., silicon oxynitride (SiO)x N y and at least one dielectric carbon oxynitride material (e.g., silicon carbon oxynitride (SiO2)). x C z N y One or more of the chemical formulas “x”, “y”, and “z” are included in this document (e.g., SiO2). x AlO x HfO x NbO x TiO x SiN y SiO x N y SiO x C z N y A chemical formula represents a material containing “x” atoms of one element, “y” atoms of another element, and “z” atoms of an additional element (if present) relative to each atom of another element (e.g., Si, Al, Hf, Nb, Ti). Because chemical formulas represent relative atomic ratios and non-strict chemical structures, insulating materials may include one or more stoichiometric compounds and / or one or more non-stoichiometric compounds, and the values ​​of “x,” “y,” and “z” (if present) may be integers or non-integers. As used herein, the term “non-stoichiometric compound” means and includes compounds having an elemental composition that cannot be represented by a well-defined ratio of natural numbers and violates the laws of definite proportions and multiple proportions.

[0036] As used in this article, “insulating structure” means and includes structures formed of insulating material and containing insulating material.

[0037] As used herein, the term "high-k dielectric material" refers to and includes silicon oxide (SiO2) having a dielectric content greater than, for example, silicon dioxide (SiO2). x High-k dielectric materials are dielectric oxide materials with a dielectric constant of _____. High-k dielectric materials may include high-k oxide materials, high-k metal oxide materials, or combinations thereof. By way of example only, high-k dielectric materials may be alumina, gadolinium oxide, hafnium oxide, niobium oxide, tantalum oxide, titanium oxide, zirconium oxide, hafnium silicate, combinations thereof, or one or more of the listed high-k dielectric materials having silicon oxide.

[0038] As used herein, the term "selectively etchable" means and includes a material exhibiting a greater etching rate relative to another material exposed to a given etching chemical and / or processing condition in response to exposure to the same etching chemical and / or processing conditions. For example, the material may exhibit an etching rate at least about five times greater than that of another material, such as about ten times, about twenty times, or about forty times greater. Those skilled in the art can select the etching chemicals and etching conditions used to selectively etch the desired material.

[0039] As used herein, the term “sacrifice” in relation to the use of a material or structure means and includes a material, structure, or part of a material or structure that is formed during the manufacturing process but removed (e.g., substantially removed) before the completion of the manufacturing process.

[0040] As used herein, the phrase “coupled to” refers to structures that are operatively connected to each other, such as by direct resistive connection or by indirect connection (e.g., via another structure).

[0041] Figures 1A to 1K A method for forming an electronic device (e.g., a memory device, such as a 3D NAND flash memory device) according to embodiments of the present disclosure is described, wherein Figure 1H yes Figure 1G The magnified portion and Figure 1I yes Figure 1G A simplified top view of a portion of the map. (Reference) Figure 1A The electronic device 100 may be configured to include a stacked structure 101 comprising a vertical (e.g., along the Z direction) alternating sequence of insulating structures 104 and additional insulating structures 106 arranged as layers 102. Each layer 102 may include at least one of the insulating structures 104 that is vertically adjacent to at least one of the additional insulating structures 106.

[0042] The number (e.g., quantity) of layers 102 in the stacked structure 101 ranges from about 32 layers 102 to about 256 layers 102. In some embodiments, the stacked structure 101 includes about 128 layers 102. However, this disclosure is not limited thereto, and the stacked structure 101 may include a different number of layers 102. The stacked structure 101 may include at least one (e.g., one, two, or more than two) stacked structures vertically superimposed on the source structure 108. For example, the stacked structure 101 may include a single-stacked structure or a double-stacked structure of a 3D memory device (e.g., a 3D NAND flash memory device).

[0043] The insulating structure 104 may be formed of, for example, at least one dielectric material and may contain at least one dielectric material, such as at least one dielectric oxide material (e.g., SiO2).x Phosphorosilicate glass, borosilicate glass, borosilicate-phosphorosilicate glass, fluorosilicate glass, AlO x HfO x NbO x TiO x ZrO x TaO x and MgO x (one or more of them). In some embodiments, the insulating structure 104 is formed of SiO2 and contains SiO2.

[0044] The additional insulating structure 106 may be formed of and comprise an insulating material that is different from and exhibits etch selectivity relative to the insulating structure 104. The additional insulating structure 106 may be made of at least one dielectric nitride material (e.g., SiN). y ) or at least one nitrogen oxide material (e.g., SiO2) x N y It forms and includes the at least one dielectric nitride material or the at least one oxynitride material. In some embodiments, the additional insulating structure 106 includes Si3N4.

[0045] The stacked structure 101 may be formed on or above the source structure 108 (e.g., a source plate). The source structure 108 may be formed of and contain a conductive material, such as a semiconductor material (e.g., polycrystalline silicon) doped with at least one P-type dopant (e.g., one or more of boron, aluminum, and gallium) or at least one N-type dopant (e.g., arsenic, phosphorus, and antimony).

[0046] Continue to refer to Figure 1AThe pillars 110 of the material may be formed to extend vertically (e.g., along the Z direction) through the stacked structure 101. The material of the pillars 110 may be used to form memory cells of the memory device after subsequent processing of the electronic device. Each pillar 110 may include an insulating material 112, a channel material 114 horizontally adjacent to the insulating material 112, a tunneling dielectric material (also referred to as "tunneling dielectric") 116 horizontally adjacent to the channel material 114, a memory material 118 horizontally adjacent to the tunneling dielectric material 116, and a dielectric barrier material (also referred to as "charge barrier material") 120 horizontally adjacent to the memory material 118. The dielectric barrier material 120 may be horizontally adjacent to a layer in an additional insulating structure 106 of a layer 102 of the stacked structure 101. The channel material 114 can be horizontally inserted between the insulating material 112 and the tunnel dielectric material 116, the tunnel dielectric material 116 can be horizontally inserted between the channel material 114 and the memory material 118, the memory material 118 can be horizontally inserted between the tunnel dielectric material 116 and the dielectric barrier material 120, and the dielectric barrier material 120 can be horizontally inserted between the memory material 118 and the layers of the additional insulating structure 106.

[0047] The insulating material 112 may be formed of and contain at least one insulating material. In some embodiments, the insulating material 112 is formed of and contains a dielectric oxide material, such as SiO2. In additional embodiments, the insulating material 112 includes an air gap.

[0048] The channel material 114 may be formed from and comprise one or more of at least one semiconductor material (at least one elemental semiconductor material, such as polycrystalline silicon; at least one III-V synthetic semiconductor material, at least one II-VI synthetic semiconductor material, at least one organic semiconductor material, GaAs, InP, GaP, GaN, other semiconductor materials) and at least one oxide semiconductor material. The channel material 114 may comprise amorphous silicon or polycrystalline silicon. The channel material 114 may comprise doped semiconductor material.

[0049] The tunnel dielectric material 116 may be formed of and contain a dielectric material through which charge tunneling can be performed under suitable electrical bias conditions, for example, by hot carrier injection or by Fowler-Nordheim tunneling-induced charge transfer. By way of non-limiting examples, the tunnel dielectric material 116 may be formed of and contain one or more of dielectric oxide materials, dielectric nitride materials, and dielectric oxide nitride materials. In some embodiments, the tunnel dielectric material 116 comprises SiO2. In other embodiments, the tunnel dielectric material 116 comprises SiO2. x N y .

[0050] Memory material 118 may include charge-trapping materials or conductive materials. By way of non-limiting examples, memory material 118 may be formed of and include one or more of the following: silicon nitride, silicon oxynitride, polycrystalline silicon (doped polycrystalline silicon), conductive materials (e.g., tungsten, molybdenum, tantalum, titanium, platinum, ruthenium and alloys thereof, or metal silicides such as tungsten silicide, molybdenum silicide, tantalum silicide, titanium silicide, nickel silicide, cobalt silicide or combinations thereof), and semiconducting materials (e.g., polycrystalline semiconducting materials, amorphous semiconductor materials). In some embodiments, memory material 118 includes Si3N4.

[0051] The dielectric barrier material 120 may be formed of and contain a dielectric material, such as a dielectric oxide (e.g., SiO2). x ), dielectric nitrides (e.g., SiN) y ) and dielectric oxide nitrides (e.g., SiO2) x N y One or more of the dielectric materials, or another dielectric material. In some embodiments, the dielectric barrier material 120 includes SiO2. x N y .

[0052] The tunnel dielectric 116, memory material 118, and dielectric barrier material 120 together may include a structure configured to trap charge, such as an oxide-nitride-oxide (ONO) structure. In some such embodiments, the tunnel dielectric 116 comprises SiO2, the memory material 118 comprises Si3N4, and the dielectric barrier material 120 comprises SiO2.

[0053] refer to Figure 1B The slot 122, also referred to as a "slit" or "replacement gate slot," can be formed through the stacked structure 101. In some embodiments, the slot 122 can be formed to extend vertically completely through the stacked structure 101 and expose a portion of the source structure 108. The slot 122 can be formed, for example, by exposing the electronic device structure 100 to one or more etchants to remove portions of the insulating structure 104 and the additional insulating structure 106 of the stacked structure 101. The slot 122 can divide the electronic device structure 100 into separate blocks, such as a first block 124 and a second block 126. Figure 1B As shown, the first block 124 and the second block 126 may each contain multiple (e.g., many, more than one) pillars 110.

[0054] refer to Figure 1C After the slot 122 is formed, the additional insulating structure 106 of the stacked structure 101 can be at least partially (e.g., substantially) removed by means of the slot 122 through a so-called "gate replacement" or "gate persistence" process. Figure 1BBy way of non-limiting examples, the additional insulating structure 106 can be at least partially removed by exposing it to at least one wet etchant, including phosphoric acid, sulfuric acid, hydrochloric acid, nitric acid, or another etching chemical. The additional insulating structure 106 can also be at least partially removed by exposing it to a so-called "wet nitride strip," including phosphoric acid.

[0055] The dielectric barrier material 130 (e.g., a high-k dielectric material) may optionally be configured to be adjacent (e.g., immediately adjacent) to the dielectric barrier material 120 and to the insulating structure 104 within the cell opening 128, such as... Figure 1C As described herein, the dielectric barrier material 130 can be formed conformally using conventional techniques. The dielectric barrier material 130 comprises aluminum oxide. Alternatively, the dielectric barrier material 130 is formed from hafnium-doped silicon dioxide, wherein the hafnium to silicon ratio is adjusted to achieve the desired etch selectivity of the dielectric barrier material 130. The dielectric barrier material 130 can be selected to exhibit high etch selectivity relative to the insulating material of the insulating structure 104 of layer 102.

[0056] The conductive liner material 132 may be formed adjacent (e.g., immediately adjacent) to the dielectric barrier material 130 (if present) within the cell opening 128. The conductive liner material 132 may be formed of and contain a seed material, from which the subsequently formed conductive material of the conductive layer may be formed, as described in more detail below. The conductive liner material 132 may be formed of and contain, for example, a metal (e.g., titanium, tantalum), a metal nitride (e.g., tungsten nitride, titanium nitride, tantalum nitride), or another conductive material. In some embodiments, the conductive liner material 132 comprises titanium nitride. In other embodiments, the dielectric barrier material 130 is adjacent to the subsequently formed conductive structure (see...). Figure 1C The insulating structure 104 is in direct contact with the electronic device 100, and the electronic device 100 is substantially (e.g., completely) free of conductive liner material 132 between the dielectric barrier material 130 and the conductive structure. In other words, each of the layers 102 may be free of conductive liner material 132 between the insulating structure 104 and the conductive structure. In an additional embodiment, the cell opening 128 is free of dielectric barrier material 130, and the conductive liner material 132 is adjacent (e.g., immediately adjacent) to the insulating structure 104 and the conductive structure. For convenience, dielectric barrier material 130 is not shown in subsequent views of the drawings; however, it should be understood that the electronic device 100 may include one or both of dielectric barrier material 130 and conductive liner material 132.

[0057] like Figure 1CAs shown, the end region 128a of the cell opening 128 may be located near the slot 122, and the central region 128b of the cell opening 128 may be located on the far side of the slot 122 (e.g., between horizontally adjacent supports 110). Therefore, portions of one or more of the dielectric barrier material 130 and the conductive liner material 132 may be located between the supports 110 and the slot 122, and additional portions of the dielectric barrier material 130 and the conductive liner material 132 may be located between horizontally adjacent supports 110.

[0058] refer to Figure 1D After removing the additional insulation structure 106 ( Figure 1B Then, a dielectric barrier material 130 is formed within the unit opening 128. Figure 1C After one or more of the conductive lining materials 132, a first conductive material 134 may be formed between vertically adjacent insulating structures 104 at an orientation corresponding to the previous orientation of the additional insulating structure 106. The first conductive material 134 may be formed of and contain any conductive material, including, but not limited to, n-doped polysilicon, p-doped polysilicon, undoped polysilicon, or metal. In some embodiments, the first conductive material 134 is n-doped polysilicon. In other embodiments, the first conductive material 134 is tungsten. In additional embodiments, the first conductive material 134 is formed of and contains one or more of titanium, ruthenium, aluminum, and molybdenum.

[0059] The first conductive material 134 may be formed adjacent (e.g., vertically adjacent, horizontally adjacent) to one or more of the dielectric barrier material 130 and conductive liner material 132 within the cell opening 128 and a portion of the slot 122. The first conductive material 134 may be formed using one or more conformal deposition or growth techniques (e.g., one or more of conventional ALD processes, conventional conformal CVD processes, and conventional in-situ growth processes). Because the first conductive material 134 is formed conformally, a portion of the cell opening 128 within the stacked structure 101 may remain substantially free of the first conductive material 134. Therefore, the first conductive material 134 is formed in the cell opening 128 and does not completely fill the cell opening 128 of the stacked structure 101. The first conductive material 134 may be formed adjacent (e.g., immediately adjacent) to the exposed surfaces (e.g., upper surface, lower surface, side surface, if present) of the conductive liner material 132. Alternatively, the first conductive material 134 may be formed adjacent (e.g., immediately adjacent) to the exposed surfaces of the insulating structure 104.

[0060] For example, a portion of the first conductive material 134 near the slot 122 can be selectively removed by etching to cause the first conductive material 134 to be recessed from the surface of the slot 122 within the defining cell opening 128, forming a recessed portion 135. In other words, the central portion of the first conductive material 134 within the cell opening 128 is recessed to form the recessed portion 135, and an additional portion of the first conductive material 134 exists within the perimeter of the cell opening 128 (e.g., adjacent to the conductive liner material 132). Since the end region 128a of the cell opening 128 is located near the slot 122, the end region 135a of the recessed portion 135 of the first conductive material 134 is located near the slot 122 at the orientation corresponding to the end region 128a. Furthermore, since the central region 128b of the unit opening 128 is located on the far side of the slot 122 and between the horizontally adjacent supports 110, the central region 135b of the recessed portion 135 is located on the far side of the slot 122 and between the horizontally adjacent supports 110, corresponding to the orientation of the central region 128b. Therefore, the end region 128a of the unit opening 128 is defined by the first conductive material 134 on three sides in the orientation near the slot 122, and the central region 128b of the unit opening 128 is defined by the first conductive material 134 on four sides in the orientation on the far side of the slot 122 and between the horizontally adjacent supports 110, as shown. Figure 1D As shown in the diagram. In other words, the end region 128a of the unit opening 128 is laterally defined on one side by the strut 110 and exposed to the slot 122 at the opposite side boundary, while the central region 128b of the unit opening 128 is laterally defined on both sides by the strut 110.

[0061] refer to Figure 1E The filler material 136 can be formed within the remaining portion (e.g., the central portion) of the unit opening 128. Figure 1D The exposed surface of the first conductive material 134 within the portion of the slot 122 is adjacent (e.g., adjacent to). The filler material 136 may substantially completely fill the recessed portion 135 of the cell opening 128 containing the first conductive material 134. Figure 1D The remaining portion of the filler material 136 extends substantially entirely between the exposed surfaces (e.g., upper, lower, and side surfaces) of the first conductive material 134. For example, the filler material 136 may be a non-conductive material, a semiconductor material, or a conductive material with a composition different from the first conductive material 134. Thus, the end portion 136a of the filler material 136 is substantially surrounded by the first conductive material 134 on three sides in an orientation near the slot 122, and the central portion 136b of the filler material 136 is substantially surrounded by the first conductive material 134 on four sides in an orientation distal to the slot 122 and between horizontally adjacent supports 110, as shown. Figure 1EAs shown in the diagram, the portion of the filler material 136 near the slot 122 (e.g., the end portion 136a) is sacrificial and subsequently removed, as shown in the reference. Figure 1F More detailed description. The filler material 136 may have a different material composition than the first conductive material 134 and may be selectively etchable relative to the first conductive material 134.

[0062] The filler material 136 can be formed using one or more conformal deposition processes (e.g., one or more conventional conformal CVD processes or conventional ALD processes). By conformally forming the filler material 136, voids in the layer 102 can be significantly reduced (e.g., minimized) during the formation of the conductive material of the stacked structure 101. Alternatively, the filler material 136 can be formed using one or more conventional non-conformal deposition processes (e.g., conventional PVD processes (e.g., conventional radio frequency PVD (RFPVD) processes) or one or more conventional non-conformal CVD processes). In some cases, the filler material 136 can be formed from and contain a non-reactive conductive material, for example, formed using a non-reactive PVD process in a non-reactive environment.

[0063] The filler material 136 may be formed of and comprise a non-conductive material (e.g., a dielectric material), such as an oxide (e.g., silicon dioxide (SiO2)), a nitride (e.g., silicon nitride (SiN)), or an oxide oxynitride. The filler material 136 may comprise a high-quality silicon oxide material, such as ALD SiO2. x For example, the filler material 136 may be a highly uniform and conformal silicon oxide material (e.g., a highly uniform and conformal silicon dioxide material) such that there are essentially no voids in the cell opening 128. Specifically, the filler material 136 may be formulated to form in high aspect ratio (HAR) openings without forming voids, such as those having a HAR of at least about 20:1, at least about 50:1, at least about 100:1, or at least about 1000:1. The filler material 136 may alternatively be formed from and comprise one or more of the following: silicon oxycarbonate (SiO₂) x C y ), silicon oxynitride (SiO) x N y ), hydrogenated carbon silicon oxide (SiC) x O y H z ) and silicon dioxide (SiO2) x C y N z The filler material 136 may comprise silicon oxide (SiO2) having a lower content than silicon nitride (Si3N4) material. xLow-k dielectric materials, such as dielectric nitride materials or dielectric oxide materials, are materials containing silicon atoms, carbon atoms, oxygen atoms and hydrogen atoms, or carbon-doped silicon oxide materials.

[0064] Filler material 136 may alternatively be formed of and comprise a conductive (e.g., metallic) material. For example, filler material 136 may be formed of and comprise a metallic material (e.g., conductive metal nitride, conductive metal silicide, conductive metal carbide, conductive metal oxide). In some embodiments, filler material 136 comprises titanium nitride. Filler material 136 may comprise a conductive material that is substantially free of (e.g., substantially absent) tungsten. Filler material 136 may also be substantially free of (e.g., substantially absent) halogens or halogen-containing compounds, such as those from halogen-containing precursors (e.g., fluorine-containing precursors) used in the formation of tungsten. For example, filler material 136 may be free of halogen-containing compounds by forming a conductive structure from a halogen-free precursor. Filler material 136 may alternatively be formed of a so-called "low-halogen" material comprising a minimum amount of halogen-containing precursor. In other embodiments, the filler material 136 may be formed of and comprise a semiconductor material, such as one or more of silicon, germanium, germanium, and polycrystalline silicon (also referred to as "polysilicon"). For example, the filler material 136 may be n-doped polycrystalline silicon, p-doped polycrystalline silicon, or undoped polycrystalline silicon. The filler material 136 may also serve as a barrier material comprising a material composition different from that of the first conductive material 134 and exhibiting etch selectivity relative to the first conductive material 134. Therefore, the chemical composition of the filler material 136 may differ from that of the first conductive material 134, thereby providing etch selectivity between the filler material 136 and the first conductive material 134.

[0065] The filler material 136 may be formed by custom-designed conductive structures that can be formed in the stacked structure 101 (see [link]). Figure 1GThe material composition that forms and contains the voids (e.g., minimizes them) that occur in layer 102 during the formation of the filler material 136. Therefore, the material composition of the filler material 136 can be selected to improve the properties when forming (e.g., depositing, growing) such a material. The filler material 136 may contain a material compatible with (e.g., non-reactive) the first conductive material 134. The filler material 136 may also be formulated to reduce the migration (e.g., diffusion) of reactive species from the surrounding conductive material (e.g., the first conductive material 134). The filler material 136 may contain a single material or, alternatively, multiple materials (e.g., two or more) having dissimilar boundaries therebetween. For example, the formation of the filler material 136 may involve forming a first portion (e.g., a liner) adjacent to (e.g., directly on) the first conductive material 134, having a first material composition, followed by forming a second portion adjacent to (e.g., directly on) the first portion, having a second material composition.

[0066] refer to Figure 1F For example, a portion of the filler material 136 can be selectively removed by etching to cause the filler material 136 to be recessed from the surface defining the slot 122. For instance, the filler material 136 can be removed from the end region 128a of the cell opening 128, which includes the end region 135a of the recessed portion 135 of the first conductive material 134. A portion of the filler material 136 can be selectively removed by exposing the filler material 136 through the slot 122 to one or more wet etchants. For example, the end portion 136a of the filler material 136 located near the slot 122 can be substantially removed from the end region 128a of the cell opening 128. Figure 1E And without significantly removing a portion of the first conductive material 134. Additionally, the central portion 136b of the filler material 136 may remain in the central region 128b of the cell opening 128, oriented distal to the slot 122 and between horizontally adjacent supports 110. In other words, the end region 128a of the cell opening 128 may be substantially free of (e.g., substantially absent, substantially none) the filler material 136, while the central region 128b of the cell opening 128 may contain the remaining portion of the filler material 136 (e.g., the central portion 136b). Therefore, the central portion 136b of the filler material 136 may be substantially surrounded by the first conductive material 134 in an orientation distal to the slot 122 and between horizontally adjacent supports 110, such as... Figure 1F As shown in the image.

[0067] refer to Figure 1G The second conductive material 138 can be in the unit opening 128 ( Figure 1F The terminal region 128a ( Figure 1FThe second conductive material 138 is formed within the slot 122, near and within a portion of the slot 122, adjacent to (e.g., immediately adjacent to) the exposed surface of the first conductive material 134. The second conductive material 138 can substantially completely fill the remaining portion of the end region 128a of the unit opening 128 (including the recessed portion 135 of the first conductive material 134). Figure 1F The terminal region 135a ( Figure 1F So that it extends substantially entirely between the exposed upper and lower surfaces of the first conductive material 134. In other words, the second conductive material 138 may be formed to fill the end portion 136a where the filler material 136 has been removed. Figure 1E The remaining portion of the end region 128a of the empty unit opening 128 after the sacrificial portion of the unit opening 128.

[0068] The second conductive material 138 may be formed of and contain any conductive material, including but not limited to n-doped polysilicon, p-doped polysilicon, undoped polysilicon, or metal. In some embodiments, the second conductive material 138 is n-doped polysilicon. In other embodiments, the second conductive material 138 is tungsten. In additional embodiments, the second conductive material 138 is formed of and contains one or more of titanium, ruthenium, aluminum, and molybdenum. The first conductive material 134 and the second conductive material 138 may contain substantially the same material composition and have no easily identifiable physical interface therebetween. Alternatively, the first conductive material 134 and the second conductive material 138 may contain different material compositions from each other. In addition, the material composition of the second conductive material 138 may differ from the material composition of the filler material 136 between horizontally adjacent pillars 110.

[0069] The second conductive material 138 can be formed using one or more conventional non-conformal deposition processes (e.g., conventional PVD processes (e.g., conventional radio frequency PVD (RFPVD) processes) or conventional non-conformal CVD processes). Additionally, the material composition of the second conductive material 138 can be formulated to exhibit less conformality compared to the material compositions of one or more of the first conductive material 134 and the filler material 136.

[0070] like Figure 1G As shown, the formation of the second conductive material 138 causes an orientation between vertically adjacent insulating structures 104 corresponding to the previous orientation of the additional insulating structure 106. Figure 1B The conductive structure 140 is formed. Subsequently, the formation of the conductive structure 140 causes the formation of the insulating structure 104, the layer 142 of the conductive structure 140, and the string 144 of the memory cells 146 extending vertically through the stacked structure 101.

[0071] The portion of an individual conductive structure 140 of layer 142 located distal to slot 122 and between horizontally adjacent supports 110 includes filler material 136 within a central portion 141 (e.g., a vertical central portion) of the conductive structure 140. The filler material 136 may be substantially centered along the horizontal centerline of the conductive structure 140. In other words, the horizontal centerline of the filler material 136 may be substantially aligned with the horizontal centerline of the conductive structure 140, wherein the portion of the first conductive material 134 above the filler material 136 is substantially equal to the portion below the filler material 136. However, this disclosure is not limited thereto and may cover additional configurations. For example, the horizontal centerline of the filler material 136 may be positioned above or alternatively below the horizontal centerline of the conductive structure 140, such that opposing portions of the first conductive material 134 have unequal thicknesses (e.g., heights) above and below the filler material 136 within the central portion 141 of the conductive structure 140.

[0072] The filler material 136 located between horizontally adjacent supports 110 may be substantially surrounded by the first conductive material 134. For example, the filler material 136 may be adjacent (e.g., close to) the first conductive material 134 along one or more horizontal directions (e.g., X direction, Y direction) and along a vertical direction (e.g., Z direction). The first conductive material 134 of the conductive structure 140 vertically intervenes between the filler material 136 and the insulating structure 104. In addition, the second conductive material 138 may be adjacent (e.g., close to) the first conductive material 134 in the portion of the individual conductive structure 140 located near the slot 122. Thus, the filler material 136 and the second conductive material 138 are laterally adjacent and separated from the second conductive material 138 by the portion of the first conductive material 134 and the support 110. In other words, the filler material 136 and the second conductive material 138 are located at the same vertical level because the second conductive material 138 is located at the end portion 136a of the previously filled material 136 of the individual conductive structure 140. Figure 1E The sacrificial part occupies the area.

[0073] The formation of a second conductive material 138 after the formation of a first conductive material 134 and a filler material 136 results in a conductive structure 140 formed and comprising one or more conductive materials tailored to reduce (e.g., minimize) voids that may occur in the layer 142 during the formation of the conductive structure 140 within the stacked structure 101. Compared to conventional conductive structures formed using a single process action (e.g., a single deposition action of a single conductive material), the conductive structure 140, comprising the filler material 136, allows for reduced voids in the layer 142 by using two or more (e.g., three) separate process actions to form the conductive structure 140.

[0074] In additional embodiments, such as those in which the filler material 136 is formed of a conductive material different from the first conductive material 134 and contains a conductive material different from the first conductive material 134, the end portion 136a of the filler material 136 ( Figure 1E The filler material 136 may exist within the stacked structure 101 and does not form a second conductive material 138 therein. In other words, the end portion 136a of the filler material 136, combined with the first conductive material 134, completes the formation of the conductive structure 140. Compared to conventional conductive structures formed using a single process action (e.g., a single deposition action of a single conductive material), the conductive structure 140, which includes the filler material 136, also causes a reduction in voids in the layer 142 by forming the conductive structure 140 using two separate process actions.

[0075] Continue to refer to Figure 1G The conductive structure 140 can be used as a word line (e.g., a local word line) of the string 144 of the memory cell 146. Additionally, one or more (e.g., one to five) conductive structures 140 of the vertical lower layer 142 (e.g., the vertical lowest layer 142) can be used as select gate structures (e.g., select gate source (SGS) structures). Furthermore, one or more (e.g., one to five) conductive structures 140 of the vertical upper layer 142 (e.g., the vertical highest layer 142) can be used as select gate structures (e.g., select gate drain (SGD) structures).

[0076] The intersection of the conductive structure 140 and the pillar 110 can form individual memory cells 146 of a string 144 of memory cells 146. According to embodiments of this disclosure, Figure 1H illustrate Figure 1G The enlarged portion of box H illustrates memory cell 146. (See reference) Figure 1H Each memory cell 146 may include a channel material 114, a tunnel dielectric material 116 horizontally adjacent to the channel material 114, a memory material 118 horizontally adjacent to the tunnel dielectric material 116, a dielectric barrier material 120, and a conductive structure 140 horizontally adjacent to the dielectric barrier material 120, comprising a first conductive material 134 and a fill material 136. In another embodiment, the memory cell 146 includes a so-called "floating gate" memory cell, which includes a floating gate (e.g., a metal floating gate) as a charge storage structure. The floating gate may be horizontally positioned between the central structure of the pillar 110 and the conductive structure 140 of the layer 142 of the stacked structure 101.

[0077] Figure 1I Explanation of the section taken along the horizontal centerline of one of the conductive structures 140 Figure 1G A simplified top view of the electronic device 100. For clarity, in... Figure 1ICertain materials and structures (e.g., dielectric barrier material 130, conductive lining material 132) are omitted in the top view. The support 110 may comprise a generally circular (e.g., generally annular) horizontal cross-sectional region. Alternatively, the horizontal cross-sectional shape of the support 110 may have another shape (e.g., non-curved, non-circular, non-annular). Figure 1I Best shown in the top view, the dielectric barrier material 120 is horizontally adjacent to the first conductive material 134 and the insulating structure 104 of the stacked structure 101. Figure 1G The memory material 118 is horizontally adjacent to the dielectric barrier material 120, and the tunnel dielectric material 116 is horizontally adjacent to the memory material 118. The channel material 114 may be horizontally adjacent to the tunnel dielectric material 116, and the insulating material 112 may be horizontally adjacent to the channel material 114 and generally surrounded by the channel material 114.

[0078] refer to Figure 1G and combined Figure 1I The first conductive material 134 may substantially surround (e.g., substantially continuously surround) the dielectric barrier material 120 of the individual pillars 110, and the filler material 136 may be in direct physical contact with the first conductive material 134 and substantially surround (e.g., substantially continuously surround) the first conductive material 134, such as Figure 1I As shown in the diagram. Therefore, the filler material 136 may substantially surround at least some of the supports 110 along at least one horizontal direction (e.g., the X direction, the Y direction). For example, the supports 110 located within the central portions of the first block 124 and the second block 126 and distal to the slot 122 may be substantially surrounded by the filler material 136, while the supports 110 closest to (e.g., closest to) the slot 122 may be partially surrounded by the filler material 136. In additional embodiments, such as those in which the filler material 136 comprises a conductive material different from the first conductive material 134, the end portions 136a of the filler material 136 may not be removed from the stack structure 101, and the supports 110 near the slot 122 may also be substantially surrounded by the filler material 136.

[0079] refer to Figure 1J After the dielectric conductive structure 140 is formed, a portion of the conductive structure 140, the conductive liner material 132, and the dielectric barrier material 130 (if present) may optionally be removed from the surface defining the slot 122 to form a recessed portion 148 of the conductive structure 140, thereby electrically isolating adjacent conductive structures 140 from each other. In other words, the removal of portions of the conductive material (e.g., the first conductive material 134 and the second conductive material 138), the conductive liner material 132, and the dielectric barrier material 130 of the conductive structure 140 can physically electrically isolate the conductive structures 140 from each other.

[0080] The conductive lining material 132 and the conductive material of the conductive structure 140 can be removed by exposing them to one or more wet etchants through slot 122. The wet etchant may contain one or more of phosphoric acid, acetic acid, nitric acid, hydrochloric acid, aqua regia, or hydrogen peroxide. However, this disclosure is not limited thereto, and the conductive lining material 132 and the conductive material of the conductive structure 140 may be removed using other etchants and / or material removal processes (e.g., vapor phase removal processes, atomic layer removal processes). Alternatively, the conductive lining material 132 may be removed by exposure to one or more dry etchants (e.g., one or more chlorine-containing dry etchants). By way of non-limiting examples, the one or more dry etchants may contain one or more of chlorine, boron trichloride (BCL3), oxygen, and argon. In some embodiments, the conductive lining material 132 is removed by exposure to a dry etchant comprising chlorine and boron trichloride.

[0081] The outermost portion of the insulating structure 104 may be removed during the formation of the slot 122 or during a subsequent material removal operation of the conductive structure 140 and the conductive liner material 132. The remaining amount of the insulating structure 104 may have a width W1 from a point opposite the outer sidewall 152 of the insulating structure 104. The conductive structure 140 and the conductive liner material 132 may be laterally recessed relative to the insulating structure 104 such that the outer sidewall 150 of the conductive structure 140 is closer to the corresponding pillar 110 in the pillar 110 than the outer sidewall 152 of the insulating structure 104 is closer to the pillar 110. In other words, the width W1 of the insulating structure 104 is greater than the width W2 of the conductive structure 140, as... Figure 1J As shown in the diagram, the conductive lining material 132 (if present) can therefore extend only a portion of the width W1 of the adjacent insulating structure 104.

[0082] The height H1 of the individual insulating structure 104 may be substantially the same as the height H2 of the individual conductive structure 140. Alternatively, the height H1 of the insulating structure 104 may be greater than the height H2 of the conductive structure 140. By means of a non-limiting example, each of the height H1 of the insulating structure 104 and the height H2 of the conductive structure 140 may be in the range of about 10 nanometers (nm) to about 50 nm, for example, from about 10 nm to about 20 nm, from about 20 nm to about 30 nm, from about 30 nm to about 40 nm, or from about 40 nm to about 50 nm. If present, the conductive liner material 132 may have a thickness (e.g., height) in the range of about 0.5 nm to about 5 nm, and the dielectric barrier material 130 (if present) may have a thickness similar to that of the conductive liner material 132.

[0083] The height H2 of the conductive structure 140 can be defined by the upper and lower surfaces of the outermost material (e.g., conductive liner material 132, if present) immediately adjacent to the surface of the vertically adjacent insulating structure 104. Therefore, the height H2 of the conductive structure 140 includes the combined thickness (e.g., height) of one or more of the first conductive material 134 and the filler material 136, the second conductive material 138, the dielectric barrier material 130, and the conductive liner material 132. The height H2 of the conductive structure 140 can be tailored at least in part based on the individual thickness (e.g., height) of the materials contained therein, such as the respective thicknesses of the first conductive material 134 and the filler material 136. The thickness Th1 of the first conductive material 134 can be greater than each of the thickness Th2 of the filler material 136 and the thickness Th3 of the second conductive material 138. For example, the thickness Th2 of the filler material 136 can be substantially the same as the thickness Th3 of the second conductive material 138, each of which is less than the thickness Th1 of the first conductive material 134, such as... Figure 1J As shown in the diagram. In other words, each of the thickness Th2 of the filling material 136 and the thickness Th3 of the second conductive material 138 is covered within the thickness Th1 of the first conductive material 134.

[0084] By way of non-limiting examples, the thickness Th1 of the first conductive material 134 may be in the range of about 10 nm to about 50 nm, for example, from about 10 nm to about 20 nm, from about 20 nm to about 30 nm, from about 30 nm to about 40 nm or from about 40 nm to about 50 nm, and each of the thickness Th2 of the filling material 136 and the thickness Th3 of the second conductive material 138 may be individually in the range of about 2 nm to about 20 nm, for example, from about 2 nm to about 5 nm, from about 5 nm to about 10 nm, from about 10 nm to about 15 nm or from about 15 nm to about 20 nm. Additionally, for example, the thickness of each of the upper portion (e.g., the upper half) and lower portion (e.g., the lower half) of the first conductive material 134, which is vertically aligned with the filling material 136, may individually range from about 2 nm to about 20 nm, such as from about 2 nm to about 5 nm, from about 5 nm to about 10 nm, from about 10 nm to about 15 nm, or from about 15 nm to about 20 nm.

[0085] The thickness Th1 of the first conductive material 134 may exceed the thickness Th2 of the filler material 136 and the thickness Th3 of the second conductive material 138 by an amount ranging from about 8 nm to about 30 nm. For example, the thickness Th2 of the filler material 136 may range from about 30% to about 70% of the thickness Th1 of the first conductive material 134, for example, about 50%. Therefore, the combined thickness of the upper and lower portions of the first conductive material 134, which are vertically aligned with the filler material 136, may be substantially equal to the thickness Th2 of the filler material 136. In other words, each of the first conductive material 134 and the filler material 136 may individually represent about half or, alternatively, less than half the height H2 of the conductive structure 140, regardless of the thickness of the dielectric barrier material 130 and the conductive liner material 132 (if present).

[0086] refer to Figure 1K The conductive rail 154 may optionally be configured to be at least horizontally adjacent to (e.g., at least on) the conductive structure 140 along a first horizontal direction (e.g., the X direction) and have an elongated portion extending along a second direction (e.g., the Y direction). Because portions of the conductive structure 140 and the conductive liner material 132 are removed through the slot 122, therefore... Figure 1J The resistance exhibited by the conductive structure 140 and conductive liner material 132 of layer 142 may be greater than the desired resistance. To reduce the resistance, conductive rails 154 may be formed to extend (e.g., laterally) from each exposed portion of the conductive structure 140 and the conductive liner material 132 (if present).

[0087] The conductive rail 154 may be formed of and contain at least one conductive material. In some embodiments, the conductive rail 154 is formed of and contains tungsten. The conductive rail 154 may or may not contain a material composition substantially the same as that of the conductive material of the conductive structure 140 (e.g., the first conductive material 134, the filler material 136, the second conductive material 138). The conductive rail 154 may exhibit a lower resistivity compared to the conductive structure 140. (Refer to the above text) Figure 1G As discussed, the conductive structure 140 may be formed and comprise one or more conductive materials tailored to reduce (e.g., minimize) voids that may occur in the layers 142 during the formation of the conductive structure 140 within the stacked structure 101. Since the resistivity of the structure may be at least partially based on the thickness (e.g., height) of the material used, in some cases, such as when the thickness of the conductive structure 140 decreases after the spacing of the layers 142 decreases, the conductive structure 140 may exhibit a lower resistivity compared to the conductive rail 154.

[0088] The conductive rail 154 can be formed using conventional processes. The conductive rail 154 can be formed (e.g., deposited, grown) to interact with... Figure 1J The remaining conductive structure 140 after the material removal operation is adjacent to the outer wall 150 (e.g., on the outer wall 150, directly on the outer wall 150). In embodiments where the conductive liner material 132 is present, the conductive rail 154 also extends laterally beyond the sidewall (e.g., the side end) of the conductive liner material 132.

[0089] In some embodiments (e.g.) Figure 1K In the embodiment, the conductive rail 154 is formed such that it extends laterally beyond the outer wall 152 of the insulating structure 104 without vertically overlapping it. In other words, the upper and lower surfaces of the conductive rail 154 are substantially coplanar with the upper and lower surfaces of the conductive structure 140 and / or the conductive lining material 132 and do not overlap with the outer wall 152 of the insulating structure 104. Figure 1J Adjacent. In other embodiments, the conductive rail 154 is formed to extend laterally beyond the outer wall 152 of the insulating structure 104 and vertically overlap the outer wall 152, while still providing electrical isolation between adjacent blocks (e.g., the first block 124, the second block 126). Thus, the conductive rail 154 exhibits a height H3 equal to or greater than the height H2 of the conductive structure 140 of the stacked structure 101.

[0090] Where the conductive rail 154 extends laterally beyond the insulating structure 104, the maximum width W3 defined by the outer sidewall 156 of the conductive rail 154 is greater than the maximum width W1 defined by the outer sidewall 152 of the insulating structure 104 and therefore greater than the maximum width W2 defined by the outer sidewall 150 of the conductive structure 140. As used herein, “outer” sidewalls 150, 152, 156 are sidewalls adjacent to the sidewalls of the respective blocks (e.g., first block 124, second block 126), opposite to the sidewalls of the adjacent pillars 110. Thus, the conductive rail 154 extends from the respective conductive structure 140 away from the pillars 110, such that the stacked structure 101 includes a conductive layer of layer 142, which includes a conductive rail 154 that is laterally wider than the insulating structure 104. The width W2 of the conductive structure 140 may be substantially similar to (e.g., substantially the same) the width between the outer surfaces of the outermost pillars 110 of the pillars 110. In other words, the conductive structure 140 may extend within the area laterally demarcated by the pillars 110 of the stacked structure 101 and may not extend beyond the outermost pillar 110 at each lateral end of the block (e.g., the first block 124, the second block 126). Alternatively, at least a portion of the conductive structure 140 may be interposed between the pillars 110 and the conductive rails 154 such that the pillars 110 do not have direct physical contact with the conductive rails 154.

[0091] By means of a non-limiting example, the amount by which the width W3 of the conductive layer exceeds the width W2 of the conductive structure 140 can range from about 5 nm to about 100 nm, for example, from about 5 nm to about 10 nm, from about 10 nm to about 20 nm, from about 20 nm to about 50 nm, or from about 50 nm to about 100 nm. Therefore, each conductive rail 154 may have a horizontal width in the range of about 5 nm to about 100 nm, for example, from about 5 nm to about 10 nm, from about 10 nm to about 20 nm, from about 20 nm to about 50 nm, or from about 50 nm to about 100 nm. Furthermore, the amount by which the width W3 of the conductive layer exceeds the width W1 of the insulating structure 104 can range from about 2 nm to about 50 nm, for example, from about 2 nm to about 5 nm, from about 5 nm to about 10 nm, from about 10 nm to about 20 nm, or from about 20 nm to about 50 nm.

[0092] Individual conductive rails 154 are spaced apart (e.g., spaced apart) from adjacent conductive rails 154 (e.g., conductive rails 154 above and / or below) by a spacing distance sufficient to electrically isolate each conductive rail 154 coupled to each conductive structure 140 of another layer 142 vertically adjacent to the individual layer 142. By means of non-limiting examples, the distance between adjacent pairs of conductive rails 154 can be in the range of about 2 nm to about 50 nm, for example, from about 2 nm to about 5 nm, from about 5 nm to about 10 nm, from about 10 nm to about 20 nm, from about 20 nm to about 30 nm, from about 30 nm to about 40 nm, or from about 40 nm to about 50 nm.

[0093] like Figure 1K As shown, the height H3 of the individual conductive rail 154 is substantially the same as the height H2 of the individual conductive structure 140. In other words, the lower surface of the conductive rail 154 may be substantially coplanar with the lower surface of the conductive structure 140, and the upper surface of the conductive rail 154 may be substantially coplanar with the upper surface of the conductive structure 140. In other embodiments, the height H3 of the conductive rail 154 is relatively larger than the height H2 of the conductive structure 140 (not shown). As used herein, the “non-track remainder” of an individual layer 142 means the portion of layer 142 located outside the boundary of the conductive rail 154 coupled to the conductive structure 140 of layer 142. The non-track remainder of an individual layer 142 includes the conductive structure 140 and the conductive liner material 132 (if present). Figure 1KIn the electronic device 100, and in other embodiments of this disclosure, the upper and lower surfaces of the non-track remainder of individual layers 142 may be defined by the conductive structure 140 in a layer 142 that contains only the conductive structure 140, or by the conductive lining material 132 in a layer 142 that contains both the conductive structure 140 and the conductive lining material 132.

[0094] By way of non-limiting examples, the height H3 of the conductive rail 154 can be in the range of about 10 nm to about 100 nm, for example, from about 10 nm to about 20 nm, from about 20 nm to about 30 nm, from about 30 nm to about 40 nm, from about 40 nm to about 50 nm, or from about 50 nm to about 100 nm. For example, the height H2 of an individual conductive rail 154 can be larger than the height H1 of an individual conductive structure 140 by from about 1% to about 250% (e.g., from about 10% to about 250%, from about 25% to about 125%, from about 50% to about 100%).

[0095] After the conductive rail 154 (if present) is formed, the slot 122 ( Figure 1J The remaining (e.g., unfilled) portion of the insulating structure 108 may be substantially filled with an additional filler material 160 (e.g., dielectric material). The additional filler material 160 may extend through the stacked structure 101 and be adjacent to (e.g., directly on) the exposed upper surface of the source structure 108. Additionally, the additional filler material 160 may be located between adjacent blocks (e.g., the first block 124 and the second block 126) corresponding to the orientation of the slot 122. Because the width W3 of the conductive rail 154 is greater than the width W1 of the insulating structure 104... Figure 1J Therefore, the lateral dimension (e.g., width) of the additional filler material 160 adjacent to the lateral side of the insulating structure 104 is larger than the lateral dimension of the additional filler material 160 adjacent to the lateral side of the conductive rail 154. The additional filler material 160 may be formed of and contain at least one insulating material (e.g., dielectric material). The additional filler material 160 may have substantially the same material composition as the insulating structure 104.

[0096] As described above, forming the stacked structure 101 containing conductive structures 140 of electronic device 100 using two or more (e.g., three) separate process actions can help improve the performance of electronic device 100. For example, the presence of filler material 136 in the central portion 141 of conductive structure 140 effectively reduces the presence of voids in the conductive material present in the conductive layer of layer 142 compared to conductive layers that do not have filler material (e.g., non-conductive material, different conductive material) in the central portion of individual conductive structures. Therefore, conductive structures can be formed without increasing the horizontal area occupied by layers 142 or blocks (e.g., first block 124, second block 126). In addition, the presence of filler material 136 adjacent to the first conductive material 134 can provide a reduction in the resistivity (e.g., resistance level) of the conductive material in each respective layer 142. Therefore, the resistance exhibited by the conductive material can be less than the resistance of the conductive material in the conventional conductive layer of a 3D NAND structure. Lower resistance can be achieved without increasing the spacing or critical dimension (CD) of the pillars 110. Therefore, resistivity reduction can still be achieved even when the spacing or CD of the pillars 110 continues to be scaled down to a smaller value and the thickness of the conductive layer of layer 142 (e.g., the height along the Z direction) continues to decrease.

[0097] Additionally, the material composition of filler material 136 can be selected to improve properties during use and operation of the electronic device 100 (e.g., reduced resistivity). Reduced resistivity of the conductive material of layer 142 can improve the performance of the string 144 of memory cells 146. In some cases, filler material 136 can provide structural support for conductive structures 140 and thus for stacked structures 101. Furthermore, filler material 136 can be formulated to reduce the migration (e.g., diffusion) of reactive species from the conductive material of conductive structures 140. Since filler material 136 can be formed within the central portion 141 of conductive structures 140, filler material 136 can limit capacitance (e.g., parasitic capacitance, stray capacitance) between vertically adjacent conductive structures 140 of layer 142 and increase short-circuit margin without significantly affecting resistance. Therefore, filler material 136 can be formulated to significantly reduce capacitance between vertically adjacent conductive structures 140 and reduce crosstalk between them during use and operation of the electronic device 100. In some cases, reduced capacitance can consequently provide reduced programming time.

[0098] Electronic devices formed according to the embodiments described herein can exhibit improved performance by reducing the void occurrence rate during the formation of conductive material of conductive structure 140 within the conductive layer of layer 142. Furthermore, resistivity reduction and thus conductivity increase can be achieved by providing additional conductive material (e.g., conductive rails 154) extending beyond the boundary of insulating structure 104 to provide an increase in the cross-sectional area of ​​the conductive material within individual layers 142. Additional performance improvements can be achieved by including filler material 136 within the conductive structure 140 of its central portion 141, a configuration that exhibits performance improvements compared to conventional electronic devices. By comparison, the manufacture of conventional electronic devices may involve forming conductive layers of a single conductive material (e.g., in a single deposition operation), and the central portion of individual conductive structures may not contain filler material (e.g., non-conductive material, different conductive materials).

[0099] Therefore, according to some embodiments of this disclosure, a method of forming an electronic device includes forming a stacked structure comprising vertically alternating insulating structures and additional insulating structures, and forming pillars comprising a channel material extending vertically through the stacked structure and at least one dielectric material. The method includes removing the additional insulating structures to form a cell opening; forming a first conductive material within a portion of the cell opening; and forming a fill material adjacent to the first conductive material within the cell opening. The fill material includes a sacrificial portion. The method includes removing the sacrificial portion of the fill material and forming a second conductive material within the cell opening in the orientation previously occupied by the sacrificial portion of the fill material.

[0100] Furthermore, according to another embodiment of this disclosure, an electronic device includes: a stacked structure comprising layers of alternating conductive and insulating structures; and pillars extending vertically through the stacked structure; and a filler material located within the central portion of individual conductive structures of the stacked structure. The filler material is positioned between adjacent pillars and is substantially surrounded by the conductive material of the individual conductive structures.

[0101] Figure 2 This is a partial cross-sectional perspective view illustrating a portion of an electronic device 200 (e.g., a microelectronic device, a memory device, such as a 3D NAND flash memory device) that includes one or more electronic device structures 201 (e.g., a microelectronic device structure). The electronic device 200 may be substantially similar to previously referenced... Figures 1A to 1K One of the described electronic devices 100. For example... Figure 2 As shown, the electronic device structure 201 of the electronic device 200 may include defining a structure for connecting the interconnect 206 to the conductive structure 205 (e.g., corresponding to the conductive structure 140). Figure 1GThe stepped structure 220 of the contact area. The electronic device structure 201 may include memory cells 203 coupled in series with each other (e.g., corresponding to memory cell 146). Figure 1G The vertical string 207 (e.g., string 144) Figure 1G The vertical string 207 may be vertical (e.g., along the Z direction) orthogonal to the conductive lines and conductive structures 205 (e.g., data lines 202, source layer 204 (e.g., containing source structure 108)). Figure 1G Interconnect 206, first select gate 208 (e.g., upper select gate, drain select gate (SGD)), select line 209, and second select gate 210 (e.g., lower select gate, source select gate (SGS)) extend horizontally (e.g., along the Y direction) through slot 230 (e.g., formed in slot 122). Figure 1J ) extra filler material 160 ( Figure 1K Multiple blocks 232 (e.g., blocks 124, 126) that are horizontally (e.g., along the Y direction) separated from each other. Figure 1G )).

[0102] Vertical conductive contacts 211 can electrically couple components to each other, as shown. For example, select line 209 can be electrically coupled to first select gate 208, and interconnect 206 can be electrically coupled to conductive structure 205. Electronic device 200 may also include a control unit 212 positioned below the memory array. The control unit 212 may include at least one of a string driver circuitry, a gate, a circuitry for selecting gates, a circuitry for selecting conductive lines (e.g., data line 202, interconnect 206), a circuitry for amplifying signals, and a circuitry for sensing signals. For example, control unit 212 may be electrically coupled to data line 202, source layer 204, interconnect 206, first select gate 208, and second select gate 210. In some embodiments, control unit 212 includes complementary metal-oxide-semiconductor (CMOS) circuitry. In such embodiments, control unit 212 may be characterized by having an "under-array CMOS" ("CuA") configuration.

[0103] The first select gate 208 may extend horizontally along a first direction (e.g., the X direction) and may be coupled at a first end (e.g., the upper end) of the vertical string 207 to a corresponding first group of vertical strings 207 of the memory cell 203. The second select gate 210 may be formed in a substantially flat configuration and may be coupled at a second opposite end (e.g., the lower end) of the vertical string 207 of the memory cell 203 to the vertical string 207.

[0104] Data lines 202 (e.g., digital lines, bit lines) may extend horizontally in a second direction (e.g., in the Y direction) at an angle (e.g., perpendicular) to a first direction in which the first select gate 208 extends. Individual data lines 202 may be coupled at a first end (e.g., the top end) of a vertical string 207 of an individual group to an individual group of vertical strings 207 extending in the second direction (e.g., the Y direction). Additional individual groups of vertical strings 207 extending in the first direction (e.g., the X direction) and coupled to individual first select gates 208 may share their specific vertical strings 207 with the individual groups of vertical strings 207 coupled to individual data lines 202. Thus, individual vertical strings 207 of memory cells 203 may be selected at the intersection of individual first select gates 208 and individual data lines 202. Therefore, the first select gate 208 may be used to select memory cells 203 of vertical strings 207 of memory cells 203.

[0105] Conductive structures 205 (e.g., word lines) may extend in a corresponding horizontal plane. The conductive structures 205 may be vertically stacked such that each conductive structure 205 is coupled to at least some of the vertical strings 207 of the memory cells 203, and the vertical strings 207 of the memory cells 203 extend vertically through the stacked structure containing the conductive structures 205. The conductive structures 205 may be coupled to or may form the control gate of the memory cells 203.

[0106] The first selection gate 208 and the second selection gate 210 can be used to select a vertical string 207 of memory cells 203 inserted between the data line 202 and the source layer 204. Thus, a single memory cell 203 can be selected and electrically coupled to the data line 202 by operating (e.g., by selecting) the first selection gate 208, the second selection gate 210, and the conductive structure 205 appropriately coupled to a particular memory cell 203.

[0107] The stepped structure 220 can be configured to provide an electrical connection between the interconnect 206 and the conductive structure 205 via vertical conductive contacts 211. In other words, individual conductive structures 205 can be selected via interconnects 206 electrically connected to corresponding vertical conductive contacts 211, which are electrically connected to the conductive structure 205.

[0108] Data line 202 can be connected via conductive contact structure 234 (e.g., formed on pillar 110). Figure 1A The contact structure above is electrically coupled to the vertical string 207.

[0109] Therefore, according to an additional embodiment of this disclosure, a memory device includes a stacked structure comprising alternating conductive and insulating structures arranged in layers. Each layer individually includes a conductive structure and an insulating structure. The memory device includes a barrier material that separates opposing portions of the conductive materials of the conductive structures; and a string of memory cells extending vertically through the stacked structure. The string of memory cells includes a channel material extending vertically through the stacked structure. The memory device includes conductive rails laterally adjacent to the conductive structures of the stacked structure. Individual conductive rails are horizontally aligned with the barrier material and conductive material of the corresponding conductive structure.

[0110] Electronic devices according to embodiments of the present disclosure may be used in embodiments of the electronic systems disclosed herein, including electronic devices (e.g., electronic devices 100, 200) that contain a filling material 136 within the central portion 141 of an individual conductive structure 140. For example, Figure 3 This is a block diagram of an electronic system 303 according to an embodiment of the present disclosure. The electronic system 303 may include, for example, a computer or computer hardware component, a server or other network-connected hardware component, a cellular phone, a digital camera, a personal digital assistant (PDA), a portable media (e.g., music) player, Wi-Fi, or a cellular-enabled tablet computer (e.g.,...). or Tablet computers, e-books, navigation devices, etc. Electronic system 303 includes at least one memory device 305. Memory device 305 may include, for example, an electronic device described herein that contains filling material 136 within the central portion 141 of an individual conductive structure 140 (e.g., previously referenced...). Figures 1A to 1K and Figure 2 Embodiments of the described electronic devices 100, 200.

[0111] Electronic system 303 may additionally include at least one electronic signal processor device 307 (generally referred to as a “microprocessor”). Electronic signal processor device 307 may optionally include the electronic devices previously described herein (e.g., previously referenced...). Figures 1A to 1K and Figure 2Embodiments of one or more of the described electronic devices 100, 200. Electronic system 303 may additionally include one or more input devices 309 for inputting information into electronic system 303 via a user (e.g., mouse or other pointing device, keyboard, touchpad, button, or control panel). Electronic system 303 may additionally include one or more output devices 311 for outputting information (e.g., visual output or audio output) to the user, such as a monitor, display, printer, audio output jack, speaker, etc. In some embodiments, input device 309 and output device 311 may include a single touchscreen device for inputting information into electronic system 303 and outputting visual information to the user. Input device 309 and output device 311 may be electrically connected to one or more of memory device 305 and electronic signal processor device 307.

[0112] refer to Figure 4 The present invention describes a processor-based system 400. The processor-based system 400 may include various electronic devices manufactured according to embodiments of the present disclosure (e.g., electronic devices including one or more of electronic devices 100, 200). The processor-based system 400 may be any of a variety of types, such as a computer, pager, cellular phone, personal assistant, control circuitry, or other electronic devices. The processor-based system 400 may include one or more processors 402, such as microprocessors, to control system functions and request processing within the processor-based system 400. The processor 402 and other sub-components of the processor-based system 400 may include electronic devices manufactured according to embodiments of the present disclosure (e.g., electronic devices including one or more of electronic devices 100, 200).

[0113] The processor-based system 400 may include a power supply 404 operatively connected to the processor 402. For example, if the processor-based system 400 is a portable system, the power supply 404 may include one or more of a fuel cell, a powerscavenging device, a permanent battery, a replaceable battery, and a rechargeable battery. For example, the power supply 404 may also include an AC adapter; thus, the processor-based system 400 can be plugged into a wall outlet. For example, the power supply 404 may also include a DC adapter, allowing the processor-based system 400 to be plugged into a vehicle cigarette lighter or a vehicle power port.

[0114] Various other devices may be connected to the processor 402 depending on the functions performed by the processor-based system 400. For example, a user interface 406 may be connected to the processor 402. The user interface 406 may include input devices such as buttons, switches, keyboards, light pens, mice, digitizers and styluses, touchscreens, voice recognition systems, microphones, or combinations thereof. A display 408 may also be coupled to the processor 402. The display 408 may include an LCD display, a SED display, a CRT display, a DLP display, a plasma display, an OLED display, an LED display, a 3D projector, an audio display, or combinations thereof. Furthermore, an RF subsystem / baseband processor 410 may also be connected to the processor 402. The RF subsystem / baseband processor 410 may include antennas (not shown) connected to an RF receiver and an RF transmitter. One or more communication ports 412 may also be coupled to the processor 402. For example, communication port 412 may be adapted to couple to one or more peripheral devices 414 (e.g., modem, printer, computer, scanner, or camera) or to a network (e.g., local area network, remote area network, corporate intranet, or Internet).

[0115] Processor 402 can control processor-based system 400 by implementing software programs stored in memory. For example, the software programs may include operating systems, database software, graphics software, word processing software, media editing software, or media playback software. Memory is operatively coupled to processor 402 to store and facilitate the execution of various programs. For example, processor 402 may be coupled to system memory 416, which may include one or more of spin torque transfer magnetic random access memory (STT-MRAM), magnetic random access memory (MRAM), dynamic random access memory (DRAM), static random access memory (SRAM), racetrack memory, and other known memory types. System memory 416 may include volatile memory, non-volatile memory, or combinations thereof. System memory 416 is typically large enough to dynamically store loaded applications and data. In some embodiments, system memory 416 may include semiconductor devices, such as the electronic devices described above (e.g., electronic devices 100, 200) or combinations thereof.

[0116] Processor 402 may also be coupled to non-volatile memory 418, which does not imply that system memory 416 is necessarily volatile. Non-volatile memory 418 may include one or more of STT-MRAM, MRAM, read-only memory (ROM) such as EPROM, resistive read-only memory (RROM), and flash memory to be used in conjunction with system memory 416. The size of non-volatile memory 418 is typically chosen to be sufficient to store only the necessary operating system, applications, and fixed data. Additionally, non-volatile memory 418 may include, for example, mass storage such as disk drive memory, such as a hybrid drive containing resistive memory, or other types of non-volatile solid-state memory. Non-volatile memory 418 may include electronic devices, such as the electronic devices described above (e.g., electronic devices 100, 200) or combinations thereof.

[0117] Therefore, in at least some embodiments, a system includes: a processor operatively coupled to input and output devices; and an electronic device operatively coupled to the processor. The electronic device includes: a string of memory cells extending vertically through a stacked structure and comprising a vertically alternating sequence of insulating and conductive structures arranged in layers; and a filler material circumferentially surrounding at least some of the memory cell strings. The filler material is situated between opposing portions of conductive material within individual conductive structures.

[0118] Compared to conventional devices and systems, the electronic devices and systems of this disclosure advantageously facilitate one or more of the following: improved simplicity of components, greater package density, and enhanced miniaturization. Compared to conventional devices (e.g., conventional equipment, conventional microelectronic devices, conventional memory devices) and conventional systems (e.g., conventional electronic systems), the methods of this disclosure facilitate the formation of devices (e.g., equipment, microelectronic devices, memory devices) and systems (e.g., electronic systems) having one or more of the following: improved performance, reliability and durability, lower cost, increased yield, increased component miniaturization, improved pattern quality, and greater package density.

[0119] The embodiments of this disclosure may be further characterized in the manner described below, but not limited to the manner described below.

[0120] Example 1: A method for forming an electronic device, the method comprising: forming a stacked structure including vertically alternating insulating structures and additional insulating structures; forming a pillar including a channel material extending vertically through the stacked structure and at least one dielectric material; removing the additional insulating structures to form a cell opening; forming a first conductive material within a portion of the cell opening; forming a fill material adjacent to the first conductive material within the cell opening, the fill material including a sacrificial portion; removing the sacrificial portion of the fill material; and forming a second conductive material within the cell opening in an orientation previously occupied by the sacrificial portion of the fill material.

[0121] Example 2: The method according to Example 1 further includes forming a slot within the stacked structure before removing the additional insulation structure, wherein removing the sacrificial portion of the filler material includes selectively removing the sacrificial portion of the filler material near the slot without removing the filler material on the far side of the slot and between horizontally adjacent supports.

[0122] Example 3: According to the method of Example 2, the formation of the second conductive material includes substantially completely filling the remaining portion of the unit opening near the slot with the second conductive material and not forming the second conductive material between the horizontally adjacent pillars.

[0123] Example 4: The method according to any one of Examples 1 to 3, wherein: forming the first conductive material includes forming the first conductive material conformally without completely filling the cell opening; and forming the second conductive material includes forming the second conductive material non-conformally using one or more of chemical vapor deposition and physical vapor deposition.

[0124] Example 5: The method according to any one of Examples 1 to 4, wherein forming the filler material adjacent to the first conductive material in the cell opening includes selecting the filler material so that it can be selectively etched relative to the first conductive material.

[0125] Example 6: The method according to any one of Examples 1 to 5, wherein forming the filler material includes conformally forming one or more of a polycrystalline silicon material and a dielectric material adjacent to the first conductive material, wherein the filler material is substantially surrounded by the first conductive material.

[0126] Example 7: The method according to any one of Examples 1 to 5, wherein forming the first conductive material in the portion of the unit opening and forming the second conductive material in the unit opening includes selecting each of the first conductive material and the second conductive material to include tungsten and selecting the filler material to include different conductive materials.

[0127] Example 8: The method according to any one of Examples 1 to 7 further includes making each of the first conductive material and the second conductive material laterally recessed relative to the insulating structure and forming a conductive rail laterally adjacent to the first conductive material and the second conductive material.

[0128] Example 9: An electronic device comprising: a stacked structure including alternating layers of conductive and insulating structures; pillars extending vertically through the stacked structure; and a filler material located within the central portion of individual conductive structures of the stacked structure, the filler material being positioned between adjacent pillars and substantially surrounded by the conductive material of the individual conductive structures.

[0129] Example 10: The electronic device according to Example 9 further includes additional conductive material located in the central portion of the individual conductive structure of the stacked structure at the vertical level of the filling material, the additional conductive material being located outside the area of ​​the stacked structure containing the pillar.

[0130] Example 11: The electronic device according to Example 10, wherein the chemical composition of the additional conductive material of the individual conductive structure is different from the chemical composition of the conductive material of the individual conductive structure.

[0131] Example 12: An electronic device according to any one of Examples 9 to 11, further comprising one or more of a high-k dielectric material and a conductive liner material located between the alternating conductive and insulating structures of the stacked structure, wherein the conductive material of the individual conductive structure is located directly between the conductive liner material and the filler material.

[0132] Example 13: An electronic device according to any one of Examples 9 to 12, wherein the filling material generally surrounds at least some of the pillars along at least one horizontal direction.

[0133] Example 14: An electronic device according to any one of Examples 9 to 13, wherein the filling material comprises a material that does not react with the conductive material of the individual conductive structure.

[0134] Example 15: An electronic device according to any one of Examples 9 to 14, wherein the filling material comprises one or more of oxide materials, nitride materials and carbide materials located in the vertical central portion of the individual conductive structure.

[0135] Example 16: An electronic device according to any one of Examples 9 to 15, wherein the conductive material of the individual conductive structure comprises an upper portion and a lower portion separated from each other by the filler material, the combined thickness of the upper portion and the lower portion of the conductive material being substantially equal to the thickness of the filler material.

[0136] Example 17: A memory device comprising: a stacked structure including alternating conductive and insulating structures arranged in layers, each layer individually including a conductive structure and an insulating structure; a barrier material separating opposing portions of the conductive materials of the conductive structures; a string of memory cells extending vertically through the stacked structure, the string of memory cells including channel material extending vertically through the stacked structure; and conductive rails laterally adjacent to the conductive structures of the stacked structure, each conductive rail being horizontally aligned with the barrier material and the conductive material of the corresponding conductive structure.

[0137] Example 18: The memory device according to Example 17, wherein the barrier material is laterally separated from the conductive rail by at least one of the memory cell strings.

[0138] Example 19: The memory device according to Example 17 or Example 18, wherein the conductive material of the conductive structure includes a conductive material having a first material composition, and the barrier material includes another conductive material having a different second material composition.

[0139] Example 20: The memory device according to Examples 17 to 19, wherein the conductive material comprises tungsten, and the barrier material comprises one or more of titanium, ruthenium, aluminum, and molybdenum.

[0140] Example 21: The memory device according to Examples 17 to 20 further includes a dielectric material between adjacent sub-blocks of the stacked structure, wherein the lateral dimension of the dielectric material laterally adjacent to the insulating structure is greater than the lateral dimension of the dielectric material laterally adjacent to the conductive rail.

[0141] Example 22: The memory device according to Example 21 further includes an additional conductive material located within the central portion of the conductive structure and laterally adjacent to the conductive material within the conductive structure, the conductive material and the additional conductive material comprising substantially the same material composition, wherein the conductive material and the additional conductive material laterally separate the barrier material from the dielectric material located between the adjacent sub-blocks of the stacked structure.

[0142] Example 23: A system comprising: a processor operatively coupled to an input device and an output device; and an electronic device operatively coupled to the processor, the electronic device comprising: a string of memory cells extending vertically through a stacked structure and including a vertically alternating sequence of insulating and conductive structures arranged in layers; and a filler material circumferentially surrounding at least some of the string of memory cells, the filler material being situated between opposing portions of conductive material within individual conductive structures.

[0143] Example 24: According to the system of Example 23, the conductive material of the conductive structure is vertically inserted between the filler material and the insulating structure.

[0144] Example 25: The system according to Example 23 or Example 24, wherein the conductive material includes one or more of tungsten, titanium, ruthenium, aluminum and molybdenum, and the filler material includes polycrystalline silicon.

[0145] While certain illustrative embodiments have been described in conjunction with the drawings, those skilled in the art will recognize and understand that the embodiments included in this disclosure are not limited to those explicitly shown and described herein. Rather, various additions, deletions, and modifications can be made to the embodiments described herein without departing from the scope of the embodiments encompassed by this disclosure (such as those claimed herein, including legal equivalents). Furthermore, features of one disclosed embodiment may be combined with features of another disclosed embodiment while still being included within the scope of this disclosure.

Claims

1. A method of forming an electronic device, the method comprising: This forms a stacked structure that includes alternating vertical insulation structures and additional insulation structures; Forming pillars comprising channel material extending vertically through the stacked structure and at least one dielectric material; Remove the additional insulation structure to form a unit opening; A first conductive material is formed within a portion of the unit opening; A filler material adjacent to the first conductive material is formed within the unit opening, the filler material including a sacrificial portion; Remove the sacrificial portion of the filler material; and A second conductive material is formed within the opening of the unit in the location previously occupied by the sacrificial portion of the filling material.

2. The method of claim 1, further comprising forming a slot within the stacked structure prior to removing the additional insulating structure, wherein removing the sacrificial portion of the filler material comprises selectively removing the sacrificial portion of the filler material near the slot without removing the filler material distal to the slot and between horizontally adjacent struts.

3. The method of claim 2, wherein forming the second conductive material comprises substantially completely filling the remaining portion of the cell opening near the slot with the second conductive material and not forming the second conductive material between the horizontally adjacent pillars.

4. The method according to any one of claims 1 to 3, wherein: Forming the first conductive material includes conformally forming the first conductive material without completely filling the cell opening; and Forming the second conductive material includes non-conformally forming the second conductive material using one or more of chemical vapor deposition and physical vapor deposition.

5. The method according to any one of claims 1 to 3, wherein forming the filler material adjacent to the first conductive material within the cell opening comprises selecting the filler material so that it can be selectively etched relative to the first conductive material.

6. The method according to any one of claims 1 to 3, wherein forming the filler material comprises conformally forming one or more of a polycrystalline silicon material and a dielectric material adjacent to the first conductive material, wherein the filler material is substantially surrounded by the first conductive material.

7. The method according to any one of claims 1 to 3, wherein forming the first conductive material within the portion of the unit opening and forming the second conductive material within the unit opening comprises selecting each of the first conductive material and the second conductive material to include tungsten and selecting the filler material to include different conductive materials.

8. The method according to any one of claims 1 to 3, further comprising causing each of the first conductive material and the second conductive material to be laterally recessed relative to the insulating structure and forming a conductive rail laterally adjacent to the first conductive material and the second conductive material.

9. An electronic device comprising: A stacked structure, comprising alternating layers of conductive and insulating structures; A support column that extends vertically through the stacked structure; A metal nitride material, adjacent to the insulating structure of the stacked structure; One or more conductive materials are surrounded by the metal nitride material; as well as A filler material is located within the central portion of an individual conductive structure and between adjacent supports, wherein the filler material is substantially surrounded by one or more conductive materials of the individual conductive structure.

10. The electronic device of claim 9, further comprising additional conductive material within the central portion of the individual conductive structure of the stacked structure at a vertical level of the filling material, the additional conductive material being located outside the region of the stacked structure containing the pillar.

11. The electronic device of claim 10, wherein the chemical composition of the additional conductive material of the individual conductive structure is different from the chemical composition of the one or more conductive materials of the individual conductive structure.

12. The electronic device according to claim 10 or claim 11, further comprising a high-k dielectric material directly between the metal nitride material and the insulating structure of the stacked structure, wherein the one or more conductive materials of the individual conductive structures generally surround three sides of the additional conductive material, the one or more conductive materials being directly between the metal nitride material and the additional conductive material.

13. The electronic device according to any one of claims 9 to 11, wherein the filling material generally surrounds at least some of the pillars in at least one horizontal direction.

14. The electronic device according to any one of claims 9 to 11, wherein the filling material comprises a material that does not react with the one or more conductive materials of the individual conductive structure.

15. The electronic device according to any one of claims 9 to 11, wherein the filling material comprises one or more of oxide materials, nitride materials, and carbide materials located in the vertical central portion of the individual conductive structure.

16. The electronic device according to any one of claims 9 to 11, wherein the one or more conductive materials of the individual conductive structure comprises upper and lower portions spaced apart from each other by the filler material, the combined thickness of the upper and lower portions of the one or more conductive materials being substantially equal to the thickness of the filler material.

17. A memory device comprising: A stacked structure comprising alternating conductive and insulating structures arranged in layers, each layer individually comprising conductive and insulating structures. A barrier material that separates opposing portions of the conductive material of the conductive structure; A string of memory cells extending vertically through the stacked structure, the string of memory cells including channel material extending vertically through the stacked structure; and The conductive rails are laterally adjacent to the conductive structures of the stacked structure, and individual conductive rails are horizontally aligned with the barrier material and the conductive material of the corresponding conductive structure.

18. The memory device of claim 17, wherein the barrier material is laterally spaced from the conductive rail by at least one of the memory cell strings.

19. The memory device of claim 17 or claim 18, wherein the conductive material of the conductive structure comprises a conductive material having a first material composition, and the barrier material comprises another conductive material having a different second material composition.

20. The memory device of claim 17 or claim 18, wherein the conductive material comprises tungsten, and the barrier material comprises one or more of titanium, ruthenium, aluminum, and molybdenum.

21. The memory device of claim 17 or claim 18, further comprising a dielectric material between adjacent sub-blocks of the stacked structure, wherein the lateral dimension of the dielectric material laterally adjacent to the insulating structure is greater than the lateral dimension of the dielectric material laterally adjacent to the conductive rail.

22. The memory device of claim 21, further comprising an additional conductive material located within a central portion of the conductive structure and laterally adjacent to the conductive material within the conductive structure, the conductive material and the additional conductive material comprising substantially the same material composition, wherein the conductive material and the additional conductive material laterally separate the barrier material from the dielectric material located between adjacent sub-blocks of the stacked structure.

23. An electronic system comprising: A processor that is operatively coupled to input and output devices; and An electronic device operatively coupled to the processor, the electronic device comprising: A string of memory cells that extends vertically through a stacked structure and includes a vertically alternating sequence of insulating and conductive structures arranged in layers; A filling material circumferentially surrounding at least some of the memory cell strings, the filling material being situated between opposing portions of conductive material within individual conductive structures; and A metal nitride material is disposed between the insulating structure and the conductive material.

24. The electronic system of claim 23, wherein the conductive material of the conductive structure is vertically inserted between the filler material and the insulating structure.

25. The electronic system of claim 23 or claim 24, wherein the conductive material comprises one or more of tungsten, titanium, ruthenium, aluminum and molybdenum, and the filler material comprises polycrystalline silicon.

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