Semiconductor memory device and method of manufacturing the same

Abstract

A semiconductor memory device and a method of manufacturing the same are disclosed. A semiconductor memory device can include a stem extending in a vertical direction, a channel layer having a first region covering a portion of a side surface of the stem and a second region covering another portion of the side surface of the stem and a bottom surface of the stem, the second region abutting the first region, and a channel passivation layer formed in the first region of the channel layer and abutting the stem.

Description

Technical Field

[0001] Various embodiments generally relate to electronic devices, and more specifically, to a semiconductor memory device and a method of manufacturing the semiconductor memory device. Background Technology

[0002] To meet consumer demands for superior performance and low prices, improvements in the integration level of semiconductor devices are necessary. Specifically, since the integration level of semiconductor memory devices is a crucial factor determining product performance and price, various attempts are underway to improve integration. For example, 3D semiconductor memory devices, which include multiple memory cells arranged in a 3D manner, are being actively researched, thereby reducing the area occupied by memory cells per unit area of ​​the substrate. Summary of the Invention

[0003] In one embodiment, a semiconductor memory device may include: a die extending in a vertical direction; a channel layer having a first region covering a portion of a side surface of the die and a second region covering another portion of the side surface of the die and a bottom surface of the die, the second region abutting the first region; and a channel passivation layer formed in the first region of the channel layer and abutting the die.

[0004] In one embodiment, a semiconductor memory device may include: a gate stack formed on a source layer, having a plurality of interlayer dielectric layers and a plurality of gate conductive layers alternately stacked therein; and a plurality of channel structures formed through the gate stack, each having a lower end extending into the source layer. Each channel structure may include: a channel layer having a first region formed in the gate stack and a second region formed in the source layer to abut the first region; and a channel passivation layer formed in the first region of the channel layer.

[0005] In one embodiment, a method of manufacturing a semiconductor memory device may include the following steps: forming a stack on a source layer by alternately stacking a plurality of interlayer dielectric layers and a plurality of gate sacrificial layers; forming a plurality of channel vias through the stack, each of the plurality of channel vias having a lower end extending into the source layer; forming a channel layer along the surface of the channel vias, the channel layer including a first region formed in the stack and a second region formed in the source layer; and forming a channel passivation layer in the first region to reduce the thickness of the channel layer in the first region.

[0006] In one embodiment, a memory system may include: a memory device, wherein the memory device includes: a core extending in a vertical direction; a channel layer having a first region configured to cover a portion of a side surface of the core core and a second region covering another portion of the side surface of the core core and a bottom surface of the core core and abutting the first region; a channel passivation layer formed in the first region of the channel layer and abutting the core core; and a memory controller coupled to the memory device and configured to control the memory device.

[0007] In one embodiment, a computing system may include: a memory system comprising: a memory device, wherein the memory device includes: a core extending in a vertical direction; a channel layer having a first region covering a portion of a side surface of the core and a second region covering another portion of the side surface of the core and a bottom surface of the core and abutting the first region; and a channel passivation layer formed in the first region of the channel layer and abutting the core; a memory controller coupled to the memory device and configured to control the memory device; a central processing unit coupled to the memory system, random access memory, a user interface, and a modem, and configured to execute instructions to operate the computing system; random access memory coupled to the central processing unit, the memory system, the user interface, and the modem, and configured to be read and changed in any order; a user interface coupled to the central processing unit, random access memory, the modem, and the memory system, and configured to allow access to the computer system; and a modem coupled to the central processing unit, the memory system, random access memory, and the user interface, configured to modulate and demodulate data between the computing system and the analog system. Attached Figure Description

[0008] Figure 1 This is a block diagram schematically illustrating the configuration of a semiconductor memory device according to an embodiment.

[0009] Figure 2 This is a circuit diagram showing a portion of the memory block of a semiconductor memory device according to an embodiment.

[0010] Figure 3 This is a schematic perspective view of a semiconductor memory device according to an embodiment.

[0011] Figure 4 This is a perspective view showing a semiconductor memory device according to an embodiment.

[0012] Figure 5 yes Figure 4 An enlarged cross-sectional view of region "A" shown.

[0013] Figure 6A , Figure 6B and Figure 6C They are along Figure 4 Plan view of the channel structure intercepted by lines I-I', II-II' and III-III'.

[0014] Figure 7 This is a flowchart schematically illustrating a method for manufacturing a semiconductor memory device according to an embodiment.

[0015] Figure 8 This is a flowchart schematically illustrating a method for manufacturing a semiconductor memory device according to an embodiment.

[0016] Figure 9A , Figure 9B , Figure 9C , Figure 9D , Figure 9E , Figure 9F , Figure 9G and Figure 9H This is a cross-sectional view showing a method for manufacturing a semiconductor memory device according to an embodiment.

[0017] Figure 10A , Figure 10B , Figure 10C and Figure 10D This is a cross-sectional view showing a method for manufacturing a semiconductor memory device according to an embodiment.

[0018] Figure 11A , Figure 11B , Figure 11C , Figure 11D , Figure 11E , Figure 11F and Figure 11G This is a cross-sectional view showing a method for manufacturing a semiconductor memory device according to an embodiment.

[0019] Figure 12 This is a block diagram illustrating the configuration of a memory system according to an embodiment.

[0020] Figure 13 This is a block diagram illustrating the configuration of a computing system according to an embodiment. Detailed Implementation

[0021] Various embodiments relate to a semiconductor memory device capable of improving operational reliability and a method of manufacturing the semiconductor memory device.

[0022] The advantages and features of this disclosure, as well as the methods for achieving these advantages and features, will become clear from the detailed description of the embodiments with reference to the accompanying drawings. However, this disclosure is not limited to the embodiments disclosed below and may be embodied in various forms. These embodiments are provided so that this disclosure will be thorough and complete, and that the scope of this disclosure will be fully conveyed to those skilled in the art. This disclosure is defined only by the scope of the claims. In the drawings, the dimensions and relative dimensions of layers and regions may be exaggerated for clarity of description. Throughout this specification, similar reference numerals denote the same components.

[0023] The embodiments described below provide a semiconductor memory device and a method for manufacturing the same, which can improve operational reliability. The semiconductor memory device may include a non-volatile semiconductor memory device with a 3D structure, such as a 3D NAND memory device.

[0024] Semiconductor memory devices according to embodiments can improve operational reliability through channel crystallization. More specifically, as semiconductor memory device technology has evolved to methods of stacking memory cells, the channels also have a 3D structure extending in the vertical direction. As a commonly used channel material, monocrystalline silicon has limitations in forming 3D channels extending in the vertical direction. Therefore, polycrystalline silicon, which can improve process speed, is attracting much attention. Since monocrystalline silicon consists of regularly arranged silicon atoms, it is defect-free and exhibits excellent electrical properties. On the other hand, polycrystalline silicon has a structure in which blocks of silicon with different lattice orientations (i.e., multiple grains and grain boundaries) are connected. In polycrystalline silicon, grain boundaries not only act as barriers that interfere with charge transfer and defects that trap charge, but also as sources of surface defects such as pinholes. Therefore, grain boundaries can degrade the characteristics of memory cells.

[0025] Therefore, the embodiments described below provide a semiconductor memory device and a method for manufacturing the same, which can improve operational reliability by increasing the grain size of the polysilicon used as the channel to reduce the area occupied by grain boundaries per unit volume or the number of grain boundaries per unit area.

[0026] Hereinafter, a semiconductor memory device according to an embodiment will be described in detail with reference to the accompanying drawings. In the following description, the first direction D1, the second direction D2, and the third direction D3 may indicate directions that intersect each other. For example, in the XYZ coordinate system, the first direction D1, the second direction D2, and the third direction D3 may indicate the X-axis direction, the Y-axis direction, and the Z-axis direction, respectively.

[0027] Figure 1 This is a block diagram schematically illustrating the configuration of a semiconductor memory device according to an embodiment.

[0028] like Figure 1As shown, the semiconductor memory device 10 may include peripheral circuitry PC and memory cell array 20.

[0029] The peripheral circuitry PC can be configured to control programming operations that store data in the memory cell array 20, reading operations that output data stored in the memory cell array 20, and erasing operations that erase data stored in the memory cell array 20. For example, the peripheral circuitry PC may include a voltage generator 31, a line decoder 33, control circuitry 35, and a page buffer set 37.

[0030] The memory cell array 20 may include multiple memory blocks. The memory cell array 20 is connected to the row decoder 33 via word line WL and to the page buffer group 37 via bit line BL.

[0031] Control circuit 35 can control peripheral circuit PC in response to command CMD and address ADD.

[0032] Voltage generator 31 can generate various operating voltages for programming, reading and erasing operations in response to control of control circuit 35, such as pre-erase voltage, erase voltage, ground voltage, programming voltage, verification voltage, pass voltage and read voltage.

[0033] The line decoder 33 can select a memory block in response to the control circuit 35. The line decoder 33 can be configured to apply an operating voltage to the word line WL connected to the selected memory block.

[0034] Page buffer group 37 can be connected to memory cell array 20 via bit line BL. In response to control of control circuitry 35, page buffer group 37 can temporarily store data received from input / output circuitry (not shown) during programming operations. In response to control of control circuitry 35, page buffer group 37 can sense the voltage or current of bit line BL during read or verification operations. Page buffer group 37 can select bit line BL in response to control of control circuitry 35.

[0035] Specifically, the memory cell array 20 may be arranged parallel to the peripheral circuit PC, or may overlap with a portion of the peripheral circuit PC.

[0036] Figure 2 This is a circuit diagram showing a portion of the memory block of a semiconductor memory device according to an embodiment.

[0037] like Figure 2 As shown, a memory block may include a source layer SL and multiple cell strings CS1 and CS2 that are connected to multiple word lines WL1 to WLn (where n is a positive integer). The multiple cell strings CS1 and CS2 may be connected to multiple bit lines BL.

[0038] Each of the cell strings CS1 and CS2 may include one or more source selection transistors SST connected to the source layer SL, one or more drain selection transistors DST connected to the bit line BL, and a plurality of memory cells MC1 to MCn connected in series between the source selection transistors SST and the drain selection transistors DST.

[0039] The gates of multiple memory cells MC1 to MCn can be connected to word lines WL1 to WLn stacked and spaced apart from each other. Multiple word lines WL1 to WLn can be arranged between the source select line SSL and two or more drain select lines DSL1 and DSL2. The two or more drain select lines DSL1 and DSL2 can be spaced apart from each other at the same height.

[0040] The source-select transistor SST may have a gate connected to the source-select line SSL. The drain-select transistor DST may have a gate connected to the drain-select line corresponding to the gate of the drain-select transistor DST.

[0041] The source layer SL can be connected to the source of the source select transistor SST. The drain select transistor DST can have a drain connected to the bit line BL corresponding to the drain of the drain select transistor DST.

[0042] Multiple unit strings CS1 and CS2 can be divided into string groups, each connected to two or more drain select lines DSL1 and DSL2. Unit strings connected to the same word line and the same bit line can be independently controlled by different drain select lines. Furthermore, unit strings connected to the same drain select line can be independently controlled by different bit lines. For example, two or more drain select lines DSL1 and DSL2 may include a first drain select line DSL1 and a second drain select line DSL2. Multiple unit strings CS1 and CS2 may include a first unit string CS1 connected to a first string group connected to the first drain select line DSL1 and a second unit string CS2 connected to a second string group connected to the second drain select line DSL2.

[0043] Figure 3 This is a schematic perspective view of a semiconductor memory device according to an embodiment.

[0044] like Figure 3 As shown, the semiconductor memory device 10 may include peripheral circuitry PC disposed on a substrate SUB and a gate stack GST overlapping the peripheral circuitry PC.

[0045] Each gate stack (GST) may include a source select line SSL, multiple word lines WL1 to WLn, and two or more drain select lines DSL1 and DSL2 that are isolated from each other at the same height by a first slit S1.

[0046] The source selection line SSL and multiple word lines WL1 to WLn can be extended in the first direction D1 and the second direction D2, and are formed into a plate shape parallel to the top surface of the substrate SUB.

[0047] Multiple word lines WL1 to WLn can be stacked on the third-party D3 to be spaced apart from each other, and can be set between the source select line SSL and two or more drain select lines DSL1 and DSL2.

[0048] The gate stacks GST can be isolated from each other by the second slit S2, wherein the first slit S1 can be formed on the third direction D3 as shorter than the second slit S2 and overlap with multiple word lines WL1 to WLn.

[0049] Each of the first slit S1 and the second slit S2 may extend in a straight line, a zigzag shape, or a wavy shape in the second direction. Furthermore, each of the first slit S1 and the second slit S2 may have a width that varies to various values ​​according to design rules.

[0050] The source select line SSL may be positioned closer to the peripheral circuit PC than the two or more drain select lines DSL1 and DSL2. The semiconductor memory device 10 may include a source layer SL disposed between the gate stack GST and the peripheral circuit PC, and multiple bit lines BL further separated from the source layer SL and the peripheral circuit PC. The gate stack GST may be disposed between the multiple bit lines BL and the source layer SL.

[0051] Multiple bit lines BL can be formed from various conductive materials (e.g., doped semiconductor layers, metal layers, and metal alloy layers). The source layer SL may include a doped semiconductor layer. For example, the source layer SL may include an n-type doped silicon layer.

[0052] Although not shown, the peripheral circuit PC can be electrically connected to multiple bit lines BL, source layer SL, and multiple word lines WL1 to WLn via interconnects with various structures.

[0053] like Figure 4 and Figure 5 As shown, the semiconductor memory device according to the embodiment may include a source layer SL, a plurality of gate stacks GST formed on the source layer SL, a slit structure 110 formed between the respective gate stacks GST, and a plurality of channel structures CH formed through the gate stacks GST.

[0054] The source layer SL may overlap with the gate stack GST and has a plate shape extending in the first direction D1 and the second direction D2. The source layer SL may have a structure in which a first source layer SL1, a third source layer SL3, and a second source layer SL2 are stacked sequentially. That is, the source layer SL may have a structure in which the third source layer SL3 is inserted between the first source layer SL1 and the second source layer SL2. The third source layer SL3 may be electrically connected to the channel layer 122 of each channel structure CH.

[0055] Each of the first source layers SL1 to the third source layer SL3 may include a doped semiconductor layer. For example, each of the first source layers SL1 to the third source layer SL3 may include an n-type doped silicon layer. Therefore, the first source layer SL1 and the second source layer SL2 may each have a higher impurity concentration than the third source layer SL3 interposed therebetween.

[0056] In this embodiment, an example is taken where the first source layer SL1 to the third source layer SL3 are formed of the same conductive material. However, the embodiment is not limited to this. In a modified example, the first source layer SL1 and the second source layer SL2 may be formed of the same conductive material, and the third source layer SL3 inserted therebetween may be formed of a different conductive material than the first source layer SL1 and the second source layer SL2. In another modified example, the first source layer SL1 to the third source layer SL3 may be formed of different materials from each other.

[0057] The gate stack (GST) can be isolated by multiple slit structures 110. Specifically, the slit structures 110 can be located on two sidewalls of each gate stack (GST) in the first direction D1. The gate stack (GST) isolated by the slit structures 110 can correspond to a memory block. The source layer SL can be located at the bottom of the gate stack (GST), and multiple bit lines (not shown, see [link]). Figure 3 It can be located on top of the gate stack GST. Therefore, as Figure 3 As shown, the source layer SL, the gate stack GST, and multiple bit lines overlap each other.

[0058] In the implementation method, such as Figure 3 The example shown illustrates a scenario where the source layer SL is located at the bottom of the gate stack GST and the bit line is located at the top of the gate stack GST. However, the implementation is not limited to this. In a modified example, the bit line may be located at the bottom of the gate stack GST, and the source layer SL may be located at the top of the gate stack GST.

[0059] Each slit structure 110 can correspond to Figure 3The second slit S2 is shown. Each slit structure 110 can be a linear pattern extending in the second direction D2. In this case, each slit structure 110 can extend in a straight line, a zigzag shape, or a wavy shape in the second direction D2. The lower end of the slit structure 110 in the third direction D3 can extend into the source layer SL. For example, as... Figure 4 As shown, the bottom surface of the slit structure 110 can abut against the third source layer SL3 inserted between the first source layer SL1 and the second source layer SL2.

[0060] like Figure 4 As shown, each slit structure 110 may include a linear slit groove 112 extending in the second direction D2, a slit spacer 114 formed on any sidewall of the slit groove in the first direction D1, and a slit layer 116 that fills the gaps in the slit groove 112. The slit spacer 114 may include a dielectric material, and the slit layer 116 may include a conductive material.

[0061] In this embodiment, the slit layer 116 is described as comprising a conductive material. However, the embodiment is not limited to this. In a modified example, the slit layer 116 may comprise a dielectric material.

[0062] like Figure 4 As shown, each gate stack GST can be a stacked structure in which multiple interlayer dielectric layers 102 and multiple gate conductive layers 104 are alternately stacked. The interlayer dielectric layers 102 can be located at each of the bottommost and topmost layers of the gate stack GST. The interlayer dielectric layer 102 located at the topmost layer of the gate stack GST can have a greater thickness than the other interlayer dielectric layers 102. Each of the interlayer dielectric layers 102 and the gate conductive layers 104 can have a plate shape extending in a first direction D1 and a second direction D2.

[0063] The interlayer dielectric layer 102 may include any dielectric layer selected from the group consisting of oxide layers, nitride layers, and oxide nitride layers. For example, the interlayer dielectric layer 102 may include an oxide layer. The gate conductive layer 104 may include a metal conductive layer. For example, the gate conductive layer 104 may include a tungsten layer. Alternatively, the gate conductive layer 104 may include a stack of titanium nitride and tungsten layers. The titanium nitride layer can be used as a barrier layer to prevent tungsten diffusion.

[0064] The bottommost gate conductive layer 104 in each gate stack GST can be used as Figure 3 The gate and source select line SSL of the source select transistor are shown.

[0065] In this embodiment, the gate conductive layer 104, which serves as the gate and source select line of the source select transistor, is formed as a single layer. However, the embodiment is not limited to this. In a modified example (not shown), a plurality of gate conductive layers 104 located at the bottom of the gate stack GST (including the gate conductive layer 104 located at the bottommost layer of the gate stack GST) can be used as the gate and source select line of the source select transistor.

[0066] In this embodiment, such as Figure 4 and Figure 5 As shown, an example is given where the lowest gate conductive layer 104 serving as the source select line in each gate stack GST is formed as a single pattern at the same height. However, the implementation is not limited to this. In a modified example (not shown), the lowest gate conductive layer 104 serving as the source select line in each gate stack GST can be configured as two or more patterns isolated from each other at the same height.

[0067] At least the uppermost gate conductive layer 104 in each gate stack GST can be used as Figure 3 The drain-select transistors shown have gate and drain-select lines DSL1 and DSL2. The uppermost gate conductive layer 104 in each gate stack GST can be separated into two or more patterns spaced apart from each other at the same height by one or more isolation layers 106. The isolation layers 106 can correspond to... Figure 3 The first slit S1 is shown. Therefore, as... Figure 4 As shown, the gate conductive layers 104 located on one side and the other side of the isolation layer 106 in the first direction D1 can respectively correspond to Figure 3 The first drain select line DSL1 and the second drain select line DSL2 are shown. The isolation layer 106 may include any dielectric layer selected from the group consisting of oxide layers, nitride layers, and oxide nitride layers. For example, the isolation layer 106 may be formed of an oxide layer.

[0068] In this embodiment, the gate conductive layer 104, which serves as the gate and drain select line of the drain select transistor, is formed as a single layer. However, the embodiment is not limited to this. In a modified example (not shown), a plurality of gate conductive layers 104 located on top of the gate stack GST (including the gate conductive layer 104 located on the uppermost layer of the gate stack GST) can be used as the gate and drain select line of the drain select transistor.

[0069] Each gate conductive layer 104 in each gate stack GST located between the gate conductive layer 104 used as the source select line and the gate conductive layer 104 used as the drain select line can be used as the gate and word line of the memory cell transistor. Therefore, as Figure 4As shown, the gate conductive layer 104 located between the uppermost gate conductive layer 104 and the lowermost gate conductive layer 104 in the gate stack GST can correspond to Figure 3 The multiple word lines WL1 to WLn are shown.

[0070] Multiple channel structures CH can be arranged in a matrix structure within a gate stack GST. Each channel structure CH may have a planar shape corresponding to a polygonal shape such as a triangle, circle, or ellipse. Each channel structure CH is formed through the gate stack GST and has a lower end extending into the source layer SL. Specifically, the lower end of the channel structure CH may be formed through the first source layer SL1 and the third source layer SL3, and the bottom surface of the channel structure CH may be located in the first source layer SL1. Through the lower end extending into the source layer SL, each channel structure CH is electrically connected to the source layer SL.

[0071] Each channel structure CH can be formed as a columnar pattern extending in the third direction D3, and has a high aspect ratio. For example... Figure 4 As shown, the linewidth TD at the uppermost end of each channel structure CH can be greater than the linewidth BD at its lowermost end, and each channel structure CH can have sloping sidewalls. That is, each channel structure CH can have a trapezoidal cross-sectional shape, with the linewidth at the top side of the trapezoid being greater than the linewidth at the bottom side, and having a linewidth that gradually decreases from top to bottom in the third direction D3.

[0072] Specifically, such as Figures 6A to 6C As shown, the first linewidth CHD1 at the top of the channel structure CH can be greater than the second linewidth CHD2 in the middle of the channel structure CH and the third linewidth CHD3 at the bottom of the channel structure CH (CHD1>CHD2 and CHD3). The second linewidth CHD2 in the middle of the channel structure CH can be greater than the third linewidth CHD3 at the bottom of the channel structure CH (CHD2>CHD3).

[0073] like Figure 4 As shown, each channel structure CH may include: a core 128 extending in the third direction D3; a capping layer 126 formed above the core 128; a channel layer 122 covering the side surface of the capping layer 126 and the side and bottom surfaces of the core 128; a memory layer 120 covering the side and bottom surfaces of the channel layer 122; and a channel passivation layer 124 inserted between the core 128 and the channel layer 122 within the gate stack GST.

[0074] The die post 128 may be formed through the gate stack GST and has a lower end formed in a pillar shape extending into the source layer SL. Therefore, the die post may have a trapezoidal cross-sectional shape. The die post 128 may include any dielectric layer selected from the group consisting of oxide layers, nitride layers, and oxide-oxygen layers. For example, the die post 128 may include an oxide layer.

[0075] Capping layer 126 may be located above post 128 and has a pillar shape. Capping layer 126 may serve as the junction region of a drain-select transistor. The interface between post 128 and capping layer 126 may be aligned with the surface of the uppermost gate conductive layer 104 of the gate stack GST, or located at a height higher than the surface of the gate conductive layer 104. The bottom surface of capping layer 126 may abut against post 128 and channel passivation layer 124. Capping layer 126 may be electrically connected to channel layer 122 covering the side surface of post 128. Capping layer 126 may include a doped semiconductor layer. For example, capping layer 126 may include an n-type doped silicon layer.

[0076] The channel layer 122 may have a cylindrical shape to cover the side surfaces of the capping layer 126 and the side and bottom surfaces of the core post 128. For example... Figure 5 As shown, the channel layer 122 may include a first region R1 covering a portion of the side surface of the core pillar 128 and a second region R2 abutting the first region R1 and covering another portion of the side surface of the core pillar 128 and the bottom surface of the core pillar 128. The first region R1 may indicate the channel layer 122 formed in the gate stack GST, and the second region R2 may indicate the channel layer 122 formed in the source layer SL. Therefore, although the channel layer 122 has a generally cylindrical shape, the channel layer 122 in the first region R1 may have a tubular shape, and the channel layer 122 in the second region R2 may have a cylindrical shape. (Refer to...) Figures 6A to 6C In the channel structure CH, the thickness T1 or T2 of the channel layer 122 in the first region R1 may be less than the thickness T3 of the channel layer 122 in the second region R2. For reference, a cylindrical shape may indicate a columnar shape with an open top surface and cavities formed therein. That is, a cylindrical shape may be similar to a cup shape. Furthermore, a tubular shape may indicate a columnar shape with open top and bottom surfaces and cavities formed therein.

[0077] The channel layer 122 is electrically connected to the source layer SL (not shown). Specifically, the channel layer 122 of the second region R2 is electrically connected to the third source layer SL3. Therefore, the channel layer 122 of the second region R2 can be used as the junction region of a source-select transistor. The channel layer 122 may include a polycrystalline semiconductor layer. For example, the channel layer 122 may include a polycrystalline silicon layer.

[0078] like Figure 5As shown, memory layer 120 may have a cylindrical shape to cover a portion of the side surface of channel layer 122. Memory layer 120 may have a structure in which barrier layer 120A, charge trapping layer 120B, and tunnel dielectric layer 120C are stacked sequentially. Each of barrier layer 120A, charge trapping layer 120B, and tunnel dielectric layer 120C may include any one selected from the group consisting of oxide layers, nitride layers, and oxide oxynitride layers. For example, tunnel dielectric layer 120C may have a shape covering a portion of the side surface of channel layer 122 and includes an oxide layer. Charge trapping layer 120B may have a shape covering the side surface of tunnel dielectric layer 120C and includes a nitride layer. Barrier layer 120A may have a shape covering the side surface of charge trapping layer 120B and includes an oxide layer.

[0079] In this embodiment, an ONO structure in which the memory layer 120 has an oxide layer, a nitride layer, and an oxide layer stacked is taken as an example. However, the embodiment is not limited to this. The memory layer 120 may include various material layers and have various stacked structures depending on the characteristics required by the semiconductor memory device.

[0080] like Figure 4 As shown, the channel passivation layer 124 may have a tubular shape to cover the side surface of the core post 128. The outer wall of the channel passivation layer 124 may be aligned with the side wall of the capping layer 126. Figure 5 As shown, the channel passivation layer 124 can be used to stably reduce the thickness of the channel layer 122 in the first region R1 and remove surface defects (e.g., pinholes) in the channel layer 122. "Reducing" means decreasing the size. "Steady reducing" means reducing the size in a manner unlikely to compromise or fail. The channel passivation layer 124 can be inserted between the die post 128 and the channel layer 122 in the gate stack GST. In other words, the channel passivation layer 124 can be formed only in the first region R1 of the channel layer 122 and not in the second region R2. Therefore, due to the channel passivation layer 124, the thickness of the channel layer 122 in the first region R1 can be less than the thickness of the channel layer 122 in the second region R2. This is to prevent excessive surface defects such as pinholes from occurring in the channel layer 122 during the process of forming the channel layer 122 and the channel passivation layer 124, and to prevent damage to the source layer SL. In addition, this is to improve the contact characteristics between the source layer SL and the channel layer 122.

[0081] Reference Figures 6A to 6CThe thickness of the memory layer 120 in each of the top, middle, and bottom of the channel structure CH is constant, but the linewidth of the core pillar 128 in the top, middle, and bottom of the channel structure CH can differ from each other depending on the linewidth of the top, middle, and bottom of the channel structure CH. That is, the channel structure CH and the core pillar 128 can have the same cross-sectional shape. Due to the channel passivation layer 124, the first thickness T1 of the channel layer 122 formed at the top of the channel structure CH can be substantially equal to the second thickness T2 of the channel layer 122 formed in the middle of the channel structure CH. However, since the channel passivation layer 124 is not formed at the bottom of the channel structure CH, the third thickness T3 of the channel layer 122 formed at the bottom of the channel structure CH can be greater than the first thickness T1 and the second thickness T2. The sum of the thickness T1 or T2 of the channel layer 122 in the first region R1 and the thickness of the channel passivation layer 124 can be substantially equal to or greater than the thickness T2 of the channel layer 122 in the second region R2. For example, in the channel structure CH, the thickness T1 or T2 of the channel layer 122 in the first region R1 can be... to Within the range, the thickness T3 of the channel layer 122 in the second region R2 can be... to Within a certain range. Furthermore, the thickness of the channel passivation layer 124 can be... to Within the range. For reference, in an embodiment, the sum of the thickness T1 or T2 of the channel layer 122 in the first region R1 and the thickness of the channel passivation layer 124 is substantially equal to the thickness T2 of the channel layer 122 in the second region R2.

[0082] The channel passivation layer 124 can be formed by oxidizing the channel layer 122. This is to remove surface defects such as pinholes while stably reducing the thickness of the channel layer 122. For this purpose, the channel passivation layer 124 may include a dielectric layer formed at a temperature higher than the crystallization annealing temperature of the channel layer 122. For example, the channel passivation layer 124 may include a silicon oxide layer formed by free radical oxidation at a temperature of 600°C to 800°C.

[0083] The channel passivation layer 124 is formed only in the first region R1 of the channel layer 122 and not in the second region R2 of the channel layer 122 because the channel layer 122 in the second region R2 serves as the junction region of the source selection transistor. Specifically, since the channel layer 122 in the second region R2 is located at the bottom of the channel structure CH with a high aspect ratio, it is practically impossible to form the junction region by ion implantation. The junction region is formed by diffusion from the source layer SL. Therefore, when the channel passivation layer 124 is formed in the channel layer 122 in the second region R2, the thickness of the channel layer 122 used as the junction region can be reduced, thereby degrading the operational reliability of the semiconductor memory device.

[0084] As described above, an advantage of this disclosure is that the semiconductor memory device according to the embodiments may include a channel passivation layer 124, thereby steadily reducing the thickness of the channel layer 122 and removing surface defects of the channel layer 122, thereby improving the operational reliability of the semiconductor memory device.

[0085] Furthermore, since the channel passivation layer 124 is formed only in the first region R1 of the channel layer 122 and not at the bottom of the channel structure CH (i.e., the second region R2 of the channel layer 122), excessive surface defects in the channel layer 122 between processes can be prevented, and damage to the source layer SL can be prevented. In addition, the contact characteristics between the source layer SL and the channel layer 122 can be improved.

[0086] Figure 7 This is a flowchart schematically illustrating a method for manufacturing a semiconductor memory device according to an embodiment.

[0087] like Figure 7 As shown, a method for manufacturing a semiconductor memory device may include step S1 of forming peripheral circuits on a substrate and step S2 of forming a memory cell array on the peripheral circuits.

[0088] In step S1, peripheral circuitry may be formed on the substrate. The peripheral circuitry may include multiple transistors. The source and drain of each transistor may be formed in a portion of the substrate, and the gate electrode of each transistor may be formed on the substrate.

[0089] In step S2, a memory cell array may be formed on the peripheral circuitry. Step S3 may include forming... Figure 3 The source layer SL shown is formed Figure 3 The gate stack GST shown is formed Figure 3 The bit line BL is shown.

[0090] Although not shown in the figure, conductive patterns for interconnects can be formed on the peripheral circuit prior to step S2, and memory cell arrays can be formed on the interconnects.

[0091] The method may further include the step of forming a memory layer on the side and bottom surfaces of the channel via prior to forming the semiconductor layer, wherein the memory layer is formed as a stack of a barrier layer, a charge trapping layer and a tunnel dielectric layer.

[0092] The method may further include the following steps: forming a core post on the channel passivation layer and the channel layer after forming the channel passivation layer, such that the core post gaps fill the channel holes; forming a recess by etching the top of the core post; extending the recess by etching the channel passivation layer exposed on the side surface of the recess; and forming a capping layer that fills the extended recess and is electrically connected to the channel layer.

[0093] The steps of forming the channel layer may include: forming a semiconductor layer having a first thickness along the surface of the channel hole; forming a crystalline semiconductor layer by performing a crystallization annealing process; and etching the crystalline semiconductor layer to have a second thickness less than the first thickness. The formation of the semiconductor layer, the crystallization annealing process, and the etching may be repeated once or more.

[0094] The method may further include a step of forming a crystal support layer on the semiconductor layer prior to performing a crystallization annealing process, wherein the crystal support layer may be removed in a step of etching the crystallized semiconductor layer to have a second thickness.

[0095] According to this embodiment, a semiconductor memory device may include a channel passivation layer, thereby stably reducing the thickness of the channel layer and removing surface defects of the channel layer.

[0096] Furthermore, since the channel passivation layer is formed only on the surface of the channel layer within the gate stack, excessive defects on the surface of the channel layer between processes can be prevented, and damage to the source layer can be prevented. Additionally, the contact characteristics between the source layer and the channel layer can be improved.

[0097] Therefore, the channel passivation layer included in the gate stack can improve the operational reliability of semiconductor memory devices.

[0098] Furthermore, when forming the channel layer, the deposition, crystallization annealing process and etching can be repeated two or more times, which allows for an effective increase in the grain size within the channel layer.

[0099] In addition, a crystal support layer can be formed when the channel layer is formed, which makes it more effective to increase the grain size within the channel layer.

[0100] Therefore, the grain size in the channel layer can be increased to further improve the operational reliability of semiconductor memory devices.

[0101] Figure 8 This is a flowchart schematically illustrating a method for manufacturing a semiconductor memory device according to an embodiment.

[0102] like Figure 8 As shown, a method for manufacturing a semiconductor memory device may include step S11 of forming a first chip including peripheral circuitry, step S12 of forming a second chip including a memory cell array, step S13 of combining the first chip and the second chip, and step S14 of removing an auxiliary substrate from the second chip.

[0103] In step S11, peripheral circuitry may be disposed on the main substrate. The first chip may include a first interconnect connected to the peripheral circuitry.

[0104] In step S12, a memory cell array may be formed on the auxiliary substrate. Step S12 may include forming Figure 3 The source layer SL shown is formed Figure 3 The gate stack GST shown and the formation Figure 3 The bit line BL is shown. The second chip may also include a second interconnect connected to the memory cell array.

[0105] Figure 3 The illustration shows a memory cell array formed by sequentially stacking a source layer SL, a gate stack GST, and a bit line BL; however, the implementation is not limited to this. In a modified example, the memory cell array in step S12 may have a structure in which the gate stack is formed on the bit line and no source layer is formed (not shown).

[0106] In step S13, the second chip can be aligned on the first chip such that the first interconnect and the second interconnect face each other, and some of the first interconnect and some of the second interconnect can be coupled to each other.

[0107] In step S14, the auxiliary substrate of the second chip can be removed to form a semiconductor memory device in which peripheral circuits and memory cell arrays overlap each other.

[0108] In the modified example, when the memory cell array in step S12 has a structure in which gate stacks are formed on bit lines and no source layer is formed (not shown), a source layer connected to the channel structure can be formed after step S14.

[0109] Figures 9A to 9H This is a cross-sectional view showing a method for manufacturing a semiconductor memory device according to an embodiment. Figures 9A to 9H This is a cross-sectional view illustrating a method for manufacturing a memory cell array of a semiconductor memory device. The following will refer to... Figures 9A to 9H The method for manufacturing the described memory cell array may include Figure 7 The steps S2 or shown Figure 8 In step S12 shown.

[0110] like Figure 9A As shown, a predetermined structure is formed (e.g., peripheral circuit PC (see...)). Figure 1 and Figure 3A pre-source layer 200A is formed on a substrate (not shown). The pre-source layer 200A may be formed as a stack of a first source layer 202, a source sacrificial layer 204, and a second source layer 206 stacked sequentially. The pre-source layer 200A may have a plate shape extending in a first direction D1 and a second direction D2. Each of the first source layer 202 and the second source layer 206 may include a doped semiconductor layer 226B. For example, each of the first source layer 202 and the second source layer 206 may include an n-type doped silicon layer. The source sacrificial layer 204 may be formed of a material having etch selectivity with the first source layer 202 and the second source layer 206. For example, the source sacrificial layer 204 may be formed as a single layer selected from the group consisting of oxide layers, nitride layers, and oxide oxynitride layers, or a stack of two or more layers selected from the group. For example, the source sacrificial layer 204 may be formed of an oxide layer.

[0111] Then, a stack 210A is formed on the pre-source layer 200A, the stack 210A comprising a plurality of interlayer dielectric layers 212 and a plurality of gate sacrificial layers 214 alternately stacked therein. The interlayer dielectric layers 212 may be located at each of the bottommost and topmost layers of the stack 210A. The topmost interlayer dielectric layer 212 of the stack 210A may be formed to have a greater thickness than the other interlayer dielectric layers 212. The gate sacrificial layers 214 may be formed of a material having etch selectivity with the interlayer dielectric layers 212. Each of the interlayer dielectric layers 212 and the gate sacrificial layers 214 may comprise any one selected from the group consisting of oxide layers, nitride layers, and oxide-nitride layers. For example, the interlayer dielectric layer 212 may be formed of an oxide layer, and the gate sacrificial layer 214 may be formed of a nitride layer.

[0112] Then, a hard mask pattern (not shown) is formed on the stack 210A, and a plurality of vias 222 are formed by etching the stack 210A and the pre-source layer 200A using the hard mask pattern as an etching barrier. In the stack 210A, the vias 222 can be arranged in a matrix structure. Each via 222 can have a hole shape that passes through the stack 210A, the second source layer 206, and the source sacrificial layer 204, and has an end extending into the first source layer 202. Each via 222 can be a pattern with a high aspect ratio and has sloping sidewalls. The linewidth TD of the top inlet of the via 222 can be smaller than the linewidth BD of the bottom surface of the via 222. That is, each via 222 can have a trapezoidal cross-sectional shape in which the linewidth gradually decreases from the top inlet towards the bottom surface.

[0113] Although not shown in the figure, an isolation layer may be formed at least through the uppermost gate sacrificial layer 214 in the stack 210A before forming the channel via 222. That is, the isolation layer may be formed to isolate the uppermost gate sacrificial layer 214 in the stack 210A into at least two or more patterns. The isolation layer may correspond to... Figure 3 The first slit S1 is shown. The insulating layer may include a dielectric layer. For example, the insulating layer may be formed of an oxide layer.

[0114] Then, a memory layer 224 is formed along the surface of each channel hole 222. The memory layer 224 can be formed as a stack of a barrier layer 224A, a charge trapping layer 224B, and a tunnel dielectric layer 224C stacked sequentially. For example, the barrier layer 224A and the tunnel dielectric layer 224C can be formed of oxide layers, and the charge trapping layer 224B can be formed of a nitride layer.

[0115] Then, a semiconductor layer 226B having a first thickness t1 is formed on the memory layer 224 along the surface of each channel hole 222. The semiconductor layer 226B may have a cylindrical shape. The semiconductor layer 226B may be amorphous or polycrystalline and includes silicon. For example, the semiconductor layer 226B may be formed from a polycrystalline silicon layer.

[0116] The initial thickness t1 of the semiconductor layer 226B can be approximately two times or more greater than the target thickness of the ultimately retained channel. This is to facilitate increasing the grain size during subsequent crystallization annealing processes. For example, the semiconductor layer 226B can be formed with... to The first thickness t1.

[0117] like Figure 9B As shown, a crystallization annealing process is performed to increase the grain size within semiconductor layer 226B to form a crystalline semiconductor layer 226A. The crystallization annealing process can be performed at a temperature of 400°C to 800°C for four to eight hours. For example, the crystallization annealing process can be performed at 600°C.

[0118] like Figure 9C As shown, the channel layer 226 is formed by etching the crystallized semiconductor layer 226A to a second thickness t2 having a thickness less than the first thickness t1. At this time, either isotropic wet etching or isotropic dry etching can be performed as the etching process.

[0119] The second thickness t2 can be approximately half the first thickness t1. For example, when the first thickness t1 is... to When the range is within the specified range, the second thickness t2 can be... to Within the range.

[0120] When the thickness of the channel layer 226 is reduced to a second thickness t2 or less during the etching process, excessive surface defects such as pinholes may appear on the surface of the channel layer 226. Furthermore, the pre-source layer 200A may be damaged by the etchant used in the etching process. However, to ensure the operational characteristics of memory cell transistors in highly integrated semiconductor memory devices, the channel layer 226 needs to have the smallest possible thickness. Therefore, a method is needed that can stably reduce the thickness of the channel layer 226 to a second thickness t2 or less.

[0121] like Figure 9D As shown, a channel passivation layer 228 is formed on a portion of the surface of the channel layer 226. The channel passivation layer 228 may be formed of a silicon-containing dielectric layer. Specifically, the channel layer 226 may be divided into a first region R1 formed in the laminate 210A and a second region R2 formed in the pre-source layer 200A to abut against the first region R1. Due to the channel passivation layer 228, the channel layer 226 in the first region R1 may have a third thickness t3 that is less than the second thickness t2. For example, when the second thickness t2 is... to When the range is within the specified range, the third thickness t3 can be... to Within the range.

[0122] The channel passivation layer 228 can be used to stably reduce the thickness of the channel layer 226 and to remove surface defects such as pinholes by covering the grain boundaries exposed on the surface of the channel layer 226. For this role, the channel passivation layer 228 can be formed by radial oxidation at a temperature higher than the crystallization annealing temperature. That is, the channel passivation layer 228 can be formed by oxidizing a portion of the channel layer 226. For example, when the channel layer 226 is formed from a polycrystalline silicon layer, the channel passivation layer 228 can be formed by oxidizing the surface of the channel layer 226 using a large number of oxygen free radicals generated from a process gas mixed with hydrogen and oxygen. In this case, in order to easily generate a large number of oxygen free radicals and uniformly form the channel passivation layer 228 in the first region R1 of the channel layer 226, free radical oxidation can be performed at a temperature of 600°C to 800°C and a pressure of 0.1 Torr to 1 Torr. When the free radical oxidation temperature is below 600°C and the process pressure exceeds 1 Torr, oxygen free radicals may not reach the bottom of the channel hole 222, making it difficult to uniformly form the channel passivation layer 228 in the first region R1 of the channel layer 226. On the other hand, when the free radical oxidation temperature exceeds 800°C and the process pressure is below 0.1 Torr, it may be difficult to selectively form the channel passivation layer 228 only in the first region R1 of the channel layer 226.

[0123] Because the channel hole 222 has a high aspect ratio, the oxidant (i.e., oxygen free radicals) may not reach the bottom of the channel hole 222, resulting in the selective formation of the channel passivation layer 228 only in the channel layer 226 of the first region R1. Furthermore, the mixing ratio of hydrogen and oxygen, the process temperature, and the process pressure can be controlled to uniformly form the channel passivation layer 228 only in the channel layer 226 of the first region R1.

[0124] In the modified example, in order to selectively form the channel passivation layer 228 only in the first region R1 of the channel layer 226, the channel passivation layer 228 can be formed after a sacrificial layer (not shown) is formed to fill the bottom of the channel hole 222 with gaps. In this case, the sacrificial layer can be removed after the channel passivation layer 228 is formed.

[0125] The reason why the channel passivation layer 228 is not formed in the second region R2 of the channel layer 226, but only selectively formed in the first region R1 of the channel layer 226, is that the channel layer 226 in the second region R2 is used as the junction region of the source selection transistor. Specifically, since the channel layer 226 in the second region R2 is located at the bottom of the channel via 222 with a high aspect ratio, it is essentially impossible to form a junction region by ion implantation. The junction region is formed by diffusion from the third source layer 208 to be formed by subsequent processes. Therefore, when the channel passivation layer 228 is formed in the channel layer 226 in the second region R2, the thickness of the channel layer 226 used as the junction region may be reduced, thereby degrading the operational reliability of the semiconductor memory device.

[0126] like Figure 9E As shown, a core post 227 is formed on the channel layer 226 and the channel passivation layer 228 to fill the gap in the channel hole 222. The core post 227 may have a trapezoidal cross-sectional shape. The core post 227 may include any dielectric layer selected from the group consisting of oxide layers, nitride layers, and oxide nitride layers. For example, the core post 227 may include an oxide layer.

[0127] The recess is then formed by etching the top of the core post 227, and extended by etching the channel passivation layer 228 exposed on the side surface of the recess. The bottom surface of the recess may be aligned with the surface of the uppermost gate sacrificial layer 214 in the stack 210A, or may be located at a higher height than the surface of the gate sacrificial layer 214.

[0128] Then, a capping layer 229 is formed to fill the gap in the recess. The capping layer 229 can be used as the junction region of a drain-select transistor. Therefore, the capping layer 229 can be formed from a doped semiconductor layer 226B (e.g., an n-type doped silicon layer).

[0129] This allows the formation of a channel structure comprising a core post 227 extending in the third direction D3, a capping layer 229 formed on the core post 227, a channel layer 226 covering the side surface of the capping layer 229 and the side and bottom surfaces of the core post 227, a memory layer 224 covering the side and bottom surfaces of the channel layer 226, and a channel passivation layer 228 inserted between the core post 227 and the channel layer 226.

[0130] like Figure 9F As shown, a hard mask pattern (not shown) is formed on a stack 210A having multiple channel structures 220, and a slot trench 232 is formed by etching the stack 210A and the pre-source layer 200A using the hard mask pattern as an etching barrier. At this time, the slot trench 232 can be formed to expose the source sacrificial layer 204 through its bottom surface. The slot trench 232 can be formed as a linear pattern extending in the second direction D2.

[0131] Then, the gate sacrificial layer 214 is removed through the slit trench 232.

[0132] like Figure 9G As shown, the gaps in the gate conductive layer 216 are used to fill the spaces where the gate sacrificial layer 214 has been removed. The gate conductive layer 216 may include a metal conductive layer. For example, the gate conductive layer 216 may be formed of a tungsten layer. Alternatively, the gate conductive layer 216 may be formed as a stack of titanium nitride and tungsten layers.

[0133] In this way, a gate stack 210 can be formed, wherein multiple interlayer dielectric layers 212 and multiple gate conductive layers 216 are alternately stacked.

[0134] Then, an etching process is performed to isolate the gate conductive layer 216 on the third-direction D3, and a slit spacer 234 is formed on either side of the slit trench 232. The slit spacer 234 may be formed of a dielectric layer.

[0135] Then, the source sacrificial layer 204 of the pre-source layer 200A is removed through the slit spacer 234. Subsequently, the channel layer 226 is exposed by etching the memory layer 224 exposed as the source sacrificial layer 204 is removed.

[0136] like Figure 9H As shown, the space where the source sacrificial layer 204 has been removed is filled using the gap of the third source layer 208. The third source layer 208 is electrically connected to the channel layer 226. The third source layer 208 can be formed from a doped semiconductor layer 226B. For example, the third source layer 208 can be formed from an n-type doped silicon layer. In this case, the third source layer 208 can have a higher doping concentration than the first source layer 202 and the second source layer 206.

[0137] Then, a slit layer 236 is formed to fill the gap in the slit trench 232. The slit layer 236 may be formed of a conductive layer. In a modified example, the slit layer 236 may be formed of a dielectric layer.

[0138] In this way, a slit structure 230 can be formed, which includes a source layer 200, a slit trench 232, a slit spacer 234, and a slit layer 236. The source layer 200 includes a first source layer 202, a third source layer 208, and a second source layer 206 stacked sequentially.

[0139] Then, subsequent processes, including bit line formation, can be performed to complete the semiconductor memory device.

[0140] Figures 10A to 10D This is a cross-sectional view showing a method for manufacturing a semiconductor memory device according to an embodiment. Figures 10A to 10D This is a cross-sectional view illustrating a method for manufacturing a memory cell array of a semiconductor memory device. The following will refer to... Figures 10A to 10D The method for manufacturing the described memory cell array may include Figure 7 The steps S2 or shown Figure 8 In step S12 shown. For ease of description, ... Figures 9A to 9H The same components shown will be represented by similar labels, and their detailed descriptions will be omitted in this document.

[0141] like Figure 10A As shown, a stack 210A is formed on the pre-source layer 200A, the stack 210A including a plurality of interlayer dielectric layers 212 and a plurality of gate sacrificial layers 214 alternately stacked therein. Then, the stack 210A and the pre-source layer 200A are selectively etched to form a plurality of channel vias 222. Subsequently, a memory layer 224 is formed along the surface of each channel via 222.

[0142] Because the pre-source layer formation process, the stack formation process, the channel via formation process, and the memory layer formation process are carried out in accordance with reference to... Figure 9A The methods described are essentially the same, so a detailed description will be omitted in this article.

[0143] Then, a semiconductor layer 252B having a first thickness t1 is formed on the memory layer 224 along the surface of each channel hole 222. The semiconductor layer 252B may have a cylindrical shape. The semiconductor layer 252B may be amorphous or polycrystalline and includes silicon. For example, the semiconductor layer 252B may be formed from a polycrystalline silicon layer. The first thickness t1 may be... to Within the range.

[0144] Then, a crystal support layer 254 is formed on the semiconductor layer 252B. The crystal support layer 254 can be used as a seed layer for grain growth, thus making it easier to increase the grain size within the semiconductor layer 252B during subsequent crystallization annealing processes. For this purpose, the crystal support layer 254 can be formed from a silicon-containing dielectric layer. For example, the crystal support layer 254 can be formed from a silicon oxide layer using DCS (dichlorosilane).

[0145] The crystal support layer 254 can be formed at a temperature higher than the crystallization annealing temperature in subsequent processes. In this case, the crystal support layer 254 can be formed along the exposed surface of the semiconductor layer 252B. That is, the crystal support layer 254 formed at a temperature higher than the crystallization annealing temperature in subsequent processes can have a cylindrical shape.

[0146] In the modified example, the crystal support layer 254 can be formed at a temperature lower than the crystallization annealing temperature in subsequent processes. In this case, the crystal support layer 254 can be formed only on the surface of the semiconductor layer 252B in the middle and top of the channel hole 222, except for the bottom of the channel hole 222. That is, the crystal support layer 254 formed at a temperature lower than the crystallization annealing temperature in subsequent processes can have a tubular shape.

[0147] like Figure 10B As shown, a crystallization annealing process is performed to increase the grain size within the semiconductor layer 252B to form a crystalline semiconductor layer 252A. The crystallization annealing process can be performed at a temperature of 400°C to 800°C in a nitrogen atmosphere for four to eight hours. For example, the crystallization annealing process can be performed at 600°C. During this process, the crystallization support layer 254 serves as a seed layer to grow grains at the interface between the crystallization support layer 254 and the semiconductor layer 252A. Therefore, the grains within the semiconductor layer 252A adjacent to the memory layer 224 can be formed to have a larger size than the grains within the semiconductor layer 252A adjacent to the crystallization support layer 254.

[0148] like Figure 10C As shown, the channel layer 252 is formed by etching the crystalline semiconductor layer 252A to a second thickness t2 that is less than the first thickness t1. During the etching process of forming the channel layer 252, the crystalline support layer 254 can be removed along with a portion of the crystalline semiconductor layer 252A. At this time, isotropic wet etching or isotropic dry etching can be performed as the etching process. The second thickness t2 can be approximately half of the first thickness t1. For example, when the first thickness t1 is... to When the range is within the specified range, the second thickness t2 can be... to Within the range.

[0149] During the etching process used to form the channel layer 252, relatively large-sized grains in the semiconductor layer 252B can be retained, and relatively small-sized grains can be removed because the relatively small-sized grains are adjacent to the crystal support layer 254.

[0150] like Figure 10D As shown, a channel passivation layer 228 is formed in a portion of the surface of the channel layer 252. The channel passivation layer 228 may be formed of a silicon-containing dielectric layer. Specifically, the channel layer 252 may be divided into a first region R1 formed in the laminate 210A and a second region R2 formed in the pre-source layer 200A to abut against the first region R1. Due to the channel passivation layer 228, the channel layer 252 in the first region R1 may have a third thickness t3 that is less than the second thickness t2. For example, when the second thickness t2 is in to When the range is within the specified range, the third thickness t3 can be... to Within the range.

[0151] The channel passivation layer 228 can be used to stably reduce the thickness of the channel layer 252 and remove surface defects such as pinholes by covering the grain boundaries exposed on the surface of the channel layer 252. For this purpose, the channel passivation layer 228 can be formed by radial oxidation at a temperature higher than the crystallization annealing temperature. That is, the channel passivation layer 228 can be formed by oxidizing a portion of the channel layer 252. For example, when the channel layer 252 is formed from a polycrystalline silicon layer, the channel passivation layer 228 can be formed by oxidizing the surface of the channel layer 252 using a large number of oxygen free radicals generated from a process gas mixed with hydrogen and oxygen. In this case, in order to easily generate a large number of oxygen free radicals and uniformly form the channel passivation layer 228 in the first region R1 of the channel layer 252, free radical oxidation can be performed at a temperature of 600°C to 800°C and a pressure of 0.1 Torr to 1 Torr.

[0152] Subsequent processes can be carried out according to the reference. Figures 9E to 9H It is executed in the same manner as described.

[0153] Figures 11A to 11G This is a cross-sectional view showing a method for manufacturing a semiconductor memory device according to an embodiment. Figures 11A to 11G This is a cross-sectional view illustrating a method for manufacturing a memory cell array of a semiconductor memory device. The following will refer to... Figures 11A to 11G The method for manufacturing the described memory cell array may include Figure 7 The steps S2 or shown Figure 8 In step S12 shown. For ease of description, ... Figures 9A to 9H Components that are identical to those shown will be represented by similar labels, and their detailed descriptions will be omitted in this document.

[0154] like Figure 11A As shown, a stack 210A is formed on the pre-source layer 200A, the stack 210A including a plurality of interlayer dielectric layers 212 and a plurality of gate sacrificial layers 214 alternately stacked therein. Then, the stack 210A and the pre-source layer 200A are selectively etched to form a plurality of channel vias 222. Subsequently, a memory layer 224 is formed along the surface of each channel via 222.

[0155] Because the pre-source layer formation process, the stack formation process, the channel via formation process, and the memory layer formation process are carried out in accordance with reference... Figure 9A The process is essentially the same as described, so its detailed description will be omitted in this article.

[0156] Then, a first semiconductor layer 242B having a first thickness t1 is formed on the memory layer 224 along the surface of each channel hole 222. The first semiconductor layer 242B may have a cylindrical shape. The first semiconductor layer 242B may be amorphous or polycrystalline and includes silicon. For example, the first semiconductor layer 242B may be formed of a polycrystalline silicon layer.

[0157] Although not shown in the figure, a first crystalline support layer may be formed on the first semiconductor layer 242B. The first crystalline support layer may be formed from a silicon-containing dielectric layer. The first crystalline support layer may be formed in accordance with reference to... Figure 10A The crystalline support layer 254 described is formed in the same manner.

[0158] like Figure 11B As shown, a first crystallization annealing process is performed to increase the grain size within the first semiconductor layer 242B to form a crystalline first semiconductor layer 242A. The first crystallization annealing process can be performed for four to eight hours at a temperature of 400°C to 800°C in a nitrogen atmosphere. For example, the first crystallization annealing process can be performed at 600°C.

[0159] like Figure 11C As shown, a first thin film 242 is formed by etching a first crystalline semiconductor layer 242A to a second thickness t2 having a thickness less than a first thickness t1. As an etching process, isotropic wet etching or isotropic dry etching can be performed.

[0160] like Figure 11D As shown, a second semiconductor layer 244B having a third thickness t3 is formed on the surface of the first thin film 242 along the surface of each channel hole 222. The second semiconductor layer 244B may have a cylindrical shape. The second semiconductor layer 244B may be amorphous or polycrystalline and includes silicon. For example, the second semiconductor layer 244B may be formed of a polycrystalline silicon layer.

[0161] Although not shown in the figure, a second crystalline support layer may be formed on the second semiconductor layer 244B. The second crystalline support layer may be formed from a silicon-containing dielectric layer. The second crystalline support layer may be formed in accordance with reference to... Figure 10A The crystalline support layer 254 described is formed in the same manner.

[0162] like Figure 11E As shown, a second crystallization annealing process is performed to increase the grain size within the second semiconductor layer 244B to form a crystalline second semiconductor layer 244A. The second crystallization annealing process can be performed for four to eight hours at a temperature of 400°C to 800°C in a nitrogen atmosphere. For example, the second crystallization annealing process can be performed at 600°C.

[0163] During the second crystallization annealing process, the crystallized first thin film 242 can be used as a seed layer to grow grains within the second semiconductor layer 244A, which allows for a more efficient increase in grain size. Furthermore, the grain size within the first thin film 242 can be further increased during the second crystallization annealing process.

[0164] like Figure 11F As shown, a second thin film 244 is formed by etching the crystallized second semiconductor layer 244A to a fourth thickness t4 having a thickness less than the third thickness t3. As an etching process, isotropic wet etching or isotropic dry etching can be performed.

[0165] Thus, a channel layer 240 can be formed, wherein a first thin film 242 having a second thickness t2 and a second thin film 244 having a fourth thickness t4 are stacked. The channel layer 240 may have a fifth thickness t5 corresponding to the sum of the second thickness t2 and the fourth thickness t4.

[0166] In this embodiment, the channel layer 240 is formed by repeatedly performing a semiconductor layer deposition process, a crystallization annealing process, and an etching process twice. However, the embodiment is not limited to this. In a modified example, the channel layer 240 can be formed by repeatedly performing the semiconductor layer deposition process, the crystallization annealing process, and the etching process two or more times.

[0167] like Figure 11G As shown, a channel passivation layer 228 is formed in a portion of the surface of the channel layer 240. Specifically, the channel layer 240 can be divided into a first region R1 formed in the laminate 210A and a second region R2 formed in the pre-source layer 200A to abut against the first region R1. Due to the channel passivation layer 228, the channel layer 240 in the first region R1 can have a sixth thickness t6 that is less than the fifth thickness t5. The channel passivation layer 228 can be formed of a silicon-containing dielectric layer.

[0168] The channel passivation layer 228 can be used to stably reduce the thickness of the channel layer 240 and remove surface defects such as pinholes by covering the grain boundaries exposed on the surface of the channel layer 240. For this purpose, the channel passivation layer 228 can be formed by radial oxidation at a temperature higher than the crystallization annealing temperature. That is, the channel passivation layer 228 can be formed by oxidizing a portion of the channel layer 240. For example, when the channel layer 240 is formed from a polycrystalline silicon layer, the channel passivation layer 228 can be formed by oxidizing the surface of the channel layer 240 using a large number of oxygen free radicals generated from a process gas mixed with hydrogen and oxygen. In this case, in order to easily generate a large number of oxygen free radicals and uniformly form the channel passivation layer 228 in the first region R1 of the channel layer 240, free radical oxidation can be performed at a temperature of 600°C to 800°C and a pressure of 0.1 Torr to 1 Torr.

[0169] Subsequent processes can be carried out according to the reference. Figures 9E to 9H It is executed in the same manner as described.

[0170] Figure 12 This is a block diagram illustrating the configuration of a memory system according to an embodiment.

[0171] like Figure 12 As shown, the memory system 1100 includes a memory device 1120 and a memory controller 1110.

[0172] Memory device 1120 may include a gate stack and a plurality of channel structures. The gate stack may be formed on a source layer and includes a plurality of interlayer dielectric layers and a plurality of gate conductive layers alternately stacked therein. The plurality of channel structures may be formed through the gate stack and each has a lower end extending into the source layer. Each channel structure may include a channel layer and a channel passivation layer. The channel layer may have a first region formed in the gate stack and a second region formed in the source layer to abut against the first region, and the channel passivation layer may be formed in the first region of the channel layer. The channel layer in the first region may have a smaller thickness than the channel layer in the second region. The channel passivation layer included in memory device 1120 may improve the operational reliability of memory device 1120.

[0173] The memory device 1120 may be a multi-chip package consisting of multiple flash memory chips.

[0174] The storage controller 1110 is configured to control the memory device 1120 and includes an SRAM (Static Random Access Memory) 1111, a CPU (Central Processing Unit) 1112, a host interface 1113, an error correction block 1114, and a memory interface 1115. The SRAM 1111 serves as the working memory of the CPU 1112, which performs overall control operations on data exchange with the storage controller 1110. The host interface 1113 may include a data exchange protocol for a host connected to the memory system 1100. The error correction block 1114 detects and corrects errors contained in data read from the memory device 1120, and the memory interface 1115 interfaces with the memory device 1120. Additionally, the storage controller 1110 may include a ROM (Read-Only Memory) configured to store code data for interfacing with the host.

[0175] Figure 13 This is a block diagram illustrating the configuration of a computing system according to an embodiment.

[0176] like Figure 13 As shown, the computing system 1200 may include a CPU 1220, RAM (random access memory) 1230, a user interface 1240, a modem 1250, and a memory system 1210 electrically connected to a system bus 1260. The computing system 1200 may be a mobile device.

[0177] Memory system 1210 may include memory device 1212 and memory controller 1211. Memory device 1212 may include a gate stack and a plurality of channel structures. The gate stack may be formed on a source layer and includes a plurality of interlayer dielectric layers and a plurality of gate conductive layers alternately stacked therein, and the plurality of channel structures may be formed through the gate stack and each has a lower end extending into the source layer. Each channel structure may include a channel layer and a channel passivation layer. The channel layer may have a first region formed in the gate stack and a second region formed in the source layer to abut the first region, and the channel passivation layer may be formed in the first region of the channel layer. The channel layer in the first region may have a smaller thickness than the channel layer in the second region. The channel passivation layer included in memory device 1212 may improve the operational reliability of memory device 1212.

[0178] Although various embodiments have been described above, those skilled in the art will understand that the described embodiments are merely examples. Therefore, the semiconductor memory devices and manufacturing methods described herein should not be limited to the described embodiments.

[0179] Cross-reference to related applications

[0180] This application claims priority to Korean Application No. 10-2021-0018105, filed with the Korean Intellectual Property Office on February 9, 2021, the entirety of which is incorporated herein by reference.

Claims

1. A semiconductor memory device, the semiconductor memory device comprising: A core post that extends in the vertical direction; A channel layer having a first region covering a portion of the side surface of the core post and a second region covering another portion of the side surface of the core post and the bottom surface of the core post, the second region abutting against the first region; as well as A channel passivation layer is formed in the first region of the channel layer and abuts against the core post. The core pillar corresponding to the first region and the core pillar corresponding to the second region are integrally formed, and A portion of the side surface of the core post and another portion of the side surface of the core post are continuously formed.

2. The semiconductor memory device according to claim 1, wherein, The channel layer in the first region has a thickness smaller than that in the second region.

3. The semiconductor memory device according to claim 1, wherein, The core post has a trapezoidal cross-sectional shape.

4. The semiconductor memory device according to claim 1, wherein, The channel layer has a cylindrical shape, the channel layer in the first region has a tubular shape, and the channel layer in the second region has a cylindrical shape.

5. The semiconductor memory device according to claim 1, wherein, The channel layer includes a polysilicon layer, the channel passivation layer includes a silicon oxide layer formed by oxidizing the channel layer, and the core includes a dielectric material.

6. A semiconductor memory device, the semiconductor memory device comprising: A gate stack formed on a source layer and having a plurality of interlayer dielectric layers and a plurality of gate conductive layers alternately stacked therein; as well as Multiple channel structures are formed through the gate stack, and each of the multiple channel structures has a lower end extending into the source layer. Each of the aforementioned channel structures includes: A core post that extends in the vertical direction; A channel layer having a first region formed in the gate stack and a second region formed in the source layer to abut the first region; and A channel passivation layer is formed in the first region of the channel layer. The first region of the channel layer covers a portion of the side surface of the core post, and the second region of the channel layer covers another portion of the side surface of the core post and the bottom surface of the core post. The core pillar corresponding to the first region and the core pillar corresponding to the second region are integrally formed, and A portion of the side surface of the core post and another portion of the side surface of the core post are continuously formed.

7. The semiconductor memory device according to claim 6, wherein, Each of the aforementioned channel structures also includes: A capping layer is formed above the core post; and A memory layer that covers the channel layer and abuts the gate stack and the source layer.

8. The semiconductor memory device according to claim 7, wherein, The channel layer covers the side surface of the capping layer and is electrically connected to the capping layer.

9. The semiconductor memory device according to claim 7, wherein, The channel passivation layer is inserted between the channel layer and the core post, and has one end that abuts against the bottom surface of the capping layer.

10. The semiconductor memory device according to claim 7, wherein, The memory layer comprises a stack of layers consisting of a blocking layer, a charge trapping layer, and a tunnel dielectric layer stacked sequentially.

11. The semiconductor memory device according to claim 6, wherein, The sum of the thickness of the channel layer in the first region and the thickness of the channel passivation layer is equal to or greater than the thickness of the channel layer in the second region.

12. The semiconductor memory device according to claim 6, wherein, Each of the aforementioned channel structures has a trapezoidal cross-sectional shape.

13. The semiconductor memory device according to claim 6, wherein, The channel layer has a cylindrical shape, the channel layer in the first region has a tubular shape, and the channel layer in the second region has a cylindrical shape.

14. The semiconductor memory device according to claim 6, wherein, The channel layer includes a polysilicon layer, and the channel passivation layer includes a silicon oxide layer formed by oxidizing the channel layer.

15. The semiconductor memory device according to claim 6, wherein, The source layer includes a stack of multiple conductive layers therein, and any one of the multiple conductive layers is electrically connected to the channel layer.

16. A method for manufacturing a semiconductor memory device, the method comprising the following steps: A stack is formed on the source layer by alternately stacking multiple interlayer dielectric layers and multiple gate sacrificial layers; Multiple channel holes are formed through the stack, each of the multiple channel holes having a lower end extending into the source layer; A channel layer is formed along the surface of the channel hole, the channel layer including a first region formed in the laminate and a second region formed in the source layer; as well as A channel passivation layer is formed in the first region to reduce the thickness of the channel layer in the first region. The method further includes the following steps: forming a sacrificial layer on the channel layer in the second region before forming the channel passivation layer, wherein the sacrificial layer is removed after forming the channel passivation layer.

17. The method of claim 16, further comprising the step of: Prior to forming the semiconductor layer, a memory layer is formed on the side and bottom surfaces of the channel via, wherein the memory layer is formed as a stack of barrier layers, charge trapping layers and tunnel dielectric layers.

18. The method of claim 16, further comprising the step of: After the channel passivation layer is formed, core pillars are formed on the channel passivation layer and the channel layer, such that the gap between the core pillars fills the channel hole; The recess is formed by etching the top of the core post; The recess is extended by etching the channel passivation layer exposed on the side surface of the recess; as well as A capping layer is formed, which fills the gaps in the expanded depressions and is electrically connected to the channel layer.

19. The method of claim 16, wherein, The steps for forming the channel layer include the following: A semiconductor layer having a first thickness is formed along the surface of the channel hole; A crystalline semiconductor layer is formed by performing a crystallization annealing process; and The crystalline semiconductor layer is etched to have a second thickness that is less than the first thickness. The steps of forming the semiconductor layer, the crystallization annealing process, and the etching process are performed repeatedly once or more.

20. The method of claim 19, further comprising the step of: Prior to performing the crystallization annealing process, a crystallization support layer is formed on the semiconductor layer, wherein the crystallization support layer is removed in the step of etching the crystallized semiconductor layer to have the second thickness.

21. The method according to claim 20, wherein, The semiconductor layer includes an amorphous silicon layer or a polycrystalline silicon layer, and the crystalline support layer includes a silicon-containing dielectric layer.

22. The method according to claim 16, wherein, The channel passivation layer is formed by selectively oxidizing the surface of the channel layer in the first region through free radical oxidation.

23. The method according to claim 22, wherein, The channel layer includes a polysilicon layer, and the channel passivation layer includes a silicon oxide layer.

24. The method of claim 16, wherein, The channel passivation layer is formed by free radical oxidation using oxygen free radicals generated from a process gas mixed with hydrogen and oxygen, and the channel passivation layer is at 600 C to 800 It is formed at a temperature of C and a pressure of 0.1 Torr to 1 Torr.

25. The method according to claim 16, wherein, After the channel passivation layer is formed, the channel layer in the first region has a thickness smaller than that in the second region.

26. The method of claim 16, wherein, The channel layer has a cylindrical shape, the channel layer in the first region has a tubular shape, the channel layer in the second region has a cylindrical shape, and the channel passivation layer has a tubular shape.

27. The method according to claim 16, wherein, Each of the aforementioned channel holes has inclined sidewalls and a trapezoidal cross-sectional shape, wherein the top inlet of the trapezoidal cross-sectional shape has a linewidth greater than the linewidth of the bottom surface of the trapezoidal cross-sectional shape.

28. The method of claim 16, further comprising the step of: A sacrificial layer is formed to fill the bottom of the channel hole with gaps before the channel passivation layer is formed, the channel passivation layer is formed, and then the sacrificial layer is removed.

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