Image sensor pixels and their manufacturing methods

Abstract

This disclosure provides a method for optically shielding a charge storage device (CSD) of an image sensor pixel, the image sensor pixel comprising a photosensitive device and a CSD, and a dielectric layer covering the photosensitive device and the CSD. The method includes: performing etching of the dielectric layer to define an undercut block beneath the dielectric layer and an access opening extending through the dielectric layer to the undercut block; and performing physical vapor deposition (PVD) of a light-blocking material to perform two operations: filling the undercut block with the light-blocking material to form a light-blocking layer covering the CSD, and filling the access opening with the light-blocking material to form a light-blocking plug. Image sensor pixels formed by this process and image sensors comprising arrays of image sensor pixels are also disclosed.

Description

Technical Field

[0001] This disclosure relates to an image sensor pixel and a method for providing optical shielding for a charge storage device of the image sensor pixel. Background Technology

[0002] The following text relates to image sensor pixels and methods for manufacturing image sensor pixels, and to image sensors including such image sensor pixels, and to related technologies. Summary of the Invention

[0003] One embodiment of this disclosure provides a method for providing light shielding for a charge storage device of an image sensor pixel. The method includes: providing a photosensitive device and the charge storage device, and a dielectric layer covering the photosensitive device and the charge storage device; performing etching of the dielectric layer to define an undercut block beneath the dielectric layer and an access opening through the dielectric layer to the undercut block; and performing physical vapor deposition (PVD) of a light-blocking material to perform two operations: filling the undercut block with the light-blocking material to form a light-blocking layer covering the charge storage device, and filling the access opening with the light-blocking material to form a light-blocking plug.

[0004] Another embodiment of this disclosure provides an image sensor pixel, including: a photosensitive device; a charge storage device; a light-blocking layer disposed above the charge storage device; a light-blocking plug disposed above the charge storage device; and a dielectric layer disposed above the light-blocking layer; wherein the light-blocking plug passes through the dielectric layer and contacts the light-blocking layer.

[0005] Another embodiment of this disclosure provides an image sensor device, including: a charge storage device; a light-blocking layer disposed above the charge storage device; a dielectric layer disposed above the light-blocking layer; and a light-blocking plug disposed above the charge storage device and passing through the dielectric layer to provide electrical access to the charge storage device; wherein the light-blocking layer and the light-blocking plug have a continuous structure. Attached Figure Description

[0006] When read in conjunction with the accompanying drawings, aspects of this disclosure will be better understood in the following detailed description. It should be noted that, in accordance with industry standard practice, the features are not drawn to scale. In fact, the dimensions of the features may be arbitrarily increased or decreased for clarity of explanation.

[0007] Figure 1A The image sensor and image sensor pixels of the image sensor according to some embodiments disclosed herein are illustrated in the diagram. Figure 1B Diagrammatically shown Figure 1A The simplified physical layout of the photodetector and charge storage device of the image sensor pixels.

[0008] Figure 2 The image acquisition method is illustrated in the diagram, which is appropriately performed by an image sensor, including, as shown in the diagram. Figure 1A and Figure 1B The image sensor pixel array described in the paper.

[0009] Figure 3 The image sensor pixels according to an illustrative embodiment are illustrated.

[0010] Figure 4A , Figure 4B , Figure 4C as well as Figure 4D The illustration depicts manufacturing processes according to some manufacturing method embodiments. Figure 3 The continuous operation in the method of image sensor pixels.

[0011] Figure 5 An illustrative embodiment of a light-blocking material comprising a Ti / TiN / W multilayer is illustrated in the diagram. Figure 4C Gas flow rate during operation.

[0012] Figure 6A and Figure 6B The diagram illustrates the corresponding Figure 5 Poor Ti / TiN / W multilayer deposition in instances of abnormal gas flow. Detailed Implementation

[0013] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. These components and arrangements are, of course, merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature may be formed between the first and second features such that the first and second features are not in direct contact. Additionally, reference numerals and / or letters may be repeated in various instances in this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0014] Furthermore, for ease of description, spatial relative terms such as “beneath,” “below,” “lower,” “above,” “upper,” and similar terms may be used herein to describe the relationship between one element or feature and another element or feature as illustrated in the figures. In addition to the orientations depicted in the figures, spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein shall be interpreted accordingly.

[0015] refer to Figure 1A The image sensor 10 includes an array of image sensor pixels 12, wherein in Figure 1A The main diagram illustrates a circuit schematic of an image sensor pixel 12. The illustrative image sensor pixel 12 includes a shutter gate transistor SHG 32, a photosensitive device 14, a first transfer gate transistor TG1 34, a charge storage device 16, and a readout circuit 18. The shutter gate transistor SHG 32 is coupled to the photosensitive device 14. In some embodiments, the source or drain of the shutter gate transistor SHG 32 is coupled to a voltage V. aa The photocharge accumulated in the photosensitive device 14 is selectively depleted. A first transfer gate transistor TG134 is located between the photosensitive device 14 and the charge storage device 16. In some embodiments, the first transfer gate transistor TG134 is capable of controlling the transfer of photocharge accumulated in the photosensitive device 14 to the charge storage device 16. The readout circuit 18 is sometimes also referred to as the drive circuit (readout circuit) 18. The readout circuit 18 includes a second transfer gate transistor TG236, a floating diffusion region FD, a reset transistor RST, a source follower transistor SF, and a row select transistor RS. In some embodiments, the second transfer gate transistor TG236 is coupled to the output of the charge storage device 16. In some embodiments, the floating diffusion region FD is referred to as the readout node. Figure 1A As shown, the reset transistor RST is coupled to the floating diffusion region FD and the voltage V. pix Furthermore, the source follower transistor SF is coupled to the floating diffusion region FD and the voltage V. aaThe row select transistor RS is coupled to the source follower transistor SF. In some embodiments, the other end of the row select transistor RS may be coupled to a readout column line (not shown) to selectively output image data Pixout. The photosensitive device 14 may, for example, include an illustrative photodiode (photosensitive device) 14, such as a PN junction photodiode formed by a first N-type doped region 20 and a second P-type doped region 22 (or vice versa). The illustrative photodiode is merely an example, and other types of photosensitive devices, such as phototransistors, may be used. The illustrative charge storage device 16 also includes a PN junction formed by a first N-type doped region 24 and a second P-type doped region 26 (or vice versa, i.e., the photodiode may typically be an NP diode or a PN diode). In some embodiments, first doped regions 20 and 24 of the respective photodiode (photosensitive device) 14 and charge storage device 16 are formed simultaneously, for example, during ion implantation or dopant diffusion steps or by epitaxial deposition, and similarly, second doped regions 22 and 26 of the respective photodiode (photosensitive device) 14 and charge storage device 16 can be formed simultaneously. However, this is merely an illustrative example, and in other embodiments, the first doped region 20 and 24 are formed in separate operations, and similarly, the second doped region 22 and 26 are formed in separate operations.

[0016] Figure 1B Another schematic representation of the image sensor pixel 12 is shown, also depicting the photosensitive element 14 and the charge storage device 16, but omitted. Figure 1B The readout circuit 18 and some other electronic components are used to focus on the basic pixel layout. For example... Figure 1B As seen, image sensor pixels 12 are fabricated on and / or in a semiconductor substrate material 28 (e.g., an illustrative silicon substrate or layer (semiconductor substrate material) 28). In some embodiments, image sensor pixels 12 are fabricated on a substrate silicon wafer or substrate (semiconductor substrate material) 28 using complementary metal-oxide-semiconductor (CMOS) technology, but other designs are covered, such as image sensors based on charge-coupled devices (CCDs) or image sensors formed on GaAs or other types of substrate semiconductors. In a typical layout, image sensor 10 is fabricated on a silicon wafer or other semiconductor wafer, and although Figure 1AThe illustrative image sensor 10 includes a 16×16 pixel array, but more generally, for some image sensors used in digital cameras or industrial imaging devices, image sensors may contain much larger pixel arrays, such as those in the megapixel range. Furthermore, pixels may be arranged above geometric regions of a different type than the illustrative square area, and / or pixels may optionally be arranged with... Figure 1A The pixels shown are arranged differently in the usual rows and columns. Figure 1B In an illustrative example, isolation region 30 (e.g., manufactured as a shallow trench isolation (STI) region) provides isolation between adjacent image sensor pixels 12 of image sensor 10.

[0017] Continue to refer to Figure 1A and Figure 1B And further reference Figure 2 A typical image acquisition sequence includes operation S1: light measurement begins by simultaneously resetting all image sensor pixels 12 of the image sensor 10 using a global shutter signal transmitted to each image sensor pixel 12 via shutter gate transistor SHG 32, thereby initiating the exposure of the image sensor. In operation S2, during the exposure time interval (e.g., set by the shutter speed in the case of a digital camera), photocharge accumulates at each image sensor pixel 12, and more specifically, at the photodiode (photosensitive device) 14 of each image sensor pixel 12. At the end of the exposure, in operation S3, the accumulated photocharge in the photodiode (photosensitive device) 14 of each image sensor pixel 12 is transferred to the charge storage device 16 of the image sensor pixel 12 via a first transfer gate transistor TG1 34. In operation S4, the readout circuit 18 of each image sensor pixel 12 reads the charge stored in the charge storage device 16 via a second transfer gate transistor TG2 36. Advantageously, since the accumulated photocharge is transferred to the charge storage device 16, the image is fixed at the end of operation S3, and the readout operation S4 may take additional time or process some pixels sequentially, for example, by sequentially reading the charge from the charge storage device 16 of a row of pixels in one manner. It should be understood that the illustrative readout circuit 18 is merely a schematic example, and the detailed readout circuit may vary depending on the design of the image sensor 10. Furthermore, the image sensor 10 may include a large number of other components not shown, such as red, green, and blue filters for pixels in the case of a panchromatic image sensor, a mechanical shutter for enhancing the described electronic shutter, on-chip exposure metering and / or image processing circuitry, etc.

[0018] In some non-limiting illustrative embodiments, the image sensor 10 is implemented as a CMOS image sensor with a global shutter. In this embodiment, as referenced... Figure 2The described image acquisition is performed, and operations S1 and S3 implement a global shutter by ensuring that the initial exposure of all image sensor pixels 12 of the image sensor 10 is simultaneously stopped from accumulating photocharge. In other embodiments, the image sensor 10 may employ another type of shutter implementation, such as a rolling shutter, where there may be a time delay between the reset and readout of consecutive rows of pixels.

[0019] Regardless of the detailed design and shutter implementation, the charge storage device 16 and associated electronics (e.g., the first transfer gate transistor TG1 34) provide a way to precisely stop exposure and temporarily store the photocharge accumulated in the photodiode (photosensitive device) 14 without further charge accumulation to allow for subsequent readout. To provide a compact layout for the image sensor 10 and minimize any photocharge loss during charge transfer, the charge storage device 16 for each image sensor pixel 12 is physically positioned close to the photodiode (photosensitive device) 14 in the device layout, for example, both are positioned within a designated pixel area. However, if the charge storage device 16 is of a light-sensitive type, any exposure to the charge storage device 16 will result in a measured accumulated charge greater than the photocharge accumulated by the photodiode (photosensitive device) 14 during exposure operation S2. As described above, in some embodiments, first doped regions 20 and 24 of the corresponding photodiode (photosensitive device) 14 and charge storage device 16 are formed simultaneously, and similarly, second doped regions 22 and 26 of the corresponding photodiode (photosensitive device) 14 and charge storage device 16 are formed simultaneously. Therefore, in these embodiments, the charge storage device 16 has photosensitivity comparable to that of the photodiode (photosensitive device) 14. Even with different manufacturing processes used for the charge storage device 16, generally any PN junction and many transistor designs are photosensitive and will accumulate photocharge when exposed to light.

[0020] Therefore, to prevent the charge storage device 16 from being exposed to light, a light-blocking shield or layer (light-blocking layer) 40 is placed above the charge storage device 16. However, forming the light-blocking shield or layer (light-blocking layer) 40 can be challenging. It is worth noting that, in addition to the light-blocking layer 40, an electrical path (light-blocking plug) 42 to the charge storage device 16 should be provided, such as... Figure 1A The diagram is drawn in Chinese.

[0021] For reference Figure 3This describes an implementation of a light-blocking layer 40 and an electrical path (light-blocking plug) 42 according to one embodiment. In this embodiment, the electrical path 42 is implemented as a light-blocking plug 42. Advantageously, the light-blocking layer 40 is not separated from the light-blocking plug 42 by a gap. This contrasts with some other designs in which an annular gap may surround the light-blocking plug. The light-blocking layer 40 and the light-blocking plug 42 are suitably made of metal or other light-absorbing materials that absorb light L detected by the photosensitive device 14, such as... Figure 3 The illustration is shown in Chinese. (See description (see...)) Figures 4A to 4D (As discussed in the relevant discussion), the light-blocking layer 40 and the light-blocking plug 42 can be formed together as a single integral structure. Therefore, in some embodiments, the light-blocking layer 40 and the light-blocking plug 42 can be made of the same material.

[0022] In a non-restrictive illustrative example, Figure 3 The light-blocking layer 40 may comprise a metal, such as a titanium / titanium nitride / tungsten (Ti / TiN / W) multilayer. A dielectric layer (ILD layer) 44 is disposed above the light-blocking layer 40, and a light-blocking plug 42 extends through the ILD layer 44 to provide electrical access to the charge storage device 16. The dielectric layer (ILD layer) 44 is often referred to as an interlayer dielectric (ILD) layer 44 because it is typically used to separate different functional layers and / or interconnect layers throughout the image sensor 10. Optionally, at least one contact etch stop layer (CESL) 46 may be deposited to serve as an etch stop in certain process steps. Figure 3 In this embodiment, the light-blocking plug 42 also passes through the CESL 46 to directly contact the underlying charge storage device 16; however, if the CESL 46 is thin enough, then in some embodiments, the light-blocking plug 42 can make electrical contact through the CESL 46.

[0023] As mentioned, in Figure 3 In this embodiment, the light-blocking layer 40 is not separated from the light-blocking plug 42 by any gap. In fact, the light-blocking layer 40 and the light-blocking plug 42 are a continuous structure made of a single material. For example, in one embodiment, the single material includes multiple layers of Ti / TiN / W.

[0024] Figure 3 The implementation of the light-blocking layer 40 and the light-blocking plug 42 has certain advantages. One advantage is that... Figure 3 The method eliminates the gap between the light-blocking plug 42 and the light-blocking layer 40. This gap will provide a light leakage path through which a portion of the light L can illuminate the underlying charge storage device 16. This will cause undesirable additional photocharge to form in the charge storage device 16. For example, refer to Figure 2Ideally, no charge should accumulate in the charge storage device 16 during the exposure time of step S2. However, if light leakage occurs through the gap between the light-blocking layer 40 and the light-blocking plug 42, some charge will accumulate in the charge storage device 16 during step S2. When the photoelectric charge accumulated in the photosensitive device 14 is transferred to the charge storage device 16 in step S3, the light leakage through this gap between the light-blocking layer and the plug will result in an excess of charge stored in the charge storage device 16—that is, the stored charge will be the sum of the photoelectric charge accumulated in the photosensitive device 14 during the exposure time and the photoelectric charge accumulated in the charge storage device 16 during the exposure time. Furthermore, unless the mechanical shutter physically blocks light L from reaching the image sensor pixel 12, the photoelectric charge in the charge storage device 16 will continue to increase during the subsequent readout operation S4 due to the continuous light leakage through this gap.

[0025] On the contrary, Figure 3 In this embodiment, there is no gap between the light-blocking layer 40 and the light-blocking plug 42, because in Figure 3 In this embodiment, the light-blocking layer 40 and the light-blocking plug 42 are continuous structures without gaps between them. This eliminates unwanted charge accumulation in the charge storage device 16 during operation S2 (and also during operation S4 if the mechanical shutter does not physically block the light L).

[0026] Those skilled in the art will first consider that the seamless contact between the light-blocking layer 40 and the light-blocking plug 42 could adversely affect the electrical operation of the charge storage device 16, because if the single material forming the continuous structure were a metal or other conductive material, then the light-blocking layer 40 would be in electrical contact with the light-blocking plug 42, which provides electrical access to the charge storage device 16. However, it should be recognized herein that the light-blocking layer 40 is electrically isolated by the ILD layer 44 (and optionally also by the underlying CESL 46 and / or silicon substrate or layer (semiconductor substrate material) 28). Therefore, such electrical contact between the light-blocking layer 40 and the light-blocking plug 42 is not problematic.

[0027] Figure 3 Another advantage of implementing the light-blocking layer 40 and the light-blocking plug 42 is that it can be carried out efficiently. Figure 3 This is because it requires fewer manufacturing steps than forming the light-blocking layer 40 and the light-blocking plug 42 separately.

[0028] refer to Figures 4A to 4D Description of the manufacturing Figure 3 An embodiment of the manufacturing process for the light-blocking layer 40 and the light-blocking plug 42. Since the focus of this manufacturing process is on the light-blocking components 40 and 42, therefore... Figures 4A to 4DThe charge storage device 16 is shown, but the photosensitive device 14 or other components of the image sensor pixel 12 are not shown. Figure 4A A charge storage device 16 is depicted on a semiconductor substrate material 28, with CESL 46 and ILD layer 44 deposited. The fabrication of these features is not described. Generally, the charge storage device 16 can be fabricated using any method suitable for the type of charge storage device employed (e.g., ion implantation, dopant diffusion, epitaxial deposition, etc., for forming the first doped region 24 and the second doped region 26, see [reference]). Figure 1A The CESL 46 is fabricated on a semiconductor substrate material 28 by means of a non-limiting illustrative example, including the deposition of a metal or other conductive layer forming the gate electrode. The optional CESL 46 may include silicon nitride, carbon-doped silicon nitride, or a combination thereof. The optional CESL 46 may be deposited using, for example, chemical vapor deposition (CVD), high-density plasma (HDP) CVD, sub-atmospheric CVD (SACVD), molecular layer deposition (MLD), or other suitable methods to serve as an etch stop in certain process steps. The ILD layer 44 may comprise silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), spin-on glass (SOG), fluorinated silica glass (FSG), carbon-doped silicon oxide (e.g., SiCOH), polyimide, low-k dielectric materials (e.g., degel, aerogel, amorphous fluorinated carbon, parylene, bis-benzocyclobutene (BCB), hydrogen silsesquioxane (HSQ), or fluorinated silicon oxide (SiOF)) and / or various combinations thereof. In some embodiments, the ILD layer 44 is formed to a suitable thickness by flowable CVD (FCVD), CVD, HDPCVD, SACVD, spin coating, sputtering, or other suitable methods.

[0029] exist Figures 4A to 4D In the process, the ILD layer 44 is formed as a first ILD layer 441 and a second ILD layer 442 deposited on top of the first ILD layer 441. The second ILD layer 442 is deposited prior to any etching that forms the light-blocking layer 40 or the light-blocking plug 42, such as... Figure 4AAs seen in the illustration. In this example, the first (lower) ILD layer 441 and the second (upper) ILD layer 442 are made of different materials. (See reference...) Figure 4C The description states that providing ILD layer 44 as two different first ILD layers 441 and second ILD layers 442 of two different materials allows for selective etching of the first (lower) ILD layer 441 to undercut the second (upper) ILD layer 442, thereby opening space for the subsequent formation of a light-blocking layer 40 beneath the second (upper) ILD layer 442. In a non-limiting illustrative example, the first (lower) ILD layer 441 comprises a BPSG layer (first ILD layer) 441, and the second (upper) ILD layer 442 comprises a PE-TEOS layer (second ILD layer) 442. These are merely illustrative examples.

[0030] refer to Figure 4B and Figure 4C Selective etching operations are performed to open continuous blocks (sub-blocks 60 and 62) in the ILD layer 44. This continuous block includes sub-blocks 60 and 62, which include an undercut sub-block 60 corresponding to a block of the light-blocking layer 40 and a sub-block 62 including an access opening corresponding to a block of the light-blocking plug 42. In an illustrative example, a first etching operation is performed through the upper ILD layer (second ILD layer) 442 (e.g., in some embodiments, a PE-TEOS layer) and through the lower ILD layer (first ILD layer) 441 (e.g., in some embodiments, a BPSG layer) and optionally CESL 46 to form an opening 64 penetrating into the charge storage device 16, such as... Figure 4B As illustrated in the figure. This opening 64 corresponds to the portion of the access opening (sub-block) 62 and sub-block 60 directly below the access opening (sub-block) 62. In an alternative embodiment, if the CESL 46 is thin enough that it does not introduce excessively high resistance between the light-blocking plug 42 and the electrodes of the charge storage device 16, then the opening 64 is not expected to penetrate the CESL 46. Photolithographic patterning can be used to selectively etch to form the access opening (sub-block) 62. The etchant (if to be etched) is appropriately selected based on the type of materials constituting the lower ILD layer (first ILD layer) 441 and the upper ILD layer (second ILD layer) 442 and the CESL 46. It is worth noting that the upper portion of the opening 64 corresponds to the sub-block 62, which includes the access opening corresponding to the block of the light-blocking plug 42.

[0031] After that, as Figure 4C As illustrated, a second etching operation is performed to extend the [etching process]. Figure 4BThe opening 64 formed in the first etching creates an undercut volume 60 corresponding to the volume of the light-blocking layer 40. The second etching is highly selective for etching the lower ILD layer (first ILD layer) 441 (e.g., BPSG) relative to the upper ILD layer (second ILD layer) 442 (e.g., PE-TEOS), to create an undercut while leaving overhanging ILD regions 68, such as... Figure 4C As indicated in the document. These overhanging ILD regions 68 ensure that the light-blocking layer 40 subsequently formed will be embedded within the ILD layer 44 (and more specifically, in this embodiment, by the upper ILD layer (second ILD layer) 442).

[0032] In a non-limiting illustrative embodiment, the lower ILD layer 441 (first ILD layer) includes BPSG and the upper ILD layer (second ILD layer) 442 includes PE-TEOS. Figure 4B and Figure 4C The etching is performed as follows. Non-selective contact etching (CT etching) in the form of isotropic dry etching is performed to form... Figure 4B The opening 64 is illustrated. This non-selective etching is laterally confined to the access opening (sub-block) 62 by photolithographic patterning. Subsequently, the photoresist is removed, for example by an ashing process, and a selective wet etching is performed that selectively etches the BPSG (i.e., the lower ILD layer (first ILD layer) 441) but not the PE-TEOS (i.e., the upper ILD layer (second ILD layer) 442), thereby leaving an overhanging ILD region 68 of the PE-TEOS (i.e., the upper layer 442). In a non-limiting illustrative embodiment, the selective wet etching uses caro's acid. In some embodiments, the boron / phosphorus (B / P) ratio of the BPSG and the etching time are experimentally optimized to obtain high etch selectivity relative to the PE-TEOS for the BPSG and a desired undercut, thereby leaving the overhanging ILD region 68. If a CESL 46 is provided, it may optionally serve as an etch termination layer for selective etching.

[0033] More generally, if ILD layer 44 contains, for example Figures 4A to 4DIn the example illustrated, with a lower ILD layer (first ILD layer) 441 and an upper ILD layer (second ILD layer) 442, the first etching is a non-selective etching process designed to etch material through the first ILD layer 441 and the second ILD layer 442 and through CESL 46 (if it is included in the device structure). The second selective etching process is suitably designed to have high etching selectivity for etching the lower ILD layer (first ILD layer) 441 relative to the upper ILD layer (second ILD layer) 442, thereby producing the desired undercut for forming the overhanging ILD region 68. The etchant can be selected based on the materials of the lower ILD layer (first ILD layer) 441 and the upper ILD layer (second ILD layer) 442.

[0034] It should be further understood that ILD layer 44 may similarly comprise ILD layers of three (or more) different materials. In these embodiments, a non-selective first etching (similar to...) should be selected. Figure 4B ( ) to etch all the material through the multilayer ILD layer 44 to expose the entrance of the charge storage device 16, and a second selective etching (similar to) Figure 4C One or more of the multilayer ILD layers 44 should be selectively etched, but not all of the material, to form an undercut bulk (sub-bulb) 60 while leaving overhanging ILD regions 68.

[0035] Furthermore, the method is also expected to be employed when the ILD layer 44 comprises a monolayer made of a single material. In this case, the etching is designed to have sufficient anisotropy to preferentially etch downwards to form the access opening (sub-block) 62 and penetrate downwards to the charge storage device 16, but also provides some lateral etching to form the undercut block (sub-block) 60.

[0036] Although Figure 4C The diagram illustrates continuous blocks (sub-blocks 60 and 62) with ideally straight edges and right-angled corners, but in practice, the edges can be curved and / or the corners can be substantially rounded, or the shapes can be otherwise consistent with... Figure 4C The ideal diagram represents a deviation. For example, the undercut block (sub-block) 60 has sufficient lateral extent to be filled to form a light-blocking layer 40 that completely covers the charge storage device 16, and sufficient vertical dimensions to ensure that the subsequently formed light-blocking layer 40 has sufficient thickness to provide substantially complete light absorption, thereby preventing optical injection of light-induced charge into the charge storage device 16.

[0037] refer to Figure 4D By reference Figure 4B and Figure 4CThe selectively etched continuous openings (sub-blocks 60 and 62) described herein are filled with metal or other light-blocking materials to form a light-blocking layer 40 and a light-blocking plug 42. In other words, a light-blocking material is deposited to perform two operations: (i) filling the undercut block (sub-block) 60 with the light-blocking material to form a light-blocking layer 40 covering the charge storage device 16, and (ii) filling the access opening 62 with the light-blocking material to form a light-blocking plug 42. These filling operations (i) and (ii) can be performed simultaneously, for example, using physical vapor deposition (PVD) technology. PVD fills the continuous blocks (sub-blocks 60 and 62) with the light-blocking material to form both the light-blocking layer 40 and the light-blocking plug 42. This results in the light-blocking layer 40 and the light-blocking plug 42 being formed as a continuous structure made of the same light-blocking material. PVD can consist of a single deposition operation, but it should be understood that the gas flow rate may vary independently as a function of time during this single deposition operation. For example, in a non-limiting illustrative embodiment, the light-blocking material is a titanium / titanium nitride / tungsten (Ti / TiN / W) multilayer formed by varying the flow rates of triethylborate (TEB), tetraethoxysilane (TEOS), and triethylphosphate (TEPO). The PVD technology options are appropriately selected based on factors such as, for example, the type of light-blocking material to be deposited, thereby providing a deposition rate that effectively and completely fills the continuous bulk blocks (sub-blocks 60 and 62).

[0038] The parameters for selective etching to form the continuous blocks (sub-blocks 60 and 62) and for PVD to fill the continuous blocks (sub-blocks 60 and 62) with light-blocking material to form the light-blocking layer 40 and the light-blocking plug 42 can be empirically optimized by forming a test structure and evaluating the resulting light-blocking layer 40 and light-blocking plug 42 using characterization techniques (e.g., transmission electron microscopy (TEM) and electrical characterization of the resistance between the light-blocking plug 42 and the charge storage device 16).

[0039] refer to Figure 5 , Figure 6A as well as Figure 6B The diagram illustrates a specific example of this type of optimization. Figure 6AThe charge storage device 16 is depicted on top of the ILD layer 44, which includes a lower ILD layer (first ILD layer) 441, which is a BPSG layer in this embodiment, and an upper ILD layer (second ILD layer) 442, which is a PE-TEOS layer in this embodiment. Figure 6A and Figure 6B Illustrative examples further include an anti-reflection coating (ARC) 80. Figure 6A The selectively etched block 82, corresponding to the continuous blocks (sub-block 60 and sub-block 62) of the previous example, is further illustrated. Arrow 84 indicates the gas flow rate (e.g., corresponding to the previous reference) of the material forming the light-blocking layer 40 and the light-blocking plug 42 during PVD into the selectively etched block 82. Figure 4D (The described operation). Figure 5 Plot the gas flow rates of TEB, TEOS, and TEPO during normal operation (top curve) and abnormal operation (bottom curve). Figure 6B This illustrates how the Ti / TiN / W multilayer 86 obtained during abnormal operation (corresponding to a continuous structure (light-blocking layer 40 and light-blocking plug 42) made of the light-blocking material of the previous embodiment) fails to completely fill the selectively etched bulk 82, leaving voids 88. Voids can adversely affect device yield. To optimize the process, multiple runs can be performed with different gas flow rate settings (e.g., flow ramp start, ramp rate, etc.) and the resulting device characterized by TEM to determine the optimal gas flow rate formulation for filling the selectively etched bulk 82.

[0040] Some additional embodiments are disclosed below.

[0041] In an illustrative embodiment, a method for providing light shielding for a charge storage device of an image sensor pixel is disclosed. The method includes providing a photosensitive device and a charge storage device, and a dielectric layer covering the photosensitive device and the charge storage device. The method further includes: performing etching of the dielectric layer to define an undercut block beneath the dielectric layer and an access opening extending through the dielectric layer to the undercut block; and performing physical vapor deposition (PVD) of a light-blocking material to perform two operations: filling the undercut block with the light-blocking material to form a light-blocking layer covering the charge storage device, and filling the access opening with the light-blocking material to form a light-blocking plug.

[0042] An embodiment of this disclosure provides a method for providing light shielding for a charge storage device for an image sensor pixel, wherein the light-blocking plug contacts the light-blocking layer.

[0043] An embodiment of this disclosure provides a method for providing light shielding for a charge storage device of an image sensor pixel, wherein the physical vapor deposition forms the light-blocking layer and the light-blocking plug as a continuous structure made of the light-blocking material.

[0044] An embodiment of this disclosure provides an optical shielding method for a charge storage device for an image sensor pixel, wherein the physical vapor deposition consists of a single deposition operation.

[0045] An embodiment of this disclosure provides a method for providing optical shielding for a charge storage device of an image sensor pixel, wherein the dielectric layer comprises: a first dielectric layer of a first material disposed above the photosensitive device and the charge storage device; and a second dielectric layer of a second material disposed above the first dielectric layer, the second material being different from the first dielectric material, and the etching comprising selectively etching the first material beneath the second material to define the undercut bulk.

[0046] An embodiment of this disclosure provides a method for providing optical shielding for a charge storage device of an image sensor pixel, wherein the etching further comprises: performing non-selective etching through a first dielectric layer and a second dielectric layer to expose the charge storage device prior to performing the selective etching, the non-selective etching defining the access opening through the dielectric layer to the undercut block.

[0047] An embodiment of this disclosure provides an optical shielding method for a charge storage device of an image sensor pixel, wherein the first material comprises borosilicate glass (BPSG) and the second material comprises plasma-enhanced tetraethoxysilane (PE-TEOS).

[0048] In another illustrative embodiment, an image sensor pixel includes: a photosensitive device; a charge storage device; a light-blocking layer disposed above the charge storage device; a light-blocking plug disposed above the charge storage device; and a dielectric layer disposed above the light-blocking layer. The light-blocking plug passes through the dielectric layer and contacts the light-blocking layer.

[0049] An image sensor pixel according to an embodiment of the present disclosure, wherein there is no gap between the light-blocking layer and the light-blocking plug.

[0050] An image sensor pixel according to an embodiment of the present disclosure, wherein the light-blocking layer and the light-blocking plug comprise a continuous structure.

[0051] An image sensor pixel according to an embodiment of the present disclosure, wherein the continuous structure is made of metal or multiple layers.

[0052] An image sensor pixel according to an embodiment of the present disclosure, wherein the light-blocking layer and the light-blocking plug are formed by a physical vapor deposition (PVD) process comprising a metallic material, the process comprising two operations: forming the light-blocking layer by filling an undercut block beneath the dielectric layer with the metallic material through an access opening through the dielectric layer, and forming the light-blocking plug by filling the access opening with the metallic material.

[0053] An image sensor pixel according to an embodiment of this disclosure, wherein the process of forming the light-blocking layer and the light-blocking plug further includes: performing etching of the dielectric layer prior to physical vapor deposition to define the access opening and the undercut body below the dielectric layer.

[0054] An image sensor pixel according to an embodiment of this disclosure, wherein the dielectric layer comprises a first dielectric layer of a first material adjacent to the charge storage device and a second dielectric layer of a second material distant from the charge storage device, and the etching includes: performing non-selective etching through the first dielectric layer and the second dielectric layer to expose the charge storage device, the non-selective etching defining the access opening; and after the non-selective etching, performing selective etching of the first material beneath the second material to define the undercut body.

[0055] An image sensor pixel according to an embodiment of the present disclosure, wherein the first material comprises borosilicate glass (BPSG) and the second material comprises plasma-enhanced tetraethoxysilane (PE-TEOS).

[0056] An image sensor pixel according to an embodiment of this disclosure further includes: a shutter gate transistor connected to reset the photosensitive device; a charge transfer path including a transfer gate transistor through which charge from the photosensitive device is transferred to a charge storage device; and a readout circuit configured to read out the charge stored in the charge storage device.

[0057] In another illustrative embodiment, the image sensor includes an array of image sensor pixels as described in the preceding paragraphs.

[0058] In another illustrative embodiment, a method for providing light shielding for a charge storage device of an image sensor pixel is disclosed. The image sensor pixel includes a photosensitive device and a charge storage device, as well as a first dielectric layer and a second dielectric layer. The first dielectric layer is made of a first material and covers the photosensitive device and the charge storage device, and the second dielectric layer is made of a second material different from the first material and covers the first dielectric layer. The method includes: performing non-selective etching through the second dielectric layer to define an access opening through the second dielectric layer and through the first dielectric layer to expose the charge storage device; after the non-selective etching, performing selective etching of the first material beneath the second material to define an undercut block extending laterally at least above the charge storage device; and after the non-selective etching, performing physical vapor deposition (PVD) of a light-blocking material to fill the access opening and the undercut block, thereby forming a light-blocking layer covering the charge storage device and the light-blocking plug.

[0059] In another illustrative embodiment, an apparatus includes a charge storage device, a light-blocking layer, a dielectric layer, and a light-blocking plug. The light-blocking layer is disposed above the charge storage device. The dielectric layer is disposed above the light-blocking layer. The light-blocking plug is disposed above the charge storage device and extends through the dielectric layer to provide electrical access to the charge storage device. The light-blocking layer and the light-blocking plug comprise a continuous structure. In some embodiments, there is no gap between the light-blocking layer and the light-blocking plug. In some illustrative examples, the continuous structure may be made of metal or multiple layers.

[0060] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

Claims

1. A method for providing optical shielding for charge storage devices of an image sensor pixel, the method comprising: A photosensitive device and a charge storage device are provided, as well as a dielectric layer covering the photosensitive device and the charge storage device, the dielectric layer comprising: A first dielectric layer of a first material is disposed above the photosensitive device and the charge storage device; as well as A second dielectric layer of a second material is disposed above the first dielectric layer, and the second material is different from the first material. Etching of the dielectric layer is performed to define an undercut body beneath the dielectric layer while preserving overhanging dielectric regions that overhang the undercut body. The etching defines an access opening through the dielectric layer to the undercut body. The etching includes: A first etching is performed to etch through the first dielectric layer and the second dielectric layer to expose the charge storage device, the first etching defining the access opening through the dielectric layer; as well as Perform a second etching of the first material beneath the second material to define the undercut block; and Following the etching, physical vapor deposition of a light-blocking material is performed to conduct the following two operations: The light-blocking material is used to fill the undercut block to form a light-blocking layer covering the charge storage device, and The light-blocking material is used to fill the access opening to form a light-blocking plug.

2. The method for providing optical shielding for a charge storage device of an image sensor pixel according to claim 1, wherein the light-blocking plug contacts the light-blocking layer.

3. The method for providing optical shielding for charge storage devices of image sensor pixels according to claim 1, wherein the light-blocking layer and the light-blocking plug are continuous structures.

4. The method for providing optical shielding for charge storage devices of image sensor pixels according to claim 1, wherein the physical vapor deposition consists of a single deposition operation.

5. The method for providing optical shielding for a charge storage device of an image sensor pixel according to claim 1, wherein the first etching comprises non-selective etching.

6. The method for providing optical shielding for a charge storage device of an image sensor pixel according to claim 1, wherein the first material comprises borosilicate glass and the second material comprises plasma-enhanced tetraethoxysilane.

7. An image sensor pixel, comprising: Photosensitive devices; Charge storage devices; A light-blocking layer is disposed above the charge storage device; A light-blocking plug is disposed above the charge storage device; as well as A dielectric layer is disposed above the light-blocking layer, an undercut block is provided below the dielectric layer, the dielectric layer has an access opening that passes through the dielectric layer to reach the undercut block, a suspended dielectric region of the dielectric layer hangs above the undercut block, the light-blocking layer fills the undercut block, and the light-blocking plug fills the access opening. The light-blocking plug passes through the dielectric layer and contacts the light-blocking layer.

8. The image sensor pixel according to claim 7, wherein there is no gap between the light-blocking layer and the light-blocking plug.

9. The image sensor pixel of claim 7, wherein the light-blocking layer and the light-blocking plug comprise a continuous structure.

10. The image sensor pixel of claim 9, wherein the continuous structure is made of metal or multiple layers.

11. The image sensor pixel of claim 7, wherein the light-blocking layer and the light-blocking plug are formed by a physical vapor deposition process comprising a metallic material, the process comprising the following two operations: The light-blocking layer is formed by filling the undercut block beneath the dielectric layer with the metallic material through the access opening passing through the dielectric layer, and The light-blocking plug is formed by filling the access opening with the metal material.

12. The image sensor pixel of claim 11, wherein the process of forming the light-blocking layer and the light-blocking plug further comprises: performing etching of the dielectric layer prior to the physical vapor deposition to define the access opening and the undercut body below the dielectric layer.

13. The image sensor pixel of claim 12, wherein the dielectric layer comprises a first dielectric layer of a first material adjacent to the charge storage device and a second dielectric layer of a second material distant from the charge storage device, and the etching comprises: A non-selective etching process is performed to etch through the first and second dielectric layers to expose the charge storage device, the non-selective etching defining the access opening; and Following the non-selective etching, selective etching of the first material beneath the second material is performed to define the undercut bulk.

14. The image sensor pixel of claim 13, wherein the first material comprises borosilicate glass and the second material comprises plasma-enhanced tetraethoxysilane.

15. The image sensor pixel of claim 7, further comprising: A shutter gate transistor is connected to reset the photosensitive device; A charge transfer path includes a transfer gate transistor through which charge from the photosensitive device is transferred to a charge storage device; as well as The readout circuit is configured to read out the charge stored in the charge storage device.

16. An image sensor comprising an array of image sensor pixels as set forth in claim 15.

17. An image sensor device, comprising: Charge storage devices; A light-blocking layer is disposed above the charge storage device; A dielectric layer is disposed above the light-blocking layer, and an undercut block is provided below the dielectric layer. The dielectric layer has an access opening that extends through the dielectric layer to the undercut block. A suspended dielectric region of the dielectric layer hangs above the undercut block. The light-blocking layer fills the undercut block, and a light-blocking plug fills the access opening. as well as A light-blocking plug is disposed above the charge storage device and extends through the dielectric layer to provide electrical access to the charge storage device; The light-blocking layer and the light-blocking plug have a continuous structure.

18. The image sensor device of claim 17, wherein there is no gap between the light-blocking layer and the light-blocking plug.

19. The image sensor device of claim 17, wherein the continuous structure is made of metal or multiple layers.

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