Display device and method of manufacturing the same

Abstract

The present disclosure relates to a display device and a method of manufacturing the same. The display device includes a first substrate; a first electrode on the first substrate; a second electrode on the first substrate and spaced apart from the first electrode; a plurality of light emitting elements each having respective end portions on the first electrode and the second electrode; a first transistor having a first terminal connected to the first electrode and a second terminal grounded; and a second transistor having a first terminal connected to the second electrode and a second terminal grounded, wherein the first transistor is forward biased to the first electrode, and the second transistor is reverse biased to the second electrode.

Description

Technical Field

[0001] This disclosure relates to a display device and a method of manufacturing the display device. Background Technology

[0002] With the development of multimedia technology, display devices are becoming increasingly important. Therefore, various display devices are now in use, such as organic light-emitting diode (OLED) displays and liquid crystal displays (LCDs).

[0003] Conventional display devices include display panels for displaying images, such as OLED display panels or LCD panels. Light-emitting display panels may include light-emitting elements such as light-emitting diodes (LEDs). For example, LEDs are classified into organic LEDs (OLEDs) that use organic light-emitting materials and inorganic LEDs (ILEDs) that use inorganic light-emitting materials. Summary of the Invention

[0004] One or more embodiments of this disclosure provide a display device and a method of manufacturing the display device, wherein the display device includes a virtual circuit for preventing or reducing static electricity generation on electrodes and is capable of stably improving the alignment of light-emitting elements.

[0005] However, the aspects and features of embodiments of this disclosure are not limited to those set forth herein. These and other aspects and features of embodiments of this disclosure will become more apparent to those skilled in the art upon which this disclosure pertains from the following detailed description.

[0006] According to embodiments of this disclosure, since the display device includes a circuit (or virtual circuit) connected to the electrodes, static electricity generated due to surface friction between the ink and the electrodes can be removed. Furthermore, an electrostatic current can flow in the circuit (or virtual circuit) due to static electricity, allowing the light-emitting element to be initially aligned by the electric field generated by the electrostatic current. Damage to the light-emitting element due to static electricity can be prevented, and the alignment degree of the light-emitting element can be improved by performing initial alignment using the electrostatic current.

[0007] It should be noted that the aspects and features of the embodiments of this disclosure are not limited to those described above, and other aspects and features of the embodiments of this disclosure will be apparent from the following description.

[0008] According to an embodiment of the present disclosure, a display device includes: a first substrate; a first electrode on the first substrate; a second electrode on the first substrate and spaced apart from the first electrode; a plurality of light-emitting elements, each light-emitting element having a corresponding end on the first electrode and the second electrode; a first transistor having a first end connected to the first electrode and a second end grounded; and a second transistor having a first end connected to the second electrode and a second end grounded, wherein the first transistor is forward biased to the first electrode and the second transistor is reverse biased to the second electrode.

[0009] The display device may further include a first voltage line and a second voltage line between the first substrate and the first electrode and between the first substrate and the second electrode, respectively, wherein the first voltage line may be electrically connected to the first electrode and the second voltage line may be electrically connected to the second electrode.

[0010] The display device may further include a first capacitor connected to a node between the first electrode and a first end of the first transistor, and a second capacitor connected to a node between the second electrode and a first end of the second transistor.

[0011] The display device may further include a third transistor connected to a node between a first voltage line and a first electrode, a third capacitor connected between the third transistor and the first electrode, a fourth transistor connected to a node between a second voltage line and a second electrode, and a fourth capacitor connected between the fourth transistor and the second electrode, wherein different voltages can be applied to the first voltage line and the second voltage line, and at least one of the third transistor and the fourth transistor can be forward biased.

[0012] The display device may further include a third transistor connected to a node between a first voltage line and a first electrode, a third capacitor connected between the third transistor and the first electrode, a fourth transistor connected to a node between a second voltage line and a second electrode, and a fourth capacitor connected between the fourth transistor and the second electrode, wherein the same voltage can be applied to the first voltage line and the second voltage line, and at least one of the third transistor and the fourth transistor can be forward biased.

[0013] The first transistor may include a first drain electrode electrically connected to a first electrode, a first source electrode grounded, and a first gate electrode electrically connected to the first drain electrode, and the second transistor may include a second drain electrode electrically connected to a second electrode, a second source electrode grounded, and a second gate electrode electrically connected to the second source electrode.

[0014] The first transistor may include a first source electrode electrically connected to a first electrode, a first drain electrode grounded, and a first gate electrode electrically connected to the first drain electrode, and the second transistor may include a second source electrode electrically connected to a second electrode, a second drain electrode grounded, and a second gate electrode electrically connected to the second source electrode.

[0015] Each of the light-emitting elements may include a first semiconductor layer, a second semiconductor layer, and a light-emitting layer between the first semiconductor layer and the second semiconductor layer. A first end of the light-emitting element is on a first electrode, wherein the first semiconductor layer is located at the first end of the corresponding light-emitting element in the light-emitting element, and a second end of the light-emitting element is on a second electrode, wherein the second semiconductor layer is located at the second end of the corresponding light-emitting element in the light-emitting element.

[0016] The display device may further include a driving transistor connected to a first voltage line and a second voltage line, wherein the first electrode may be connected to the driving transistor and the second electrode may be connected to the second voltage line.

[0017] The display device may further include a via layer between the first substrate and the first electrode and the second electrode, wherein the first transistor, the second transistor and the driving transistor may be located between the via layer and the first substrate.

[0018] The display device may further include a first conductive layer on a first substrate, a buffer layer on the first conductive layer, an active layer on the buffer layer, a first gate insulating layer on the active layer, a second conductive layer on the first gate insulating layer, a first interlayer insulating layer on the second conductive layer, and a third conductive layer on the first interlayer insulating layer, wherein the source electrode and drain electrode of the first transistor, the second transistor, and the driving transistor may be formed by the third conductive layer.

[0019] The first voltage line and the second voltage line can be formed by a third conductive layer. The first electrode can be connected to the source electrode of the driving transistor through a contact hole in the via layer, and the second electrode can be connected to the second voltage line through another contact hole in the via layer.

[0020] The display device may further include a first connecting electrode on and in contact with the first end of the first electrode and the first end of the light-emitting element, a second connecting electrode on and in contact with the second end of the second electrode and the second end of the light-emitting element, a first insulating layer covering the first electrode and the second electrode, and a second insulating layer surrounding a portion of the outer surface of each of the light-emitting elements, wherein at least a portion of the first connecting electrode and at least a portion of the second connecting electrode may be on the second insulating layer.

[0021] According to embodiments of the present disclosure, a method of manufacturing a display device includes: forming a first transistor, a first electrode electrically connected to a first voltage line, a second transistor, and a second electrode electrically connected to a second voltage line on a first substrate; spraying ink having a light-emitting element dispersed therein onto the first electrode and the second electrode; generating a first electric field by utilizing static electricity flowing in the first electrode and the first transistor and another static electricity flowing in the second electrode and the second transistor to initially align the light-emitting element onto the first electrode and the second electrode; and secondary aligning the light-emitting element by applying an alignment voltage to the first electrode and the second electrode to generate a second electric field between the first electrode and the second electrode, wherein the first transistor can be forward biased to the first electrode and the second transistor can be reverse biased to the second electrode.

[0022] The first transistor may have a first drain electrode connected to a first electrode, a first source electrode grounded, and a first gate electrode connected to the first drain electrode, and the second transistor may have a second drain electrode connected to a second electrode, a second source electrode grounded, and a second gate electrode connected to the second source electrode.

[0023] During the initial alignment of the light-emitting elements, a first electrostatic current will flow from the first electrode to the first transistor, and a second electrostatic current will flow from the second transistor through the second electrode to the second voltage line. The light-emitting elements can be aligned by the first electric field, such that the two ends of each of the light-emitting elements are on the first electrode and the second electrode.

[0024] During the secondary alignment of the light-emitting element, an AC power supply can be applied to the first voltage line, and the second voltage line can be grounded.

[0025] During the secondary alignment of the light-emitting element, the light-emitting element can be aligned such that the first end and the second end of the light-emitting element are respectively on the first electrode and the second electrode.

[0026] The secondary alignment of the light-emitting element may include applying light to the light-emitting element, and an alignment voltage may be applied to the first electrode and the second electrode, and light is applied to the light-emitting element.

[0027] Each of the light-emitting elements may include a first semiconductor layer, a second semiconductor layer, and a light-emitting layer between the first semiconductor layer and the second semiconductor layer. A first end of the light-emitting element is on a first electrode, wherein the first semiconductor layer of the corresponding light-emitting element is at the first end of the corresponding light-emitting element, and a second end of the light-emitting element is on a second electrode, wherein the second semiconductor layer of the corresponding light-emitting element is at the second end of the corresponding light-emitting element. Attached Figure Description

[0028] The above and other aspects and features of the embodiments of this disclosure will become more apparent from the detailed description of the embodiments with reference to the accompanying drawings, in which:

[0029] Figure 1 This is a plan view of a display device according to an embodiment of the present disclosure;

[0030] Figure 2 It is shown Figure 1 A plan view of the display area and non-display area of ​​the display device;

[0031] Figure 3 yes Figure 1 The equivalent circuit diagram of the sub-pixels of the display device;

[0032] Figure 4 yes Figure 1 A plan view of the pixels of the display device;

[0033] Figure 5 yes Figure 4 The planar image of the first sub-pixel;

[0034] Figure 6 It is along Figure 5 A cross-sectional view taken by line Q1-Q1';

[0035] Figure 7 It is along Figure 5 A cross-sectional view taken by line Q2-Q2';

[0036] Figure 8 This is a perspective cut view of a light-emitting element according to an embodiment of the present disclosure;

[0037] Figure 9 It is shown Figure 1 A cross-sectional view of electrodes in a sub-pixel of a display device and multiple transistors connected to the electrodes;

[0038] Figure 10 It is shown Figure 9 A schematic diagram illustrating how the electrodes and transistors are connected;

[0039] Figure 11 It is shown Figure 9 A schematic diagram of another example of how the electrodes and transistors are connected;

[0040] Figures 12 to 17 This is a schematic diagram illustrating the steps of a method for manufacturing a display device according to an embodiment of the present disclosure;

[0041] Figure 18 This is a cross-sectional view showing electrodes in a sub-pixel of a display device according to an embodiment of the present disclosure and a plurality of transistors connected to the electrodes;

[0042] Figure 19 It is shown Figure 18 A schematic diagram illustrating how the electrodes and transistors are connected;

[0043] Figure 20 and Figure 21 This is a schematic diagram illustrating an example of how the electrodes and transistors of a display device according to an embodiment of the present disclosure are connected;

[0044] Figure 22 This is a schematic diagram illustrating the steps of a method for manufacturing a display device according to an embodiment of the present disclosure; and

[0045] Figure 23 This is a plan view of a tiled display device according to an embodiment of the present disclosure. Detailed Implementation

[0046] Embodiments of this disclosure will now be described more fully below with reference to the accompanying drawings, in which embodiments of this disclosure are illustrated. However, this disclosure may be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art.

[0047] It will also be understood that when a layer is referred to as being "on" another layer or substrate, it can be directly on said other layer or substrate, or an intervening layer may be present. Throughout the specification, the same reference numerals denote the same components.

[0048] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the teachings of this disclosure, the first element discussed below may be referred to as the second element. Similarly, the second element may also be referred to as the first element.

[0049] For ease of description, spatially relative terms such as “below,” “under,” “down,” “below,” “above,” and “above” may be used herein to describe the relationship between one element or feature as shown in the figures and another element(s). It will be understood that, in addition to the orientation depicted in the figures, these spatially relative terms are also intended to include different orientations of the device in use or operation. For example, if the device in the figures is flipped, an element described as “below,” “under,” or “below” other elements or features will then be oriented “above” other elements or features. Thus, the exemplary terms “below” and “below” can include both the orientations above and below. The device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein should be interpreted accordingly. Furthermore, it will be understood that when a layer is referred to as being “between” two layers, it may be the only layer between those two layers, or there may be one or more intervening layers.

[0050] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the inventive concept. As used herein, the terms “substantially,” “about,” and similar terms are used as approximate terms rather than as terms of degree and are intended to explain the inherent biases of measurements or calculations that will be recognized by one of ordinary skill in the art.

[0051] As used herein, the singular forms “a” and “an” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that, when used in this specification, the terms “comprising” and / or “including” specify the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. When following a list of elements, expressions such as “at least one of” modify the entire list of elements, not individual elements in the list. Furthermore, when describing embodiments of the inventive concept, the use of “may” means “one or more embodiments of this disclosure.” Additionally, the term “exemplary” is intended to indicate an example or illustration. As used herein, the terms “use,” “using,” and “used” may be considered synonymous with the terms “utilize,” “utilizing,” and “utilized,” respectively.

[0052] In the following description, embodiments will be described with reference to the accompanying drawings.

[0053] Figure 1 This is a plan view of a display device according to an embodiment of the present disclosure.

[0054] refer to Figure 1 The display device 10 displays moving or still images. The display device 10 can refer to virtually any type of electronic device that provides a display screen. Examples of the display device 10 may include televisions (TVs), laptop computers, monitors, billboards, Internet of Things (IoT) devices, mobile phones, smartphones, tablet PCs, electronic watches, smart cards, smart phone watches, head-mounted displays (HMDs), mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation devices, game consoles, digital cameras, portable video cameras, etc.

[0055] Display device 10 includes a display panel that provides a display screen. Examples of display panels for display device 10 include inorganic light-emitting diode (ILED) display panels, organic light-emitting diode (OLED) display panels, quantum dot light-emitting diode (QLED) display panels, plasma display panels (PDP), field emission display (FED) panels, etc. In the following description, the display panel of display device 10 will be described as, for example, an ILED display panel, but this disclosure is not limited thereto. That is, various other display panels may also be used for the display panel of display device 10.

[0056] The shape of the display device 10 can vary. In one example, the display device 10 can have a rectangular shape that extends longer horizontally than vertically, a rectangular shape that extends longer vertically than horizontally, a square shape, a quadrilateral shape with rounded corners, a non-quadrilateral polygonal shape, or a circular shape. The shape of the display area DPA of the display device 10 can be similar to the shape of the display device 10. Figure 1 The display device 10 and the display area DPA are shown to have rectangular shapes that extend longer in the second direction DR2 than in the first direction DR1.

[0057] The display device 10 may include a display area DPA and a non-display area NDA surrounding (e.g., encircling) the display area DPA along its edge or periphery. The display area DPA may be the area in which a screen is displayed, and the non-display area NDA may be the area in which a screen is not displayed. The display area DPA may also be referred to as the active area, and the non-display area NDA may also be referred to as the inactive area. The display area DPA may occupy the middle (or central) portion of the display device 10.

[0058] The display area DPA may include multiple pixels PX. Pixels PX may be arranged along both row and column directions. For example, pixels PX may be arranged along the rows and columns of a matrix. Each of the pixels PX may include one or more light-emitting elements that emit light within a specific wavelength range. The light-emitting portion of the pixel PX may have a rectangular or square shape in a plan view, but this disclosure is not limited thereto. Alternatively, the light-emitting portion of the pixel PX may have a rhombus shape with sides tilted relative to a specific direction.

[0059] The non-display area NDA may be positioned around the display area DPA. The non-display area NDA may surround (e.g., encircle) the entire display area DPA or a portion of the display area DPA. The display area DPA may have a rectangular shape, and the non-display area NDA may be positioned adjacent to the four sides of the display area DPA. The non-display area NDA may form the bezel of the display device 10. Line or circuit drivers included in the display device 10 may be positioned within the non-display area NDA, or external devices may be mounted within the non-display area NDA.

[0060] Figure 2 It is shown Figure 1 A plan view of the display area and non-display area of ​​the display device.

[0061] refer to Figure 2 The display device 10 may include a plurality of pixels PX arranged along multiple rows and columns. For example, the pixels PX may be arranged along the rows and columns of a matrix. The pixels PX may be arranged sequentially along a first direction DR1 and a second direction DR2 in a display area DPA. The display device 10 may include light-blocking regions BA between the pixels PX. The light-blocking regions BA can prevent light beams emitted from different pixels PX from mixing together.

[0062] Each of the pixels PX or sub-pixels SPXn in the display device 10 (where n is an integer from 1 to 3) (see...) Figure 3 Each of the pixels in the PX array includes a pixel driving circuit. A line may be configured to pass through or through each of the pixels PX or each of the sub-pixels SPXn, and apply a driving signal to each of the pixel driving circuits. Each of the pixel driving circuits may include a transistor and a capacitor. The number of transistors and capacitors included in each of the pixel driving circuits may vary. In one example, the pixel driving circuit may have a “3T1C” structure comprising three transistors and one capacitor. Hereinafter, the pixel driving circuit will be described as having a “3T1C” structure, but this disclosure is not limited thereto. Alternatively, various other structures such as “2T1C”, “7T1C”, or “6T1C” structures may also be applied to the pixel driving circuit.

[0063] Figure 3 yes Figure 1 The equivalent circuit diagram of the sub-pixels of the display device.

[0064] refer to Figure 3 The sub-pixel SPXn of the display device 10 includes a light-emitting diode (LED) "EL", three transistors (e.g., a driving transistor DT and a first switching transistor ST1 and a second switching transistor ST2), and a storage capacitor Cst.

[0065] An LED "EL" emits light according to a current applied to it via a driving transistor DT. An LED "EL" includes a first electrode, a second electrode, and at least one light-emitting element disposed between the first and second electrodes. The light-emitting element can emit light within a specific wavelength range according to an electrical signal transmitted to it from the first and second electrodes.

[0066] The first terminal of LED "EL" can be connected to the source electrode of the driving transistor DT, and the second terminal of LED "EL" can be connected to the second voltage line VSL, providing a low potential voltage (hereinafter referred to as the second power supply voltage) lower than the high potential voltage (hereinafter referred to as the first power supply voltage) to the second voltage line VSL. In some embodiments, the first terminal of LED "EL" can be connected to the source electrode of the second switching transistor ST2. In some other embodiments, the second terminal of LED "EL" can be connected to the source electrode of the first switching transistor ST1.

[0067] The driving transistor DT controls the current flowing from the first voltage line VDL to the LED "EL" based on the voltage difference between its gate and source electrodes, where a first power supply voltage is provided. In one example, the driving transistor DT may be a transistor used to drive the LED "EL". The gate electrode of the driving transistor DT may be connected to the source electrode of the first switching transistor ST1, the source electrode of the driving transistor DT may be connected to the first electrode of the LED "EL", and the drain electrode of the driving transistor DT may be connected to the first voltage line VDL, where the first power supply voltage is provided.

[0068] The first switching transistor ST1 is turned on by a first scan signal from the first scan line SL1 to connect the data line DTL to the gate electrode of the driving transistor DT. The gate electrode of the first switching transistor ST1 can be connected to the first scan line SL1, the source electrode of the first switching transistor ST1 can be connected to the gate electrode of the driving transistor DT, and the drain electrode of the first switching transistor ST1 can be connected to the data line DTL.

[0069] The second switching transistor ST2 is turned on by a second scan signal from the second scan line SL2 to connect the initialization voltage line VIL to the first terminal of the LED "EL". The gate electrode of the second switching transistor ST2 can be connected to the second scan line SL2, the drain electrode of the second switching transistor ST2 can be connected to the initialization voltage line VIL, and the source electrode of the second switching transistor ST2 can be connected to the first terminal of the LED "EL" or the source electrode of the driving transistor DT.

[0070] The source and drain electrodes of the driving transistor DT, the first switching transistor ST1, and the second switching transistor ST2 are not limited to those described above. The driving transistor DT, the first switching transistor ST1, and the second switching transistor ST2 can be formed as thin-film transistors (TFTs). Figure 3 The diagram shows the driving transistor DT, the first switching transistor ST1, and the second switching transistor ST2 configured as N-type metal-oxide-semiconductor field-effect transistors (MOSFETs), but this disclosure is not limited thereto. That is, alternatively, the driving transistor DT, the first switching transistor ST1, and the second switching transistor ST2 can all be configured as P-type MOSFETs. Even alternatively, some of the driving transistor DT, the first switching transistor ST1, and the second switching transistor ST2 can be configured as N-type MOSFETs, and the others can be configured as P-type MOSFETs.

[0071] A storage capacitor Cst is formed between the gate and source electrodes of the driving transistor DT. The storage capacitor Cst stores the differential voltage (or charge) corresponding to the voltage difference between the gate and source electrodes of the driving transistor DT.

[0072] The structure of the pixel PX of the display device 10 will be described in more detail below.

[0073] Figure 4 yes Figure 1 A plan view of the pixels of a display device.

[0074] refer to Figure 4 A pixel PX may include multiple sub-pixels SPXn (where n is an integer from 1 to 3). In one example, a pixel PX may include a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3. The first sub-pixel SPX1 may emit light of a first color, the second sub-pixel SPX2 may emit light of a second color, and the third sub-pixel SPX3 may emit light of a third color. In one example, the first, second, and third colors may be blue, green, and red, respectively, but this disclosure is not limited thereto. Alternatively, all sub-pixels SPXn may emit light of the same color. In one example, all sub-pixels SPXn may emit blue light. Figure 4The illustration shows that pixel PX may include three sub-pixels SPXn, but this disclosure is not limited thereto. Alternatively, pixel PX may include more than three sub-pixels SPXn.

[0075] Each subpixel SPXn may include an emitting region EMA and a non-emitting region. The emitting region EMA may be a region that outputs light of a specific wavelength range due to the presence of a light-emitting element ED, and the non-emitting region may be a region in which no light-emitting element ED is present, light emitted by the light-emitting element ED does not reach, and therefore no light is output. The emitting region EMA may include the region where the light-emitting element ED is present and the region surrounding the light-emitting element ED that outputs light emitted by the light-emitting element ED.

[0076] However, this disclosure is not limited thereto. The emission region EMA may also include a region that outputs light emitted by the light-emitting element ED and then reflected or refracted by other components. A plurality of light-emitting elements ED may be disposed in each of the sub-pixels SPXn to form the emission region EMA, which includes a region in which the plurality of light-emitting elements ED are disposed and the area surrounding the region in which the plurality of light-emitting elements ED are disposed.

[0077] Figure 4 The diagram shows that the emission regions EMA of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 have substantially the same size. In some embodiments, the emission regions EMA of the sub-pixel SPXn can have different sizes depending on the color or wavelength of the light emitted by the light-emitting element ED.

[0078] Each of the sub-pixels SPXn may further include a sub-region SA disposed in the non-emitting region of the corresponding sub-pixel SPXn. The sub-region SA may be disposed on a first side of the emission region EMA of the corresponding sub-pixel SPXn along the first direction DR1, between the emission region EMA of the corresponding sub-pixel SPXn and the emission region EMA of a neighboring sub-pixel SPXn adjacent to the corresponding sub-pixel SPXn along the first direction DR1. In one example, multiple emission regions EMA may be arranged one after another along the second direction DR2, multiple sub-region SA may be arranged one after another along the second direction DR2, and multiple emission regions EMA and multiple sub-region SA may be arranged alternately along the first direction DR1. However, this disclosure is not limited to this example.

[0079] The second dam section BNL2 can be disposed between sub-regions SA of sub-pixels SPXn, between emitting regions EMA of sub-pixels SPXn, and between sub-regions SA and emitting regions EMA of sub-pixels SPXn. The distances between sub-regions SA of sub-pixels SPXn, between emitting regions EMA of sub-pixels SPXn, and between sub-regions SA and emitting regions EMA of sub-pixels SPXn can vary depending on the width of the second dam section BNL2. Since no light-emitting element ED is disposed in the sub-regions SA of sub-pixels SPXn, light can be not output from the sub-regions SA of sub-pixels SPXn, but the electrode RME can be partially disposed in the sub-regions SA of sub-pixels SPXn. The two sets of electrode RME from two different sub-pixels SPXn (adjacent in the first direction DR1) can be separated from each other in the separation section ROP of the sub-region SA of one of the two different sub-pixels SPXn.

[0080] The second dam portion BNL2 may include portions extending in the first direction DR1 and portions extending in the second direction DR2, and may be arranged in a grid pattern throughout the entire display area DPA in a plan view. The second dam portion BNL2 may be positioned along the boundary of each of the sub-pixels SPXn to separate the sub-pixels SPXn from each other. Furthermore, the second dam portion BNL2 may be configured to surround each of the emission regions EMA of the sub-pixels SPXn to separate the emission regions EMA of the sub-pixels SPXn from each other.

[0081] Figure 5 yes Figure 4 The planar image of the first sub-pixel. Figure 6 It is along Figure 5 A sectional view taken from line Q1-Q1'. Figure 7 It is along Figure 5 A cross-sectional view taken from line Q2-Q2'. Figure 5 The first sub-pixel SPX1 of pixel PX is shown, and Figure 6 It shows the results from including Figure 5 A cross-sectional view taken from one end to the other of the light-emitting element ED in the first sub-pixel SPX1. Figure 7 It shows the span Figure 5 A cross-sectional view of multiple contacts of the first sub-pixel SPX1 (i.e., first contact CT1 and second contact CT2).

[0082] refer to Figures 5 to 7 And also refer to Figure 4 The display device 10 may include a first substrate SUB in the first sub-pixel SPX1, and may also include a plurality of insulating layers, a plurality of conductive layers, and an active layer disposed on the first substrate SUB. The active layer, conductive layer, and insulating layer may form the circuit layer CCL and the display element layer of the display device 10.

[0083] The first substrate SUB can be an insulating substrate. The first substrate SUB can be formed of an insulating material such as glass, quartz, or polymer resin. The first substrate SUB can be a rigid substrate or a flexible substrate that is bendable, foldable, and / or rollable.

[0084] A first conductive layer may be disposed on a first substrate SUB. The first conductive layer includes a lower metal layer CAS, and the lower metal layer CAS is configured to overlap with the active layer ACT_DT of the driving transistor DT in the thickness direction (e.g., third direction DR3) of the first substrate SUB. The lower metal layer CAS may include a material capable of blocking light transmission and preventing light from incident on the active layer ACT_DT of the driving transistor DT. The lower metal layer CAS may not be provided.

[0085] The buffer layer BL can be disposed on the lower metal layer CAS and the first substrate SUB. The buffer layer BL can be formed on the first substrate SUB to protect the transistor of the first sub-pixel SPX1 from moisture that can penetrate the first substrate SUB (which is susceptible to moisture penetration), and can perform surface planarization function.

[0086] An active layer is disposed on the buffer layer BL. The active layer may include the active layer ACT_DT for driving the transistor DT. The active layer ACT_DT for driving the transistor DT may be configured to partially overlap with the gate electrode G_DT in the second conductive layer, which will be described later, in the thickness direction of the first substrate SUB (e.g., the third direction DR3).

[0087] The active layer may comprise monocrystalline silicon or an oxide semiconductor. Alternatively, the active layer may comprise polycrystalline silicon. The oxide semiconductor may be an oxide semiconductor containing indium (In). In one example, the oxide semiconductor may be at least one of indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), indium zinc tin oxide (IZTO), indium gallium tin oxide (IGTO), and indium gallium zinc tin oxide (IGZTO).

[0088] Figures 4 to 7 The illustration shows that the first sub-pixel SPX1 includes only one transistor (i.e., the driving transistor DT), but this disclosure is not limited thereto. That is, the first sub-pixel SPX1 may include more than one transistor.

[0089] The first gate insulating layer GI is disposed on the active layer ACT_DT and the buffer layer BL. The first gate insulating layer GI can be used as the gate insulating film for driving transistor DT.

[0090] A second conductive layer is disposed on the first gate insulating layer GI. The second conductive layer may include the gate electrode G_DT for driving the transistor DT. The gate electrode G_DT may be configured to overlap with the channel region of the active layer ACT_DT in the thickness direction of the first substrate SUB (i.e., in the third direction DR3).

[0091] A first interlayer insulating layer IL1 is disposed on the second conductive layer. The first interlayer insulating layer IL1 can serve as an insulating film between the second conductive layer and the layers disposed on the second conductive layer, and can protect the second conductive layer.

[0092] A third conductive layer is disposed on the first interlayer insulating layer IL1. The third conductive layer may include a first voltage line VDL and a second voltage line VSL, as well as multiple electrode patterns (e.g., CDP1 and CDP2).

[0093] A high potential voltage (or first power supply voltage) to be delivered to the first electrode RME1 can be applied to the first voltage line VDL, and a low potential voltage (or second power supply voltage) to be delivered to the second electrode RME2 can be applied to the second voltage line VSL. A portion of the first voltage line VDL can contact the active layer ACT_DT of the driving transistor DT through a contact hole that penetrates the first interlayer insulating layer IL1 and the first gate insulating layer GI. The first voltage line VDL can be used as the first drain electrode D_DT of the driving transistor DT.

[0094] In some implementations, a first power supply voltage may be applied to a first voltage line VDL, and a driving transistor DT may be connected to the first voltage line VDL. In this case, the first voltage line VDL may be used as the first drain electrode D_DT of the driving transistor DT.

[0095] The first electrode pattern CDP1 can contact the active layer ACT_DT of the driving transistor DT through a contact hole penetrating the first interlayer insulating layer IL1 and the first gate insulating layer GI. Furthermore, the first electrode pattern CDP1 can contact the lower metal layer CAS through another contact hole penetrating the first interlayer insulating layer IL1, the first gate insulating layer GI, and the buffer layer BL. The first electrode pattern CDP1 can be used as the first source electrode S_DT of the driving transistor DT.

[0096] The second electrode pattern CDP2 can be electrically connected to the driving transistor DT via the first electrode pattern CDP1. The first electrode pattern CDP1 and the second electrode pattern CDP2 are shown spaced apart from each other; however, alternatively, the first electrode pattern CDP1 and the second electrode pattern CDP2 can be directly connected to each other or connected via another pattern from a different layer. In some embodiments, the second electrode pattern CDP2 can be integrally formed with the first electrode pattern CDP1, and thus can form a single pattern together with the first electrode pattern CDP1. The second electrode pattern CDP2 can be connected to the first electrode RME1, and the driving transistor DT can transmit a first power supply voltage applied to it from the first voltage line VDL to the first electrode RME1.

[0097] The first electrode pattern CDP1 and the second electrode pattern CDP2 are shown to be formed on the same layer, but this disclosure is not limited thereto. Alternatively, the second electrode pattern CDP2 may be formed in a different conductive layer than the first electrode pattern CDP1, for example, in a fourth conductive layer disposed on a third conductive layer, with multiple insulating layers interposed between the third and fourth conductive layers. In this case, the first voltage line VDL and the second voltage line VSL may be formed in the fourth conductive layer instead of the third conductive layer, and the first voltage line VDL may be electrically connected to the first drain electrode D_DT of the driving transistor DT via another electrode pattern. In some embodiments, the second and third conductive layers may include electrodes for a storage capacitor. The electrodes for the storage capacitor may be disposed in different layers and may be formed together in a first interlayer insulating layer IL1 to form a capacitor. In some embodiments, the electrodes for the storage capacitor may be integrally formed with the gate electrode G_DT and the first source electrode S_DT of the driving transistor DT, but this disclosure is not limited thereto.

[0098] Each of the buffer layer BL, the first gate insulating layer GI, and the first interlayer insulating layer IL1 may consist of a plurality of alternately stacked inorganic layers. In one example, each of the buffer layer BL, the first gate insulating layer GI, and the first interlayer insulating layer IL1 may be formed in which silicon oxide (SiO2) is formed. x ), silicon nitride (SiN) x ) and silicon nitride oxide (SiO) x N y The present disclosure is not limited to the alternating stacking of at least one inorganic layer in the form of two or more layers. In another example, each of the buffer layer BL, the first gate insulating layer GI, and the first interlayer insulating layer IL1 may be formed as comprising silicon oxide (SiO2). x ), silicon nitride (SiN) x ) or silicon nitride oxide (SiO) x N yA single inorganic layer. Furthermore, in some embodiments, the first interlayer insulation layer IL1 may be formed of an organic insulating material such as polyimide (PI).

[0099] The second and third conductive layers may be formed as a single layer or multiple layers of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu) or alloys thereof, but this disclosure is not limited thereto.

[0100] The via layer (VIA) is disposed on the third conductive layer. The via layer (VIA) may include an organic insulating material such as polyimide (PI) and may perform surface planarization.

[0101] Multiple electrodes RME, multiple first dams BNL1, multiple second dams BNL2, multiple light-emitting elements ED, and multiple connecting electrodes CNE are disposed on the via layer VIA. Multiple first insulating layers PAS1, second insulating layers PAS2, and third insulating layers PAS3 may be disposed on the via layer VIA.

[0102] The first dam portion BNL1 can be directly disposed on the via layer VIA. The first dam portions BNL1 can extend in the first direction DR1 and can be spaced apart from each other in the second direction DR2. In one example, the first dam portions BNL1 can extend in the first direction DR1 within the emission region EMA and can be disposed on both sides of the center of the emission region EMA in the second direction DR2. The first dam portions BNL1 can be spaced apart from each other in the second direction DR2, and the light-emitting elements ED can be disposed between the first dam portions BNL1.

[0103] The length of the first embankment BNL1 in the first direction DR1 may be less than the length of the emitting area EMA surrounded by the second embankment BNL2 in the first direction DR1. In the display area DPA, the first embankment BNL1 may be disposed throughout the entire display area DPA in the emitting area EMA to form a narrow island pattern that extends in one direction (e.g., the first direction DR1).

[0104] The first dam portion BNL1 may protrude at least partially from the top surface of the via layer VIA. Each of the protrusions of the first dam portion BNL1 may have a sloping side surface, and light emitted by the light-emitting element ED may be reflected by the electrode RME on the first dam portion BNL1 to be emitted upward from the via layer VIA. However, this disclosure is not limited thereto. Alternatively, each of the first dam portions BNL1 may have a semi-circular or semi-elliptical shape on its outer side. The first dam portion BNL1 may comprise an organic insulating material such as polyimide (PI), but this disclosure is not limited thereto.

[0105] Multiple electrodes RMEs can be disposed in the first sub-pixel SPX1 and extend in one direction (e.g., first direction DR1). The electrodes RMEs can extend in the first direction DR1 to be disposed in and across the emission region EMA and sub-region SA of the first sub-pixel SPX1, and can be spaced apart from each other in the second direction DR2.

[0106] The first electrode RME1 and the second electrode RME2 can be disposed in the first sub-pixel SPX1, spaced apart from each other in the second direction DR2. The first electrode RME1 and the second electrode RME2 can be disposed in the emission region EMA of the first sub-pixel SPX1, spaced apart from each other in the second direction DR2, and can extend beyond the second embankment BNL2 to be partially disposed in the sub-region SA of the neighboring sub-pixel SPXn adjacent to the first sub-pixel SPX1 in the first direction DR1. The two sets of electrode RMEs of two different sub-pixels SPXn, for example, the first electrode RME1 and the second electrode RME2 of the first sub-pixel SPX1 and the first electrode RME1 and the second electrode RME2 of the sub-pixel SPXn adjacent to the first sub-pixel SPX1 in the first direction DR1, can be separated by the separation portion ROP of the sub-region SA of the first sub-pixel SPX1 and the sub-region SA of another neighboring sub-pixel SPXn adjacent to the first sub-pixel SPX1 in the first direction DR1.

[0107] The electrode RME can be obtained by forming electrode lines extending in the first direction DR1 and cutting the electrode lines after the light-emitting element ED is arranged in the first sub-pixel SPX1. During the manufacturing of the display device 10, the electrode lines can be used to generate an electric field in the first sub-pixel SPX1 to align the light-emitting element ED in the first sub-pixel SPX1. Once the light-emitting element ED is aligned, the electrode lines can be cut in the separation portion ROP of the first sub-pixel SPX1 to form electrode RMEs spaced apart from each other in the first direction DR1.

[0108] The first electrode RME1 and the second electrode RME2 can be disposed on different first embankments BNL1. The first electrode RME1 can be disposed on the left side of the center of the emission region EMA, and can be partially disposed on the left first embankment BNL1. The second electrode RME2 can be spaced apart from the first electrode RME1 in the second direction DR2, and can be disposed on the right side of the center of the emission region EMA. The second electrode RME2 can be partially disposed on the right first embankment BNL1.

[0109] The electrode RME can be disposed on at least one inclined side surface of the first embankment BNL1. In one example, the width of the electrode RME in the second direction DR2 can be smaller than the width of the first embankment BNL1 or the second embankment BNL2 in the second direction DR2. The electrode RME can be configured to cover at least one side surface of each of the first embankments BNL1, thereby reflecting the light emitted by the light-emitting element ED.

[0110] The distance between electrodes RME in the second direction DR2 can be less than the distance between the first embankment portions BNL1 in the second direction DR2. At least a portion of the electrodes RME can be directly disposed on the via layer VIA, and therefore can fall on the same plane (or at the same plane).

[0111] The first electrode RME1 and the second electrode RME2 can be connected to the third conductive layer through the first electrode contact hole CTD and the second electrode contact hole CTS, respectively. The first electrode contact hole CTD and the second electrode contact hole CTS are formed in the region overlapping with the second embankment BNL2 on the third-direction DR3. The first electrode RME1 can contact the second electrode pattern CDP2 through the first electrode contact hole CTD penetrating the via layer VIA. The second electrode RME2 can contact the second voltage line VSL through the second electrode contact hole CTS penetrating the via layer VIA. The first electrode RME1 can be electrically connected to the driving transistor DT via the first electrode pattern CDP1 and the second electrode pattern CDP2, and thus can receive the first power supply voltage; the second electrode RME2 can be electrically connected to the second voltage line VSL, and thus can receive the second power supply voltage.

[0112] However, this disclosure is not limited thereto. Alternatively, the first electrode RME1 may be electrically connected to the second voltage line VSL, and the second electrode RME2 may be electrically connected to the first voltage line VDL. As will be described later, the pattern of the arrangement of the electrodes RME and the light-emitting element ED may vary depending on the type of line used for aligning the light-emitting element ED. The first electrode contact hole CTD and the second electrode contact hole CTS are shown located below the second embankment BNL2, but this disclosure is not limited thereto. Alternatively, the first electrode contact hole CTD and the second electrode contact hole CTS may be formed inside the emitting region EMA or the sub-region SA.

[0113] The electrode RME can be electrically connected to the light-emitting element ED. The electrode RME can be connected to the light-emitting element ED via the connecting electrode CNE, and can transmit electrical signals applied to it from the conductive layer below the via layer VIA to the light-emitting element ED.

[0114] The electrode RME may include a conductive material with high reflectivity. In one example, the electrode RME may include a material with high reflectivity, such as a metal like silver (Ag), Cu, or Al, or an alloy of Al, Ni, or lanthanum (La). The electrode RME may reflect upward light emitted by the light-emitting element ED and then traveling toward the side surface of the first embankment BNL1.

[0115] However, this disclosure is not limited thereto. Alternatively, the electrode RME may also include a transparent conductive material. In one example, the electrode RME may include a material such as ITO, IZO, or ITZO. In some embodiments, the electrode RME may be formed as a stack of more than one transparent conductive material layer and more than one metal layer with high reflectivity, or as a monolayer comprising a transparent conductive material and a metal with high reflectivity. In one example, the electrode RME may have a stack of ITO / Ag / ITO, ITO / Ag / IZO, or ITO / Ag / ITZO / IZO.

[0116] A first insulating layer PAS1 is disposed on the via layer VIA and the electrode RME. The first insulating layer PAS1 can be configured to cover (e.g., completely cover) the electrode RME and can protect and insulate the electrode RME. In addition, the first insulating layer PAS1 can prevent the light-emitting element ED disposed on the first insulating layer PAS1 from contacting and being damaged by other elements.

[0117] In one example, the first insulating layer PAS1 may be formed to be partially recessed between electrodes RME spaced apart from each other in the second direction DR2. A light-emitting element ED may be disposed on the top surface of the recessed portion of the first insulating layer PAS1, and a space may be formed between the light-emitting element ED and the first insulating layer PAS1.

[0118] The first insulating layer PAS1 may include a first contact CT1 and a second contact CT2, which expose portions of the top surface of the electrode RME. The first contact CT1 and the second contact CT2 may penetrate the first insulating layer PAS1 (and the second insulating layer PAS2 (see, for example, see...) Figure 7 The connecting electrode CNE, which will be described later, can contact the portion of the electrode RME exposed by the first contact CT1 and the second contact CT2.

[0119] The second dam portion BNL2 can be disposed on the first insulating layer PAS1. The second dam portion BNL2 may include portions extending in the first direction DR1 and portions extending in the second direction DR2, and therefore can be arranged in a grid pattern in a plan view. The second dam portion BNL2 can be disposed along the boundary of the first sub-pixel SPX1 to separate the first sub-pixel SPX1 from other neighboring sub-pixels SPXn. Furthermore, the second dam portion BNL2 can be disposed around (e.g., surrounding) the emission region EMA and sub-region SA of the first sub-pixel SPX1, and the area defined and opened by the second dam portion BNL2 can be the emission region EMA and sub-region SA of the first sub-pixel SPX1.

[0120] The second dam portion BNL2 may have an appropriate height (e.g., a predetermined height). In some embodiments, the height of the second dam portion BNL2 may be greater than the height of the first dam portion BNL1, and the thickness of the second dam portion BNL2 may be equal to or greater than the thickness of the first dam portion BNL1. The second dam portion BNL2 can prevent ink from overflowing from one sub-pixel SPXn to another sub-pixel SPXn (e.g., adjacent sub-pixels SPXn) during inkjet printing performed during the manufacture of the display device 10. The second dam portion BNL2 can prevent inks having different light-emitting element ED groups for different sub-pixels SPXn from mixing together. Like the first dam portion BNL1, the second dam portion BNL2 may include polyimide (PI), but this disclosure is not limited thereto.

[0121] A light-emitting element (ED) can be disposed on a first insulating layer (PAS1) between electrodes (RME). Each of the light-emitting elements (EDs) may include a plurality of layers arranged along a direction parallel to the top surface of the first substrate (SUB). The light-emitting elements (EDs) may be arranged such that the light-emitting elements (EDs) in their extending direction are parallel to the first substrate (SUB), and the semiconductor layers included in each of the light-emitting elements (EDs) may be arranged sequentially along a direction parallel to the top surface of the first substrate (SUB). However, this disclosure is not limited thereto. Alternatively, the plurality of layers included in each of the light-emitting elements (EDs) may be arranged in a direction perpendicular to the first substrate (SUB).

[0122] The light-emitting element ED can be disposed between the first diaphragm portions BNL1 on electrodes RME spaced apart from each other in the second direction DR2. The light-emitting element ED can be disposed spaced apart from each other in the direction in which the electrodes RME extend (i.e., in the first direction DR1) and can be substantially parallel to each other. The light-emitting element ED can extend in one direction, and the length of the light-emitting element ED can be greater than the distance between the electrodes RME spaced apart from each other in the second direction DR2. The light-emitting element ED can be arranged such that its two ends can be placed on different electrodes RME, and the electrodes RME in their direction of extension (e.g., the first direction DR1) can be substantially perpendicular to the light-emitting element ED in its direction of extension (e.g., the second direction DR2). However, this disclosure is not limited thereto. Alternatively, the light-emitting element ED can be disposed obliquely relative to the electrodes RME in their direction of extension (e.g., the first direction DR1).

[0123] Light-emitting elements (EDs) can emit light in different wavelength ranges depending on the material of the semiconductor layers included therein, but this disclosure is not limited thereto. Alternatively, EDs can emit light of the same color. Furthermore, each of the EDs can include a semiconductor layer doped with dopants of different conductivity types and can be aligned such that one end of it can be oriented in a specific direction by an electric field formed between electrodes RMEs.

[0124] Each of the light-emitting elements (EDs) may include multiple semiconductor layers, and a first end and a second end of each ED may be defined based on one of the multiple semiconductor layers. The first end of the ED may be disposed on a first electrode RME1, and the second end of the ED may be disposed on a second electrode RME2. The first end of the ED may face a second side, i.e., the left side, in the second direction DR2.

[0125] The light-emitting element (ED) can contact the connecting electrode (CNE) and therefore can be electrically connected to the electrode (RME). When some of the semiconductor layers included in each of the EDs are exposed at both ends along the length of each ED, the exposed semiconductor layers can contact the connecting electrode (CNE). The ED can be electrically connected to the electrode (RME) or the conductive layer beneath the via layer (VIA) via the connecting electrode (CNE), and electrical signals can be applied to the ED, causing it to emit light within a specific wavelength range.

[0126] A second insulating layer PAS2 can be disposed on the light-emitting element ED. In one example, the second insulating layer PAS2 can be configured to cover a portion of the outer surface of the light-emitting element ED, but not cover the sides or both ends of each of the light-emitting elements ED. In a plan view, a portion of the second insulating layer PAS2 on the light-emitting element ED extends across the first insulating layer PAS1 in the first direction DR1, and thus can form a linear pattern or island pattern in the first sub-pixel SPX1. The second insulating layer PAS2 can protect and fix the light-emitting element ED during the manufacture of the display device 10. Furthermore, the second insulating layer PAS2 can be configured to fill the space between the light-emitting element ED and the first insulating layer PAS1.

[0127] The second insulating layer PAS2 can also be disposed on the first embankment BNL1 and the second embankment BNL2. The second insulating layer PAS2 can be disposed on the first insulating layer PAS1, but can expose both ends of each of the light-emitting elements ED and a portion of the area where the electrode RME will be disposed. The second insulating layer PAS2 can initially be formed on the entire surface of the first insulating layer PAS1, and can then be partially removed to expose both ends of each of the light-emitting elements ED.

[0128] The second insulating layer PAS2 can even be disposed in the sub-region SA of the first sub-pixel SPX1. The first insulating layer PAS1 and the second insulating layer PAS2 can be partially removed during the cutting of the electrode lines after the light-emitting element ED is disposed, and a portion of the via layer VIA can be exposed in the separation section ROP. The third insulating layer PAS3 can be directly disposed on the exposed portion of the via layer VIA.

[0129] The connecting electrode CNE and the third insulating layer PAS3 can be disposed on the second insulating layer PAS2.

[0130] The connecting electrode CNE can be disposed on the light-emitting element ED and the electrode RME. The connecting electrode CNE can be partially disposed on the second insulating layer PAS2 and can be insulated from each other through the second insulating layer PAS2 and the third insulating layer PAS3. The connecting electrode CNE can be in contact with the light-emitting element ED and the electrode RME. The connecting electrode CNE can be in direct contact with the semiconductor layers disposed at both ends of each of the light-emitting elements ED, and can be in contact with at least one of the electrodes RME through the first contact CT1 and the second contact CT2. Both ends of each of the light-emitting elements ED can be electrically connected to the electrode RME via the connecting electrode CNE.

[0131] A first connecting electrode CNE1 can extend along a first direction DR1 and can be disposed on a first electrode RME1. The first connecting electrode CNE1 can contact the first electrode RME1 via a first contact CT1 exposing the top surface of the first electrode RME1, and also contact the first end of the light-emitting element ED. A second connecting electrode CNE2 can extend along the first direction DR1 and can be disposed on a second electrode RME2. The second connecting electrode CNE2 can contact the second electrode RME2 via a second contact CT2 exposing the top surface of the second electrode RME2, and also contact the second end of the light-emitting element ED. The first connecting electrode CNE1 and the second connecting electrode CNE2 can transmit electrical signals applied to the first electrode RME1 and the second electrode RME2 to the light-emitting element ED.

[0132] In the plan view, the connecting electrodes CNE can be spaced apart from each other in the second direction DR2. The first connecting electrode CNE1 and the second connecting electrode CNE2 can be spaced apart from each other (e.g., spaced apart by a predetermined distance) so that they are not directly connected to each other. The connecting electrodes CNE can not only be spaced apart from each other so that they are not directly connected to each other, but are also insulated from each other by a third insulating layer PAS3 (and a second insulating layer PAS2) disposed between them.

[0133] The first contact CT1 and the second contact CT2 can be configured not to overlap with the light-emitting element ED in the third direction DR3. In one example, the first contact CT1 and the second contact CT2 can be formed to be spaced apart from the area where the light-emitting element ED is disposed in the first direction DR1. The first contact CT1 and the second contact CT2 are shown disposed in a sub-region SA, but the present disclosure is not limited thereto. Alternatively, the first contact CT1 and the second contact CT2 can be formed in the portion of the emitting region EMA where the light-emitting element ED is not disposed.

[0134] The connecting electrode CNE may include a conductive material. In one example, the connecting electrode CNE may include ITO, IZO, ITZO, or Al. The connecting electrode CNE may include, for example, a transparent conductive material, and light emitted from the light-emitting element ED can travel through the connecting electrode CNE toward the electrode RME. However, this disclosure is not limited thereto.

[0135] A third insulating layer PAS3 is disposed on the second connecting electrode CNE2 and the second insulating layer PAS2. The third insulating layer PAS3 can be disposed on the entire surface of the second insulating layer PAS2 to cover the second connecting electrode CNE2, and the first connecting electrode CNE1 can be disposed on the third insulating layer PAS3. The third insulating layer PAS3 can be disposed on the entire surface of the via layer VIA, except for the area where the first connecting electrode CNE1 is disposed. That is, the third insulating layer PAS3 can be disposed not only on the first insulating layer PAS1 and the second insulating layer PAS2, but also on the first embankment BNL1 and the second embankment BNL2. The third insulating layer PAS3 can insulate the first connecting electrode CNE1 and the second connecting electrode CNE2, which are not in direct contact with each other.

[0136] In some implementations, the third insulating layer PAS3 may be omitted. In this case, the connection electrode CNE can be disposed directly on the second insulating layer PAS2, and therefore can be placed in substantially the same layer.

[0137] In some embodiments, an additional insulating layer may also be disposed on the first connecting electrode CNE1 and the third insulating layer PAS3. The additional insulating layer can protect the components disposed on the first substrate SUB from the influence of the external environment.

[0138] The first insulating layer PAS1, the second insulating layer PAS2, and the third insulating layer PAS3 may include inorganic or organic insulating materials, but this disclosure is not limited thereto.

[0139] Figure 8 This is a three-dimensional cut view of a light-emitting element according to an embodiment of the present disclosure.

[0140] refer to Figure 8 The light-emitting element (ED) can be a light-emitting diode (LED), especially an ILED with a size of a few nanometers or micrometers and formed of inorganic materials. If an electric field is formed in a specific direction between two opposing electrodes, the light-emitting element (ED) can be aligned between the two electrodes forming the polarity.

[0141] The light-emitting element (ED) can have a shape that extends in one direction. The ED can have the shape of a cylinder, rod, wire, or tube, but there are no particular limitations on the shape of the ED. Alternatively, the ED can have the shape of a polygonal prism such as a regular cube, a rectangular parallelepiped, or a hexagonal prism, or it can have a shape that extends in one direction but has a partially inclined outer surface.

[0142] The light-emitting element (ED) may include a semiconductor layer doped with impurities of any conductivity type (e.g., p-type or n-type). The semiconductor layer can receive electrical signals from an external power source to emit light within a specific wavelength range. The ED may include a first semiconductor layer 31, a second semiconductor layer 32, a light-emitting layer 36, an electrode layer 37, and an insulating film 38.

[0143] The first semiconductor layer 31 may include an n-type semiconductor. The first semiconductor layer 31 may include a semiconductor material, namely Al. x Ga y In 1-x-y N (where 0 ≤ x ≤ 1, 0 ≤ y ≤ 1, and 0 ≤ x + y ≤ 1). In one example, the first semiconductor layer 31 may include at least one of AlGaInN, GaN, AlGaN, InGaN, AlN, and InN doped with an n-type dopant. The n-type dopant may be Si, Ge, Se, or Sn.

[0144] The second semiconductor layer 32 may be disposed on the first semiconductor layer 31, and the light-emitting layer 36 may be interposed between them. The second semiconductor layer 32 may include a p-type semiconductor. The second semiconductor layer 32 may include a semiconductor material, namely Al. x Ga y In 1-x-y N (where 0 ≤ x ≤ 1, 0 ≤ y ≤ 1, and 0 ≤ x + y ≤ 1). In one example, the second semiconductor layer 32 may include at least one of AlGaInN, GaN, AlGaN, InGaN, AlN, and InN doped with a p-type dopant. The p-type dopant may be Mg, Zn, Ca, or Ba.

[0145] Figure 8 The first semiconductor layer 31 and the second semiconductor layer 32 are shown to be formed as a single layer, but this disclosure is not limited thereto. Alternatively, depending on the material of the light-emitting layer 36, each of the first semiconductor layer 31 and the second semiconductor layer 32 may include more than one layer, such as, for example, a cladding layer or a tensile strain barrier reduction (TSBR) layer.

[0146] A light-emitting layer 36 may be disposed between a first semiconductor layer 31 and a second semiconductor layer 32. The light-emitting layer 36 may comprise a single-quantum-well structure material or a multi-quantum-well structure material. When the light-emitting layer 36 comprises a material with a multi-quantum-well structure, the light-emitting layer 36 may have a structure in which multiple quantum layers and multiple well layers are alternately stacked. The light-emitting layer 36 can emit light by causing electron-hole pairs to recombine according to an electrical signal applied to it via the first semiconductor layer 31 and the second semiconductor layer 32. The light-emitting layer 36 may comprise materials such as AlGaN or AlGaInN. Specifically, when the light-emitting layer 36 has a multi-quantum-well structure in which multiple quantum layers and multiple well layers are alternately stacked, the quantum layers may comprise materials such as AlGaN or AlGaInN, and the well layers may comprise materials such as GaN or AlInN.

[0147] The light-emitting layer 36 may have a structure in which semiconductor materials with large band gaps and semiconductor materials with small band gaps are stacked alternately, or may include group III or group V semiconductor materials, depending on the wavelength of the light to be emitted. There are no particular limitations on the type of light emitted by the light-emitting layer 36. The light-emitting layer 36 may emit light in the red or green wavelength range, instead of blue light, as needed.

[0148] Electrode layer 37 may be disposed on the second semiconductor layer 32. Electrode layer 37 may be disposed on the surface of the second semiconductor layer 32, which faces the surface of the second semiconductor layer 32 that contacts the light-emitting layer 36. Electrode layer 37 may be an ohmic connection electrode, but this disclosure is not limited thereto. Alternatively, electrode layer 37 may be a Schottky connection electrode. The light-emitting element ED may include at least one electrode layer 37. The light-emitting element ED may include more than one electrode layer 37, but this disclosure is not limited thereto. For example, an additional electrode layer 37 may be disposed on the surface of the first semiconductor layer 31, which faces the surface of the first semiconductor layer 31 that contacts the light-emitting layer 36. Alternatively, electrode layer 37 may not be provided.

[0149] When the light-emitting element ED is electrically connected to the electrode RME or the connecting electrode CNE, the electrode layer 37 can reduce the resistance between the light-emitting element ED and the electrode RME or the connecting electrode CNE. The electrode layer 37 may include a conductive metal. In one example, the electrode layer 37 may include at least one of Al, Ti, In, gold (Au), Ag, ITO, IZO, and ITZO.

[0150] The insulating film 38 may be configured to surround (e.g., encircle) the outer surfaces (e.g., the outer peripheral surfaces) of the first semiconductor layer 31 and the second semiconductor layer 32, the light-emitting layer 36, and the electrode layer 37. In one example, the insulating film 38 may be configured to at least surround the light-emitting layer 36, but expose both ends of the light-emitting element ED in the longitudinal direction. In the region adjacent to at least one end of the light-emitting element ED, the insulating film 38 may be formed as circular in cross-sectional view.

[0151] The insulating film 38 may include a material with insulating properties, such as, for example, silicon oxide (SiO2). x ), silicon nitride (SiN) x ), silicon nitride oxide (SiO) x N y ), aluminum nitride (AlN) x ) or aluminum oxide (AlO) x The insulating film 38 is shown as a single-layer film, but this disclosure is not limited thereto. Alternatively, in some embodiments, the insulating film 38 may be formed as a multilayer film in which multiple layers are stacked.

[0152] The insulating film 38 protects other components of the light-emitting element (ED). The insulating film 38 prevents any short circuits that may occur in the ED if it comes into direct contact with the electrodes to which an electrical signal is applied. Furthermore, the insulating film 38 prevents degradation of the ED's emission efficiency.

[0153] The outer surface of the insulating film 38 can undergo surface treatment. The light-emitting element ED can be sprayed onto the electrode while being dispersed in ink (e.g., a predetermined ink). Here, the surface of the insulating film 38 can be treated with hydrophobic or hydrophilic properties to keep the light-emitting element ED dispersed in the ink and prevent it from agglomerating with other adjacent light-emitting elements ED.

[0154] As described above, multiple light-emitting elements (EDs) are disposed on the electrode RME. In one example, the EDs can be prepared in a dispersed state in ink and can be obtained by printing using an inkjet printing apparatus. The ink including the EDs can be jetted onto the electrode RME, an alignment voltage can be applied to the electrode RME, and thus, the alignment direction and position of the EDs change, allowing the EDs to be placed on the electrode RME.

[0155] When solvent molecules of the ink, including the light-emitting element (ED), are located on the electrode RME electrically connected to the circuit layer CCL, static electricity may be generated due to surface friction between the ink and the electrode RME. This static electricity may interfere with the alignment of the light-emitting element (ED) and may damage the light-emitting layer 36 of the ED. Since the display device 10 includes circuitry (or virtual circuitry) for removing static electricity that may be generated on the electrode RME during inkjet printing, misalignment of the light-emitting element (ED) and damage to the ED can be prevented or reduced.

[0156] Figure 9 It is shown Figure 1 A cross-sectional view of electrodes in a sub-pixel of a display device and multiple transistors connected to the electrodes. Figure 10 It is shown Figure 9 A schematic diagram illustrating how the electrodes and transistors are connected.

[0157] refer to Figure 9 and Figure 10 In the sub-pixel SPXn, the display device 10 may include an electrode RME (i.e., a first electrode RME1 and a second electrode RME2) and a plurality of transistors connected to the electrode RME (i.e., a first transistor T1 and a second transistor T2 electrically connected to the first electrode RME1 and the second electrode RME2, respectively).

[0158] The first transistor T1 includes a first active layer ACT1, a first gate electrode G1, a first source electrode S1, and a first drain electrode D1. The second transistor T2 includes a second active layer ACT2, a second gate electrode G2, a second source electrode S2, and a second drain electrode D2. Similar to the active layer ACT_DT of the driving transistor DT, the first active layer ACT1 and the second active layer ACT2 are disposed on the buffer layer BL. The first gate electrode G1 and the second gate electrode G2 can be formed by a second conductive layer disposed on the first gate insulating layer GI, and the first source electrode S1, the second source electrode S2, the first drain electrode D1, and the second drain electrode D2 can be formed by a third conductive layer disposed on the first interlayer insulating layer IL1. That is, the first transistor T1 and the second transistor T2 can be disposed in the same layers as the driving transistor DT.

[0159] The first electrode RME1 can be connected to one end of the first transistor T1, and the second electrode RME2 can be connected to one end of the second transistor T2. The first electrode RME1 and the second electrode RME2 can be directly connected or electrically connected to the first transistor T1 and the second transistor T2, respectively. In one example, the first electrode RME1 can be directly connected to the first drain electrode D1 of the first transistor T1 through a contact hole in the via layer VIA, and the second electrode RME2 can be directly connected to the second drain electrode D2 of the second transistor T2 through a contact hole in the via layer VIA. However, this disclosure is not limited to this example. In another example, the first electrode RME1 and the second electrode RME2 can be electrically connected to the first transistor T1 and the second transistor T2, respectively, via another element such as a capacitor, but not directly connected to the first transistor T1 and the second transistor T2, or they can be connected to the first source electrode S1 and the second source electrode S2, respectively, but not connected to the first drain electrode D1 and the second drain electrode D2, respectively.

[0160] As used herein, the term "connection" means not only that one element is physically connected to another element, but also that one element is connected to another element via yet another element. A monolithic component can be understood as having parts connected to each other. Furthermore, a connection between two elements can include not only a direct connection between the two elements, but also an electrical connection between the two elements.

[0161] The first transistor T1 and the second transistor T2 can be connected to the first electrode RME1 and the second electrode RME2, respectively, thus allowing static electricity generated on the electrodes RME to flow in one direction. When static electricity is generated on the electrodes RME, the light-emitting layer 36 of the light-emitting element ED may be damaged, or the light-emitting element ED may not be properly aligned due to static electricity. The first transistor T1 and the second transistor T2 allow static electricity to flow in one direction, thus preventing damage to the light-emitting element ED by static electricity.

[0162] The direction in which the first transistor T1 and the first electrode RME1 are connected can be opposite to the direction in which the second transistor T2 and the second electrode RME2 are connected, and the direction in which static electricity generated in the first electrode RME1 flows can also be opposite to the direction in which static electricity generated in the second electrode RME2 flows. In one example, the first transistor T1 can be forward biased to the first electrode RME1, and the second transistor T2 can be reverse biased to the second electrode RME2. Static electricity generated in the first electrode RME1 can flow toward the first transistor T1, which is forward biased to the first electrode RME1, and static electricity generated in the second electrode RME2 can flow away from the second transistor T2, which is reverse biased to the second electrode RME2. When the first electrode RME1 and the second electrode RME2 are electrically connected to the first voltage line VDL and the second voltage line VSL, respectively, electrostatic currents flowing in opposite directions can be generated between the first transistor T1 and the second transistor T2 and the first voltage line VDL and the second voltage line VSL. These electrostatic currents can cause a potential difference, and therefore, an electrostatic field can be generated between the electrodes RME. An electrostatic field can be used for the initial alignment of light-emitting elements (EDs). This will be described in detail later.

[0163] In one example, the first terminals (e.g., drain electrodes D1 and D2) of the first transistor T1 and the second transistor T2 can be connected to electrode RME, the second terminals (e.g., source electrodes S1 and S2) of the first transistor T1 and the second transistor T2 can be grounded, and the first gate electrodes G1 and the second gate electrodes G2 of the first transistor T1 and the second transistor T2 can be connected to either the first or second terminal of the first transistor T1 and the second transistor T2 for forward bias connection or reverse bias connection. That is, the first gate electrodes G1 and the second gate electrodes G2 can be at the same potential as the first or second terminal of the first transistor T1 and the second transistor T2, and the first or second terminal of the first transistor T1 and the second transistor T2 can be connected to the first electrode RME1 and the second electrode RME2 or grounded, and the forward bias or reverse bias can be determined according to which of the first electrode RME1 and the second electrode RME2, and the first transistor T1 and the second transistor T2 are respectively connected to.

[0164] In one example, the first terminal of the first transistor T1 (e.g., the first drain electrode D1) can be connected to the first electrode RME1, the second terminal of the first transistor T1 (e.g., the first source electrode S1) can be grounded, and the first gate electrode G1 of the first transistor T1 can be forward biased by connecting to the first terminal of the first transistor T1 (e.g., the first drain electrode D1). In another example, the first terminal of the second transistor T2 (e.g., the second drain electrode D2) can be connected to the second electrode RME2, the second terminal of the second transistor T2 (e.g., the second source electrode S2) can be grounded, and the second gate electrode G2 of the second transistor T2 can be reverse biased by connecting to the second terminal of the second transistor T2 (e.g., the second source electrode S2). When the first terminal of the first transistor T1 connected to the first electrode RME1 is the first drain electrode D1, the first gate electrode G1 can be turned on by connecting to the first drain electrode D1. When the first terminal of the second transistor T2 connected to the second electrode RME2 is the second drain electrode D2, the second gate electrode G2 can be turned off by connecting to the grounded second source electrode S2.

[0165] During the manufacturing of the display device 10, when ink is sprayed onto the electrode RME, since the first transistor T1 is in a forward-biased conducting state to the first electrode RME1, the static electricity generated on the first electrode RME1 can flow to the first source electrode S1 of the first transistor T1, and since the second transistor T2 is in a reverse-biased cutoff state to the second electrode RME2, the static electricity generated on the second electrode RME2 can flow to the second voltage line VSL. By allowing the static electricity generated by the ink sprayed onto the electrode RME to flow in one direction via the first transistor T1 and the second transistor T2, damage to the light-emitting element ED by static electricity can be prevented.

[0166] The first transistor T1 and the second transistor T2 may be independent of or included in the driving circuitry of the corresponding sub-pixel SPXn in the display device 10. During the driving of the display device 10, the driving transistor DT, as well as the first switching transistor ST1 and the second switching transistor ST2, can be driven, as shown below. Figure 3 As shown in the diagram. As will be described later, the characteristics and dimensions of the first transistor T1 and the second transistor T2 can be controlled such that the first transistor T1 and the second transistor T2 can be appropriately configured with forward bias or reverse bias connections to allow static electricity generated during the manufacture of the display device 10 to flow in one direction without affecting the operation of the drive circuit. That is, the first transistor T1 and the second transistor T2 can have dimensions sufficient to control the static electricity generated during the manufacture of the display device 10 without affecting the operation of the drive circuit.

[0167] The first transistor T1 and the second transistor T2 are shown as, but not limited to, n-type transistors, and the first drain electrode D1 and the second drain electrode D2 are shown as, but not limited to, connected to the first electrode RME1 and the second electrode RME2, respectively. Alternatively, the first transistor T1 and the second transistor T2 can be p-type transistors, depending on the material of the active layer of the display device 10, in which case the first source electrode S1 and the second source electrode S2 can be connected to the electrode RME.

[0168] Figure 11 It is shown Figure 9 A schematic diagram of another example of how electrodes and transistors are connected.

[0169] refer to Figure 11 The first transistor T1 and the second transistor T2 can be p-type transistors. The first source electrode S1 and the second source electrode S2 of the first transistor T1 and the second transistor T2 can be connected to the electrode RME, and the first drain electrode D1 and the second drain electrode D2 of the first transistor T1 and the second transistor T2 can be grounded. When the active layer of the display device 10 is formed as a p-type semiconductor layer, the first transistor T1 and the second transistor T2 can be p-type transistors, and in accordance with the following aspects... Figure 11 The implementation method can be with Figure 10 The implementation is the opposite: which electrodes of the first transistor T1 and the second transistor T2 are connected to electrode RME, and which electrodes of the first transistor T1 and the second transistor T2 are grounded. The first gate electrode G1 of the first transistor T1 can be connected to the first drain electrode D1 of the first transistor T1, and thus grounded, so that the first transistor T1 can be forward biased to the first electrode RME1, and the second gate electrode G2 of the second transistor T2 can be connected to the second source electrode S2 of the second transistor T2, so that the second transistor T2 can be reverse biased to the second electrode RME2.

[0170] Although not specifically shown, since the first transistor T1 and the second transistor T2 are p-type transistors, the driving transistor DT, as well as the first switching transistor ST1 and the second switching transistor ST2, can also be p-type transistors.

[0171] The method of manufacturing the display device 10 will be described below.

[0172] Figures 12 to 17 This is a schematic diagram illustrating the steps of a method for manufacturing a display device according to an embodiment of the present disclosure. Figures 12 to 17 This illustrates how the light-emitting element ED is aligned during the manufacture of the display device 10 by the electric fields EC1 and EC2 generated between the electrodes RME.

[0173] refer to Figures 12 to 17A method for manufacturing a display device 10 may include: forming a first electrode RME1 electrically connected to a first transistor T1 and a first voltage line VDL and a second electrode RME2 electrically connected to a second transistor T2 and a second voltage line VSL on a first substrate SUB; spraying ink Ink having light-emitting elements ED dispersed therein onto the first electrode RME1 and the second electrode RME2; a first alignment step, generating a first electric field EC1 using electrostatic ESD flowing in the first electrode RME1 and the first transistor T1 and electrostatic ESD flowing in the second electrode RME2 and the second transistor T2, and thereby aligning the light-emitting elements ED using the first electric field EC1; and a second alignment step, generating a second electric field EC2 between the first electrode RME1 and the second electrode RME2 by applying a first alignment voltage V1 and a second alignment voltage V2 to the first electrode RME1 and the second electrode RME2 respectively, and thereby aligning the light-emitting elements ED using the second electric field EC2.

[0174] First, refer to Figure 12 This forms a first electrode RME1 and a second electrode RME2, respectively connected to the first transistor T1 and the second transistor T2. The arrangement of the first electrode RME1, the second electrode RME2, and the first transistor T1 and the second transistor T2 is as described above. Figures 4 to 10 The description is the same. The first transistor T1 can be forward biased to the first electrode RME1, and the second transistor T2 can be reverse biased to the second electrode RME2. The first electrode RME1 and the second electrode RME2 can be connected to the first voltage line VDL and the second voltage line VSL, respectively. The first voltage line VDL and the second voltage line VSL can be used to apply a first alignment voltage V1 and a second alignment voltage V2, respectively, during the alignment of the light-emitting element ED (see [link to documentation]). Figure 17 ).

[0175] Subsequently, refer to Figure 13 and Figure 14 The light-emitting element (ED) is sprayed onto the electrode RME. In one example, the ED can be prepared in a state dispersed in ink (Ink) and sprayed onto the electrode RME. The ED receives a first electric field EC1 and a second electric field EC2 generated between the electrodes RME (see [link to documentation]). Figure 17 When the force is applied, the alignment direction and position of the light-emitting element ED can be changed, and therefore, the light-emitting element ED can be aligned on the electrode RME.

[0176] The electrode RME can be electrically connected to the first voltage line VDL and the second voltage line VSL of the circuit layer CCL below the via layer VIA, as well as the first transistor T1 and the second transistor T2. When ink Ink is sprayed onto the electrode RME, electrostatic discharge (ESD) can be generated due to surface friction between the electrode RME and the ink Ink. If the light-emitting element ED is aligned using the ESD that still needs to be removed, some of the light-emitting elements ED may become stuck to the electrode RME, or the light-emitting layer 36 of the light-emitting element ED may be damaged due to the ESD. That is, ESD may affect the alignment of the light-emitting element ED and the emission characteristics of the light-emitting element ED. However, as described above, since the display device 10 includes the electrode RME and the first transistor T1 and the second transistor T2 connected to the electrode RME, the display device 10 includes a circuit (e.g., a virtual circuit) capable of removing the ESD generated on the electrode RME. Therefore, the static electricity generated due to surface friction between the ink Ink and the electrode RME can flow in one direction due to the circuit (e.g., the virtual circuit) including the first transistor T1 and the second transistor T2, and thus, damage to the light-emitting element ED can be prevented or reduced.

[0177] Furthermore, as described above, when the first transistor T1 and the second transistor T2 are forward or reverse biased to the electrode RME, the direction of flow of the electrostatic ESD generated on the first electrode RME1 can be opposite to the direction of flow of the electrostatic ESD generated on the second electrode RME2. Therefore, a potential difference can be generated due to the current flowing in the first electrode RME1 and the second electrode RME2 due to the electrostatic ESD, and thus, an electric field can be generated between the electrodes RME.

[0178] like Figure 15 and Figure 16 As shown, a first electrostatic current E1 flowing to the first transistor T1, which is forward-biased to the first electrode RME1, can flow in the first electrode RME1, and a second electrostatic current E2 flowing to the second transistor T2, which is reverse-biased to the second electrode RME2, can flow in the second electrode RME2. Since the first electrostatic current E1 and the second electrostatic current E2 are different from each other, a potential difference can occur between them. Therefore, due to the potential difference between the first electrostatic current E1 and the second electrostatic current E2, a first electric field EC1 can be generated in the ink Ink on the first electrode RME1 and the second electrode RME2.

[0179] Since each of the light-emitting elements EDs, which are provided with a first semiconductor layer 31 and a second semiconductor layer 32, has different polarities at its two ends, the light-emitting element ED can have a dipole moment. The light-emitting element ED can receive a force from the first electric field EC1 while being dispersed in the ink Ink, according to the direction of its dipole moment, and the light-emitting element ED can be aligned such that the two ends of each of the light-emitting elements ED can be located on the first electrode RME1 and the second electrode RME2. However, since the first electric field EC1 is relatively weak, aligning the light-emitting element ED with the first electric field EC1, i.e., the first alignment step, can be a preliminary alignment step. The first alignment step can also be a step to prevent the light-emitting element ED from sticking to the electrode RME and to remove static electricity (ESD) to prevent or reduce damage to the light-emitting element ED.

[0180] After that, as Figure 17 As shown, the light-emitting element ED is aligned twice by a second electric field EC2, which is generated by applying a first alignment voltage V1 and a second alignment voltage V2 to the first electrode RME1 and the second electrode RME2, respectively. The first electrode RME1 and the second electrode RME2 can receive the first alignment voltage V1 and the second alignment voltage V2 via a first voltage line VDL and a second voltage line VSL, respectively. The first alignment voltage V1 and the second alignment voltage V2 can generate the second electric field EC2 due to the potential difference between them, and the light-emitting element ED can be aligned on the electrode RME by receiving the force from the second electric field EC2. In one example, in the second alignment step, the first alignment voltage V1 applied to the first electrode RME1 can be an alternating current (AC) voltage, and the second alignment voltage V2 applied to the second electrode RME2 can be a ground voltage. The light-emitting element ED can have a dipole moment and can be aligned such that a particular end of the light-emitting element ED can be oriented in a particular direction due to the second electric field EC2 generated by the first alignment voltage V1 and the second alignment voltage V2. In one example, the light-emitting element ED can be aligned such that the first end and the second end of the light-emitting element ED can be placed on the first electrode RME1 and the second electrode RME2, respectively.

[0181] Subsequently, although not specifically shown, the display device 10 can be obtained by drying ink Ink and then forming an insulating layer and connecting electrode CNE on the light-emitting element ED.

[0182] Since the display device 10 includes a circuit (e.g., a virtual circuit) consisting of a first transistor T1 and a second transistor T2 connected to the electrode RME, electrostatic ESD generated by surface friction between the ink Ink and the electrode RME during ink jetting can be removed. Furthermore, a first electrostatic current E1 and a second electrostatic current E2 can flow in the circuit (e.g., the virtual circuit) connected to the electrode RME, and therefore, the light-emitting element ED can be initially aligned by, for example, a first electric field EC1. The display device 10 can prevent or reduce damage to the light-emitting element ED by electrostatic ESD, and the alignment degree of the light-emitting element ED can be improved by utilizing the first electrostatic current E1 and the second electrostatic current E2 for initial alignment.

[0183] Other embodiments of the display device according to this disclosure will be described below.

[0184] Figure 18 This is a cross-sectional view showing electrodes in a sub-pixel of a display device according to an embodiment of the present disclosure and a plurality of transistors connected to the electrodes. Figure 19 It is shown Figure 18 A schematic diagram illustrating how the electrodes and transistors are connected.

[0185] refer to Figure 18 and Figure 19 In each sub-pixel SPXn, the display device 10_1 may further include a first capacitor C1 connected to a node between the first transistor T1 and the first electrode RME1, and a second capacitor C2 connected to a node between the second transistor T2 and the second electrode RME2. The display device 10_1 may further include a first capacitor electrode CSE1 and a second capacitor electrode CSE2 formed by a second conductive layer, and the first capacitor electrode CSE1 and the second capacitor electrode CSE2 may respectively form the first capacitor C1 and the second capacitor C2 with the first terminals (e.g., the first drain electrode D1 and the second drain electrode D2) of the first transistor T1 and the second transistor T2, respectively.

[0186] In one example, the first capacitor electrode CSE1 can be spaced apart from the first drain electrode D1 of the first transistor T1 via the first interlayer insulating layer IL1. The first capacitor C1 can be generated between the first drain electrode D1 and the first capacitor electrode CSE1. In one example, the second capacitor electrode CSE2 can be spaced apart from the second drain electrode D2 of the second transistor T2 via the first interlayer insulating layer IL1. The second capacitor C2 can be generated between the second drain electrode D2 and the second capacitor electrode CSE2. The circuit for removing electrostatic discharge (ESD) (e.g., a virtual circuit) can consist not only of the first transistor T1 and the second transistor T2, but also of the first capacitor C1 and the second capacitor C2. The first capacitor C1 connected to the node between the first transistor T1 and the first electrode RME1, and the second capacitor C2 connected to the node between the second transistor T2 and the second electrode RME2, can store ESD generated on the electrode RME according to the directions in which the first transistor T1 and the second transistor T2 are biased to the first electrode RME1 and the second electrode RME2, respectively (e.g., whether the first transistor T1 and the second transistor T2 are forward or reverse biased to the first electrode RME1 and the second electrode RME2, respectively).

[0187] By using a first capacitor C1 and a second capacitor C2, a first transistor T1 and a second transistor T2 to control the electrostatic discharge (ESD) generated on the electrode RME, and by controlling the first alignment voltage V1 and the second alignment voltage V2 applied from the first voltage line VDL and the second voltage line VSL respectively, the light-emitting element ED can be aligned between the first electrode RME1 and the second electrode RME2.

[0188] Figure 20 and Figure 21 This is a schematic diagram illustrating an example of how the electrodes and transistors of a display device according to an embodiment of the present disclosure are connected.

[0189] refer to Figure 20 and Figure 21 In each sub-pixel SPXn, the display device 10 may include a first transistor T1 and a second transistor T2 connected to the first electrode RME1 and the second electrode RME2, respectively, and a third transistor T3 and a fourth transistor T4 connected between the electrode RME and the first voltage line VDL and the second voltage line VSL. A first capacitor C1 may be connected between the first electrode RME1 and the first transistor T1, and a third capacitor C3 may be connected between the first electrode RME1 and the third transistor T3. A second capacitor C2 may be connected between the second electrode RME2 and the second transistor T2, and a fourth capacitor C4 may be connected between the second electrode RME2 and the fourth transistor T4.

[0190] and Figure 19 The implementation methods are different, in Figure 20 and Figure 21 In this embodiment, the first electrode of the first capacitor C1 can be connected to the first electrode RME1, and the second electrode of the first capacitor C1 can be connected to the first terminal of the first transistor T1 (e.g., the first drain electrode D1). Furthermore, with... Figure 19 The implementation methods are different, in Figure 20 and Figure 21 In one embodiment, the first electrode of the second capacitor C2 can be connected to the second electrode RME2, and the second electrode of the second capacitor C2 can be connected to the first terminal of the second transistor T2 (e.g., the second drain electrode D2).

[0191] The first terminal of the third transistor T3 can be connected to the first electrode RME1 via the third capacitor C3. The second terminal of the third transistor T3 can be grounded, and the gate electrode of the third transistor T3 can be connected to the first terminal of the third transistor T3 connected to the first electrode RME1 (e.g., the drain electrode). The first terminal of the fourth transistor T4 can be connected to the second electrode RME2 via the fourth capacitor C4. The second terminal of the fourth transistor T4 can be grounded, and the gate electrode of the fourth transistor T4 can be connected to the grounded second terminal of the fourth transistor T4 (e.g., the source electrode). The first electrode of the third capacitor C3 can be connected to the first voltage line VDL to which the first alignment voltage V1 is applied and the first electrode RME1, and the second electrode of the third capacitor C3 can be connected to the first terminal of the third transistor T3 (e.g., the drain electrode). The first electrode of the fourth capacitor C4 can be connected to the second voltage line VSL to which the second alignment voltage V2 is applied and the second electrode RME2, and the second electrode of the fourth capacitor C4 can be connected to the first terminal of the fourth transistor T4 (e.g., the drain electrode).

[0192] If, during the manufacturing of the display device 10, ink (Ink) is sprayed onto the first electrode RME1 and the second electrode RME2, generating electrostatic discharge (ESD), the ESD can flow in one direction according to the bias directions of the first transistor T1 and the second transistor T2. Since the first transistor T1 is forward biased to the first electrode RME1, the ESD generated on the first electrode RME1 can be removed by storing it in the first capacitor C1, and since the second transistor T2 is reverse biased to the second electrode RME2, the ESD generated on the second electrode RME2 can be released from the second electrode RME2. Here, a first electric field EC1 can be generated according to the direction of the ESD generated on the first electrode RME1 and the second electrode RME2, and the light-emitting element ED can be initially aligned.

[0193] When the first transistor T1 is reverse-biased to the first electrode RME1 and the second transistor T2 is forward-biased to the second electrode RME2, the static electricity generated on the first electrode RME1 can be released, and the static electricity generated on the second electrode RME2 can be stored in the second capacitor C2 through the second transistor T2. Even in this case, the light-emitting element ED can be initially aligned.

[0194] The first alignment voltage V1 and the second alignment voltage V2, applied from the first voltage line VDL and the second voltage line VSL respectively, can be stored in the third capacitor C3 and the fourth capacitor C4, and can be released to the first electrode RME1 and the second electrode RME2 respectively, depending on the bias direction of the third transistor T3 and the fourth transistor T4. The first alignment voltage V1 from the first voltage line VDL can be stored in the third capacitor C3 and can be released to the first electrode RME1 due to the third transistor T3 being forward biased to the first electrode RME1. The second alignment voltage V2 from the second voltage line VSL can be stored in the fourth capacitor C4 and can be released to the second electrode RME2 due to the fourth transistor T4 being reverse biased to the second electrode RME2. Since the first alignment voltage V1 and the second alignment voltage V2 are stored in the third capacitor C3 and the fourth capacitor C4 respectively and then released to the first electrode RME1 and the second electrode RME2, the first alignment voltage V1 and the second alignment voltage V2 can be converted into direct current (DC) voltages.

[0195] In this configuration, the voltage stored in the third capacitor C3 and the fourth capacitor C4 can be converted into a DC voltage and released to the first electrode RME1 and the second electrode RME2 according to the bias direction of the third transistor T3 and the fourth transistor T4. That is, even if the same voltage is applied to the first voltage line VDL and the second voltage line VSL, the electrodes to which the voltage stored in the third capacitor C3 and the fourth capacitor C4 can be released can vary according to the bias direction of the third transistor T3 and the fourth transistor T4, and thus, an electric field can be generated.

[0196] The same voltage, such as a first alignment voltage V1, can be applied to both the first voltage line VDL and the second voltage line VSL connected to the first electrode RME1 and the second electrode RME2, and can be stored in both the third capacitor C3 and the fourth capacitor C4. If the third transistor T3 is forward biased to the first electrode RME1 and the fourth transistor T4 is reverse biased to the second electrode RME2, a DC alignment voltage can be applied to the first electrode RME1, and an alignment voltage with the opposite sign to the DC alignment voltage can be applied to the second electrode RME2. Conversely, if the third transistor T3 is reverse biased to the first electrode RME1 and the fourth transistor T4 is forward biased to the second electrode RME2, a DC alignment voltage can be applied to the second electrode RME2, and an alignment voltage with the opposite sign to the DC alignment voltage can be applied to the first electrode RME1. Therefore, a second electric field EC2 can be generated between the first electrode RME1 and the second electrode RME2, allowing the light-emitting element ED to be aligned.

[0197] Figure 22 This is a schematic diagram illustrating the steps of a method for manufacturing a display device according to an embodiment of the present disclosure.

[0198] refer to Figure 22 In the second alignment step of the method for aligning the light-emitting element ED by applying a first alignment voltage V1 and a second alignment voltage V2 to the first electrode RME1 and the second electrode RME2 respectively, a step of applying light hv to the light-emitting element ED may also be included. When a second electric field EC2 for aligning the light-emitting element ED is generated in the second alignment step, light hv can be applied to the light-emitting element ED using a light irradiation device 900. Since the light-emitting element ED includes a light-emitting layer 36, the dipole moment of the light-emitting element ED can increase in response to the excitons generated by the light hv. The light-emitting element ED with an increased dipole moment can receive a greater force from the second electric field EC2 and can be aligned such that a particular end of the light-emitting element ED can be properly oriented in a particular direction. In the second alignment step, the first alignment voltage V1 and the second alignment voltage V2 can be applied to the first electrode RME1 and the second electrode RME2 respectively, and light hv is applied to the light-emitting element ED. Since the light-emitting element ED is aligned by applying the first alignment voltage V1 and the second alignment voltage V2 simultaneously with the application of light hv, the degree of alignment of the light-emitting element ED can be further improved.

[0199] Display device 10 can be used as a single display device for displaying screen images, but this disclosure is not limited thereto. In some embodiments, display device 10 can be connected to other display devices, and thus can form a single tiled display device.

[0200] Figure 23This is a plan view of a tiled display device according to an embodiment of the present disclosure.

[0201] refer to Figure 23 The tiled display device TD may include a plurality of display devices 10. The display devices 10 may be arranged in a grid pattern, but this disclosure is not limited thereto. The display devices 10 may be connected in a first direction DR1 and / or a second direction DR2, and the tiled display device TD may have a specific shape. In one example, all the display devices 10 may have the same size, but this disclosure is not limited thereto. In another example, the display devices 10 may have different sizes.

[0202] A tiled display device TD can typically have a flat shape, but this disclosure is not limited thereto. The tiled display device TD can have a three-dimensional shape and thus provide a sense of depth to the user. In one example, where the tiled display device TD has a three-dimensional shape, at least some of the display devices 10 can have a curved shape. In another example, all of the display devices 10 can have a flat shape and can be connected to each other at appropriate angles (e.g., predetermined angles) such that the tiled display device TD can have a three-dimensional shape.

[0203] A tiled display device TD may include bonding regions SM disposed between multiple adjacent display areas DPA of a display device 10. The tiled display device TD can be obtained by connecting non-display areas NDA of the display device 10. The display devices 10 can be connected to each other via bonding members or adhesive members disposed in the bonding regions SM. The bonding regions SM of the display device 10 may not include pad portions and flexible films attached to the pad portions. Therefore, the distance between the display areas DPA of the display device 10 can be very close, making the bonding regions SM of the display device 10 almost invisible to the user. The reflectivity of the display areas DPA of the display device 10 can be substantially the same as the reflectivity of the bonding regions SM of the display device 10. Therefore, the tiled display device TD can overcome the feeling of discontinuity between the display devices 10 by preventing the bonding regions SM of the display device 10 from becoming recognizable to the user, and improve image immersion.

[0204] The tiled display device TD can be arranged by connecting the long or short sides of each of the display devices 10. Some of the display devices 10 can be arranged along the edge of the tiled display device TD to form the side of the tiled display device TD. Some of the display devices 10 can be arranged at the corners of the tiled display device TD to form each pair of adjacent sides of the tiled display device TD. Some of the display devices 10 can be located in the middle (or center) of the tiled display device TD and can be surrounded by other display devices 10.

[0205] Since a single tiled display device TD can be configured by connecting multiple display devices 10, large-sized screen images can be displayed.

[0206] In concluding this detailed description, those skilled in the art will understand that many variations and modifications can be made to the embodiments without substantially departing from the principles of this disclosure. Therefore, the embodiments of this disclosure are used only in a general and descriptive sense and not for limiting purposes. Embodiments are also defined in the appended claims and their equivalents.

Claims

1. A display device, comprising: First substrate; The first electrode is on the first substrate; The second electrode is on the first substrate and spaced apart from the first electrode; A plurality of light-emitting elements, each of the light-emitting elements having a corresponding end on the first electrode and the second electrode; The first transistor includes a first terminal connected to the first electrode and a second terminal grounded; as well as The second transistor includes a first terminal connected to the second electrode and a second terminal grounded. The first transistor is forward biased to the first electrode, and the second transistor is reverse biased to the second electrode.

2. The display device according to claim 1, further comprising: The first voltage line and the second voltage line are respectively located between the first substrate and the first electrode, and between the first substrate and the second electrode. The first voltage line is electrically connected to the first electrode, and the second voltage line is electrically connected to the second electrode.

3. The display device according to claim 2, further comprising: A first capacitor is connected to a node between the first electrode and the first terminal of the first transistor; as well as A second capacitor is connected to the node between the second electrode and the first terminal of the second transistor.

4. The display device according to claim 3, further comprising: The third transistor is connected to the node between the first voltage line and the first electrode; A third capacitor is connected between the third transistor and the first electrode; The fourth transistor is connected to the node between the second voltage line and the second electrode; as well as A fourth capacitor is connected between the fourth transistor and the second electrode. Different voltages are applied to the first voltage line and the second voltage line, and at least one of the third transistor and the fourth transistor is forward biased.

5. The display device according to claim 3, further comprising: The third transistor is connected to the node between the first voltage line and the first electrode; A third capacitor is connected between the third transistor and the first electrode; The fourth transistor is connected to the node between the second voltage line and the second electrode; as well as A fourth capacitor is connected between the fourth transistor and the second electrode. The same voltage is applied to the first voltage line and the second voltage line, and at least one of the third transistor and the fourth transistor is forward biased.

6. The display device according to claim 2, wherein: The first transistor includes a first drain electrode electrically connected to the first electrode, a first source electrode grounded, and a first gate electrode electrically connected to the first drain electrode; as well as The second transistor includes a second drain electrode electrically connected to the second electrode, a second source electrode grounded, and a second gate electrode electrically connected to the second source electrode.

7. The display device according to claim 2, wherein: The first transistor includes a first source electrode electrically connected to the first electrode, a first drain electrode grounded, and a first gate electrode electrically connected to the first drain electrode. The second transistor includes a second source electrode electrically connected to the second electrode, a second drain electrode grounded, and a second gate electrode electrically connected to the second source electrode.

8. The display device according to claim 2, wherein: Each of the light-emitting elements includes a first semiconductor layer, a second semiconductor layer, and a light-emitting layer between the first semiconductor layer and the second semiconductor layer; The first end of the light-emitting element is on the first electrode, wherein the first semiconductor layer is located at the first end of the corresponding light-emitting element in the light-emitting element; and The second end of the light-emitting element is on the second electrode, wherein the second semiconductor layer is located at the second end of the corresponding light-emitting element in the light-emitting element.

9. The display device according to claim 2, further comprising: The driving transistor is connected to the first voltage line and the second voltage line. Wherein, the first electrode is connected to the driving transistor, and The second electrode is connected to the second voltage line.

10. The display device according to claim 9, further comprising: A via layer is formed between the first substrate and the first and second electrodes. The first transistor, the second transistor, and the driving transistor are located between the via layer and the first substrate.

11. The display device according to claim 10, further comprising: A first conductive layer is disposed on the first substrate; A buffer layer is provided on the first conductive layer; The active layer is located on the buffer layer. A first gate insulating layer is disposed on the active layer; The second conductive layer is on the first gate insulating layer; The first interlayer insulating layer is on the second conductive layer; as well as The third conductive layer is located on the first interlayer insulating layer. The source and drain electrodes of the first transistor, the second transistor, and the driving transistor are formed by the third conductive layer.

12. The display device according to claim 11, wherein: The first voltage line and the second voltage line are formed by the third conductive layer. The first electrode is connected to the source electrode of the driving transistor through a contact hole penetrating the via layer, and The second electrode is connected to the second voltage line through another contact hole that penetrates the via layer.

13. The display device according to claim 2, further comprising: A first connecting electrode is located on the first end of the first electrode and the first end of the light-emitting element, and is in contact with the first end of the first electrode and the first end of the light-emitting element; The second connecting electrode is located on the second end of the second electrode and the second end of the light-emitting element, and is in contact with the second electrode and the second end of the light-emitting element; A first insulating layer covers the first electrode and the second electrode; as well as The second insulating layer surrounds a portion of the outer surface of each of the light-emitting elements. Wherein, at least a portion of the first connecting electrode and at least a portion of the second connecting electrode are on the second insulating layer.

14. A method for manufacturing a display device, comprising: A first transistor, a first electrode electrically connected to a first voltage line, a second transistor, and a second electrode electrically connected to a second voltage line are formed on a first substrate; Ink containing light-emitting elements dispersed therein is sprayed onto the first electrode and the second electrode; By utilizing the static electricity flowing in the first electrode and the first transistor and another static electricity flowing in the second electrode and the second transistor to generate a first electric field, the light-emitting element is initially aligned on the first electrode and the second electrode; as well as The light-emitting element is then aligned secondaryly by applying an alignment voltage to the first and second electrodes to generate a second electric field between them. The first transistor is forward biased to the first electrode, and the second transistor is reverse biased to the second electrode.

15. The method according to claim 14, wherein, The first transistor includes a first drain electrode connected to the first electrode, a first source electrode grounded, and a first gate electrode connected to the first drain electrode, and the second transistor includes a second drain electrode connected to the second electrode, a second source electrode grounded, and a second gate electrode connected to the second source electrode.

16. The method of claim 14, wherein, During the initial alignment of the light-emitting element A first electrostatic current will flow from the first electrode to the first transistor. The second electrostatic current will flow from the second transistor through the second electrode to the second voltage line, and The light-emitting elements are aligned by the first electric field such that the two ends of each of the light-emitting elements are on the first electrode and the second electrode.

17. The method according to claim 14, wherein, During the second alignment of the light-emitting element, AC power is applied to the first voltage line, and the second voltage line is grounded.

18. The method according to claim 17, wherein, During the secondary alignment of the light-emitting element, the light-emitting element is aligned such that the first end and the second end of the light-emitting element are on the first electrode and the second electrode, respectively.

19. The method of claim 17, wherein, Secondary alignment of the light-emitting element includes: applying light to the light-emitting element, and The alignment voltage is applied to the first electrode and the second electrode, and the light is applied to the light-emitting element.

20. The method of claim 14, wherein, Each of the light-emitting elements includes a first semiconductor layer, a second semiconductor layer, and a light-emitting layer between the first semiconductor layer and the second semiconductor layer. Wherein, the first end of the light-emitting element is on the first electrode, and the first semiconductor layer of the corresponding light-emitting element is located at the first end of the corresponding light-emitting element. Wherein, the second end of the light-emitting element is on the second electrode, and Wherein, the second semiconductor layer of the corresponding light-emitting element in the light-emitting element is located at the second end of the corresponding light-emitting element in the light-emitting element.

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