Thin film transistor array panel and related manufacturing method

Abstract

A thin film transistor array panel and a related manufacturing method are provided. The thin film transistor array panel includes a transistor, which can include a semiconductor, a source electrode, a drain electrode, and a gate electrode. The semiconductor can include a first doped region, a second doped region, a source region, a drain region, and a channel region. The channel region is disposed between the source region and the drain region. The first doped region is disposed between the channel region and the source region. The second doped region is disposed between the channel region and the drain region. A doping concentration of the first doped region is lower than a doping concentration of the source region. A doping concentration of the second doped region is lower than a doping concentration of the drain region. The source electrode is electrically connected to the source region. The drain electrode is electrically connected to the drain region. The gate electrode overlaps the channel region.

Description

[0001] This application is a divisional application of the invention patent application "Thin Film Transistor Array Panel and Related Manufacturing Method" filed on September 5, 2017, with application number 201710790406.8. Technical Field

[0002] The technical field relates to transistors (e.g., thin-film transistors), thin-film transistor array panels, and methods for manufacturing transistors and / or thin-film transistor array panels. Background Technology

[0003] Thin-film transistors (TFTs) can be used in electronic devices such as display devices. A TFT may include a gate electrode connected to a gate line for transmitting scan signals, a source electrode connected to a data line for transmitting signals to pixel electrodes, a drain electrode facing the source electrode, and a semiconductor electrically connected to each of the source electrode and the drain electrode.

[0004] The information disclosed in this background section is intended to enhance understanding of the background of the described techniques. This background section may include information that does not constitute prior art known to a person skilled in the art. Summary of the Invention

[0005] The embodiments may relate to transistors (e.g., thin-film transistors), thin-film transistor array panels, and methods of manufacturing transistors and / or thin-film transistor array panels. The embodiments may prevent or minimize undesirable current reduction in lightly doped regions of a transistor.

[0006] The embodiment may relate to a thin-film transistor array panel, the thin-film transistor array panel including the following elements: a substrate; a lower gate electrode disposed on the substrate and comprising polysilicon; a semiconductor disposed on the lower gate electrode and comprising a channel region, a source region and a drain region disposed on opposite sides of the channel region, a first lightly doped region disposed between the channel region and the source region, and a second lightly doped region disposed between the channel region and the drain region; an upper gate electrode disposed on the semiconductor; a source electrode connected to the source region of the semiconductor; and a drain electrode connected to the drain region of the semiconductor.

[0007] The thin-film transistor array panel may also include a gate insulating layer disposed between the semiconductor and the upper gate electrode, wherein the width of the gate insulating layer may be wider than the width of the upper gate electrode.

[0008] Semiconductors can include oxide semiconductor materials.

[0009] The surface of a semiconductor can be crystallized.

[0010] The thin-film transistor array panel may further include: a passivation layer disposed on the semiconductor and the upper gate electrode; a first contact hole formed in the passivation layer to overlap with the source region of the semiconductor; a second contact hole formed in the passivation layer to overlap with the drain region of the semiconductor; a first dummy hole formed in the passivation layer to overlap with a first lightly doped region of the semiconductor; and a second dummy hole formed in the passivation layer to overlap with a second lightly doped region of the semiconductor.

[0011] The source electrode can be connected to the source region of the semiconductor through the first contact hole, and the drain electrode can be connected to the drain region of the semiconductor through the second contact hole.

[0012] The first lightly doped region and the second lightly doped region can be configured to be adjacent to the surface of the semiconductor.

[0013] The embodiment may relate to a thin-film transistor array panel, the thin-film transistor array panel comprising the following elements: a substrate; a semiconductor disposed on the substrate and including a channel region, a source region and a drain region respectively disposed on opposite sides of the channel region, a first lightly doped region disposed between the channel region and the source region, and a second lightly doped region disposed between the channel region and the drain region; an upper gate electrode disposed on the semiconductor; a passivation layer disposed on the semiconductor and the upper gate electrode; a first contact hole formed in the passivation layer and exposing the source region of the semiconductor; a second contact hole formed in the passivation layer and exposing the drain region of the semiconductor; a first dummy hole formed in the passivation layer and exposing the first lightly doped region of the semiconductor; a second dummy hole formed in the passivation layer and exposing the second lightly doped region of the semiconductor; a source electrode connected to the source region of the semiconductor through the first contact hole; and a drain electrode connected to the drain region of the semiconductor through the second contact hole.

[0014] The first lightly doped region and the second lightly doped region can be configured to be adjacent to the surface of the semiconductor.

[0015] Semiconductors can be made of oxide semiconductor materials, and the surface of a semiconductor can be crystallized.

[0016] The embodiments may relate to a method for manufacturing a thin-film transistor array panel. The method may include the following steps: forming a lower gate electrode on a substrate using a low-temperature polysilicon process; forming a semiconductor on the lower gate electrode; forming an upper gate electrode on the semiconductor; forming an undoped channel region, a highly doped source region and a drain region, and a first lightly doped region and a second lightly doped region by doping the semiconductor with impurities; forming a source electrode connected to the source region of the semiconductor; and forming a drain electrode connected to the drain region of the semiconductor.

[0017] The manufacturing method of a thin-film transistor array panel may further include forming a gate insulating layer on a semiconductor, wherein the width of the gate insulating layer may be wider than the width of the upper gate electrode, the channel region may be stacked with the upper gate electrode and the gate insulating layer, and the first lightly doped region and the second lightly doped region may be stacked with the gate insulating layer.

[0018] Semiconductors can include oxide semiconductor materials.

[0019] The surface of a semiconductor can be crystallized.

[0020] The manufacturing method of a thin-film transistor array panel may further include: forming a passivation layer on a semiconductor and an upper gate electrode; forming a first dummy hole and a second dummy hole in the passivation layer adjacent to the upper gate electrode; and performing an oxygen plasma process or a heat treatment process under an oxygen atmosphere on the portion of the semiconductor exposed through the first dummy hole and the second dummy hole.

[0021] The manufacturing method of a thin-film transistor array panel may further include forming a first contact hole in a passivation layer superimposed with the source region of a semiconductor, and forming a second contact hole in a passivation layer superimposed with the drain region of a semiconductor, wherein the source electrode can be connected to the source region through the first contact hole, and the drain electrode can be connected to the drain region through the second contact hole.

[0022] The first and second lightly doped regions of a semiconductor can be expanded by oxygen plasma processes or thermal treatment processes under an oxygen atmosphere.

[0023] The embodiments may relate to a method for manufacturing a thin-film transistor array panel. The manufacturing method may include the following steps: forming a semiconductor on a substrate; forming an upper gate electrode on the semiconductor; forming an undoped channel region and highly doped source and drain regions by doping the semiconductor with impurities; forming a passivation layer on the semiconductor and the upper gate electrode; forming a first dummy via and a second dummy via in the passivation layer adjacent to the upper gate electrode; forming a lightly doped first and second lightly doped regions by performing an oxygen plasma process or a heat treatment process under an oxygen atmosphere on the portions of the semiconductor exposed through the first and second dummy vias; forming a first contact hole in the passivation layer superimposed on the source region of the semiconductor; forming a second contact hole in the passivation layer superimposed on the drain region of the semiconductor; forming a source electrode on the passivation layer connected to the source region of the semiconductor through the first contact hole; and forming a drain electrode on the passivation layer connected to the drain region of the semiconductor through the second contact hole.

[0024] The first lightly doped region can be disposed between the channel region and the source region, and the second lightly doped region can be disposed between the channel region and the drain region. Furthermore, the first lightly doped region and the second lightly doped region can be disposed adjacent to the surface of the semiconductor.

[0025] A first dummy hole, a second dummy hole, a first contact hole, and a second contact hole can be formed simultaneously in the passivation layer.

[0026] The embodiment may relate to a transistor, such as a thin-film transistor. The transistor may include a semiconductor, a source electrode, a drain electrode, and a first gate electrode. The semiconductor may include a first doped region, a second doped region, a source region, a drain region, and a channel region. The channel region may be disposed between the source region and the drain region. The first doped region may be disposed between the channel region and the source region. The second doped region may be disposed between the channel region and the drain region. The doping concentration of the first doped region may be lower than the doping concentration of the source region and may be greater than 0 (and may be greater than the doping concentration of the channel region). The doping concentration of the second doped region may be lower than the doping concentration of the drain region and may be greater than 0 (and may be greater than the doping concentration of the channel region). The source electrode may be electrically connected to the source region. The drain electrode may be electrically connected to the drain region. The first gate electrode may be stacked with the channel region.

[0027] The transistor may include a substrate. A first gate electrode may be disposed between the substrate and the semiconductor. The minimum distance between the substrate and the first doped region may be greater than the minimum distance between the substrate and the source region.

[0028] A transistor may include a substrate. A first gate electrode may be disposed between the substrate and a semiconductor. The minimum distance between the substrate and the channel region may be greater than the minimum distance between the substrate and the first doped region. The minimum distance between the substrate and the first doped region may be greater than the minimum distance between the substrate and the source region. The minimum distance between the substrate and the second doped region may be greater than the minimum distance between the substrate and the drain region.

[0029] The first gate electrode can directly contact the substrate and can be formed from polycrystalline silicon.

[0030] The transistor may include a second gate electrode and a gate insulating layer. A channel region may be disposed between the first gate electrode and the second gate electrode. The gate insulating layer may be disposed between the channel region and the second gate electrode and may directly contact at least one of the first doped region and the second doped region.

[0031] The transistor may include a gate insulating layer. The gate insulating layer may be disposed between the channel region and the second gate electrode and may directly contact at least one of the first doped region and the second doped region.

[0032] The gate insulating layer may not directly contact the source region or the drain region.

[0033] The gate insulating layer can directly contact each of the first doped region, the second doped region, and the channel region.

[0034] A transistor may include a gate insulating layer and a passivation layer. The gate insulating layer may be disposed between the channel region and the second gate electrode. The passivation layer may directly contact the semiconductor and may directly contact at least three sides of the gate insulating layer.

[0035] A transistor may include a gate insulating layer and a passivation layer. The gate insulating layer may be disposed between the channel region and the second gate electrode. The surface of the gate insulating layer may directly contact the second gate electrode. The passivation layer may directly contact the surface of the gate insulating layer.

[0036] The transistor may include a passivation layer. The passivation layer may directly contact at least one of the first doped region and the second doped region.

[0037] The first via can extend through the passivation layer and expose the first doped region. The second via can extend through the passivation layer and expose the second doped region.

[0038] The transistor may include a passivation layer. The passivation layer may directly contact at least one of the source and drain regions. A first via may extend through the passivation layer and expose a first doped region. A second via extends through the passivation layer and exposes a second doped region.

[0039] The first surface of the channel region can be disposed between the first gate electrode and the second surface of the channel region. The first direction can be perpendicular to the first surface of the channel region. The thickness of the first doped region in the first direction can be smaller than the thickness of the source region in the first direction. The thickness of the second doped region in the first direction can be smaller than the thickness of the drain region in the first direction.

[0040] The embodiments may relate to a method for manufacturing a transistor. The method may include the steps of: preparing a semiconductor; forming a first doped region, a second doped region, a source region, a drain region, and a channel region in the semiconductor, wherein the channel region is disposed between the source region and the drain region, wherein the first doped region is disposed between the channel region and the source region, wherein the second doped region is disposed between the channel region and the drain region, wherein the doping concentration of the first doped region is lower than the doping concentration of the source region and greater than 0, and wherein the doping concentration of the second doped region is lower than the doping concentration of the drain region and greater than 0; forming a source electrode electrically connected to the source region; forming a drain electrode electrically connected to the drain region; and forming a first gate electrode, wherein the first gate electrode and the channel region are stacked on top of each other.

[0041] The method may include the following steps: forming a gate insulating layer on a semiconductor; forming a first gate electrode on the gate insulating layer; and doping the semiconductor to form a first doped region, a second doped region, a source region, a drain region, and a channel region. Both the first and second portions of the semiconductor may be covered by the gate insulating layer during doping but not by the first gate electrode. A third portion of the semiconductor may be covered by both the gate insulating layer and the first gate electrode during doping. The first doped region may be formed at the first portion of the semiconductor. The second doped region may be formed at the second portion of the semiconductor. The channel region may be formed at the third portion of the semiconductor.

[0042] The method may include the following steps: forming a second gate electrode before forming the semiconductor. The two edges of the gate insulating layer may overlap with the second gate electrode but not with the first gate electrode.

[0043] The method may include the following steps: forming a passivation layer on a semiconductor; forming two processing holes through the passivation layer to expose two doped portions of the semiconductor; and performing at least one of a plasma process and a heat treatment on the two doped portions of the semiconductor through the two processing holes to form a first doped region and a second doped region.

[0044] Plasma processing and / or heat treatment can cause a decrease in the doping concentration of the two doped portions of a semiconductor and / or a widening of the two doped portions of the semiconductor.

[0045] The method may include the following steps: after at least one of plasma processing and heat treatment has been performed, forming a first contact hole and a second contact hole through the passivation layer; providing a portion of a source electrode inside the first contact hole; and providing a portion of a drain electrode inside the second contact hole.

[0046] The method may include the following steps: forming a first contact hole and a second contact hole through the passivation layer when forming two machining holes; setting a portion of a source electrode inside the first contact hole; and setting a portion of a drain electrode inside the second contact hole.

[0047] According to embodiments, adverse current reduction in a transistor (e.g., in a lightly doped region of the transistor) can be prevented, or adverse current reduction in a transistor (e.g., in a lightly doped region of the transistor) can be minimized. Attached Figure Description

[0048] Figure 1 A cross-sectional view of a thin-film transistor array panel according to an embodiment is shown.

[0049] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 and Figure 8 A cross-sectional view is shown of a structure formed in a method of manufacturing a thin-film transistor array panel according to an embodiment.

[0050] Figure 9 A cross-sectional view of a thin-film transistor array panel according to an embodiment is shown.

[0051] Figure 10 , Figure 11 , Figure 12 and Figure 13 A cross-sectional view is shown of a structure formed in a method of manufacturing a thin-film transistor array panel according to an embodiment. Detailed Implementation

[0052] Embodiments are described with reference to the accompanying drawings. As those skilled in the art will recognize, the described embodiments can be modified in various different ways.

[0053] Although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms can be used to distinguish one element from another. Therefore, without departing from the teachings of one or more embodiments, a first element discussed below may be referred to as a second element. Describing an element as a “first” element may not require or imply the presence of a second element or other elements. The terms “first,” “second,” etc., may also be used herein to distinguish elements of different classes or groups. For brevity, the terms “first,” “second,” etc., may respectively represent “first class (or first group),” “second class (or second group),” etc.

[0054] The same reference numerals may be used to denote the same elements throughout the specification.

[0055] In the accompanying drawings, the thickness of layers, films, panels, regions, etc., may be exaggerated for clarity.

[0056] When a first element (such as a layer, film, region, or substrate) is referred to as being "on" a second element, the first element may be directly on the second element, or one or more intermediate elements may exist between the first and second elements. When the first element is referred to as being "directly on" a second element, no intentionally placed intermediate elements (except for environmental factors such as air) exist between the first and second elements.

[0057] Unless explicitly stated otherwise, the words “including” and variations such as “comprising” or “consisting of” may mean including the elements stated, but do not exclude any other elements.

[0058] Figure 1A cross-sectional view of a thin-film transistor array panel according to an embodiment is shown.

[0059] like Figure 1 As shown, the thin-film transistor array panel includes a substrate 110 and a lower gate electrode 124 disposed on the substrate 110.

[0060] The substrate 110 may be made of at least one material such as glass, polymer and stainless steel. The substrate 110 may have a flat shape and is flexible, stretchable, foldable, bendable and / or rollable.

[0061] The lower gate electrode 124 may include and / or may be formed of polysilicon.

[0062] A first gate insulating layer 120 is disposed on the lower gate electrode 124 and the substrate 110. The first gate insulating layer 120 may be made of materials such as silicon oxide (SiO2). x ), aluminum oxide (AlO) x It is made of at least one of the insulating materials such as ( ). The first gate insulating layer 120 may be formed as a single layer or multiple layers.

[0063] Semiconductor 130 is disposed on the first gate insulating layer 120. Semiconductor 130 is stacked with the lower gate electrode 124. Semiconductor 130 may be made of an oxide semiconductor material. For example, the oxide semiconductor material may be made of an oxide of a metal such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), titanium (Ti), or other materials, or a combination of a metal and an oxide of some of the metals such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti). In embodiments, the oxide semiconductor material may include zinc oxide (ZnO), zinc tin oxide (ZTO), zinc indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium gallium zinc oxide (IGZO), indium zinc tin oxide (IZTO), or other materials. Semiconductor 130 may have stacked layers, and the uppermost layer of semiconductor 130 may be crystallized. In embodiments, the surface of semiconductor 130 may be crystallized.

[0064] Semiconductor 130 may include a channel region 131, a source region 132 and a drain region 133 disposed on opposite sides of the channel region 131, a first lightly doped region 135 disposed between the channel region 131 and the source region 132, and a second lightly doped region 136 disposed between the channel region 131 and the drain region 133. Impurities are doped at a high concentration in the source region 132 and the drain region 133, and impurities are doped at a low concentration in the first lightly doped region 135 and the second lightly doped region 136.

[0065] The second gate insulating layer 140 is disposed on the semiconductor 130. The second gate insulating layer 140 may be made of materials such as silicon nitride (SiN).x ), silicon dioxide (SiO) x It is made of inorganic insulating materials such as 140 or other materials. The second gate insulating layer 140 may have a single-layer structure or a multi-layer structure.

[0066] The upper gate electrode 154 is disposed on the second gate insulating layer 140. The upper gate electrode 154 may be made of a low-resistivity metal material such as gold, silver, copper, nickel, aluminum, molybdenum, etc., or an alloy thereof.

[0067] The width of the second gate insulating layer 140 may be greater than the width of the upper gate electrode 154. The second gate insulating layer 140 may be stacked with the channel region 131, the first lightly doped region 135, and the second lightly doped region 136 of the semiconductor 130. The upper gate electrode 154 may be stacked with the channel region 131 of the semiconductor 130. The second gate insulating layer 140 may not be stacked with the source region 132 and the drain region 133 of the semiconductor 130. The upper gate electrode 154 may not be stacked with the source region 132, the drain region 133, the first lightly doped region 135, and the second lightly doped region 136 of the semiconductor 130.

[0068] A passivation layer 160 is disposed on the semiconductor 130, the second gate insulating layer 140, and the upper gate electrode 154. The passivation layer 160 includes a first passivation layer 160a and a second passivation layer 160b. The first passivation layer 160a may be made of silicon nitride (SiN). x It is made of silicon dioxide (SiO2) and can include silicon oxide (SiO2). x ) set in silicon nitride (SiN) x The first passivation layer 160a is a double layer on top of the second passivation layer 160b. The second passivation layer 160b can be disposed on top of the first passivation layer 160a. The second passivation layer 160b can be made of silicon nitride (SiN). x ), aluminum oxide (AlO) x Made of (or other materials).

[0069] A first contact hole 163 is formed in the passivation layer 160 to overlap with the source region 132 of the semiconductor 130, and a second contact hole 165 is formed in the passivation layer 160 to overlap with the drain region 133 of the semiconductor 130.

[0070] The source electrode 173 and the drain electrode 175 can be disposed on the passivation layer 160. The source electrode 173 is connected to the source region 132 of the semiconductor 130 through the first contact hole 163, and the drain electrode 175 is connected to the drain region 133 of the semiconductor 130 through the second contact hole 165.

[0071] Thus, semiconductor 130, upper gate electrode 154, source electrode 173, and drain electrode 175 form a thin-film transistor. The thin-film transistor array panel may include multiple pixels and a driving section for driving the multiple pixels. The thin-film transistor described above can be used as a switching element directly connected to each pixel, or as a switching element included in the driving section.

[0072] The semiconductor 130 of the thin-film transistor can be made of an oxide semiconductor material. When the thin-film transistor is used as a switching element included in the driving section, a high voltage (Vds) can be applied to the semiconductor 130. In the semiconductor 130 of the thin-film transistor, a first lightly doped region 135 is disposed between the channel region 131 and the source region 132, and a second lightly doped region 136 is disposed between the channel region 131 and the drain region 133. Therefore, the doping concentration can be changed slowly in the semiconductor 130, thereby preventing the electric field from being changed rapidly. In an embodiment, because the lower gate electrode 124 is disposed below the semiconductor 130, undesirable current reduction in the first lightly doped region 135 and the second lightly doped region 136 can be prevented.

[0073] The lower gate electrode 124 can be stacked with the channel region 131 of the semiconductor 130, and it can also be stacked with the first lightly doped region 135 and the second lightly doped region 136. The lower gate electrode 124 is connected to the upper gate electrode 154, such that the same gate voltage can be applied to both the upper gate electrode 154 and the lower gate electrode 124. Therefore, the current quantity and current mobility can be increased in the semiconductor 130 of the thin-film transistor. The lower gate electrode 124 can be connected to the source electrode 173 instead of the upper gate electrode 154.

[0074] The lower gate electrode 124 can be made of polycrystalline silicon, and because polycrystalline silicon has a low band gap, it can absorb photons in the main wavelength bandwidth that affects the reliability of thin-film transistors. Therefore, when the thin-film transistor array panel is used in a liquid crystal display, the lower gate electrode 124 can be used to block light from the backlight emitted from the bottom of the thin-film transistor array panel.

[0075] Figures 2 to 8 A cross-sectional view is shown of a structure formed using a method for manufacturing a thin-film transistor array panel according to an embodiment.

[0076] Reference Figure 2 The lower gate electrode 124 is formed on the substrate 110 using a low-temperature polycrystalline silicon (LTPS) process.

[0077] Subsequently, silicon oxide (SiO2) is deposited on the substrate 110 and the lower gate electrode 124. x ), aluminum oxide (AlO) x The first gate insulating layer 120 is formed by patterning an insulating material of at least one of the following:

[0078] Reference Figure 3 A semiconductor 130 is formed on the first gate insulating layer 120, and in this embodiment, an oxide semiconductor material is used. The semiconductor 130 may have stacked layers, and the uppermost layer of the semiconductor 130 may be crystallized. In this embodiment, the surface of the semiconductor 130 may be crystallized.

[0079] Silicon nitride (SiN) deposited on semiconductor 130 x ) layer and / or silicon oxide (SiO) x The upper gate metal layer 156 is formed on the second gate insulating layer 140 by patterning the upper gate metal layer 156 using a metallic material. A photoresist 500 is then coated on the upper gate metal layer 156.

[0080] The mask 600 is configured to correspond to the photoresist 500, and then an exposure process is performed. The mask 600 can be formed as a slot mask or a halftone mask. The mask 600 includes a non-transmissive region (NR) that blocks most of the light, a semi-transmissive region (HR) that blocks some light and allows the remaining light to pass through, and a transmissive region (TR) that allows most of the light to pass through. When the mask 600 is a slot mask, the semi-transmissive region (HR) can have a slot shape.

[0081] The non-transmissive region (NR) substantially corresponds to the central portion of the lower gate electrode 124, the semi-transmissive region (HR) substantially corresponds to the edge or peripheral region of the lower gate electrode 124, and the transmissive region (TR) substantially corresponds to the left and right portions of the lower gate electrode 124. In an embodiment, the transmissive region (TR) is disposed on the opposite side of the non-transmissive region (NR), and the semi-transmissive region (HR) is disposed between the non-transmissive region (NR) and the transmissive region (TR).

[0082] The portion of photoresist 500 corresponding to the non-transmissive region (NR) of mask 600 is essentially not exposed to light, the portion of photoresist 500 corresponding to the semi-transmissive region (HR) of mask 600 is exposed to some light, and the portion of photoresist 500 corresponding to the transmissive region (TR) of mask 600 is exposed to most of the light.

[0083] Reference Figure 4 The photoresist 500, to which the exposure process has been performed, is developed into a pattern. When the photoresist 500 is a positive photoresist, the light-exposed portions are removed, the partially light-exposed portions are thinned, and the light-unexposed portions are retained. In an embodiment, the photoresist 500 is divided into two portions with different thicknesses; in an embodiment, the photoresist 500 can be a negative photoresist. In the mask 600, non-transmissive areas can be changed to transmissive areas, and transmissive areas can be changed to non-transmissive areas.

[0084] Subsequently, a patterned photoresist 500 is used as a mask to pattern the upper gate electrode 154 and the second gate insulating layer 140. In this embodiment, the width of the upper gate electrode 154 is the same as the width of the second gate insulating layer 140.

[0085] Reference Figure 5 The thickness of the patterned photoresist 500 is reduced through an ashing process. This removes relatively thin portions of the photoresist 500, thinning out the relatively thick portions.

[0086] Next, the upper gate electrode 154 is patterned using a photoresist 500 to which an ashing process has been performed. In this embodiment, the width of the upper gate electrode 154 is reduced, and the width of the second gate insulating layer 140 becomes wider than the width of the upper gate electrode 154.

[0087] Next, after doping the semiconductor 130 with impurities using the upper gate electrode 154 as a mask, refer to Figure 6 A channel region 131, a source region 132, a drain region 133, a first lightly doped region 135, and a second lightly doped region 136 are formed in semiconductor 130. Any remaining portion of the photoresist 500 is completely removed.

[0088] The channel region 131 may be stacked with the upper gate electrode 154 and the second gate insulating layer 140. The channel region 131 may be blocked by the upper gate electrode 154 and the second gate insulating layer 140 to remain substantially undoped. The channel region 131 may be stacked with the lower gate electrode 124.

[0089] The first lightly doped region 135 and the second lightly doped region 136 may be stacked with the second gate insulating layer 140, but may not be stacked with the upper gate electrode 154. The first lightly doped region 135 and the second lightly doped region 136 are not blocked by the upper gate electrode 154, but they are partially blocked by the second gate insulating layer 140 to be doped at a low concentration. The first lightly doped region 135 and the second lightly doped region 136 may be stacked with the lower gate electrode 124. The first lightly doped region 135 and the second lightly doped region 136 may be located on opposite sides of the channel region 131.

[0090] The source region 132 and drain region 133 may not be stacked with the upper gate electrode 154 and the second gate insulating layer 140. The source region 132 and drain region 133 may be highly doped. The source region 132 may be adjacent to a first lightly doped region 135, and the drain region 133 may be adjacent to a second lightly doped region 136. The first lightly doped region 135 may be disposed between the channel region 131 and the source region 132, and the second lightly doped region 136 may be disposed between the channel region 131 and the drain region 133.

[0091] Next, a passivation layer 160 is formed on the semiconductor 130 and the upper gate electrode 154. The passivation layer 160 may include a first passivation layer 160a and a second passivation layer 160b. First, silicon nitride (SiN) is deposited on the semiconductor 130 and the upper gate electrode 154. x A first passivation layer 160a is formed by continuously depositing silicon nitride (SiN). In an embodiment, this can be achieved by continuously depositing silicon nitride (SiN). x ) layer and / or silicon oxide layer (SiO) x A first passivation layer 160a is formed. This is achieved by depositing materials such as silicon nitride (SiN) on the first passivation layer 160a. x ), aluminum oxide (AlO) x (or other insulating materials) form a second passivation layer 160b.

[0092] like Figure 7 As shown, a first contact hole 163 is provided in the passivation layer 160 to expose the source region 132 of the semiconductor 130, and a second contact hole 165 is provided in the passivation layer 160 to expose the drain region 133 of the semiconductor 130. The upper surface of the source region 132 of the semiconductor 130 is partially exposed by the first contact hole 163, and the upper surface of the drain region 133 of the semiconductor 130 is partially exposed by the second contact hole 165.

[0093] Reference Figure 8 A source electrode 173 and a drain electrode 175 are formed by depositing and patterning a metal material on a passivation layer 160. The source electrode 173 is connected to the source region 132 of the semiconductor 130 through a first contact hole 163, and the drain electrode 175 is connected to the drain region 133 of the semiconductor 130 through a second contact hole 165.

[0094] Recently, thin-film transistor (TFT) array panels have been developed that incorporate both thin-film transistors made of polycrystalline silicon and thin-film transistors made of oxide semiconductor materials. In the case of such TFT array panels, the process can be simplified because the lower gate electrode of the thin-film transistors made of oxide semiconductor materials is formed together with the thin-film transistors made of polycrystalline silicon during the formation process.

[0095] In the following text, reference will be made to Figure 9 A thin-film transistor array panel according to an embodiment is described.

[0096] Reference Figure 9 Some features of the described thin-film transistor array panel can be compared with those of the reference panel. Figure 1 The thin-film transistor array panels described have some of the same or similar features.

[0097] Figure 9 A cross-sectional view of a thin-film transistor array panel according to an embodiment is shown.

[0098] like Figure 9 As shown, the thin-film transistor array panel according to an embodiment includes a substrate 110, a lower gate electrode 124 disposed on the substrate 110, a first gate insulating layer 120 disposed on the lower gate electrode 124, a semiconductor 130 disposed on the first gate insulating layer 120, a second gate insulating layer 140 disposed on the semiconductor 130, and an upper gate electrode 154 disposed on the second gate insulating layer 140. The semiconductor 130 includes a channel region 131, a source region 132, a drain region 133, a first lightly doped region 135, and a second lightly doped region 136. A passivation layer 160 is disposed on the upper gate electrode 154, and a source electrode 173 and a drain electrode 175 are disposed on the passivation layer 160.

[0099] A first contact hole 163 superimposed on the source region 132 of the semiconductor 130 and a second contact hole 165 superimposed on the drain region 133 of the semiconductor 130 are disposed in the passivation layer 160. In an embodiment, a first dummy hole 167 (or a first processing hole 167) exposing a first lightly doped region 135 of the semiconductor 130 and a second dummy hole 169 (or a second processing hole 169) exposing a second lightly doped region 136 of the semiconductor 130 are disposed in the passivation layer 160.

[0100] The first lightly doped region 135 and the second lightly doped region 136 may be configured to be adjacent to the surface of the semiconductor 130. In an embodiment, the first lightly doped region 135 and the second lightly doped region 136 may be disposed in the upper portion of the semiconductor 130. In an embodiment, the thickness of the first lightly doped region 135 and the second lightly doped region 136 in the direction perpendicular to the substrate 110 may be thinner than the thickness of other regions of the semiconductor 130 in the direction perpendicular to the substrate 110 (e.g., the thickness of the source region 132, the drain region 133, and / or the channel region 131). In an embodiment, a portion of the source region 132 may be disposed below the first lightly doped region 135 and / or closer to the substrate 110 than the first lightly doped region 135, and a portion of the drain region 133 may be disposed below the second lightly doped region 136 and / or closer to the substrate 110 than the second lightly doped region 136. Because the first lightly doped region 135 and the second lightly doped region 136 of the semiconductor 130 are thinner than other regions of the semiconductor 130, it is possible to prevent or minimize the adverse current reduction in the first lightly doped region 135 and the second lightly doped region 136.

[0101] In this embodiment, by forming the lower gate electrode 124, an undesirable reduction in current in the first lightly doped region 135 and the second lightly doped region 136 can be prevented or minimized. In this embodiment, since the reduction in current in the first lightly doped region 135 and the second lightly doped region 136 can be prevented by adjusting the thickness of the first lightly doped region 135 and the second lightly doped region 136 of the semiconductor 130, the lower gate electrode 124 may not be necessary.

[0102] In one embodiment, the second gate insulating layer 140 may be wider than the upper gate electrode 154. Alternatively, the second gate insulating layer 140 may have the same width as the upper gate electrode 154.

[0103] Figures 10 to 13 A cross-sectional view is shown of a structure formed using a method for manufacturing a thin-film transistor array panel according to an embodiment.

[0104] Reference Figure 10 The lower gate electrode 124 is formed on the substrate 110 using a low-temperature polycrystalline silicon (LTPS) process. As described above, the process for forming the lower gate electrode 124 can be omitted.

[0105] Next, a first gate insulating layer 120 is formed on the substrate 110 and the lower gate electrode 124. A semiconductor 130 is formed on the first gate insulating layer 120; in this embodiment, an oxide semiconductor material is used.

[0106] Next, a second gate insulating layer 140 is formed on the semiconductor 130, and an upper gate electrode 154 is formed on the second gate insulating layer 140. In an embodiment, the second gate insulating layer 140 may have a width wider than the upper gate electrode 154. Alternatively, as described above, the second gate insulating layer 140 may have the same width as the upper gate electrode 154.

[0107] Next, impurities are doped into semiconductor 130 to form channel region 131, source region 132, drain region 133, first lightly doped region 135, and second lightly doped region 136. A passivation layer 160 is formed on semiconductor 130, second gate insulating layer 140, and upper gate electrode 154. Passivation layer 160 may include first passivation layer 160a and second passivation layer 160b. Photoresist 700 is coated on passivation layer 160.

[0108] The mask 800 is configured to correspond to the photoresist 700, and then an exposure process is performed. The mask 800 can be formed as a slot mask or a halftone mask. The mask 800 includes a non-transmissive region (NR) that blocks most of the light, a semi-transmissive region (HR) that blocks some light and allows the remaining light to pass through, and a transmissive region (TR) that allows most of the light to pass through.

[0109] The portion of photoresist 700 corresponding to the non-transmissive region (NR) of mask 800 is essentially not exposed to light, the portion of photoresist 700 corresponding to the semi-transmissive region (HR) of mask 800 is exposed to some light, and the portion of photoresist 700 corresponding to the transmissive region (TR) of mask 800 is exposed to most of the light.

[0110] Reference Figure 11 The photoresist 700, to which the exposure process has been performed, is developed into a pattern. When the photoresist 700 is a positive photoresist, the light-exposed portions are removed, the partially light-exposed portions are thinned, and the light-unexposed portions are retained. In an embodiment, the photoresist 700 is divided into two portions with different thicknesses. In an embodiment, the photoresist 700 can be a negative photoresist. In the mask 800, non-transmissive areas can be changed to transmissive areas, and transmissive areas can be changed to non-transmissive areas.

[0111] Next, the passivation layer 160 is patterned using a patterned photoresist 700 as a mask to form a first dummy via 167 and a second dummy via 169. The first dummy via 167 and the second dummy via 169 are formed adjacent to the upper gate electrode 154.

[0112] Some regions of semiconductor 130 are exposed through first dummy vias 167 and second dummy vias 169. Specifically, highly doped portions of semiconductor 130 can be exposed. The portions of semiconductor 130 exposed through first dummy vias 167 and second dummy vias 169 are processed using an oxygen plasma process, or heat-treated in an oxygen atmosphere. Therefore, the doping concentration of the portions of semiconductor 130 processed by the oxygen plasma process or heat-treated is reduced. Therefore, the width of the existing lightly doped regions 135 and 136 of semiconductor 130 can be widened. The widened portions of the first lightly doped regions 135 and 136 are positioned adjacent to the surface of semiconductor 130. When performing an oxygen plasma process or a heat treatment process in an oxygen atmosphere, because the lightly doped regions can be formed adjacent to the surface of semiconductor 130, a decrease in current in the first lightly doped regions 135 and 136 can be prevented.

[0113] As described above, the second gate insulating layer 140 may have the same width as the upper gate electrode 154. In this embodiment, during the process of doping impurities into the semiconductor 130, a channel region, a source region, and a drain region are formed, but a lightly doped region is formed separately. Subsequently, a first dummy via 167 and a second dummy via 169 are formed in the passivation layer 160. The doping concentration of a portion of the heavily doped region can then be reduced by an oxygen plasma process or heat treatment under an oxygen atmosphere to form a lightly doped region.

[0114] Reference Figure 12 The thickness of the patterned photoresist 700 is reduced through an ashing process. This removes relatively thin portions of the photoresist 700, thinning out the relatively thick portions.

[0115] Next, the passivation layer 160 is patterned using a photoresist 700 to which an ashing process has been performed. In an embodiment, in the passivation layer 160, a first contact hole 163 is configured to overlap with the source region 132 of the semiconductor 130, and a second contact hole 165 is configured to overlap with the drain region 133 of the semiconductor 130.

[0116] Reference Figure 13 The remaining portion of the photoresist 700 is completely removed. A source electrode 173 and a drain electrode 175 are formed by depositing and patterning a metal material on the passivation layer 160. The source electrode 173 is connected to the source region 132 of the semiconductor 130 through a first contact hole 163, and the drain electrode 175 is connected to the drain region 133 of the semiconductor 130 through a second contact hole 165.

[0117] In one embodiment, firstly, a first dummy via 167 and a second dummy via 169 are disposed in a passivation layer 160. Semiconductor 130 is then processed using an oxygen plasma process or heat-treated in an oxygen atmosphere. Then, a first contact via 163 and a second contact via 165 are disposed in the passivation layer 160. In another embodiment, the first contact via 163 and the second contact via 165 are not formed during the oxygen plasma process or the heat treatment process in an oxygen atmosphere. In yet another embodiment, the first dummy via 167, the second dummy via 169, the first contact via 163, and the second contact via 165 can be formed simultaneously in the passivation layer 160. In yet another embodiment, the first contact via 163 and the second contact via 165 can be formed during the oxygen plasma process or the heat treatment process in an oxygen atmosphere. In yet another embodiment, the doping concentration of the portion of semiconductor 130 exposed by the first contact via 163 and the second contact via 165 can also be reduced. In this embodiment, because the portion of semiconductor 130 exposed by the first contact hole 163 is connected to the source electrode 173 and the portion of semiconductor 130 exposed by the second contact hole 165 is connected to the drain electrode 175, the thin-film transistor can still operate normally even if the doping concentration is reduced.

[0118] Although exemplary embodiments have been described, actual embodiments are not limited to those described, but cover various modifications and equivalent arrangements that are limited to the spirit and scope of the claims.

Claims

1. A thin-film transistor array panel, the thin-film transistor array panel comprising: Base; A semiconductor is disposed on the substrate and includes a channel region, a source region and a drain region disposed on opposite sides of the channel region, a first lightly doped region disposed between the channel region and the source region, and a second lightly doped region disposed between the channel region and the drain region. The upper gate electrode is disposed on the semiconductor; A passivation layer is disposed on the semiconductor and the upper gate electrode; A first contact hole is formed in the passivation layer to overlap with the source region of the semiconductor; A second contact hole is formed in the passivation layer to overlap with the drain region of the semiconductor; A first dummy via is formed in the passivation layer to overlap with the first lightly doped region of the semiconductor; A second dummy via is formed in the passivation layer to overlap with the second lightly doped region of the semiconductor; The source electrode is connected to the source region of the semiconductor through the first contact hole; as well as The drain electrode is connected to the drain region of the semiconductor through the second contact hole. The passivation layer is partially stacked with the first lightly doped region and the second lightly doped region, and Wherein, the portion of the first lightly doped region that overlaps with the first dummy via overlaps with a portion of the source region, and the portion of the second lightly doped region that overlaps with the second dummy via overlaps with a portion of the drain region.

2. The thin-film transistor array panel according to claim 1, wherein, The first lightly doped region and the second lightly doped region are configured to be adjacent to the surface of the semiconductor.

3. The thin-film transistor array panel according to claim 1, wherein, The semiconductor is made of oxide semiconductor material, and The surface of the semiconductor is crystallized.

4. A method for manufacturing a thin-film transistor array panel, the method comprising: Forming semiconductors on a substrate; An upper gate electrode is formed on the semiconductor; By doping impurities into the semiconductor, an undoped channel region and a source and drain region with a high concentration of doping are formed; A passivation layer is formed on the semiconductor and the upper gate electrode; A first dummy via and a second dummy via are formed in the passivation layer adjacent to the upper gate electrode; A first lightly doped region and a second lightly doped region are formed by performing an oxygen plasma process or a heat treatment process under an oxygen atmosphere on the portions of the semiconductor exposed through the first dummy hole and the second dummy hole. A first contact hole is formed in the passivation layer in superposition with the source region of the semiconductor; A second contact hole is formed in the passivation layer in overlap with the drain region of the semiconductor; A source electrode is formed on the passivation layer and connected to the source region of the semiconductor through the first contact hole; as well as A drain electrode is formed on the passivation layer, which is connected to the drain region of the semiconductor through the second contact hole. The passivation layer is partially stacked with the first lightly doped region and the second lightly doped region, and... Wherein, the portion of the first lightly doped region that overlaps with the first dummy via overlaps with a portion of the source region, and the portion of the second lightly doped region that overlaps with the second dummy via overlaps with a portion of the drain region.

5. The method for manufacturing a thin-film transistor array panel according to claim 4, wherein, The first lightly doped region is disposed between the channel region and the source region. The second lightly doped region is disposed between the channel region and the drain region, and The first lightly doped region and the second lightly doped region are configured to be adjacent to the surface of the semiconductor.

6. The method for manufacturing a thin-film transistor array panel according to claim 4, wherein, The first dummy hole, the second dummy hole, the first contact hole, and the second contact hole are simultaneously formed in the passivation layer.

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