Semiconductor device and inductor device

Abstract

A semiconductor device includes a substrate, a first terminal and a second terminal, and a conductor disposed between the first terminal and the second terminal on the substrate to constitute an inductor, which is shaped to form a first loop and a second loop, wherein the conductor has a first intersection with itself existing between the first loop and the second loop, wherein the first loop and the second loop define a first closed area and a second closed area, respectively, wherein the first closed area is smaller than the second closed area. By the asymmetric arrangement of the first loop relative to the axis and the second loop, the coupling noise can be greatly reduced, and the negative interference on other circuits can be alleviated.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more particularly to a semiconductor device and an inductor device. Background Technology

[0002] Integrated circuit inductors are crucial for the voltage-controlled oscillators (VCOs) required to implement many fully integrated transceiver chips that serve various wireless communication protocols. It is known to form inductors using multiple loops, each loop having multiple paths. The conductive tracks are preferably arranged on two horizontal planes, with intersections or crossing points between the paths of the conductive tracks.

[0003] One approach to reducing mutual electromagnetic coupling between VCO resonators on a single semiconductor chip or die involves using inductors that are substantially symmetrical about their horizontal and / or vertical axes, and supplying current to the inductors in a way that the resulting magnetic field components tend to cancel each other out due to the symmetry. Furthermore, two such inductors can be placed close to each other and oriented in a way that significantly reduces the induced current in the second inductor due to the magnetic field originating from the first inductor. Symmetrical figure-eight inductors are a common implementation method for on-die inductors. Summary of the Invention

[0004] In view of this, the present invention provides a semiconductor device and an inductor device, including an asymmetric figure-eight inductor, which can reduce interference from an inductor-capacitor voltage-controlled oscillator (LC-VCO) to solve the above-mentioned problems.

[0005] According to a first aspect of the present invention, a semiconductor device is disclosed, comprising:

[0006] substrate;

[0007] First terminal and second terminal; and

[0008] A conductor is disposed on the substrate between the first terminal and the second terminal to form an inductor, the shape of which is used to form a first loop and a second loop, wherein a first intersection point of the conductor with itself exists between the first loop and the second loop, wherein the first loop and the second loop respectively define a first closed region and a second closed region, wherein the first closed region is smaller than the second closed region.

[0009] According to a second aspect of the present invention, an inductor device is disclosed, comprising:

[0010] substrate;

[0011] First terminal and second terminal; and

[0012] A conductor is disposed on the substrate between the first terminal and the second terminal to form an inductor, the shape of which is used to form a first loop and a second loop, wherein a first intersection point of the conductor with itself exists between the first loop and the second loop, wherein the first loop and the second loop respectively define a first closed region and a second closed region, wherein the first closed region is smaller than the second closed region.

[0013] The semiconductor device of the present invention includes: a substrate; a first terminal and a second terminal; and a conductor disposed on the substrate between the first terminal and the second terminal to form an inductor, the shape of which is used to form a first loop and a second loop, wherein a first intersection point of the conductor with itself exists between the first loop and the second loop, wherein the first loop and the second loop respectively define a first closed region and a second closed region, wherein the first closed region is smaller than the second closed region. By asymmetrically arranging the first loop with respect to the axis and the second loop, coupling noise can be greatly reduced, mitigating negative interference to other circuits. Attached Figure Description

[0014] Figure 1 An asymmetric figure-eight inductor according to an embodiment of the present invention is shown;

[0015] Figure 2 An asymmetric figure-eight inductor according to another embodiment of the present invention is shown;

[0016] Figure 3 An asymmetric figure-eight inductor according to another embodiment of the present invention is shown;

[0017] Figure 4 An asymmetric figure-eight inductor according to yet another embodiment of the present invention is shown;

[0018] Figure 5 An asymmetric figure-eight inductor according to yet another embodiment of the present invention is shown; and

[0019] Figure 6 An asymmetric figure-eight inductor according to yet another embodiment of the present invention is shown. Detailed Implementation

[0020] In the following detailed description of embodiments of the invention, reference is made to the accompanying drawings, which form part of the invention, and which illustrate specific preferred embodiments in which the invention can be practiced. These embodiments have been described in sufficient detail to enable those skilled in the art to practice them, and it should be understood that other embodiments may be utilized, and mechanical, structural, and procedural changes may be made, without departing from the spirit and scope of the invention. Therefore, the following detailed description should not be construed as limiting, and the scope of the embodiments of the invention is defined only by the appended claims.

[0021] It will be understood that although the terms “first,” “second,” “third,” “primary,” “secondary,” etc., may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or portion from another. Therefore, without departing from the teachings of the inventive concept, the first or primary element, component, region, layer, or portion discussed below may be referred to as a second or secondary element, component, region, layer, or portion.

[0022] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “under,” “above,” and “above” may be used herein to describe the relationship of an element or feature to it. Another element or feature is shown in the figure. In addition to the orientation described in the figure, the spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptive terms used herein may be interpreted accordingly. Additionally, it will be understood that when a “layer” is referred to as being “between” two layers, it can be the only layer between the two layers, or there may be one or more intermediate layers.

[0023] The terms “about,” “roughly,” and “about” generally mean a range of ±20%, ±10%, ±5%, ±3%, ±2%, ±1%, or ±0.5% of a specified value. The specified values ​​in this invention are approximate. Unless otherwise specified, the specified values ​​include the meanings of “about,” “roughly,” and “about.” The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, the singular terms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise.

[0024] It will be understood that when an “element” or “layer” is referred to as being “on,” “connected to,” “coupled to,” or “adjacent to” another element or layer, it can be directly on, connected to, coupled to, or adjacent to the other element or layer, or there may be intermediate elements or layers. Conversely, when an element is referred to as being “directly on,” “directly connected to,” “directly coupled to,” or “immediately adjacent to” another element or layer, there are no intermediate elements or layers.

[0025] Note: (i) the same features will be represented by the same reference numerals throughout the figures and will not necessarily be described in detail in every figure in which they appear, and (ii) a series of figures may show different aspects of a single item, each of which is associated with various reference labels that may appear throughout the series or only in selected figures of the series.

[0026] As the integration surface on silicon becomes smaller, the interaction between the sensitive block and electromagnetic (EM) sources (such as VCOs) becomes increasingly stronger. Inductor-capacitor voltage-controlled oscillators (LC-VCOs) consist of negative gm (transconductance) units, switched capacitor arrays (SCAs), inductors, etc. As mentioned earlier, symmetrical figure-eight inductors are commonly used in LC-VCOs. However, noise coupling becomes a problem with such symmetrical figure-eight inductors, especially when adjacent ground top metals are present.

[0027] This invention provides a semiconductor device (inductor device) comprising an asymmetric figure-eight inductor for mitigating on-die inductive coupling, thereby addressing the problem. The inductor according to the invention can achieve better electrical performance when used, for example, in voltage-controlled oscillators. According to experimental results, a 20 dB reduction in coupling noise can be observed at the inductor in the victim circuit.

[0028] Figure 1 An asymmetric figure-eight inductor according to an embodiment of the present invention is shown. For example... Figure 1 As shown, a semiconductor device (inductor device) 1a includes a substrate 100, such as a silicon substrate, and an inductor IN fabricated on the substrate 100. According to one embodiment, the inductor IN is at least partially surrounded by a grounding metal ring GR. According to one embodiment, for example, the grounding metal ring GR is constructed at a top metal layer 202 above the substrate 100. The top metal layer mentioned herein is not limited to the topmost metal layer. For example, the top metal layer may include a topmost metal layer and several upper metal layers located below the topmost metal layer. It should be understood that the grounding metal ring GR can be defined in any top metal layer, such as the topmost metal layer or upper metal layers.

[0029] According to one embodiment, for example, the top metal layer 202 may be an aluminum layer, but is not limited thereto. The inductor IN is formed using a conductor 210 disposed between two terminals A and B of the interfered circuit VC, which is disposed near the open end OP of the ground metal ring GR. Although an open-loop ground ring GR is shown, it should be understood that in some embodiments, the ground metal ring GR may be a closed-loop ground ring. According to one embodiment, for example, the interfered circuit VC may be a switched capacitor array of an inductor-capacitor voltage-controlled oscillator, but is not limited thereto.

[0030] According to one embodiment, conductor 210 is shaped to form a first loop L1 and a second loop L2 of a single-turn inductor IN. A crossover point C exists between the first loop L1 and the second loop L2. The first loop L1 surrounds a first region (a first closed region), and the second loop L2 surrounds a second region (a second closed region). The first loop L1 is defined by conductor 210 and crossover point C, which ensures that the first closed region is completely closed at least in its projection onto a direction perpendicular to the plane in which the first loop is arranged. The second loop L2 is defined by conductor 210 and crossover point C. According to one embodiment, the second closed region is not completely closed. The closed region can be completely or incompletely closed.

[0031] According to one embodiment, the first loop L1 is asymmetrical with respect to the axis AS and the second loop L2, where the axis AS can be an axis passing through the intersection point C. According to one embodiment, the first enclosed region is smaller than the second enclosed region. According to one embodiment, the second loop L2 is arranged closer to the interfered circuit VC and the first loop L1 is arranged farther from the interfered circuit VC, thereby reducing the negative impact on the interfered circuit VC. Through the asymmetrical arrangement of the first loop L1 with respect to the axis AS and the second loop L2 in this invention, coupling noise can be greatly reduced, and in this embodiment, the influence of electromagnetic coupling is eliminated or reduced by the grounded metal ring GR disposed on the periphery, at least partially surrounding the first loop L1 and the second loop L2.

[0032] The inductor IN can be fabricated on the substrate 100 using conventional semiconductor manufacturing processes, including but not limited to deposition, photolithography, etching, cleaning, polishing, and annealing. The inductor IN can consist of at least two interconnect layers. Typically, the thicker top interconnect layer has lower resistance, and the inductor IN is usually disposed within the top metal layer, except where the conductor 210 intersects with itself. At those intersections, a lower interconnect layer is used (i.e., intersection C is formed in a metal layer below the top metal layer). For example, in… Figure 1 In this configuration, conductor 210 may be located in the top metal layer and connected to the underlying interconnect layer 211 at intersection C1. Interconnect layer 211 may be located in the lower metal layer.

[0033] Figure 2 An asymmetric figure-eight inductor (semiconductor device and / or inductor device including inductor) according to another embodiment of the invention is shown, wherein the same regions, layers or elements are represented by the same numerical designations or labels. Figure 2 As shown, similarly, the single-turn figure-eight inductor 1b includes a substrate 100, such as a silicon substrate, and an inductor IN fabricated on the substrate 100. According to one embodiment, the inductor IN is at least partially surrounded by a grounded metal ring GR. According to one embodiment, for example, the grounded metal ring GR is constructed at a top metal layer 202 above the substrate 100. According to one embodiment, for example, the top metal layer 202 may be an aluminum layer, but is not limited thereto. The inductor IN is formed using a conductor 210 disposed between two terminals A and B of a disturbance circuit VC, which is disposed near the open end OP of the grounded metal ring GR. According to one embodiment, for example, the disturbance circuit VC may be a switched capacitor array of an inductor-capacitor voltage-controlled oscillator, but is not limited thereto.

[0034] According to one embodiment, conductor 210 is shaped to form a first loop L1 and a second loop L2 of a single-turn inductor IN. A first intersection point C1 exists between the first loop L1 and the second loop L2. The first loop L1 surrounds a first region (a first closed region), and the second loop L2 surrounds a second region (a second closed region). The first loop L1 is defined by conductor 210 and the first intersection point C1 constituting the first closed region. The second loop L2 is defined by conductor 210, the first intersection point C1, and the second loop L2, and a second intersection point C2 between terminals A and B. According to one embodiment, the first loop L1 and the second loop L2 are asymmetrical with respect to axis AS. According to one embodiment, the first closed region is smaller than the second closed region. According to one embodiment, the second loop L2 is arranged closer to the interfered circuit VC, and the first loop L1 is arranged farther from the interfered circuit VC. In this embodiment, by crossing terminals A and B to form intersection point C2 and then connecting them to the interfered circuit VC, the impact of noise can be further reduced, and the negative impact on the interfered circuit VC can be reduced.

[0035] The inductor IN can be fabricated on the substrate 100 using conventional semiconductor manufacturing processes, including but not limited to deposition, photolithography, etching, cleaning, polishing, and annealing. The inductor IN can consist of at least two interconnect layers. Typically, the thicker top interconnect layer has lower resistance, and the inductor IN is usually disposed within the top metal layer, except where the conductor 210 intersects with itself. At those intersections, a lower interconnect layer is used (i.e., intersection C1 is formed in a metal layer below the top metal layer). For example, in… Figure 2 In this configuration, conductor 210 may be located in the top metal layer and connected to the underlying interconnect layers 211 and 212 at intersections C1 and C2, respectively. Interconnect layers 211 and 212 may be located in a metal layer below the top metal layer.

[0036] Figure 3 An asymmetric figure-eight inductor (semiconductor device and / or inductor device including inductor) according to another embodiment of the invention is shown, wherein the same regions, layers or elements are represented by the same numerical designations or labels. Figure 3As shown, the semiconductor device 1c includes a substrate 100, such as a silicon substrate, and a double-turn figure-eight inductor IN fabricated on the substrate 100. It is understood that the invention is applicable to multi-turn inductors (e.g., three or more turns), and is not limited to double-turn inductors. According to one embodiment, the inductor IN is at least partially surrounded by a grounded metal ring GR. According to one embodiment, for example, the grounded metal ring GR is constructed at a top metal layer 202 above the substrate 100. According to one embodiment, for example, the top metal layer 202 may be an aluminum layer, but is not limited thereto. The inductor IN is formed using a conductor 210 disposed between two terminals A, B of a switched capacitor array 20, which is arranged adjacent to the open end OP of the grounded metal ring GR. According to one embodiment, for example, the switched capacitor array 20 may be electrically connected to a negative gm unit 30. It should be understood that the arrangement of the inductor IN, the switched capacitor array 20, and the negative gm unit 30 is for illustrative purposes only. The negative gm unit 30 can be used as an example of a circuit subject to interference.

[0037] According to one embodiment, conductor 210 is shaped to form a first loop L1 and a second loop L2 of inductor IN. A first intersection point C1 exists between the first loop L1 and the second loop L2. The first loop L1 surrounds a first region, and the second loop L2 surrounds a second region. The first loop L1 is generally defined by conductor 210 and the first intersection point C1 forming the first enclosed region. The second loop L2 is generally defined by conductor 210, the first intersection point C1, and terminals A and B. According to one embodiment, the first loop L1 is asymmetrical about axis AS with respect to the second loop L2. According to one embodiment, the first enclosed region is smaller than the second enclosed region. According to one embodiment, the second loop L2 is arranged closer to the switched capacitor array 20, and the first loop L1 is arranged further away from the switched capacitor array 20.

[0038] According to one embodiment, conductor 210 is further shaped to form a third loop L3 and a fourth loop L4. According to one embodiment, a third intersection point C3 between conductor 210 and itself exists between the third loop L3 and the fourth loop L4. According to one embodiment, the third loop L3 and the fourth loop L4 define a third closed region and a fourth closed region, respectively. According to one embodiment, the fourth closed region is larger than the third closed region.

[0039] According to one embodiment, conductor 210 is further provided with a fourth intersection point C4, which itself connects the first loop L1 and the third loop L3, thereby further defining the boundary between the first closed region and the third closed region.

[0040] According to one embodiment, the first circuit L1 is connected between the fourth circuit L4 and the second circuit L2. According to another embodiment, the fourth circuit L4 is connected between the first circuit L1 and the third circuit L3 to obtain an 8-shaped (or figure-eight) structure in series with the 8-shaped (or figure-eight) structure.

[0041] According to one embodiment, a third loop L3 is arranged within a first loop L1 and a fourth loop L4 is arranged within a second loop L2, thereby forming a fifth intersection C5 for further defining a fourth enclosed region, and a sixth intersection C6 for further defining the first and second enclosed regions, to obtain an 8-within-8 (or 8-in-8) shaped structure. That is, in this embodiment, the first loop L1 can be... Figure 3 The large loop on the outer perimeter of the left-hand region of the inductor (to the left of axis AS), for example, a loop from intersection C1 to intersection C4 and back to intersection C1; the second loop L2 can be... Figure 3 The large outer circle of the right-hand area of ​​the inductor (to the right of axis AS), for example, from terminal B, to intersection C1, and then to terminal A; the third circuit L3 can be... Figure 3 The small loop within the first loop L1 in the left region of the inductor (to the left of axis AS), for example, a loop from crosspoint C4 to crosspoint C6 and back to crosspoint C4; the fourth loop L4 can be... Figure 3 The small loop within the second circuit L2 in the right region of the inductor (to the right of axis AS), for example, a loop from cross point C5 back to cross point C5.

[0042] The inductor IN can be fabricated on the substrate 100 using conventional semiconductor manufacturing processes, including but not limited to deposition, photolithography, etching, cleaning, polishing, and annealing. The inductor IN can consist of at least two interconnect layers. Typically, the thicker top interconnect layer has lower resistance, and the inductor IN is usually disposed within the top metal layer, except where it intersects with the conductor 210. A lower interconnect layer is used at those intersections. For example, in… Figure 3 In this configuration, conductor 210 can be patterned in the top metal layer and connected to the underlying interconnect layers 211, 213, 214, and 215 at intersections C1, C3, C4, and C5-C6, respectively. Interconnect layers 211, 214, and 215 can be located in a lower metal layer directly below the top metal layer. Interconnect layer 213 can be located in a metal layer below interconnect layers 211, 214, and 215.

[0043] Figure 4 An asymmetric figure-eight inductor (semiconductor device and / or inductor device including inductor) according to another embodiment of the invention is shown, wherein the same regions, layers or elements are represented by the same numerical designations or labels. Figure 4As shown, device 1d includes a substrate 100, such as a silicon substrate, and a two-turn figure-eight inductor IN fabricated on the substrate 100. It is understood that the invention is applicable to multi-turn inductors, but not limited to two-turn inductors. According to one embodiment, the inductor IN is at least partially surrounded by a grounded metal ring GR. According to one embodiment, for example, the grounded metal ring GR is constructed at a top metal layer 202 above the substrate 100. According to one embodiment, for example, the top metal layer 202 may be an aluminum layer, but is not limited thereto. The inductor IN is formed using a conductor 210 disposed between two terminals A, B of a switched capacitor array 20, which is arranged adjacent to the open end OP of the grounded metal ring GR. According to one embodiment, for example, the switched capacitor array 20 may be electrically connected to a negative gm unit 30. It should be understood that the arrangement of the inductor IN, the switched capacitor array 20, and the negative gm unit 30 is for illustrative purposes only.

[0044] According to one embodiment, conductor 210 is shaped to form a first loop L1 and a second loop L2 of inductor IN. A first intersection point C1 exists between the first loop L1 and the second loop L2. The first loop L1 surrounds a first region, and the second loop L2 surrounds a second region. The first loop L1 is generally defined by conductor 210 and the first intersection point C1 forming the first closed region. The second loop L2 is generally defined by conductor 210, the first intersection point C1, and the second loop L2 and a second intersection point C2 between terminals A and B. According to one embodiment, the first loop L1 and the second loop are asymmetrical L2 with respect to axis AS. According to one embodiment, the first closed region is smaller than the second closed region. According to one embodiment, the second loop L2 is arranged closer to the switched capacitor array 20 and the first loop L1 is arranged further away from the switched capacitor array 20. In this embodiment, by crossing terminals A and B to form intersection point C2 and then connecting them to the negative GM unit 30, the impact of noise can be further reduced, and the negative impact on the negative GM unit 30 can be reduced.

[0045] According to one embodiment, conductor 210 is further shaped to form a third loop L3 and a fourth loop L4. According to one embodiment, a third intersection point C3 between conductor 210 and itself exists between the third loop L3 and the fourth loop L4. According to one embodiment, the third loop L3 and the fourth loop L4 define a third closed region and a fourth closed region, respectively. According to one embodiment, the fourth closed region is larger than the third closed region.

[0046] According to one embodiment, conductor 210 is further provided with a fourth intersection point C4, which itself connects the first loop L1 and the third loop L3, thereby further defining the boundaries of the first closed region and the third closed region.

[0047] According to one embodiment, the first loop L1 is connected between the fourth loop L4 and the second loop L2. According to another embodiment, the fourth loop L4 is connected between the first loop L1 and the third loop L3 to obtain an 8-shaped structure in series with the 8-shaped structure.

[0048] According to one embodiment, a third loop L3 is arranged within a first loop L1 and a fourth loop L4 is arranged within a second loop L2 to form a fifth intersection C5 for further defining a fourth closed region, and a sixth intersection C6 for further defining a first closed region and a second closed region, to obtain an 8-shaped structure.

[0049] The inductor IN can be fabricated on the substrate 100 using conventional semiconductor manufacturing processes, including but not limited to deposition, photolithography, etching, cleaning, polishing, and annealing. The inductor IN can consist of at least two interconnect layers. Typically, the thicker top interconnect layer has lower resistance, and the inductor IN is usually disposed within the top metal layer, except where it intersects with the conductor 210. A lower interconnect layer is used at those intersections. For example, in… Figure 4 In this configuration, conductor 210 can be patterned in the top metal layer and connected to the underlying interconnect layers 211, 212, 213, 214, and 215 at intersections C1, C2, C3, C4, and C5-C6, respectively. Interconnect layers 211, 212, 214, and 215 can be located in a lower metal layer directly below the top metal layer. Interconnect layer 213 can be located in a metal layer below interconnect layers 211, 212, 214, and 215.

[0050] Figure 5 An asymmetric figure-eight inductor (semiconductor device and / or inductor device including inductor) according to another embodiment of the invention is shown, wherein the same regions, layers or elements are represented by the same numerical designations or labels. Figure 5 As shown, device (semiconductor device) 1e includes a substrate 100 (e.g., a silicon substrate) and a single-turn 8-shaped inductor IN fabricated on the substrate 100. It is understood that the invention is applicable to multi-turn inductors, but not limited to two-turn inductors. According to one embodiment, the inductor IN is at least partially surrounded by a grounded metal ring GR. According to one embodiment, for example, the grounded metal ring GR is constructed at a top metal layer 202 above the substrate 100. According to one embodiment, for example, the top metal layer 202 may be an aluminum layer, but is not limited thereto. The inductor IN is formed using a conductor 210, which merges with connection portions 22, 24 of a switched capacitor array 20 disposed adjacent to the open end OP of the grounded metal ring GR. According to one embodiment, for example, the switched capacitor array 20 may be electrically connected to a negative gm cell 30. It should be understood that the arrangement of the inductor IN, the switched capacitor array 20, and the negative gm cell 30 is for illustrative purposes only.

[0051] Cancel Figure 3 Terminals A and B are beneficial because the metal connection between the switched capacitor array 20 and the inductor IN could introduce an additional current loop and thus reduce the aggressor of inductor coupling. By merging the connection portions 22 and 24 of the inductor IN with those of the switched capacitor array 20, unwanted current loops can be avoided. Specifically, in this embodiment, this is achieved by eliminating… Figure 3 Terminals A and B are used to shorten the distance from inductor IN to negative gm unit 30, so that inductor IN is directly connected to connection parts 22 and 24. Therefore, the influence of noise can be further reduced, and the negative impact on negative gm unit 30 can be reduced.

[0052] According to one embodiment, conductor 210 is similarly shaped to form a first loop L1 and a second loop L2 for inductor IN. A first intersection point C1 exists between the first loop L1 and the second loop L2. The first loop L1 surrounds a first region, and the second loop L2 surrounds a second region. The first loop L1 is generally defined by conductor 210 and the first intersection point C1 forming the first enclosed region. The second loop L2 is generally defined by conductor 210, the first intersection point C1, and connection portions 22, 24 of the switched capacitor array 20. According to one embodiment, the first loop L1 and the second loop L2 are asymmetrical with respect to axis AS. According to one embodiment, the first enclosed region is smaller than the second enclosed region. According to one embodiment, the second loop L2 (larger) is arranged closer to the switched capacitor array 20, and the first loop L1 (smaller) is arranged further away from the switched capacitor array 20.

[0053] The inductor IN can be fabricated on the substrate 100 using conventional semiconductor manufacturing processes, including but not limited to deposition, photolithography, etching, cleaning, polishing, and annealing. The inductor IN can consist of at least two interconnect layers. Typically, the thicker top interconnect layer has lower resistance, and the inductor IN is usually disposed within the top metal layer, except where it intersects with the conductor 210. A lower interconnect layer is used at those intersections. For example, in… Figure 5 In this process, conductor 210 can be patterned in the top metal layer and connected to the underlying interconnect layer 211 at intersection C1.

[0054] Figure 6 An asymmetric figure-eight inductor (semiconductor device and / or inductor device including inductor) according to another embodiment of the invention is shown, wherein the same regions, layers or elements are represented by the same numerical designations or labels. Figure 6As shown, device 1f includes a substrate 100, such as a silicon substrate, and a two-turn figure-eight inductor IN fabricated on the substrate 100. It is understood that the invention is applicable to multi-turn inductors, but not limited to two-turn inductors. According to one embodiment, the inductor IN is at least partially surrounded by a grounded metal ring GR. According to one embodiment, for example, the grounded metal ring GR is constructed at a top metal layer 202 above the substrate 100. According to one embodiment, for example, the top metal layer 202 may be an aluminum layer, but is not limited thereto. The inductor IN is formed using a conductor 210, which merges with connection portions 22, 24 of a switched capacitor array 20 disposed adjacent to the open end OP of the grounded metal ring GR. According to one embodiment, for example, the switched capacitor array 20 may be electrically connected to a negative gm unit 30. It should be understood that the arrangement of the inductor IN, the switched capacitor array 20, and the negative gm unit 30 is for illustrative purposes only.

[0055] Cancel Figure 3 Terminals A and B depicted are beneficial because the metal connection between the switched capacitor array 20 and the inductor IN could introduce additional current loops and thus reduce interference sources from inductor coupling. Undesirable current loops can be avoided by merging the connection portions 22 and 24 of the switched capacitor array 20 with the inductor IN.

[0056] According to one embodiment, conductor 210 is similarly shaped to form a first loop L1 and a second loop L2 for inductor IN. A first intersection point C1 exists between the first loop L1 and the second loop L2. The first loop L1 surrounds a first region, and the second loop L2 surrounds a second region. The first loop L1 is generally defined by conductor 210 and the first intersection point C1 forming the first enclosed region. The second loop L2 is generally defined by conductor 210, the first intersection point C1, and connection portions 22, 24 of the switched capacitor array 20. According to one embodiment, the first loop L1 and the second loop L2 are asymmetrical with respect to axis AS. According to one embodiment, the first enclosed region is smaller than the second enclosed region. According to one embodiment, the second loop L2 is arranged closer to the switched capacitor array 20, and the first loop L1 is arranged further away from the switched capacitor array 20.

[0057] According to one embodiment, conductor 210 is further shaped to form a third loop L3 and a fourth loop L4. According to one embodiment, a third intersection point C3 between conductor 210 and itself exists between the third loop L3 and the fourth loop L4. According to one embodiment, the third loop L3 and the fourth loop L4 define a third closed region and a fourth closed region, respectively. According to one embodiment, the fourth closed region is larger than the third closed region.

[0058] According to one embodiment, conductor 210 is further provided with a fourth intersection point C4, which itself connects the first loop L1 and the third loop L3, thereby further defining the boundaries of the first closed region and the third closed region.

[0059] According to one embodiment, the first loop L1 is connected between the fourth loop L4 and the second loop L2. According to another embodiment, the fourth loop L4 is connected between the first loop L1 and the third loop L3 to obtain an 8-shaped structure in series with the 8-shaped structure.

[0060] According to one embodiment, a third loop L3 is arranged within a first loop L1 and a fourth loop L4 is arranged within a second loop L2, thereby forming a fifth intersection C5 for further defining a fourth enclosed region, and a sixth intersection C6 for further defining the fourth enclosed region. The first and second enclosed regions are defined to obtain an 8-in-8 shape structure.

[0061] The inductor IN can be fabricated on the substrate 100 using conventional semiconductor manufacturing processes, including but not limited to deposition, photolithography, etching, cleaning, polishing, and annealing. The inductor IN can consist of at least two interconnect layers. Typically, the thicker top interconnect layer has lower resistance, and the inductor IN is usually disposed within the top metal layer, except where it intersects with the conductor 210. A lower interconnect layer is used at those intersections. For example, in… Figure 6 In this embodiment, conductor 210 is located in the top metal layer and connects to the underlying interconnect layers 211, 213, 214, and 215 at intersections C1, C3, C4, and C5-C6, respectively. Interconnect layers 211, 214, and 215 may be located in a lower metal layer below the top metal layer. Interconnect layer 213 may be located in a metal layer below interconnect layers 211, 214, and 215. The inductor device and / or semiconductor device in this invention includes an inductor, as well as other components (such as the terminals described above).

[0062] Those skilled in the art will readily observe that numerous modifications and alterations can be made to the apparatus and method while maintaining the teachings of this invention. Therefore, the foregoing disclosure should be interpreted as being limited only by the scope and limits of the appended claims.

Claims

1. A semiconductor device, characterized by comprising: include: substrate; First terminal and second terminal; as well as A conductor is disposed on the substrate between the first terminal and the second terminal to form an inductor, the shape of which is used to form a first loop and a second loop, wherein a first intersection point of the conductor with itself exists between the first loop and the second loop, wherein the first loop and the second loop respectively define a first closed region and a second closed region, wherein the first closed region is smaller than the second closed region; The conductor is further shaped to form a third loop and a fourth loop, wherein a third intersection point of the conductor with itself exists between the third loop and the fourth loop, and wherein the third loop and the fourth loop define a third closed region and a fourth closed region, respectively, wherein the fourth closed region is larger than the third closed region; The conductor also has a fourth intersection point, which itself connects the first loop to the third loop, thereby further defining the boundaries of the first closed region and the third closed region. The first circuit is connected between the fourth circuit and the second circuit, and the fourth circuit is connected between the first circuit and the third circuit to obtain another octagonal structure in series with an octagonal structure.

2. The semiconductor device according to claim 1, wherein The first terminal and the second terminal are two terminals of the switched capacitor array.

3. The semiconductor device according to claim 2, wherein The second circuit is close to the switched capacitor array, while the first circuit is far from the switched capacitor array.

4. The semiconductor device according to claim 1, wherein The inductor is at least partially surrounded by a grounded metal ring.

5. The semiconductor device according to claim 4, wherein The grounding metal ring is constructed on the top metal layer above the substrate.

6. The semiconductor device according to claim 1, wherein The conductor has a second intersection point with itself between the first terminal or the second terminal and the second circuit.

7. The semiconductor device according to claim 1, wherein The third loop is arranged within the first loop and the fourth loop is arranged within the second loop to form a fifth intersection point for further defining the fourth closed area, and a sixth intersection point for further defining the first closed area and the second closed area, to obtain an 8-in-8 shape structure.

8. The semiconductor device according to claim 1, wherein The inductor is part of the inductor capacitor voltage-controlled oscillator.

9. An inductor device, characterized by include: substrate; First terminal and second terminal; as well as A conductor is disposed on the substrate between the first terminal and the second terminal to form an inductor, the shape of which is used to form a first loop and a second loop, wherein a first intersection point of the conductor with itself exists between the first loop and the second loop, wherein the first loop and the second loop respectively define a first closed region and a second closed region, wherein the first closed region is smaller than the second closed region; The conductor is further shaped to form a third loop and a fourth loop, wherein a third intersection point of the conductor with itself exists between the third loop and the fourth loop, and wherein the third loop and the fourth loop define a third closed region and a fourth closed region, respectively, wherein the fourth closed region is larger than the third closed region; The conductor also has a fourth intersection point, which itself connects the first loop to the third loop, thereby further defining the boundaries of the first closed region and the third closed region. The first circuit is connected between the fourth circuit and the second circuit, and the fourth circuit is connected between the first circuit and the third circuit to obtain another octagonal structure in series with an octagonal structure.

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