Image sensor

Abstract

Embodiments of the present disclosure relate to image sensors. An electronic device includes a first array of image pixels having an input coupled to a first selection rail and an output coupled to a first output rail; a second array of test pixels having an input coupled to a second selection rail and an output coupled to the first output rail; a third array of test pixels having an input coupled to the first selection rail and an output coupled to the second output rail. A processor is coupled to receive output signals at the first and second output rails. In the absence of defects, the output signals from the second and third arrays are fixed at one or the other of only two values. The output signals received by the processor are processed on the first and second output rails to determine the presence or absence of defects.

Description

[0001] Priority declaration

[0002] This application claims the benefit of priority of French Patent No. 2100897, filed on January 29, 2021, the contents of which are hereby incorporated by reference to the maximum extent permitted by law. Technical Field

[0003] The present disclosure relates generally to image sensors, and in particular to CMOS image sensors. Background Art

[0004] Typically, an image sensor comprises pixels arranged in rows and columns. For each row, the pixels in the row are coupled to a plurality of row conductive rails, which enable selection and control of all pixels in the row. For each column, the pixels in the column are coupled to a conductive rail of the column, which enables collection of a signal representing the intensity of light captured by the pixels of the selected column. The column rails of the sensor are connected to the output stage of the sensor, and in particular perform the functions of sampling, amplification, analog-to-digital conversion and storage of signal levels read from the column rails. Typically, pixels of the same row are read simultaneously (in parallel) by the sensor output stage, and pixels of different rows are read consecutively.

[0005] For certain applications, by way of non-limiting example, in the field of CMOS image sensors employed in sensors for motor vehicles, it is desirable to perform an integrity check of the sensor elements before, after, and / or during each acquisition of an image by the sensor. Summary of the invention

[0006] Embodiments overcome all or part of the deficiencies of known image sensors.

[0007] An embodiment provides an electronic device comprising a first array of image pixels having an input coupled to a first selection rail and an output coupled to a first output rail; at least one second array of test pixels having an input coupled to the second selection rail and an output coupled to the first output rail; at least one second array of test pixels having an input coupled to the first selection rail and an output coupled to the second output rail; and a processor, wherein each test pixel of the second array and the third array is configured to provide an output signal of one or the other of two values ​​to the processor using at least one of the first selection rails or one of the first output rails in the absence of a defect, and wherein the processor is configured to determine the presence of a defect in response to the test pixel delivering another value different from one or the other of the two values ​​by one or more output signals.

[0008] According to an embodiment, each image pixel includes at least one photodiode and is configured to generate an output voltage at its output that is dependent on the light reaching the at least one photodiode, and each test pixel includes an input receiving one or the other of two reference voltages such that the test pixel delivers an output signal at one or the other of the two values ​​in the absence of a defect.

[0009] According to an embodiment, an electronic device includes: a circuit for controlling a first selection rail and a second selection rail; an analog processing and analog-to-digital conversion circuit coupled to a first output and a second output rail; and a support having a first array, a second array, and a third array, the control circuit and the analog processing and analog-to-digital conversion circuit being arranged on the support, the second array being located on the support, the control circuit being on a side of the first array opposite to the analog processing and analog-to-digital conversion circuit, and the third array being located on the support on a side of the first array opposite to the control circuit.

[0010] According to an embodiment, the image pixels of the first array are configured to transmit a video signal when acquiring an image. The second array and / or the third array include at least one component of test pixels, the component of the test pixels including a first alignment portion of the test pixels, which is configured to deliver output signals, each output signal being at one or the other of two values ​​in the absence of defects. The processor is configured to use the video signals of the image pixels of the first array to continuously receive a sequence of output signals of the first alignment portion readings to determine from the continuous reading of any portion of the continuous reading output signals including at least a given number of first alignment portions whether the orientation of the acquired image is correct, and / or which position of the first array of image pixels corresponds to the video signal read using the output signal of the portion.

[0011] According to an embodiment, a given number of consecutive read output signals corresponds to a minimum region of interest length of the image on which the processor is configured to apply the processing.

[0012] According to an embodiment, the processor is configured to determine whether the orientation of the acquired image is correct and / or which position of the first array of image pixels corresponds to the video signal read using the output signals of the portions, even though one of the output signals of the portions is not at one of the two values.

[0013] According to an embodiment, the processor is configured to determine, for each output signal, whether the output signal is at one or the other of two values, and in case the output signal is not at one or the other of the two values, indicating that the image pixel coupled to the same selection rail and / or the same output rail is invalid, as the output signal delivered by the test pixel.

[0014] According to an embodiment, the test pixels of the first alignment portion are distributed into consecutive groups of test pixels, each group including a first set of test pixels and a second set of test pixels, the first set of test pixels of each group being configured to deliver the same output signal at one or the other of two values, and at least a portion of the second set of test pixels of each group being configured to deliver an output signal at one or the other of the two values ​​different from that of another group.

[0015] According to an embodiment, each of the first set of test pixels is configured to deliver a series of output signals alternating between a first value and a second value.

[0016] According to an embodiment, the second set of test pixels of each group is configured to deliver an output signal encoding a unique identifier of said group.

[0017] According to an embodiment, the test pixels of each second set of test pixels are distributed into pairs of test pixels, which pairs of test pixels are configured to deliver the same output signal.

[0018] According to an embodiment, each component of the test pixels includes a second alignment portion adjacent to the first alignment portion of the test pixel, the pixels of the first alignment portion and the second alignment portion are paired, and the test pixels of each pair of test pixels are configured to deliver a different output signal between two values.

[0019] According to an embodiment, the processor is configured to determine, for each pair of test pixels, whether the output signals delivered by the paired test pixels are different, and in case the output signals are not different, indicate that the image pixels coupled to the same select rail and / or the same first output rail as the paired test pixels are invalid.

[0020] According to an embodiment, the image pixels of the first array are arranged in rows and columns, the device is delivered to operate in a first configuration and all rows of the first array are selected successively, and in a second configuration, only a portion of the rows of the first array are read successively, the number of test pixels per group of the first alignment portion being smaller than the number of rows of said portion.

[0021] According to an embodiment, each test pixel includes: a first MOS transistor having a drain coupled to an input node, a source coupled to a second node, and a gate coupled to one of the selection rails, a second MOS transistor having a drain coupled to a high reference voltage, a source coupled to the second node, and a gate coupled to a reset signal rail, a first follower coupled to the second node and configured to replicate a voltage at the second node toward an output of the first follower, and a third transistor having a drain occasionally to the output of the first follower, a source coupled to a read output, and a gate coupled to the readout signal rail. Each image pixel includes: a photodiode having a fourth MOS transistor having a drain coupled to the anode or cathode of the photodiode, a source coupled to a third node, and a gate coupled to one of the select rails, a fifth MOS transistor having a drain coupled to a high reference voltage, a source coupled to the third node, and a gate coupled to a reset signal rail, a second follower coupled to the third node and configured to replicate a voltage on the third node toward an output of the second follower, and a sixth transistor having a drain coupled to the output of the second follower, a source coupled to a read output, and a gate coupled to the read output rail.

[0022] An embodiment also provides a method for designing an electronic device, such as previously defined, comprising determining that each test pixel delivers an output signal at one or two values ​​in the absence of defects, and that each test pixel delivers an output signal at the other of the two values ​​in the absence of defects, so that the test pixels of the second array and / or the third array form an assembly of test pixels, which includes a first alignment portion of the test pixels, and will be able to determine from continuous readings of any portion of the output signal including continuous readings of at least a given number of first alignment portions whether the orientation of the acquired image is correct, and / or which position of the first array of image pixels corresponds to the video signal read using the output signal of said portion. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The above features and advantages and other features and advantages will be described in detail in the following description of specific embodiments given by way of illustration and not limitation with reference to the accompanying drawings, in which:

[0024] Figure 1 An embodiment of an image sensor is shown;

[0025] Figure 2 Shows Figure 1 A more detailed embodiment of a portion of an image sensor;

[0026] Figure 3 Shows Figure 2 Embodiments of the distribution of values ​​of test pixels of an image sensor;

[0027] Figure 4 Shows Figure 2 Embodiments of the distribution of values ​​of test pixels of an image sensor;

[0028] Figure 5 The flowchart shows the Figure 1 Embodiments of the method for acquiring an image using an image sensor;

[0029] Figure 6 Shows Figure 2 Examples of embodiments of image pixels of an image sensor of; and

[0030] Figure 7 Shows Figure 2 An embodiment of a test pixel of an image sensor in FIG. DETAILED DESCRIPTION

[0031] Similar features have been indicated with similar reference numerals in the various figures. In particular, common structural and / or functional characteristics in various embodiments may have the same reference numerals and may be provided with the same structural, dimensional and material characteristics. For clarity, only steps and elements useful for understanding of the embodiments are set forth and described in detail.

[0032] Unless otherwise indicated, when referring to two elements connected together, this means a direct connection without an intermediate element except for a conductor, and when referring to two elements coupled together, this means that the two elements can be connected or they can be coupled via one or more other elements. Unless otherwise specified, the expression "about", "approximately", "substantially" and "in the order of magnitude of..." are expressed within 10%, preferably within 5%. In addition, a signal alternating between a first constant state (e.g., a low state, labeled "0") and a second constant state (e.g., a high state, labeled "1") is referred to as a binary signal. The high state and low state of different binary signals of the same electronic circuit can be different. In fact, a binary signal can correspond to a voltage or current, which may not be perfectly constant in a high state or a low state.

[0033] The embodiment of the image sensor will be described in the example of an application where the image sensor forms part of an advanced driver assistance system which may be included in a vehicle. However, it should be clear that the image sensor of this embodiment may be implemented wherever there is a need to implement a test of the correct operation of the image sensor.

[0034] Figure 1 An embodiment of an image sensor 10 is shown partially and schematically.

[0035] Image sensor 10 includes a pixel array 12 (not shown). Figure 1 ), at least some of the pixel arrays 12 capture image data in an analog format and analogly deliver the image data to analog processing (AP) and analog-to-digital conversion (ADC) circuitry 14, which filters the image data in the analog domain and converts the image data to the digital domain to generate digital image data. The analog processing and ADC circuitry 14 transmits the digital image data to a processor 16, which performs the desired digital processing functions based on the data received from the control circuitry 18. As an example, the processor 16 may perform processing operations that are intended to improve the image.

[0036] The processor 16 delivers the output signal directly to other components of the vehicle associated with the sensor 10 via an appropriate data interface, such as a parallel data interface or a serial data interface, or delivers the output signal directly to these components via a data bus. A phase locked loop (PLL) 20 delivers a clock signal to be used by the processor 16, and a memory (Mem) 22 provides non-volatile data storage or volatile data storage to the processor 16. As an example, when the image sensor 10 forms part of an advanced driver assistance system, the image acquired by the image sensor can be transmitted to the processor, which can implement functions such as determining that a vehicle with the on-board image sensor 10 is about to collide.

[0037] Figure 2 Shows Figure 1 A more specific embodiment of a portion of the image sensor 10 is shown. Figure 2 As shown, the pixel array 12 includes:

[0038] The first array M1, or network, of pixels is arranged in rows R i and column C j Wherein M and N are natural integers, i is a natural integer in the range from 1 to M, and j is a natural integer in the range from 1 to N.

[0039] The second array M2, or network, of pixels comprises pixels arranged along a first edge of the first array M1 in rows RT k and column C j The test pixel T in st , R is a natural integer greater than or equal to 2, k is a natural integer in the range from 1 to R, and j is a positive integer in the range from 1 to N, Figure 2 In R, it is equal to 2;

[0040] The third array M3, or network, of pixels comprises test pixels T along a second edge of the first array M1. st , connected to the first edge and along the edge of the second array M2, in row R i and RTk and CT p In which Q is an integer greater than or equal to 2, i is an integer in the range from 1 to M, and p is an integer in the range from 1 to Q, Q is Figure 2 The middle is equal to 2;

[0041] For each row R i and RT k , row conductive track 24, also called selection track, for each row R i Coupled to row R i The first array M1 has image pixels at its input Pix, and the row conductive rails 24 are coupled to the row R i The input of the test pixel Tst of the third array M3; and for each row RT k , row conductor rail 24 is coupled to row RT k The input of the test pixel Tst of the second array M2 and the row conductive rail 24 are coupled to the row RT k The input of the test pixel Tst of the third array M3; and

[0042] For each column C j and CT p , the conductive rail 26 is along row C j or CT p extension, hereinafter indiscriminately referred to as row rail or output rail, for each column C j , conductive track 26 is coupled to column C j The outputs of the first array M1 of image pixels Pix and the conductive track 26 are coupled to the columns C j The output of the second array M2 of test pixels Tst, and for each column CT p , the conductive rail 26 is coupled to the column CT p The output of the test pixel Tst of the third array M3.

[0043] According to an embodiment, M varies from 1 to tens of thousands, and N varies from 1 to tens of thousands. According to an embodiment, R is an even number and Q is an even number. According to an embodiment, R varies from 2 to tens of thousands, and Q varies from 2 to tens of thousands.

[0044] The image sensor 10 further comprises a row control circuit 28 configured to control the selection rails 24, for example configured to deliver a binary selection signal RD on each selection rail 24. According to an embodiment, the row control circuit 28 is connected to all rows R on a side of the third array M3 of the first array M1 opposite to the test pixels Tst. i and RT k The analog processing and digital-to-analog conversion circuit (Ap ADC) 14 is connected to all columns C on one side of the first array M1 relative to the second array of the test array Tst. j and CTp The column track is 26.

[0045] Each image pixel Pix comprises a light-sensitive element, for example a photodiode, configured to capture incident light radiation during a so-called integration phase and to deliver an analog electrical signal representative of the light intensity captured during the integration phase. The output signal delivered by each image pixel Pix may vary between a first limit value and a second limit value, one of the limit values ​​representing a minimum or even zero light intensity received during the integration phase, and the other limit value representing a maximum light intensity received during the integration phase.

[0046] According to an embodiment, the test pixels Tst have the same, or substantially the same, electrical structure as the image pixels Pix, and share the same selection rails 24 and / or the same column rails 26 with significant differences from the first array M1. The difference is that, instead of a photosensitive element, each test pixel Tst includes a node that delivers a known voltage having one of two values. Since the voltage Tst delivered by the test pixel is known, execution on a given operation of the test pixel Tst should provide a known result. When a known result is not generated, it can be inferred that one or more of the selection rails 24 and output rails 26 are not operating correctly, or that the readout circuitry such as the processing and analog-to-digital conversion circuitry 14 or the row control circuitry 28 is not operating correctly. Therefore, it can be inferred that the output of the image pixel Pix is ​​not reliable because the first array M1 shares exactly the same selection rails 24 and output rails 26 with the test pixels Tst, and uses the same analog processing and analog-to-digital conversion circuitry 14 and the same row control circuitry 28. Therefore, in the case where the image sensor 10 forms part of an advanced driver assistance system, the processor 16 can take correct actions based on this knowledge. Thus, where the image sensor 10 forms part of an advanced driver assistance system, the processor 16 can take appropriate action based on this knowledge (e.g. deactivation of an autonomous driving mode, a warning to the driver that collision detection or lane departure warning is offline, etc.).

[0047] According to another embodiment, the test pixel Tst can take a different form and be electrically different from the image pixel Pix. Typically, the structure of the test pixel Tst is such that each test pixel Tst delivers an expected output signal when the electronic circuit of the readout link operates correctly, and does not deliver an expected output signal when the readout link does not operate correctly.

[0048] According to an embodiment, each test pixel Tst is configured to deliver an output signal at a first value or at a second value during a read operation. As an example, the first value may be the same output signal as the image pixel Pix having the minimum light intensity received during the integration phase, and the second value may be the same output signal as the image pixel having the maximum light intensity received during the integration phase. When the test pixel Tst delivers an output signal at the second value, the test pixel Tst is referred to as being at "0", and when the test pixel delivers an output signal at the first value, the test pixel is referred to as being at "1".

[0049] Figure 3 The distribution of the value of the test pixel Tst is schematically shown. Figure 3 , the test pixel Tst at the first value “1” has been represented by a white square and the test pixel Tst at the second value “0” has been represented by a black square.

[0050] According to an embodiment, the distribution of "0" and "1" in the second array M2 and the third array M3 of test pixels TST is determined according to a set of rules. The rule is that for the second array M2, for at least one row RT k , there is another row RT k’ , k' is different from k, so that for each column C j , as j changes from 1 to N, the row RT k The test pixel Tst and row RT k’ When the second array M2 includes only two rows RT 1 and RT 2 This means that for each row C 1 to C N , line RT 1 The value RT of the test pixel Tst 1 With RT 2 The value of the test pixel Tst is relative. Another rule is that for at least one row CT p In the third array M3, there is another column CT p’ , p' is different from p, so that for each row R i , as i changes from 1 to M, column CT p and CT p’ When the third array M3 includes only two columns CT 1 and CT 2 This means that for each row R 1 to R M , CT 1 and CT 2 The values ​​of the test pixels Tst are relative. In addition, the second array M2 belongs to the same column Cj The relative value of the test pixel set row RT k and RT k’ The two test pixels Tst are called a pair of test pixels or belong to the same row R of the third array M3. i The columns of the test pixel set CT p and CT p’ Two test pixels of are called a pair of test pixels. In the following description, when the first test pixel is at "1" and the second test pixel is at "0", a pair of the first test pixel and the second test pixel is referred to as being at "1", and when the first test pixel is at "0" and the second test pixel is at "0", a pair of the first test pixel and the second test pixel is referred to as being at "0". According to an embodiment, a pair of test pixels may allow encoding of one bit. As an example, each pair of test pixels encodes bit "1" with "1" and each pair of test pixels encodes bit "0" with "0", or vice versa.

[0051] In the following description, the row RT of the second array M2 of the previously described rule is verified. k and RT k’ The test pixels of a row in are called component E, or columns CT of the third array M3 verifying the previously defined rule p and CT p’ A column in is called component E. Figure 3 In FIG. 4 , as an example, the second array M2 and the third array M3 each include a single component E of test pixels.

[0052] Figure 4 An example of the distribution of values ​​"0" and "1" of a test pixel Tst of an assembly E of test pixels is shown. Each assembly comprises a series of groups G of test pixels Tst. Each group G comprises a number SIZE_G of test pixels. The number SIZE_G is preferably the same for all groups G of the assembly. The number SIZE_G may depend on the number of rows M and / or the number of columns N. The number SIZE_G may be the same as whether the assembly belongs to the second array M2 or whether the assembly belongs to the third array M3. According to an embodiment, the number SIZE_G varies from 16 to 128. Typically, the number SIZE_G is substantially equal to the minimum size of the image portion that is desired to be located (also referred to as the region of interest). However, the number SIZE_G must be large enough to allow the encoding of a single identifier for each group, as described in further detail herein.

[0053] Each group G comprises a series of at least a first pattern P1 and a second pattern P2, also referred to as a first set P1 and a second set P2.

[0054] The first pattern P1 comprises a number SIZE_P1 of consecutive test pixels Tst having alternating values, for example consecutively, a test pixel at "0", a test pixel at "1", a test pixel at "0", etc. According to an embodiment, the number SIZE_P1 is an even number. According to one embodiment, the number SIZE_P1 is greater than or equal to 4 and is for example equal to 4. The first pattern P1 is hereinafter referred to as a synchronization code.

[0055] The second pattern P2 comprises a number SIZE_P2 of consecutive test pixels Tst and enables the identifier of the coding group G. Advantageously, the second pattern P2 cannot be confused with the first pattern P1. For this purpose, the second pattern P2 does not overlap with the values ​​of the first pattern P1 by any translation or inversion. The identification of each group G of component E is unique. The second patterns P2 of two groups G of component E are therefore different. According to an embodiment, the second mode P2 enables a coding counter having values ​​that grow from the first group to the last group G of component E. The second pattern P2 is therefore called a group identifier. According to an embodiment, the number SIZE_P2 is an even number. According to an embodiment, the number SIZE_P2 varies from 12 to 124. The sum of the numbers SIZE_P1 and SIZE_P2 is equal to SIZE_G.

[0056] According to an embodiment, in the second mode P2, the values ​​of the test pixels are duplicated. This means that the test pixels of the second mode P2 are arranged in a pair of test pixels of the same value, preferably in consecutive test pixels of the same value. According to an embodiment, the number SIZE_P2 is an even number. According to an embodiment, the second mode P2 allows the encoding of the identifier of the group G using the number of test pixels SIZE_P2 / 2.

[0057] According to an embodiment, when each test pixel encodes one bit, the second mode P2 may correspond to a (SIZE_P2) / 2 bit counter. As an example, for the 36th group G of component E, the number 36 is encoded by the binary code "00100100", in which SIZE_P2 is equal to 26, the second mode P2 corresponds to the binary code "00000000000000110000110000".

[0058] Figure 5 The flowchart shows the Figures 1 to 4 An embodiment of a method for acquiring an image by the image sensor 10.

[0059] At step 50, a row of array 12 is selected, and the output signals delivered by the pixels of the selected row are read by analog processing and analog-to-digital conversion circuit 14 and converted into digital signals for transmission to processor 16. The digital signals resulting from the analog-to-digital conversion of the output signals delivered by test pixels Tst are referred to as test signals, and the digital signals resulting from the analog-to-digital conversion of the output signals delivered by image pixels Pix are referred to as video signals. The method is executed at step 51.

[0060] In step 51, the processor 16 selects a test signal and a video signal from among the digital signals received in step 50. When a row of the second array M2 of the test pixels Tst is selected, all digital signals received by the processor 16 are test signals, and for other rows of the array 12, the digital signals received by the processor 16 include test signals and video signals. The method at step 52A for processing the test signal is performed by the processor 16, and the method at step 52B for processing the video signal is performed by the processor 16. Steps 52A and 52B may be performed sequentially or in parallel by the processor 16. According to an embodiment, the processor 16 may determine whether the selected pixel row is a row of the second array M2 based on the rank of the selected row.

[0061] In step 52A, the processor 16 performs processing on a pair of test pixels Tst associated with a set of the second array M2 of test pixels Tst obtained after reading the output signals of two rows of the array 12 or a test signal of the third array M3 of a pair of test pixels Tst obtained after reading the output signals of the rows of the array 12. In general, the processing can be performed after the complete acquisition of the image or with the acquisition of consecutive rows of the image. The processing may include the assignment of the value "0" or "1" of the test signal. For example, if the test signal is greater than a first threshold, it is set to "1"; if the test signal is less than a second threshold, it is set to "0". The first threshold and the second threshold may be stored in a memory or may be generated by the processor 16. If the test signal is contained between the first threshold and the second threshold, the processor determines whether an error has occurred. Since each test pixel is used to transmit an output signal at one or the other of the two values, the method of assigning the values ​​"0" and "1" is less sensitive to the noise present on the readout chain. The error may correspond to a problem in the actual test pixel or the readout chain that delivers the test signal. The test pixel values ​​of each pair of test pixels must be relative. If the processor 16 assigns the same value "0" or "1" to two test pixels of the same test pair, this means that an error has occurred.

[0062] Processing may then include decoding of the test signal. According to one embodiment, when each pair of test pixels enables encoding of a bit, the decoding operation may include determining the bit encoded by the pair of test pixels. Advantageously, for the first mode P1 of each group G, if an error is obtained during the assignment of the value "0" or "1" to the test signal of a pair of test pixels, the bit encoded by the pair of test pixels can still be determined based on the test signals of the other test pixel pairs of the first mode P1. Advantageously, for the second mode P2 of each group G, if an error is obtained during the assignment of the value "0" or "1" to the test signal, the bit encoded by the pair of test pixels can still be determined because there are test pairs with the same value. This enables a robust decoding method to be obtained.

[0063] Based on the first pattern P1 of each group G, the processor can determine whether the obtained image is correctly oriented, or whether an inversion between the top and the bottom and / or an inversion between the left-hand side and the right-hand side has occurred. For example, if the first pattern P1 of the second array M2 expects the binary code "1010", and the processor 16 determines the binary code "0101", this means that the image has its right and left sides inverted. For example, if the first pattern P1 of the third array M3 is expected to have the binary code "1010", and the processor 16 determines the binary code "0101", this means that the top and bottom of the image are inverted.

[0064] Based on the second pattern P2 of each group G, the processor 16 can determine which position of the array 12 the test signal corresponds to. For example, based on the determination of the identifier of the group G of the second array M2, the processor 16 can determine where along the column of the image it is located, and based on the determination of the identifier of the group G of the third array M3, the processor 16 can determine where along the row of the image it is located.

[0065] According to an embodiment, in a first configuration, the processor 16 may control the reading of the entire new image, or in a second configuration, may control the reading of only a portion of the new image. The second configuration may be advantageous, for example, when an area of ​​interest is determined by the processor 16 in the newly acquired image, in order to update the area of ​​interest with a higher frequency, or for example when the size of the array M1 is larger than the size of the required image, it is possible to select only a sub-portion of the image to acquire the required size. Furthermore, when the image sensor is arranged in a vehicle, the position of the sub-portion may depend on the precise orientation of the sensor in the vehicle and may be determined for each vehicle to compensate for errors in mechanical distribution. According to the first configuration, the reading of the newly acquired image may comprise the continuous reading of all pixel rows of the array 12, i.e., by sequentially reading the rows RT of the second array M2 and the third array M3. 1 to RT R , then read the row R of the first array M1 and the third array M31 to R M According to the second configuration, the reading of a portion of the acquired image may include the continuous reading of all rows RT of the second array M2 and the third array M3. 1 to RT R , then jump to the first row of the first array M1 and the third array M3 of the region of interest, and then continuously read the pixel rows of the first array M1 and the third array M3 from the first row of the first array M1 and the third array M3 of the region of interest until the last row of pixels of the first array M1 and the third array M3 of the region of interest. In addition, for the second array M2, all columns C can be read 1 to C N All output signals of the column CT of the third array M3 can be compared with the output signals of the column CT of the third array M3. 1 To CT Q Based on the second pattern P2 of each group G, the processor 16 can determine whether the reading effectively affects the region of interest of the image.

[0066] Advantageously, the size SIZE_G of each group is less than or equal to the minimum value of the area that can be read. Thus, the reading of the area of ​​interest allows the reading of more than SIZE_G consecutive pairs of test pixels of the third array M3, regardless of the position of the first row of the area of ​​interest. The processor 16 is configured to determine, among the read pairs of the array, at least one first pattern P1 and to reconstruct at least one complete second pattern P2 from which the position of the area of ​​interest can be determined.

[0067] According to one embodiment, if the processor 16 determines an error when assigning the value "0" or "1" to the test signal, the processor 16 determines that the row and / or column to which the test pixel delivering the test signal belongs is invalid. In addition, if the processor 16 determines an error during the verification of the fact that the values ​​of the test pixels of each pair of test pixels should be relative, the processor 16 determines that the row and / or column to which the test pixel pair delivering these test signals belongs is invalid. Advantageously, if the rows and / or columns are considered invalid, the processor 16 can determine the orientation of the image and / or its position in the array 12. According to one embodiment, if two or more rows or two or more columns of the image are considered invalid, the processor 16 can determine that it cannot guarantee that the orientation and position of the image are correct, and thus determine that the entire image must be considered corrupted.

[0068] According to an embodiment, if the processor 16 determines that the orientation of the image is incorrect based on the first pattern P1 and / or the second pattern based on the position of the image is not expected, the processor 16 may determine that the entire image must be considered corrupted.

[0069] The method continues at step 53A.

[0070] In step 53A, the processor 16 determines whether the alarm condition is satisfied after performing the verification in step 52A, and sends an alarm message when the alarm condition is satisfied. According to one embodiment, the processor 16 can send an alarm message if it is detected that the image is not correctly oriented, for example, if it is detected that it is left-right and / or up-down inverted. According to one embodiment, the alarm message can be sent regardless of whether it is detected that the readout and analog-to-digital conversion circuit 14 is not working correctly for the column. According to an embodiment, the alarm message can be sent if it is detected that the position of the reading area of ​​interest is incorrect. The method proceeds in step 54. According to one embodiment, the processor 16 can send an alarm message if it is detected that the row control signal is incorrect, in particular when the test pixel of the array M3 is invalid.

[0071] At step 54, the next row of array 12 to be selected is determined. The method returns to step 50.

[0072] At step 52B, the processor performs processing on the video signal. The processor may be performed after complete acquisition of the image of the region of interest, and / or along the acquisition of successive lines of the image of the region of interest. The processing may depend, among other things, on the application with the image sensor used herein. According to an embodiment, the processor 16 may perform processing operations intended to improve image quality (e.g., clarity of the image).

[0073] The method continues at step 53B where the processor 16 transmits the signal to the outside of the image sensor. For example, the processor 16 transmits the video signal after a processing operation for improving the image quality.

[0074] The method continues at step 54 .

[0075] Advantageously, step 52A may be implemented directly by processor 16 of image sensor 10. This enables accelerated image processing.

[0076] As a variant, steps 52A and 53A may be implemented by another processor 16 of the image sensor 10 , based on a test signal delivered by the processor 16 .

[0077] Figure 6 An embodiment of an image pixel Pix is ​​shown.

[0078] Each image pixel includes a photodiode 101, a storage node K formed by the cathode of the photodiode, a capacitive sensing node SN, a MOS transistor 103 or transfer transistor coupling the storage node K to the sensing node SN, a MOS transistor 105 or reset transistor coupling the sensing node SN to a node to which a high reset voltage VRT is applied, and a read circuit coupling the sensing node SN to the output rail 26. In this example, in each pixel Pix, the readout circuit of the pixel includes a MOS transistor 107 or amplifier transistor assembled as a source follower with its gate connected to the sensing node SN of the pixel, and a MOS transistor 109 or select transistor coupling the source of transistor 107 to the output rail 26 of the pixel. In the example shown, transistors 103, 105, 107 and 109 are N-channel transistors, and the drain of transistor 107 is coupled to a node to which a potential VRT is applied. In addition, in this example, the anode of the photodiode 101 is coupled to a node to which a low reference voltage GND is applied, which is lower than the voltage VRT, such as ground.

[0079] In addition, Figure 6 In the example, each row of pixels Pix has i Associated with: a node for controlling the application of a transfer transistor 103 of a pixel in a row; a node for controlling the application of a signal RST of a reset transistor 105 of a pixel in a row; and a node for controlling the application of a signal RD of a select transistor 109 of a pixel in a row. Node RD, node TG, row R i The node RST of the pixel Pix is ​​coupled to the row R i The selection rail 24 (not shown) is provided.

[0080] Figure 7 An embodiment of a test pixel Tst is shown. Each test pixel Tst includes a MOS transistor 123 or transfer transistor, coupling the node N1 of the test pixel to a sensing node N2, a MOS transistor 125 or reset transistor, coupling the sensing node N2 of the test pixel to a node for application of a reset potential (potential VRT in this example), and a readout circuit, coupling the sensing node N2 to an output rail 26 associated with the test pixel Tst. Node N1 is coupled to, preferably connected to, a high potential of a rail VL for providing a low potential. In Figure 7 In the example of FIG. 1 , the node N1 is shown connected to the high potential supply rail VH. For the test pixel Tst of the third array M3, the rails VH and VL are connected along the columns CT of the third array M3. p extend.

[0081] exist Figure 7In the example shown, each test pixel Tst is connected, via its readout circuit, to one and only one output rail 26 of the sensor, and different test pixels Tst are connected, via their readout circuits, to different output rails 26. In this example, in each test pixel Tst, the readout circuit of the test pixel comprises a MOS transistor 127 or amplifier transistor, assembled as a follower source, having a gate connected to the sensing node N2 of the pixel, and a MOS transistor 129 or select transistor, which couples the source of transistor 127 to the output rail 26 associated with the test pixel Tst. In the example shown, transistors 123, 125, 127 and 129 are N-channel transistors, and the drain of transistor 127 is coupled to the drain of the node to which the voltage VRT is applied. In this example, each test pixel Tst differs from the image pixel Pix of the sensor only in that, in the test pixel, there is no photodiode 101. In this example, the anode and cathode of the photodiode are mixed in the node N1.

[0082] According to an embodiment, when a value "1" is to be "stored" in the test pixel Tst, the node N1 of the test pixel Tst is coupled to, preferably connected to, the low potential supply rail VL, and when a value "0" is to be "stored" in the test pixel Tst, the node N1 of the test pixel Tst is coupled to, preferably connected to, the high potential rail VH. This advantageously enables, in accordance with the photodiode image pixel Pix, for which light capture generates reverse conduction of the photodiode and reduces the potential at the storage node K.

[0083] Various embodiments and variations have been described. Those skilled in the art will appreciate that certain features of these various embodiments and variations may be combined, and that those skilled in the art will recognize other variations. In particular, in the aforementioned embodiments, the "0" and "1" stored in each pixel Tst are constants. As a variation, each test pixel Tst may have a first controllable switch coupled to rail VH, and may be coupled to rail VL by a second controllable switch, the second switch being disconnected and opposite when the first switch is turned on. This enables the value stored in the test pixel Tst to be changed. As an example, the value stored in at least one particular test pixel Tst is reversed for each acquisition of a new image.

[0084] Finally, the described embodiments and variants are within the capabilities of a person skilled in the art based on the functional indications given above.

Claims

1. An electronic device, include: a first array of image pixels having an input coupled to a first selection rail and an output coupled to a first output rail; at least one second array of test pixels having an input coupled to a second selection rail and an output coupled to said first output rail; at least one third array of test pixels having an input coupled to said first selection rail and an output coupled to a second output rail; as well as a processor coupled to receive output signals on the first output rail and the second output rail; wherein each test pixel of the second array and the third array is configured to generate the output signal at one of only two possible voltage values ​​set by circuit connections of the test pixel in the absence of a select rail defect or an output rail defect; as well as Wherein the processor is configured to identify the presence of a select rail defect or an output rail defect in response to the output signal received from one or more of the test pixels, the output signal having the other of the two possible voltage values ​​set by the circuit connection.

2. The electronic device according to claim 1, wherein each image pixel include: at least one photodiode configured to generate an output voltage dependent on received light, and wherein each test pixel includes an input coupled by the circuit connection to receive one or the other of a first reference voltage and a second reference voltage, the first reference voltage corresponding to one of the two possible voltage values ​​and the second reference voltage corresponding to the other of the two possible voltage values.

3. The electronic device according to claim 1, further comprising: include: a row control circuit configured to control the first selection rail and the second selection rail; as well as analog processing and analog-to-digital conversion circuitry coupled to the first and second output rails; wherein the row control circuit is positioned adjacent to the first array and the at least one second array; wherein the analog processing and analog-to-digital conversion circuitry is positioned adjacent to the first array and the at least one second array; wherein said at least one second array is positioned adjacent to said first array on a side opposite to said analog processing and analog-to-digital conversion circuitry; Wherein the at least one third array is positioned adjacent to the first array on a side opposite to the row control circuit.

4. The electronic device of claim 1 , wherein the image pixels of the first array are configured to deliver a video signal when acquiring an image, wherein one or more of the at least one second array or the at least one third array comprises at least one component of a test pixel, the component comprising a first alignment portion of the test pixel configured to deliver an output signal, and The processor is configured to: receive the output signal of the first alignment portion and a video signal in sequence; determine whether the orientation of the image is correct from a portion of the output signal including at least a given number of the first alignment portion; and determine which position of the first array of image pixels corresponds to the video signal read using the output signal. 5 . The electronic device of claim 4 , wherein the given number of output signals corresponds to the length of a minimum region of interest of the image over which the processor is configured to apply a processing operation.

6. An electronic device according to claim 4, wherein even if the output signal of the portion is not at one of the two voltage values ​​set by the circuit connection of the test pixel, it is still determined by the processor whether the orientation of the acquired image is correct, and the processor still determines that the position of the first array of image pixels corresponds to the video signal read using the output signal of the portion.

7. An electronic device according to claim 4, wherein the processor is configured to determine, for each output signal, whether the output signal is at one of the two voltage values ​​set by the circuit connection of the test pixel, and if the output signal is not at one of the two voltage values ​​set by the circuit connection of the test pixel, indicate that the image pixel coupled to the same selection rail and / or the same first output rail as the test pixel is invalid.

8. An electronic device according to claim 4, wherein the test pixels of the first alignment portion are allocated in consecutive groups of test pixels, each group including a first set of test pixels and a second set of test pixels, wherein the first set of test pixels of each group is configured to deliver the same output signal, and wherein at least a portion of the second set of test pixels is configured to deliver the output signal at one of the two voltage values, and the voltage value varies from one group to another. 9 . The electronic device of claim 8 , wherein each first set of test pixels is configured to deliver a series of output signals alternating between a first value and a second value, the first value being different from the second value.

10. The electronic device of claim 8, wherein the second set of test pixels of each group is configured to deliver an output signal encoding a unique identifier of the group. 11 . The electronic device of claim 10 , wherein the test pixels of each second set are assigned to test pixel pairs configured to deliver the same voltage value.

12. An electronic device according to claim 4, wherein each component of the test pixel includes a second alignment portion of the test pixel adjacent to the first alignment portion of the test pixel, the first alignment portion and the second alignment portion are paired, and the test pixel or each pair of test pixels is configured to deliver different signal outputs among the two voltage values.

13. The electronic device according to claim 12, wherein the processor is configured to determine, for each pair of test pixels, whether the output signals delivered by the test pixels in the pair are different, and in the case where the output signals are not different, indicate that the image pixels coupled to the same selection rail and / or coupled to the same first output rail as the test pixels in the pair are invalid.

14. The electronic device according to claim 4, wherein the image pixels of the first array are arranged in rows and columns, the electronic device is configured to operate in a first configuration, in which all rows of the first array are continuously selected, and the electronic device is configured to operate in a second configuration, in which only a portion of the rows of the first array are continuously selected, and wherein the number of test pixels in each group of the first alignment portion is less than the number of rows of the portion.

15. The electronic device according to claim 1: wherein each test pixel comprises: a first MOS transistor having a drain coupled to an input node, a source coupled to a second node, and a gate coupled to one of the selection rails; a second MOS transistor having a drain coupled to a high reference voltage, a source coupled to the second node, and a gate coupled to a reset signal rail; a first follower coupled to the second node and configured to replicate the voltage on the second node towards the output of the first follower, and a third transistor having a drain coupled to the output of a second follower, a source coupled to a readout output, and a gate coupled to a readout signal rail; and wherein each image pixel comprises: a photodiode; a fourth MOS transistor having a drain coupled to the anode or cathode of the photodiode, a source coupled to a third node, and a gate coupled to one of the selection rails; a fifth MOS transistor having a drain coupled to the high reference voltage, a source coupled to the third node, and a gate coupled to a reset signal rail; a second follower coupled to the third node and configured to replicate the voltage on the third node towards the output of the second follower; and a sixth transistor having a drain coupled to the output of the second follower, a source coupled to a readout output, and a gate coupled to a readout signal rail.

16. The electronic device according to claim 15, wherein the circuit connection connects the input node at the drain of the first MOS transistor to a first reference voltage node to set the first voltage value of the two possible voltage values, or connects to a second reference voltage node to set the second voltage value of the two possible voltage values.

17. An electronic device, comprising: an image pixel array having an input coupled to a first selection rail and an output coupled to a first output rail; a test pixel array having an input coupled to a second selection rail and an output coupled to the first output rail; and a processor coupled to receive an output signal on the first output rail; wherein each test pixel of the test pixel array is configured to generate the output signal at one of only two possible voltage values ​​set by circuit connections of the test pixel in the absence of a select rail defect or an output rail defect; as well as Wherein the processor is configured to identify the presence of a select rail defect or an output rail defect in response to an output signal received from one or more of the test pixels, the output signal having the other of the two possible voltage values ​​set by the circuit connection.

18. The electronic device of claim 17, wherein each image pixel include: at least one photodiode configured to generate an output voltage dependent on received light, and wherein each test pixel includes an input coupled by the circuit connection to receive one or the other of a first reference voltage and a second reference voltage, the first reference voltage corresponding to one of the two possible voltage values ​​and the second reference voltage corresponding to the other of the two possible voltage values.

19. The electronic device according to claim 17, wherein each test pixel include: a first MOS transistor having a drain coupled to the input node, a source coupled to the second node, and a gate coupled to one of the selection rails, and a second MOS transistor having a drain coupled to a high reference voltage, a source coupled to the second node, and a gate coupled to a reset signal rail; a first follower coupled to the second node and configured to replicate a voltage at the second node toward an output of the first follower; and a third transistor having: a drain coupled to the output of the second follower, a source coupled to the read output, and a gate coupled to the readout signal rail; as well as Each image pixel includes: a photodiode; a fourth MOS transistor having: a drain coupled to the anode or cathode of the photodiode, a source coupled to a third node, and a gate coupled to one of the selection rails, a fifth MOS transistor having: a drain coupled to the high reference voltage, a source coupled to the third node, and a gate coupled to the reset signal rail; a second follower coupled to the third node and configured to replicate a voltage at the third node toward an output of the second follower; and a sixth transistor having: a drain coupled to the output of the second follower, a source coupled to a read output, and a gate coupled to a readout signal rail.

20. An electronic device according to claim 19, wherein the circuit connection connects the input node at the drain of the first MOS transistor to a first reference voltage node to set a first voltage value among the two possible voltage values, or to a second reference voltage node to set a second voltage value among the two possible voltage values.

21. An electronic device, include: an image pixel array having an input coupled to a first selection rail and an output coupled to a first output rail; A test pixel array having an input coupled to the first select rail and an output coupled to a second output rail; And A processor coupled to receive output signals on the first output rail and the second output rail; Wherein each test pixel of the test pixel array is configured to generate the output signal at one of only two possible voltage values set by the circuit connection of the test pixel in the absence of a select rail defect or an output rail defect; And Wherein the processor is configured to identify the presence of the select rail defect or the output rail defect in response to the output signals received from one or more of the test pixels, the test pixel having a voltage value different from the one of the two possible voltage values set by the circuit connection.

22. The electronic device according to claim 21, wherein each image pixel Comprises: At least one photodiode configured to generate an output voltage depending on the received light, and wherein each test pixel includes an input coupled by the circuit connection to receive one of a first reference voltage and a second reference voltage or the other reference voltage, the first reference voltage corresponding to one of the two possible voltage values and the second reference voltage corresponding to the other of the two possible voltage values.

23. The electronic device according to claim 21: Wherein each test pixel Comprises: A first MOS transistor having a drain coupled to an input node, a source coupled to a second node, and a gate coupled to one of the select rails; A second MOS transistor having a drain coupled to a high reference voltage, a source coupled to the second node source, and a gate coupled to a reset signal rail; A first follower coupled to the second node and configured to replicate the voltage on the second node towards the output of the first follower; And a third transistor having a drain coupled to the output of a second follower, a source coupled to a readout output, and a gate coupled to a readout signal rail; And Wherein each image pixel includes: a photodiode; a fourth MOS transistor having a drain coupled to the anode or cathode of the photodiode, a source coupled to a third node, and a gate coupled to one of the select rails, a fifth MOS transistor having a drain coupled to the high reference voltage, a source coupled to the third node, and a gate coupled to a reset signal rail; a second follower coupled to the third node and configured to replicate the voltage on the third node towards the output of the second follower; and a sixth transistor having a drain coupled to the output of the second follower, a source coupled to a readout output, and a gate coupled to a readout signal rail.

24. An electronic device according to claim 23, wherein the circuit connection connects the input node at the drain of the first MOS transistor to a first reference voltage node to set a first voltage value among the two possible voltage values, or to a second reference voltage node to set a second voltage value among the two possible voltage values.

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