Non-volatile memory device, memory system, and programming method

Abstract

The embodiments of the present disclosure provide a non-volatile memory device, a memory system and a programming method, the non-volatile memory device comprises a plurality of pages, each of the pages comprises a plurality of single-level memory cells, the programming method comprises: performing a programming operation on a first page of the plurality of pages using a signal comprising a first programming pulse, a program verify pulse and a second programming pulse, wherein the first programming pulse is a starting programming pulse and a second signal value of the second programming pulse is greater than a first signal value of the first programming pulse, the program verify pulse is used to obtain a failed bit number of the first page after the first programming pulse and before the second programming pulse is applied; and performing a programming operation on a second page of the plurality of pages using only a third programming pulse, wherein a third signal value of the third programming pulse is determined based on at least the first signal value and the failed bit number.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a non-volatile memory device, a memory system, and a programming method. Background Technology

[0002] NAND flash memory, characterized by its non-volatility, fast read / write speeds, low power consumption, and long lifespan, is widely used in various electronic products such as mobile phones, computers, smart sensors, and positioning devices. As consumers demand higher performance and reliability from electronic products, the market is placing higher demands on the read / write speeds and lifespan of NAND flash memory. NAND flash memory involves three basic operations: erasing, writing (also known as programming), and reading. Current NAND flash memory programming methods either involve excessively long programming times, resulting in slow write speeds, or over-programming, leading to shorter lifespans. These programming methods are unsatisfactory and fail to meet the market's overall performance requirements for NAND flash memory. Summary of the Invention

[0003] In view of this, embodiments of the present disclosure provide a non-volatile memory device, a memory system, and a programming method.

[0004] According to a first aspect of this disclosure, a programming method for a non-volatile memory device is provided, the non-volatile memory device comprising a plurality of pages, each page comprising a plurality of single-level memory cells, the programming method comprising:

[0005] The first page of the plurality of pages is programmed using a signal including a first programming pulse, a programming verification pulse, and a second programming pulse, wherein the first programming pulse is a start programming pulse and the second signal value of the second programming pulse is greater than the first signal value of the first programming pulse, and the programming verification pulse is used to obtain the number of failure bits of the first page after the first programming pulse and before the second programming pulse is applied; and

[0006] The second page of the plurality of pages is programmed using only a third programming pulse, wherein the third signal value of the third programming pulse is determined based at least on the first signal value and the number of failure bits.

[0007] According to a second aspect of this disclosure, a non-volatile memory device is provided, comprising:

[0008] A memory cell array comprising multiple pages, each page comprising multiple single-level memory cells;

[0009] Peripheral circuitry coupled to the memory cell array, the peripheral circuitry being configured as follows:

[0010] The first page of the plurality of pages is programmed using a signal including a first programming pulse, a programming verification pulse, and a second programming pulse, wherein the first programming pulse is a start programming pulse and the second signal value of the second programming pulse is greater than the first signal value of the first programming pulse, and the programming verification pulse is used to obtain the number of failure bits of the first page after the first programming pulse and before the second programming pulse is applied; and

[0011] The second page of the plurality of pages is programmed using only a third programming pulse, wherein the third signal value of the third programming pulse is determined based at least on the first signal value and the number of failure bits.

[0012] According to a third aspect of this disclosure, a memory system is provided, comprising:

[0013] One or more non-volatile memory devices as provided in the second aspect of this disclosure;

[0014] A memory controller, coupled to the non-volatile memory device and configured to control the non-volatile memory device. Attached Figure Description

[0015] Figure 1 This is a block diagram of an exemplary system with memory provided in an embodiment of this disclosure;

[0016] Figure 2A and 2B A block diagram of a memory system provided in an embodiment of this disclosure;

[0017] Figure 3 A schematic circuit diagram of a memory including peripheral circuitry provided for embodiments of this disclosure;

[0018] Figure 4 A schematic diagram of the peripheral circuit provided in the embodiments of this disclosure;

[0019] Figure 5 A graph showing the threshold voltage tolerance distribution of pages with different erase / write cycles obtained using DSLC programming.

[0020] Figure 6 A schematic flowchart illustrating a programming method for a non-volatile memory device provided in an embodiment of this disclosure;

[0021] Figure 7 A flowchart illustrating a programming method for a memory system provided in an embodiment of this disclosure;

[0022] Figure 8 Threshold voltage distribution diagram of the test page memory cell provided in the embodiments of this disclosure;

[0023] Figure 9 This disclosure provides a first correspondence between a programming pulse compensation value and the number of failure bits in an embodiment.

[0024] Figure 10 A graph showing the relationship between the position of a page and the characteristic signal value of a page is provided in an embodiment of this disclosure;

[0025] Figure 11 This is a schematic diagram illustrating a programming process for a block to be programmed, provided as an embodiment of this disclosure.

[0026] Figure 12 Threshold voltage distribution diagram of memory cells in two pages within block 234 provided in this embodiment of the disclosure;

[0027] Figure 13 Threshold voltage distribution diagram of memory cells in two pages within block 80 provided in this embodiment of the disclosure;

[0028] Figure 14 To adopt the DSLC method and Figure 5 The diagram shows the threshold voltage distribution of memory cells in a page after 100 erase / write cycles performed on the page using the programming method shown.

[0029] Figure 15 The cumulative distribution of the erase state threshold voltage and tolerance between specific voltages for pages of blocks 234 and 236;

[0030] Figure 16 This is a schematic flowchart illustrating a method for fabricating a memory system according to an embodiment of the present disclosure. Detailed Implementation

[0031] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and specific embodiments. In the description of this disclosure, it should be understood that the terms "length," "width," "depth," "upper," "lower," "outer," etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0032] Figure 1 This is a block diagram of an exemplary system with memory provided in embodiments of this disclosure. System 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 1As shown, system 100 may include a host 108 and a memory system 102, the memory system 102 having one or more memories 104 and a memory controller 106. The host 108 may be a processor (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). The host 108 may be configured to send data to or receive data from the memory 104.

[0033] Memory 104 can be any memory disclosed herein, such as a non-volatile memory device. A non-volatile memory device can be a NAND flash memory (e.g., a three-dimensional (3D) NAND flash memory).

[0034] In some embodiments, memory controller 106 is coupled to memory 104 and host 108 and is configured to control memory 104. Memory controller 106 can manage data stored in memory 104 and communicate with host 108. In some embodiments, memory controller 106 is configured to perform programming methods provided in embodiments of this disclosure to control memory 104.

[0035] In some embodiments, the memory controller 106 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal calculators, digital cameras, mobile phones, etc.

[0036] In some embodiments, the memory controller 106 is designed to operate in a high duty cycle environment within an SSD or embedded multimedia card (eMMC), which serves as data storage for mobile devices such as smartphones, tablets, laptops, etc., as well as enterprise storage arrays. The memory controller 106 can be configured to control the operation of the memory 104, such as read, erase, and program operations.

[0037] The memory controller 106 can also be configured to manage various functions related to data stored or to be stored in the memory 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc.

[0038] In some embodiments, the memory controller 106 is also configured to process error correction codes (ECC) regarding data read from or written to the memory 104. The memory controller 106 may also perform any other suitable functions, such as formatting the memory 104. The memory controller 106 may communicate with external devices (e.g., host 108) according to a specific communication protocol. For example, the memory controller 106 may communicate with external devices via at least one of a variety of interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronic Devices (IDE), Firewire, etc.

[0039] The memory controller 106 and one or more memories 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of end electronic products.

[0040] In such Figure 2A In one embodiment shown, the memory controller 106 and a single memory 104 may be integrated into the memory card 202. The memory card 202 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 may also include a connection between the memory card 202 and a host computer (e.g., Figure 1 The memory card connector 204 is coupled to the host 108.

[0041] In such Figure 2B In another embodiment shown, the memory controller 106 and a plurality of memories 104 may be integrated into the SSD 206. The SSD 206 may also include a connection between the SSD 206 and a host (e.g., Figure 1 The SSD connector 208 is coupled to the host 108 in the host. In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0042] Figure 3 A schematic circuit diagram of a memory 300 including peripheral circuitry provided for embodiments of this disclosure. The memory 300 may be... Figure 1An example of memory 104 is shown. Memory 300 may include a memory cell array 301 and peripheral circuitry 302 coupled to the memory cell array 301. The memory cell array 301 may be a NAND flash memory cell array, wherein memory cells 306 are provided in the form of an array of NAND memory strings 308, each NAND memory string 308 extending vertically above a substrate (not shown).

[0043] In some embodiments, the peripheral circuitry 302 is configured to execute the programming methods provided in the embodiments of this disclosure. It is understood that the peripheral circuitry 302 may be configured to execute the programming methods provided in the embodiments of this disclosure according to instructions received from the memory controller 106.

[0044] In some embodiments, each NAND memory string 308 includes a plurality of memory cells 306 that are series-coupled and vertically stacked. Each memory cell 306 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the memory cell 306. Each memory cell 306 may be a floating-gate type memory cell that includes a floating-gate transistor, or a charge-trapping type memory cell that includes a charge-trapping transistor.

[0045] In some embodiments, each memory cell 306 is a single-level memory cell (SLC) having two possible memory states and thus capable of storing one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. Figure 3 As shown, each NAND memory string 308 may include a source select gate (SSG) 310 at its source end and a drain select gate (DSG) 312 at its drain end. The SSG 310 and DSG 312 may be configured to activate the selected NAND memory string 308 (column of the array) during read and program operations.

[0046] In some embodiments, the sources of NAND memory strings 308 in the same block 304 are coupled through the same source line (SL) 314 (e.g., common SL). In other words, according to some embodiments, all NAND memory strings 308 in the same block 304 have an array common source (ACS). According to some embodiments, the DSG 312 of each NAND memory string 308 is coupled to a corresponding bit line 316, and data can be read from or written to the bit line 316 via an output bus (not shown).

[0047] In some embodiments, each NAND memory string 308 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having DSG 312) or a deselection voltage (e.g., 0V) to the corresponding DSG 312 via one or more DSG lines 313 and / or by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having SSG 310) or a deselection voltage (e.g., 0V) to the corresponding SSG 310 via one or more SSG lines 315.

[0048] like Figure 3 As shown, the NAND memory string 308 can be organized into multiple blocks 304, each of which may have a common source line 314 (e.g., coupled to ground). In some embodiments, each block 304 is a basic data unit for an erase operation, i.e., all memory cells 306 on the same block 304 are erased simultaneously. To erase memory cells 306 in a selected block, a source line 314 biased to the selected block and unselected blocks on the same plane as the selected block can be used. It should be understood that in some examples, the erase operation can be performed at the half-block level, at the quarter-block level, or at any suitable number of blocks or any suitable fraction of blocks.

[0049] Memory cells 306 of adjacent NAND memory strings 308 can be coupled via word lines 318, which select which row of memory cells 306 is affected by read and program operations. In some embodiments, each word line 318 is coupled to a page 320 of memory cells 306, which is a basic unit of data used for programming operations. The size of a page 320, in bits, can be related to the number of NAND memory strings 308 coupled by word lines 318 in a block 304. Each word line 318 may include multiple control gates (gate electrodes) at each memory cell 306 in the corresponding page 320, as well as gate lines coupling the control gates.

[0050] Peripheral circuitry 302 can be coupled to memory cell array 301 via bit line 316, word line 318, source line 314, SSG line 315, and DSG line 313. Peripheral circuitry 302 can include any suitable analog, digital, and mixed-signal circuitry to facilitate operation of memory cell array 301 by applying voltage and / or current signals to each target memory cell 306 via bit line 316, word line 318, source line 314, SSG line 315, and DSG line 313, and by sensing voltage and / or current signals from each target memory cell 306. Peripheral circuitry 302 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 4 This is a schematic diagram of the peripheral circuitry provided in an embodiment of the present disclosure. The peripheral circuitry 302 includes a page buffer / sensor amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, a control logic unit 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, it may also include... Figure 4 Additional peripheral circuitry not shown.

[0051] Page buffer / sensor amplifier 504 can be configured to read data from memory cell array 301 and program (write) data to memory cell array 301 according to control signals from control logic unit 512. In one example, page buffer / sensor amplifier 504 can store a page of programming data (write data) to be programmed into a page 320 of memory cell array 301. In another example, page buffer / sensor amplifier 504 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 306 coupled to selected word line 318. In yet another example, page buffer / sensor amplifier 504 can also sense a low-power signal from bit line 316 representing a data bit stored in memory cell 306 and amplify a small voltage swing to a recognizable logic level during read operations. Column decoder / bit line driver 506 can be configured to be controlled by control logic unit 512 and select one or more NAND memory strings 308 by applying a bit line voltage generated from voltage generator 510.

[0052] The row decoder / word line driver 508 can be configured to be controlled by the control logic unit 512 and to select / deselect block 304 of the memory cell array 301 and select / deselect word line 318 of block 304. The row decoder / word line driver 508 can also be configured to drive word line 318 using word line voltages generated from the voltage generator 510. In some embodiments, the row decoder / word line driver 508 can also select / deselect and drive SSG line 315 and DSG line 313. As described in detail below, the row decoder / word line driver 508 is configured to perform an erase operation on memory cell 306 coupled to one or more selected word lines 318. The voltage generator 510 can be configured to be controlled by the control logic unit 512 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 301.

[0053] Control logic unit 512 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. Register 514 can be coupled to control logic unit 512 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Interface 516 can be coupled to control logic unit 512 and acts as a control buffer to buffer control commands received from a host (not shown) and relay them to control logic unit 512, as well as to buffer status information received from control logic unit 512 and relay it to the host. Interface 516 can also be coupled to column decoder / bitline driver 506 via data bus 518 and acts as a data I / O interface and data buffer to buffer data and relay it to or from memory cell array 301.

[0054] In NAND flash memory, single-level cells (SLCs) occupy a certain share of the memory market due to their advantages such as fast read / write speeds, high reliability, and long lifespan.

[0055] Typically, incremental step-pulse programming (ISPP) is used to perform write operations on NAND flash memory. For NAND flash memory, write operations are performed on a page-by-page basis, with each page consisting of multiple arrayed memory cells.

[0056] Specifically, at the start of programming, a first programming pulse is applied to the selected page in memory. Then, programming verification is performed on that page to check if the threshold voltage of each memory cell in the page reaches the target threshold voltage. If the number of memory cells not written to the target threshold voltage exceeds the allowable range, a second programming pulse with a higher voltage is applied, and programming verification is performed again after the second programming pulse. This process of applying programming pulses and performing programming verification is repeated until the number of memory cells not written to the target threshold voltage is within the allowable range, at which point the programming of the entire page is complete.

[0057] To facilitate the evaluation of the number of memory cells in a page that have not been written to the target threshold voltage after a programming pulse is applied, the failed bit count (FBC) is introduced. The failed bit count refers to the number of bits in the page that have not been written to the target threshold voltage. In practical applications, during programming verification, the relationship between the failed bit count and the target failed bit count can be used to determine whether programming has succeeded.

[0058] For example, if the number of failure bits for a page is greater than the target number of failure bits (i.e., the number of failure bits for a page is not within the allowable range of the target number of failure bits), a new programming pulse with a higher voltage is applied, and programming verification is performed again after applying this new programming pulse. This process of applying programming pulses and performing verification is repeated until the number of failure bits for a page is less than or equal to the target number of failure bits (i.e., the number of failure bits for a page is within the allowable range of the target number of failure bits), at which point the programming of the entire page is complete.

[0059] In some embodiments, a maximum number of programming pulses can be set. When the number of programming pulses applied is less than this maximum number, the process of applying programming pulses and performing verification can be repeated until the number of failure bits is less than or equal to the target number of failure bits. When the number of programming pulses applied is equal to the maximum number, and the number of failure bits is still greater than the target number of failure bits, programming of the page can be stopped, and the programming of the page is considered to have failed.

[0060] It should be noted that the target threshold voltage is used to determine whether a memory cell has reached the programming state. Specifically, when the threshold voltage of a memory cell is greater than or equal to the target threshold voltage, the memory cell has reached the programming state. When the threshold voltage of a memory cell is less than the target threshold voltage, the memory cell has not reached the programming state.

[0061] Taking a single-level memory cell (SLC) as an example, a single-level memory cell can store 1 bit of data, including a programmed state and an erased state. The programmed state can be represented by "1", and the erased state by "0". Alternatively, the programmed state can be represented by "0", and the erased state by "1". For example, the erased state "1" corresponds to a first voltage range, and the programmed state "0" corresponds to a second voltage range. A write operation is performed by applying a programming pulse to the memory cell to raise its threshold voltage from the first voltage range corresponding to the erased state to the second voltage range corresponding to the programmed state.

[0062] As mentioned above, the programming method requires multiple programming pulses, and after each programming pulse, a verification voltage needs to be applied to check the programming result of the page. Therefore, the programming time (Tprog) is relatively long.

[0063] In the PCIe 3.0 era, to shorten programming time, the Dynamic Single-Level Cell (DSLC) mode evolved. In DSLC mode, a large programming pulse is applied to a page, causing the page to be written to the programming state in one go. Here, writing a page to the programming state means making the number of failure bits of the page less than or equal to the target number of failure bits. This DSLC programming mode can shorten programming time.

[0064] However, DSLC mode can cause the threshold voltage of the memory cell in the page to be much higher than the target threshold voltage (also known as overprogramming). With increasing write cycles, overprogramming causes the threshold voltage of the programmed state of the memory cell to shift, and the erase state to degrade, reducing the reliability of the NAND flash memory. Furthermore, overprogramming also reduces the durability of the memory cell, thus reducing the overall lifespan of the NAND flash memory. In NAND flash memory, the lifespan is generally characterized by the number of write cycles (P / E cycling). Using DSLC programming, the write cycle lifespan of NAND memory is approximately 3,000 (3k) cycles.

[0065] Figure 5 This is a distribution of threshold voltage tolerances for pages with different erase / write cycles obtained using DSLC programming. Figure 5 In the graph, the horizontal axis represents the number of erase / write cycles, and the vertical axis represents the threshold voltage margin (E1 margin) for programmed mode (E1). "Number" refers to the number of pages, and "Median" refers to the median of the threshold voltage margins for programmed mode across multiple pages. For example... Figure 5As shown, as the number of erase / write cycles increases from the initial number (init, for example, 0) to 100k, the median threshold voltage tolerance of the programmed state gradually increases. In particular, when the number of erase / write cycles increases to 100k, the median threshold voltage tolerance of the programmed state of the page increases by 410mV compared to the median threshold voltage tolerance of the programmed state of the un-erased page (the page with the initial number of erase / write cycles).

[0066] according to Figure 5 Analysis shows that when the same programming pulse is applied to pages in the erase state at different erase cycles, the changes in the threshold voltage of the memory cells differ. Furthermore, the increase in the threshold voltage of the memory cells gradually increases with the number of erase cycles. In other words, with the increase in the number of erase cycles, the degree of over-programming of the pages gradually increases, exacerbating the shortening of the memory's lifespan.

[0067] To address the issues of short memory lifespan and low reliability caused by over-programming in the DSLC mode, a High Program Erase Single-Level Cell (HPE SLC) mode is proposed. When programming in HPE SLC mode, two programming pulses are applied sequentially to a page. The first programming pulse has a lower signal value, preventing the page from being programmed; then, a second programming pulse with a higher signal value is applied to program the page.

[0068] Compared to DSLC mode, while HPE SLC mode can reduce over-programming and improve the durability of memory cells, enabling NAND flash memory to achieve 100k or 120k erase / write cycles, the application of two programming pulses to each page in HPE SLC mode increases programming time. Furthermore, as the number of erase / write cycles increases, the programming speed becomes increasingly faster. After tens of thousands of erase / write cycles, often only one programming pulse is needed to program the page. However, HPE SLC mode, by applying two programming pulses to each page, leads to over-programming after tens of thousands of erase / write cycles. This causes the threshold voltage of the memory cells in the page to shift in the programming state, degrades the erase state, and consequently reduces memory reliability and shortens its lifespan.

[0069] It is evident that neither ISPP, DSLC, nor HPE SLC programming methods can enable memory to possess the comprehensive advantages of fast read / write speeds, long lifespan, and high reliability.

[0070] In view of this, the present disclosure proposes a programming method for a non-volatile memory device. Figure 6A programming method for a non-volatile memory device is provided in this disclosure embodiment. The non-volatile memory device includes at least one block, the block includes multiple pages, and each page includes a single-level memory cell. The programming method for the non-volatile memory device includes:

[0071] S110: The first page of a plurality of pages is programmed using a signal including a first programming pulse, a programming verification pulse, and a second programming pulse, wherein the first programming pulse is a start programming pulse and the second signal value of the second programming pulse is greater than the first signal value of the first programming pulse, and the programming verification pulse is used to obtain the number of failure bits of the first page after the first programming pulse and before the second programming pulse is applied.

[0072] S120: The second page of multiple pages is programmed using only the third programming pulse, wherein the third signal value of the third programming pulse is determined based at least on the first signal value and the number of failure bits.

[0073] Here, the first page can be any page in the block. In some embodiments, the multiple pages included in the block can be stacked sequentially, and the first page can be the bottom page of the block, or the first page can be the top page of the block.

[0074] The second page consists of all pages in the block except the first page. The number of second pages is greater than or equal to 2. For example, the block contains 128 pages, with one first page and 127 second pages.

[0075] Here, the first programming pulse, the second programming pulse, and the third programming pulse can be either a voltage pulse signal or a current pulse signal. Correspondingly, the first signal value, the second signal value, and the third signal value can be either a voltage value or a current value.

[0076] Here, the first programming pulse is the initial programming pulse. For example, the initial programming pulse can be the first programming pulse applied to the block after it has been erased. It is understood that when programming the block, the initial programming pulse is first applied to the first page. The second programming pulse is the second programming pulse applied to the first page. In some embodiments, the second signal value of the second programming pulse is greater than the first signal value of the first programming pulse. After the second programming pulse is applied to the first page, the first page is written to the programming state, and there is no over-programming.

[0077] The third programming pulse is the only programming pulse applied to the second page after the block has been erased and before the next erase of that block. After the third programming pulse is applied to the second page, the second page is written to the programming state, and there is no over-programming.

[0078] In some embodiments, the signal value of the programming verification pulse may be equal to the target threshold voltage of a single-level memory cell to verify whether each single-level memory cell in the first page has been written to the target threshold voltage.

[0079] like Figure 5 As shown, in DSLC mode, when the same programming pulse value is applied to pages with different erase / write cycles, causing all pages to be written to the programming state, pages with more erase / write cycles will be over-programmed. Based on this, this disclosure proposes: adaptively adjusting the signal value of the programming pulse applied to the page according to the page's erase / write cycle to reduce the probability of over-programming as the page's erase / write cycle increases.

[0080] This disclosure reveals that the number of failure bits per page is related to the signal value of the programming pulse applied to the page, and that after applying the same signal value of a programming pulse to different pages in the erase state, the number of failure bits per page varies with the number of erase cycles. In some embodiments, the number of failure bits per page gradually decreases as the number of erase cycles increases.

[0081] Based on this, this disclosure proposes to first apply a first programming pulse to the first page and obtain the number of failure bits of the first page. Then, the first signal value is adjusted according to the number of failure bits of the first page to obtain a second signal value. Here, the second signal value enables the first page to be programmed into a programmed state without over-programming.

[0082] It is understood that the second signal value is related to the number of failure bits of the first page, and the number of failure bits of the first page is related to the number of erase / write cycles of the first page. Therefore, the second signal value is related to the number of erase / write cycles of the first page. The programming method provided in this disclosure adaptively adjusts the second signal value according to the number of erase / write cycles of the first page, so that the second programming pulse applied to the first page can enable the first page to be programmed into a programming state, and reduces the probability of overprogramming.

[0083] It's also understandable that when NAND flash memory is erased in blocks, each page within the same block is erased the same number of times. Therefore, after applying a first programming pulse to the first page of the block, obtaining the number of failure bits, and determining the second signal value, only one programming pulse (i.e., a third programming pulse) needs to be applied to the second page of the same block (i.e., all other pages besides the first page). The third signal value of the third programming pulse must equal the second signal value for the second page to be programmed.

[0084] As can be seen from the above analysis, compared to applying at least two programming pulses to each page in the block, the programming method provided in this embodiment is applied to programming a single-level memory cell. Since more than one programming pulse is required for the first page, and only one programming pulse is required for the other pages in the block (i.e., the second page), the number of programming pulses applied is reduced. Therefore, the programming time can be shortened and the write speed can be improved.

[0085] Furthermore, the programming method provided in this disclosure adaptively adjusts the value of the programming pulse signal applied to the page based on the number of page erase / write cycles. This reduces the probability of over-programming while ensuring the page is programmed into the programming state, achieving dynamic and refined programming. It also reduces threshold voltage shifts in the programming state and erase state degradation of memory cells within the page, thereby improving memory reliability and extending memory lifespan. In summary, the programming method provided in this disclosure enables non-volatile memory devices using this method to possess excellent overall performance, including high read / write speeds, long lifespan, and high reliability.

[0086] In some embodiments, the third signal value of the third programming pulse is equal to the sum of the first signal value and the first compensation value;

[0087] The first compensation value is the difference between the first target programming pulse signal value and the first signal value on the first page, and the second target programming pulse signal value on the second page is equal to the first target programming pulse signal value. The first compensation value is obtained based on the number of failure bits on the first page.

[0088] Here, the first target programming pulse signal value is the signal value of the programming pulse that makes the number of failure bits of the first page equal to the target number of failure bits. In other words, it is the signal value of the first page being written to the programming state and there is no over-programming.

[0089] The second target programming pulse signal value is the signal value of the programming pulse that makes the number of failure bits of the second page equal to the target number of failure bits; that is, the signal value that indicates the second page is programmed into the programming state and there is no overprogramming. The second target programming pulse signal value may be equal to, greater than, or less than the first target programming pulse signal value. For example, if the characteristics of the memory cells between layers in a block are small, then the second target programming pulse signal values ​​of multiple second pages may be equal and equal to the first target programming pulse signal value. As another example, if the characteristics of the memory cells between layers in a block are large, then the target programming pulse signal values ​​of the first page and multiple second pages in the block may not be exactly the same.

[0090] In this embodiment, the second target programming pulse signal value is equal to the first programming pulse signal value. This equality allows for measurement error between the two values.

[0091] This embodiment provides a method for adjusting a first signal value based on the number of failure bits on the first page. Specifically, the first signal value is set to be less than the first target programming pulse signal value, and a first compensation value is determined based on the number of failure bits on the first page. A third signal value is obtained by summing the first signal value and the first compensation value.

[0092] It is understandable that the first programming pulse using the first signal value did not put the first page into the programming state, but the sum of the first signal value and the first compensation value equals the first target programming pulse signal value. Therefore, using a programming pulse with the sum of the first signal value and the first compensation value can put the first page into the programming state. Since the second target programming pulse signal value of the second page equals the first target programming pulse signal value, when the third signal value equals the sum of the first signal value and the first compensation value, the third programming pulse can put the second page into the programming state. Based on this, this embodiment can program the second page using only the third programming pulse, without repeating the programming steps of the first page on the second page, thus avoiding an increase in programming time.

[0093] In some embodiments, when the second target programming pulse signal value is less than the first target programming pulse signal value, if the third signal value is equal to the sum of the first signal value and the first compensation value, then the third programming pulse can also write the second page to the programming state, but there may be a certain degree of overprogramming. In some embodiments, the second target programming pulse signal value is greater than the first target programming pulse signal value. If the third signal value is equal to the first signal value and the first compensation value, then the third programming pulse may not be able to prevent the second page from being written to the programming state. Therefore, when determining the third signal value of the third programming pulse applied to the second page, it is also necessary to consider the positional relationship of other pages relative to the first page, so that the second page is written to the programming state without overprogramming.

[0094] In some embodiments, the third signal value of the third programming pulse is determined based on the first signal value, the number of failure bits, and the positional relationship of the second page relative to the first page.

[0095] For example, the third signal value of the third programming pulse is equal to the sum of the first signal value, the first compensation value, and the second compensation value; wherein the first compensation value is obtained based on the number of failure bits, and the second compensation value is obtained based on the positional relationship of the second page relative to the first page.

[0096] In this embodiment, the first compensation value is related to the number of failure bits, while the number of failure bits of the first page under the first programming pulse is related to the number of erase / write cycles of the block, i.e., the first compensation value is related to the number of erase / write cycles of the block; the second compensation value is related to the position of the second page in the block. In other words, the programming method provided in this embodiment adaptively adjusts the magnitude of the programming pulse signal applied to the page based on the number of erase / write cycles and the page's position in the block, so that the programming pulse applied to the page is sufficient to bring the page to the programming state while reducing the probability of over-programming, achieving dynamic and fine-grained programming.

[0097] In some embodiments, the first compensation value is obtained based on the number of failure bits of the first page and a first correspondence;

[0098] The first correspondence includes multiple fitting functions for programming pulse signal values ​​and failure bit counts, with the multiple fitting functions being different and applied to pages with different erase / write cycles; or, the first correspondence includes a single fitting function for programming pulse signal values ​​and failure bit counts, with the fitting function applicable to pages with different erase / write cycles.

[0099] In some embodiments, the second compensation value is obtained based on the position of the second page and the second correspondence;

[0100] The second correspondence is used to indicate the relationship between the second compensation value and the position of the second page.

[0101] Here, the steps of determining the first compensation value based on the first correspondence and determining the second compensation value based on the second correspondence can be performed by the memory controller. Therefore, this disclosure is detailed in the programming method of the memory system below.

[0102] In some embodiments, prior to step S110, the programming method further includes:

[0103] Obtain the first signal value of the first programming pulse applied to the first page.

[0104] In some embodiments, prior to step S120, the programming method further includes:

[0105] Obtain the third signal value of the third programming pulse applied to the second page.

[0106] In some embodiments, after step S120, the programming method further includes:

[0107] Programmatically validate the second page.

[0108] For example, programmatic validation for the second page includes:

[0109] Apply a programming verification pulse to the second page to obtain the number of failure bits on the second page;

[0110] Compare the number of failure bits on the second page with the target number of failure bits.

[0111] The verification passes when the number of failure bits on the second page is less than or equal to the target number of failure bits.

[0112] In this embodiment of the disclosure, by verifying the programming of the second page, the programming result of the second page can be confirmed, and the failure of programming the second page can be detected in a timely manner so that corresponding remedial measures can be taken.

[0113] This disclosure also provides a method for programming a memory system, the memory system including a memory controller and a non-volatile memory device. The non-volatile memory device is as described above, and the memory controller is configured to control the non-volatile memory device. The programming method for the memory system is as follows: Figure 7 As shown, it includes the following steps:

[0114] S210: The first page is programmed sequentially using a first programming pulse, a programming verification pulse, and a second programming pulse; wherein, the first programming pulse is the starting programming pulse, the second signal value of the second programming pulse is greater than the first signal value of the first programming pulse, and the programming verification pulse is used to obtain the number of failure bits of the first page after the first programming pulse and before the second programming pulse is applied;

[0115] S220: Based on the first signal value and the number of failure bits, determine the third signal value of the third programming pulse applied to the second page; wherein the second page is different from the first page;

[0116] S230: Program the second page using only the third programming pulse.

[0117] Here, step S210 can be executed under the control of the memory controller. For example, the memory controller issues a first write command, which may include a first signal value, a programming verification pulse signal value, and a second signal value. After receiving the first write command, the non-volatile memory device generates a first programming pulse, a programming verification pulse, and a second programming pulse to program the first page and count the number of failure bits of the first page after applying the programming verification pulse. In some embodiments, the signal value of the programming verification pulse may be stored in the peripheral circuit and directly accessed by the peripheral circuit without needing to be sent by the memory controller.

[0118] In some embodiments, step S210 may be jointly executed by the memory controller and the non-volatile memory device. For example, the memory controller issues a first write command, which may include a first signal value, a programming verification pulse signal value, and a second signal value. After receiving the first write command, the peripheral circuit generates a first programming pulse, a programming verification pulse, and a second programming pulse to program the first page and count the number of failure bits of the first page after applying the programming verification pulse.

[0119] In some embodiments, step S210 may be performed by a non-volatile memory device. For example, the peripheral circuitry stores a first signal value, a programming verification pulse signal value, and a second signal value. The peripheral circuitry directly generates the first programming pulse, the programming verification pulse, and the second programming pulse to program the first page.

[0120] Step S220 can be executed by the memory controller. After obtaining the number of failure bits of the first page, the memory controller determines the third signal value based on the first signal value and the number of failure bits.

[0121] Step S230 can be performed by the memory controller, for example, the memory controller issues a second write command, which includes a third signal value.

[0122] In some embodiments, this step may also be performed jointly by the memory controller and the non-volatile memory device. For example, the memory controller issues a second write command including a third signal value; after receiving the second write command, the peripheral circuitry generates a third programming pulse to program the second page.

[0123] In some embodiments, in step 210, the second signal value can be an empirical value, a large signal value sufficient to enable the first page to be written to the programming state, without needing to be determined by the first signal value and the number of failure bits.

[0124] In some embodiments, step S210 includes: sequentially programming the first page using a first programming pulse and a programming verification pulse; determining a second signal value based on a first signal value and the number of failure bits; and programming the first page using a second programming pulse.

[0125] In some embodiments, prior to step S210, the programming method further includes:

[0126] Determine the first signal value to be applied to the first page.

[0127] In some embodiments, the step of determining a first signal value applied to the first page may include the following steps:

[0128] Apply the first programming test pulse to the first page and verify the programming to obtain the first test failure bit count;

[0129] When the number of first test failure bits is greater than the target number of failure bits, a second programming test pulse is applied to the first page and the program is verified to obtain the second number of test failure bits; wherein, the signal value of the second programming test pulse is greater than the signal value of the first programming test pulse;

[0130] When the number of failed bits in the second test is less than or equal to the target number of failed bits, the signal value of the first programming test pulse is determined to be the signal value of the first programming pulse.

[0131] Here, "programming verification for the first page" means applying a programming verification pulse to the first page.

[0132] In some embodiments, the signal value of the second programming test pulse is equal to the sum of the signal value of the first programming test pulse and a preset increment value.

[0133] In some embodiments, the preset increment value is a fixed value.

[0134] In some embodiments, the preset increment value ranges from 300mV to 600mV. For example, it could be 300mV, 400mV, 450mV, 500mV, 600mV, etc. Figure 5 In the above, the median threshold voltage tolerance of the programming state for pages with 100k erase / write cycles is 410mV higher than that of pages without erase / write cycles. The programming efficiency of pages with 100k erase / write cycles is about 80% of that of pages without erase / write cycles. Therefore, a preset increment value of 500mV can be set so that the first signal value of the first programming pulse can adapt to programming different pages with large differences in the number of erase / write cycles.

[0135] It should be noted that after obtaining the first test failure bit count, if the first test failure bit count is less than or equal to the target failure bit count, it indicates that the signal value of the first programming test pulse has already written the first page to the programming state, and the signal value of the first programming test pulse is too large. Therefore, it is necessary to reapply the first programming test pulse with a smaller signal value starting from the erase state and verify.

[0136] Specifically, when the number of first test failure bits is less than or equal to the target number of failure bits, the first page is erased, and a third programming test pulse is applied to the erased first page, wherein the signal value of the third programming test pulse is less than the signal value of the first programming test pulse.

[0137] Here, the third programming test pulse is the first programming test pulse with a smaller signal value applied to the first page in the erase state.

[0138] Repeat the steps of "erasing the first page and applying a first programming test pulse with a smaller signal value to the erased first page" until the number of first test failure bits is greater than the target number of failure bits, then continue to apply a second programming test pulse with a larger signal value to the test page.

[0139] After obtaining the second test failure bit count, if the second test failure bit count is greater than the target failure bit count, it means that the first page has not been written to the programming state. Then, the first page is erased and a first programming test pulse with a larger signal value is applied for verification.

[0140] Specifically, when the number of second test failure bits is greater than the target number of failure bits, the first page is erased, and a fourth programming test pulse is applied to the erased first page; wherein the signal value of the fourth programming test pulse is greater than the signal value of the first programming test pulse.

[0141] Here, the fourth programming test pulse is the first programming test pulse with a larger signal value applied to the first page in the erase state.

[0142] Here, after applying a first programming test pulse with a larger signal value to the first page in the erase state, a second programming test pulse is also required for verification. This process continues until the number of first test failure bits is greater than the target number of failure bits, and the number of second test failure bits is less than or equal to the target number of failure bits, at which point the first signal value is determined.

[0143] In the step of determining the first signal value of the first programming pulse provided in the embodiments of this disclosure, the maximum number of programming test pulses can be set to 2, and the preset increment value (referring to the difference between the signal value of the second programming test pulse and the signal value of the first programming test pulse) is a fixed value. By adjusting the signal value of the first programming test pulse, the first page is not written to the programming state after the first programming test pulse is applied and before the second programming test pulse is applied, but the first page is written to the programming state after the second programming test pulse is applied, thereby obtaining the first signal value of the first programming pulse of the first page.

[0144] In some embodiments, when adjusting the signal value of the first programming test pulse, the signal value of the first programming test pulse can be increased or decreased by a preset increment to obtain the signal values ​​of the third programming test pulse and the fourth programming test pulse.

[0145] It is understood that in some embodiments, the range of the first programming test pulse signal value can be limited based on experience, so that the signal value of the first programming test pulse is as close as possible to the finally determined first signal value, thereby shortening the time to determine the first signal value and thus saving programming time.

[0146] In some embodiments, the step of determining the first signal value of the first programming pulse can be performed by a non-volatile memory device, which programs the non-volatile memory device using ISPP and sets the maximum number of programming pulses to 2. When the first page is written to the programming state and the number of programming pulses is 2, the first signal value is determined by the non-volatile memory device.

[0147] In some embodiments, the step of determining the first signal value of the first programming pulse can be performed by a memory controller. The memory controller issues a third write command, which includes: applying a first programming test pulse to the first page; the memory controller acquiring a first test failure bit count and comparing the first test failure bit count with a target failure bit count; when the first test failure bit count is greater than the target failure bit count, the memory controller sends a fourth write command, which includes: applying a second programming test pulse to the first page, the signal value of the second programming test pulse being greater than the signal value of the first programming test pulse; the memory controller acquiring a second test failure bit count and comparing the second test failure bit count with a target failure bit count; when the second test failure bit count is less than or equal to the target failure bit count, determining the signal value of the first programming test pulse as the first signal value.

[0148] In some embodiments, the step of determining the first signal value of the first programming pulse can be jointly performed by the memory controller and the non-volatile memory device. For example, the memory controller issues a third write command including the signal value of the first programming test pulse; after receiving the third write command, the peripheral circuit generates the first programming test pulse and the programming verification pulse to program the first page and counts the first test failure bits; the memory controller obtains the first test failure bits and compares it with the target failure bits; when the first test failure bits are greater than the target failure bits, the memory controller sends a fourth write command including the signal value of the second programming test pulse; after receiving the fourth write command, the peripheral circuit generates the second programming test pulse and the programming verification pulse to program the first page and counts the second test failure bits; the memory controller obtains the second test failure bits and compares it with the target failure bits; when the second test failure bits are less than or equal to the target failure bits, the memory controller determines the signal value of the first programming test pulse as the first signal value.

[0149] Figure 8 This diagram shows the threshold voltage distribution of memory cells within the first page after applying a first programming test pulse and a second programming test pulse. The horizontal axis represents the threshold voltage, and the vertical axis represents the number of memory cells in the page. Figure 8It can be seen that for the first programming test pulse that meets the requirements, after applying the first programming test pulse, the threshold voltage of some memory cells is less than the target threshold voltage (Vpv), that is, the first page is not written to the programming state. After applying the second programming test pulse, the threshold voltage of most memory cells is greater than the target threshold voltage, that is, the first page is written to the programming state.

[0150] In some embodiments, a first signal value applied to the first page can be determined before each execution of step S210 on the first page of the block. Furthermore, an erasure operation is performed on the first page before executing step S210.

[0151] In some embodiments, a first signal value applicable to all blocks in a die can be determined. Specifically, the step of determining the first signal value applied to the first page may include the following steps:

[0152] Obtain first test signal values ​​for multiple first test pages; wherein, the number of erase / write cycles for the multiple first test pages is different, and each first test signal value is the signal value of the first programming test pulse when the number of first test failure bits after the first programming test pulse is applied to the first test page is greater than the target number of failure bits, and the number of second test failure bits after the second programming test pulse is applied to the first test page is less than or equal to the target number of failure bits;

[0153] Based on multiple first test signal values, determine the first signal value applied to the first page.

[0154] Here, a bare die may include multiple blocks. Within a bare die, several blocks at specific locations are selected as test blocks. These test blocks have different erase / write cycles, and each test block may include at least one first test page. For example, the erase / write cycles of the test blocks may not be exactly the same; that is, each erase / write cycle may correspond to multiple test blocks.

[0155] Here, the steps of obtaining the first test signal values ​​of multiple first test pages and determining the first signal value based on the multiple first test signal values ​​can be performed by the memory controller.

[0156] Here, before the step of obtaining the first test signal values ​​of multiple first test pages, the programming method further includes: determining the first test signal values ​​of multiple first test pages.

[0157] The steps for determining the first test signal value of the first test page are the same as those for determining the first signal value of the first page described above. Specifically: apply a first programming test pulse to the first test page and perform programming verification to obtain the first test failure bit count; when the first test failure bit count is greater than the target failure bit count, apply a second programming test pulse to the first test page and perform programming verification to obtain the second test failure bit count; when the second test failure bit count is less than or equal to the target failure bit count, determine the signal value of the first programming test pulse as the first test signal value of the first test page.

[0158] In some embodiments, determining the first signal value applied to the first page based on a plurality of first test signal values ​​includes:

[0159] The minimum value among multiple first test signal values ​​of multiple first test pages is determined as the first signal value of the first programming pulse applied to the first page.

[0160] In some embodiments, determining the first signal value applied to the first page based on a plurality of first test signal values ​​includes:

[0161] The average value of multiple first test signal values ​​of multiple first test pages is determined as the first signal value of the first programming pulse applied to the first page.

[0162] In some embodiments, the steps described above may be performed before programming the bare chip to determine the first signal value of the first page applicable to all blocks in the bare chip.

[0163] It should be noted that, in some embodiments, the step of determining the first signal value of the first page applicable to all blocks in a bare chip can also be completed during the fabrication stage of the non-volatile memory device.

[0164] In some embodiments, the step of determining the first signal value of the first page applicable to all blocks in a bare die may be performed by a non-volatile memory device and a test machine during the fabrication stage, or by a non-volatile memory device, a memory controller, and a test machine.

[0165] For example, the tester and peripheral circuits jointly execute the step of determining the first test signal value of multiple first test pages. Specifically, the tester issues a third write command including the signal value of a first programming test pulse; after receiving the third write command, the peripheral circuit generates a first programming test pulse and a programming verification pulse to program the first test page and counts the number of first test failure bits; the tester obtains the number of first test failure bits and compares it with the target number of failure bits. When the number of first test failure bits is greater than the target number of failure bits, the tester sends a fourth write command including the signal value of a second programming test pulse; after receiving the fourth write command, the peripheral circuit generates a second programming test pulse and a programming verification pulse to program the first page and counts the number of second test failure bits; the tester obtains the number of second test failure bits and compares it with the target number of failure bits. When the number of second test failure bits is less than or equal to the target number of failure bits, the signal value of the first programming test pulse is determined to be the first test signal value.

[0166] In some embodiments, the test machine may send a write command to the peripheral circuit through the memory controller and obtain multiple first test signal values ​​through the memory controller.

[0167] The testing machine determines the first signal value based on multiple first test signal values.

[0168] After determining the first signal value of the first page applicable to all blocks in a bare chip, the first signal value is stored in a non-volatile memory device or memory controller.

[0169] Non-volatile memory devices typically include multiple bare chips, each with variations in manufacturing process. Therefore, in some embodiments, the non-volatile memory device or memory controller stores at least one first signal value, each first signal value corresponding to one bare chip. Here, some of the multiple first signal values ​​may be equal.

[0170] Correspondingly, in the above programming method, before step S110 or step S210, the programming method may further include: obtaining the first signal value of the stored first programming pulse according to the address of the first page. This can further shorten the programming time.

[0171] Here, the first signal value can be obtained from the page address of the first page, the block address of the block containing the first page, or the address of the bare chip containing the first page.

[0172] In some embodiments, a basic first signal value may also be stored in the non-volatile memory device. During the programming phase of the non-volatile memory device, when programming the bare chip, the basic first signal value can be adjusted according to the location of the bare chip to obtain a first signal value applicable to different bare chips. Here, the basic first signal value may be the first signal value corresponding to a specific bare chip.

[0173] This disclosure provides four methods for determining the first signal value. As described above, the first method is to directly determine the first signal value on the first page before executing step S210. This method of determining the first signal value is more suitable and does not require setting up a test page for determining the first test signal value, which is beneficial for improving memory integration.

[0174] The second approach is to determine the first signal value of the first page applicable to all blocks within a bare chip before programming it each time. This method improves programming efficiency.

[0175] The third approach involves determining the first signal value of the first page applicable to all blocks within each bare die during the non-volatile memory device fabrication stage, and storing this value in the non-volatile memory device or memory controller. These first signal values ​​can then be directly used when programming the non-volatile memory device. While this method increases the fabrication cycle time, it significantly improves programming efficiency.

[0176] The fourth approach involves storing a basic first signal value in the non-volatile memory device during the fabrication phase, and storing this value in the non-volatile memory device or memory controller. During the programming phase of the non-volatile memory device, when programming the bare chip, the basic first signal value is adaptively adjusted according to the location of the bare chip. This approach balances the fabrication cycle time and programming efficiency of the non-volatile memory device.

[0177] In some embodiments, step S220 includes:

[0178] The first compensation value is determined based on the number of failure bits; wherein, the first compensation value is the difference between the first target programming pulse signal value and the first signal value on the first page, and the second target programming pulse signal value on the second page is equal to the first target programming pulse signal value;

[0179] The sum of the first signal value and the first compensation value is determined as the third signal value.

[0180] In some embodiments, a first correspondence is stored in the memory controller or non-volatile memory device. The first correspondence includes a plurality of fitting functions for programming pulse signal values ​​and failure bit counts, wherein the plurality of fitting functions are different and are applied to pages with different erase / write cycles. Alternatively, the first correspondence includes a fitting function for programming pulse signal values ​​and failure bit counts, wherein the fitting function is applicable to pages with different erase / write cycles.

[0181] Here, the first correspondence is obtained by applying programming pulses with different signal values ​​to pages with different erase / write cycles, and by applying a programming verification pulse after each programming pulse to obtain the number of failure bits.

[0182] In some embodiments, the non-volatile memory device may include a plurality of second test pages, the plurality of second test pages having different erase / write cycles, and determining the first correspondence may include the following steps:

[0183] Multiple programming test pulses are sequentially applied to each second test page, and the second test page is programmed and verified after each programming test pulse is applied to obtain the number of test failure bits of the multiple second test pages; wherein the signal values ​​of the multiple programming test pulses change in a step-by-step manner;

[0184] Based on the signal values ​​of multiple programming test pulses applied to multiple second test pages, and the number of test failure bits obtained after each programming test pulse is applied, multiple fitting functions are determined for the programming pulse signal values ​​and failure bits of pages with different erase / write cycles, and the first correspondence includes the multiple fitting functions.

[0185] Here, program verification of the second test page can be achieved by applying a program verification pulse to the second test page.

[0186] In some embodiments, the number of erase / write cycles for multiple second test pages is not exactly the same. That is, each number of erase / write cycles may correspond to multiple test pages.

[0187] In some embodiments, the non-volatile memory device may include multiple test blocks, each with a different number of erase / write cycles. Each test block may include a second test page located in the same position as the first page within the block. For example, if the first page is WL0, then the second test page is also WL0.

[0188] In some embodiments, the step of determining the first correspondence may be performed jointly by the non-volatile memory device and the memory controller.

[0189] For example, the memory controller sequentially sends multiple fifth write commands to the peripheral circuit. Each fifth write command includes the address of the second test page and the signal values ​​of multiple programming test pulses applied to the second test page. After receiving each fifth write command, the peripheral circuit applies multiple programming test pulses to the second test page using the ISPP method to obtain multiple test failure bit counts. The memory controller obtains the multiple test failure bit counts corresponding to each second test page from the peripheral circuit and determines the first correspondence based on the signal values ​​of the programming test pulses stored in its own memory.

[0190] In some embodiments, the process of determining the first correspondence using a plurality of second test pages can determine the first correspondence before the first page of the first block of the non-volatile memory device is programmed for the first time.

[0191] In some embodiments, the process of obtaining the first correspondence using multiple second test pages can also be completed after the non-volatile memory device is manufactured and before the memory system is packaged and shipped. The determined first correspondence can be stored in the memory controller or the non-volatile memory device, so that the stored first correspondence can be directly obtained when the above programming process is executed.

[0192] In some embodiments, the step of determining the first correspondence may be performed jointly by the non-volatile memory device and the test machine during the fabrication stage.

[0193] For example, the tester sequentially sends multiple fifth write commands to the peripheral circuit. Each fifth write command includes the address of the second test page and the signal values ​​of multiple programming test pulses applied to the second test page. After receiving each fifth write command, the peripheral circuit generates multiple programming test pulses and programming verification pulses to program the second test page and counts multiple test failure bits. The tester retrieves the multiple test failure bits corresponding to each second test page from the non-volatile memory device and determines the first correspondence based on the signal values ​​of the multiple programming test pulses stored in its own memory.

[0194] In some embodiments, the step of determining the first correspondence may be jointly performed by the non-volatile memory device, the memory controller, and the test machine. For example, the test machine sends a fifth write command to the peripheral circuit through the memory controller and obtains the number of test failure bits through the memory controller.

[0195] Furthermore, it should be noted that in some embodiments, during the fabrication stage of a non-volatile memory device or memory system, a first correspondence was obtained through experiments on a large number of bare chips and a large number of test blocks. Therefore, the first correspondence provided in the embodiments of this disclosure is basically applicable to all bare chips with the same or similar structures.

[0196] Figure 9 This is a schematic diagram of a first correspondence provided in an embodiment of the present disclosure. Figure 9 The point values ​​that form the solid line by connecting the points are obtained through the steps described above. Figure 9 The horizontal axis (x-axis) represents the programming pulse bias value, and the vertical axis (y-axis) represents the number of page failure bits (FBC).

[0197] Here, the programming pulse bias value is the difference between the programming pulse signal value and the preset programming pulse signal value, set only to simplify the fitting function. The preset programming pulse signal value can be any value and does not affect the magnitude of the first compensation value.

[0198] For example, the default programming pulse signal value can be 17V. Then... Figure 9 In the diagram, the programming pulse bias value on the horizontal axis is 0mV, corresponding to a programming pulse signal value of 17V. Similarly, the programming pulse bias values ​​on the horizontal axis of 100mV, 200mV, 300mV, 400mV, 500mV, 600mV, 700mV, 800mV, 900mV, and 1000mV correspond to programming pulse signal values ​​of 17.1V, 17.2V, 17.3V, 17.4V, 17.5V, 17.6V, 17.7V, 17.8V, 17.9V, and 18V, respectively.

[0199] Figure 9 The fitted lines are shown for the programming pulse bias value versus the logarithm of the number of failure bits for an unerased page (erased 10k times, for example, 0 times), and for a page with 10k erases.

[0200] It is important to note here that the number of failure bits and the programming pulse bias value are not linearly related. Instead, the value is the logarithm of the number of failure bits taken to the base 10 (logarithm of the programming pulse bias value). 10 There is a linear relationship between (FBC) and the programmed pulse bias value, therefore, Figure 9 The central vertical axis is not equally divided. In other words, if you want... Figure 9 If the vertical axis is equally divided, then it can be... Figure 9 The vertical axis is modified to the logarithm of the number of failed bits per page, base 10 (log). 10 (FBC)).

[0201] Taking the fitted line corresponding to the unerased page as an example, each point on the fitted line represents the number of failure bits obtained after programming and verifying the unerased page under a certain preset programming pulse signal value. In some embodiments, the preset programming pulse signal value may include 17V. The point value corresponding to a programming pulse bias value of 0 indicates programming under 17V conditions, with approximately 4000 failure bits; the point value corresponding to a programming pulse bias value of 300 millivolts (mV) indicates programming under 17.3V conditions, with approximately 1000 failure bits; and the point value corresponding to a programming pulse bias value of 400 millivolts indicates programming under 17.4V conditions, with approximately 600 failure bits.

[0202] In other words, Figure 9 It is obtained by starting with a preset programming pulse signal value, adding different programming pulse bias values ​​to the preset programming pulse signal value, obtaining the programming pulse signal value, applying the programming pulse signal value to the page, and obtaining the number of failure bits after verification.

[0203] Figure 9 In this process, by fitting multiple point values ​​obtained from programming the unerased page with different programming pulse signal values, a fitting line is obtained between the programming pulse bias value of the unerased page and the number of failure bits. The fitting function corresponding to this fitting line is log 10 (y) = 3.66 - 0.0021x', R 2 = 0.998. Where x' is the programming pulse bias value, y is the number of failure bits, and R 2 It is the coefficient of determination for linear regression, reflecting the goodness of fit of the model, R0. 2 The closer the value is to 1, the better the fitted equation and the more accurate the model. In some embodiments, the least squares method can be used to fit multiple point values ​​to obtain the fitted line and fitted function corresponding to the unerased page.

[0204] Using the same method as obtaining the fitted line corresponding to an unerased page, a fitted line can be obtained for the programming pulse bias value and the number of failure bits for a page with 10k erase cycles. The fitting function corresponding to this fitted line is log... 10 (y) = 3.31 - 0.0027x', R 2 =0.986.

[0205] Similarly, multiple fitting functions can be obtained for the programming pulse bias value and the number of failure bits of pages with different erase / write cycles. The first relationship includes the multiple fitting functions.

[0206] The following is combined Figure 9 This paper introduces a method for determining the first compensation value based on the first correspondence and the number of failed bits, and analyzes the reliability of the method.

[0207] Figure 9The vertical axis of the dashed line L1 extending parallel to the horizontal axis represents the number of failure bits corresponding to the page being written to the programming state, i.e., the target number of failure bits. In this embodiment, the target number of failure bits is 300. The horizontal axis corresponding to the intersection of the dashed line L1 and the fitted line is the programming pulse bias value corresponding to the page being written to the programming state. For example, the horizontal axis corresponding to the intersection point A1 of the dashed line L1 and the fitted line of the unerased page is 550mV, and the programming pulse signal value is 17.55V.

[0208] In some embodiments, such as Figure 9 As shown, the first correspondence includes fitting functions for the number of failure bits and programming pulse signal values ​​of multiple pages based on different erase / write cycles. Among the multiple fitting functions, there is a first fitting function, which is a fitting function corresponding to the number of erase / write cycles of the first page.

[0209] Here, the fitting function based on the number of failure bits and programming pulse signal values ​​of multiple pages at different erase / write cycles includes: log 10 (y)=a1+b1x、log 10 (y) = a² + b²x, ... log 10 (y)=a i +b i x、...log 10 (y)=a n +b n x; where i and n are integers, and n is less than or equal to the number of erasable / write cycles for the first page, x is the programming pulse signal value, y is the number of failure bits, and a i and b i 'a' is a constant among multiple fitting functions. i and b i Not exactly the same.

[0210] It is understandable that the programming pulse bias value x' is equal to the difference between the programming pulse signal value x and the preset programming pulse signal value c. That is, x' = xc. The fitting function between the programming pulse compensation bias value of the unerased page and the number of failed bits is log... 10 When (y) = 3.66 - 0.0021x', the programming pulse value of the unerased page and the number of failure bits satisfy log... 10 (y)=3.66-0.0021(xc)=(3.66+0.0021c)-0.0021x.

[0211] Step S120, the step of determining the first compensation value based on the number of failure bits, includes:

[0212] Obtain the first correspondence; wherein, the first correspondence includes a fitting function of the number of failure bits and the programming pulse signal value of multiple pages based on different erase / write cycles, and the first fitting function is a fitting function corresponding to the number of erase / write cycles of the first page;

[0213] The first fitting function is determined from multiple fitting functions based on the first signal value and the number of failure bits;

[0214] Substitute the number of target failure bits into the first fitting function to determine the value of the first target programming pulse signal;

[0215] The first compensation value is determined based on the difference between the first target programming pulse signal value and the first signal value.

[0216] Here, the step of determining the first compensation value based on the number of failure bits is performed by the memory controller. Obtaining the first correspondence can be either the memory controller calling the first correspondence in its own memory or the memory controller calling the first correspondence stored in the non-volatile memory device.

[0217] The steps for selecting the first fitting function may be as follows: substituting the first signal value of the first page into each of the multiple fitting functions in the first correspondence to calculate the number of failure bits corresponding to different fitting functions, and selecting the fitting function that is closest to the number of failure bits of the first page as the first fitting function for determining the first compensation value of the first page.

[0218] Combination Figure 9 The specific implementation is analyzed as follows: For example, when the signal value of the first programming pulse is 17V (the programming pulse bias value is 0mV) and the number of failed bits obtained is 4000, in the vertical axis direction, this point value is closest to the fitted line of the unerased page. Therefore, the fitted line of the unerased page is determined to be the fitted line corresponding to the first fitting function. Next, as... Figure 9 As shown, the x-coordinate of the intersection point A1 of the fitted straight line of the unerased page and the dashed line L1 is the target programming pulse signal value of 17.55V (corresponding to the programming pulse bias value of 550mV). The first compensation value can be determined to be 550mV from the difference between 17.55V and 17V.

[0219] See also Figure 9 When the signal value of the first programming pulse is still 17V (the programming pulse bias value is 0mV), and the number of failed bits obtained is 2000, the value at this point on the vertical axis is closest to the fitted line of a page with 10K erase / write cycles. Therefore, the fitted line of a page with 10K erase / write cycles is determined to be the fitted line corresponding to the first fitted function. Figure 9As shown, the x-coordinate of the intersection point B1 of the fitted line of the page with 10K erase / write cycles and the dashed line L1 is the target programming pulse signal value of 17.3V (corresponding to a programming pulse bias value of 300mV). The first compensation value of 300mV can be determined from the difference between 17.3V and 17V.

[0220] As can be seen from the two specific embodiments above, after applying a first programming pulse value of 17V to both the unwritten page and the page with 10k erase cycles, the first compensation value can be determined to be 550mV based on the failure bit count of 4000 for the unwritten page, and 300mV based on the failure bit count of 2000 for the page with 10k erase cycles. It is evident that the first compensation value gradually decreases as the number of erase cycles increases, which is consistent with the above... Figure 5 The observed pattern of the page's programming state threshold voltage tolerance gradually increasing with the number of erase / write cycles is consistent with this. This is understandable. Figure 5 In the DSLC mode, after applying the same signal value of programming pulse to pages with different erase / write cycles, the programming state threshold voltage tolerance of pages with more erase / write cycles is larger, indicating that the degree of over-programming is greater. Therefore, when programming using the programming method provided in the embodiments of this application, a smaller first compensation value is required.

[0221] This indicates that the method for determining the first compensation value provided in the embodiments of this application is reliable. First, it can adaptively adjust the first compensation value according to the number of page erases and writes. Second, the method for determining the first compensation value based on the number of first failure bits can satisfy the rule that the first compensation value gradually decreases as the number of page erases and writes increases.

[0222] Furthermore, from Figure 9 It can be seen that the slopes of the fitted lines corresponding to pages with different erase / write cycles are basically the same.

[0223] Taking the first signal value of the first programming pulse as 17V and the number of failure bits as 2000 as an example, as can be seen from the above embodiment, the fitting line of the page with 10k erase / write cycles should be selected as the fitting line corresponding to the first fitting function for determining the first compensation value, and the first compensation value should be the difference between the abscissa value of point B1 and the abscissa value of point B2.

[0224] Here, in Figure 9A dashed line L2 parallel to the horizontal axis is drawn, with its intercept on the vertical axis being 2000. This means the dashed line L2 passes through point B2, and its intersection with the fitted line of the unerased page is at point A2. Since the slopes of the fitted lines for the page with 10k erase cycles and the unerased page are the same, it's easy to deduce that the difference between the x-coordinates of points A1 and A2 is equal to the difference between the x-coordinates of points B1 and B2. This indicates that the first compensation value determined by the fitted line of the unerased page is equal to the first compensation value determined by the page with 10k erase cycles. Therefore, the fitted line of the unerased page can be used instead of the fitted line of the page with 10k erase cycles to determine the first compensation value corresponding to a first signal value of 17V and 2000 failure bits for the first page.

[0225] By analogy, it can be concluded that in this embodiment of the present disclosure, the first compensation value for pages with different erase / write cycles can be determined using only the fitted straight line corresponding to the unerased page. Therefore, in some embodiments, the first correspondence includes a fitting function of a programming pulse signal value and the number of failure bits, and the fitting function is applicable to pages with different erase / write cycles.

[0226] Here, the fitting function is log 10 (y) = a + bx; where x is the value of the programming pulse signal, y is the number of failure bits, and a and b are constants.

[0227] Step S120, the step of determining the first compensation value based on the number of failure bits, includes:

[0228] Obtain the first correspondence; wherein, the first correspondence includes a fitting function of a programming pulse signal value and the number of failure bits, and the fitting function is applicable to pages with different erase / write cycles;

[0229] Substitute the target failure bit count into the fitting function to determine the value of the first relative programming pulse signal;

[0230] Substitute the number of failure bits from the first page into the fitting function to determine the value of the second relative programming pulse signal;

[0231] The first compensation value is determined based on the difference between the first relative programming pulse signal value and the second relative programming pulse value.

[0232] It should be noted here that the first correspondence may include a fitting function of a page programming pulse signal value and the number of failure bits for any number of erase / write cycles.

[0233] In some embodiments, the first correspondence includes a fitting function of the programming pulse signal value of the unerased page and the number of failure bits.

[0234] Combination Figure 9 The specific implementation examples are described below: Figure 9As shown, the intersection point A1 of the dashed line L1 and the fitted line corresponding to the unerased page indicates that by substituting the target number of failed bits into the fitted function corresponding to the unerased page, the first relative programming pulse signal value is determined to be 17.55V (programming pulse compensation value is 550mV).

[0235] When the signal value of the first programming pulse is still 17V and the number of failure bits obtained is 2000, the intersection point A2 of the dashed line L2 and the fitted line corresponding to the unerased page indicates that substituting the number of failure bits of the first page into the fitted function corresponding to the unerased page determines the second relative programming pulse signal value to be 17.17V (programming pulse compensation value is 170mV). Based on the difference between 550mV and 170mV, the first compensation value is determined to be 380mV. This has a certain error compared to the 300mV determined above, mainly due to the slopes of the unerased page and the page with 10k erase cycles being -0.0021 and -0.2217 respectively, which are not completely consistent. However, the error is within an acceptable range.

[0236] Here, we further verify this using a fitting function of the programming pulse signal value of the unerased page and the number of failure bits. The fitting function is log [value of the programming pulse bias value of the unerased page and the number of failure bits]. 10 From (y) = 3.66 - 0.0021x', we can deduce that the fitting function between the programming pulse signal value of the unerased page and the number of failure bits is log 10 (y) = 3.66 - 0.0021(x - 17) = (3.66 + 0.0021 * 17) - 0.0021x. Set the target failure bit count to y1, the first relative programming pulse signal value to x1, the failure bit count of the first page to y2, and the second relative programming pulse signal value to x2, to obtain log... 10 (y1)=(3.66+0.0021*17)-0.0021x1, log 10 (y2)=(3.66+0.0021*17)-0.0021x2; The first compensation value Δ is equal to the difference between the first relative programming pulse signal value and the second relative programming pulse signal value, that is, Δ=x1-x2=(log 10 (y1)-log 10 Substituting (y2)) / -0.0021 into y1=300, y2=2000, we get the first compensation value as 392mV. This is consistent with the value obtained from... Figure 9 The result determined by the fitted straight line is consistent with 380V.

[0237] Furthermore, the formula for calculating the first compensation value is Δ=x1-x2=(log 10 (y1)-log 10As shown in (y2) / b, the first compensation value is independent of the preset programming pulse signal value and the first signal value. The first compensation value is only related to the target number of failure bits, the number of failure bits on the first page, and the slope b of the first fitting function. Among them, the target number of failure bits and the slope b of the first fitting function are known. Therefore, in the actual programming process, the first compensation value can be calculated directly based on the number of failure bits on the first page.

[0238] Compared to the embodiment where the first correspondence includes multiple fitting functions, this embodiment can eliminate the step of determining the first fitting function from multiple fitting functions corresponding to pages with different erase / write cycles, and only needs to apply the formula Δ=(log 10 (y1)-log 10 By substituting the number of failure bits from the first page into (y2)) / b, the first compensation value can be determined, which simplifies the steps of determining the first compensation value and speeds up the programming process.

[0239] As can be seen from the above embodiments of this disclosure, when the slopes of the fitting functions for the logarithmic values ​​of the failure bit counts and the programming pulse signal values ​​of multiple pages with different erase / write cycles are not the same and the differences are large, the first correspondence should include the fitting function based on the programming pulse signal values ​​and failure bit counts of multiple pages with different erase / write cycles. This makes the obtained first compensation value more accurate.

[0240] When the slope of the fitting function for the logarithmic value of the failure bits of multiple pages with different erase / write cycles and the programming pulse signal value is approximately the same, the first correspondence can be set to include only the fitting function for the failure bits of a single page with any erase / write cycle and the programming pulse signal value. This simplifies the process of determining the first compensation value and speeds up the programming process.

[0241] Here, the slope of the linear function of the logarithmic value of the number of failure bits of multiple pages with different erase / write cycles and the value of the programming pulse signal is basically the same, including the slopes being exactly the same, as well as multiple slopes not being exactly the same, but the differences are small and within the allowable error range.

[0242] In some embodiments, step S220 includes:

[0243] The third signal value applied to the second page is determined based on the first signal value, the number of failure bits, and the positional relationship between the second page and the first page.

[0244] For example, the step of determining the third signal value applied to the second page based on the first signal value, the number of failure bits, and the positional relationship of the second page relative to the first page includes:

[0245] The first compensation value is determined based on the number of failed bits;

[0246] The second compensation value is determined based on the positional relationship between the second page and the first page;

[0247] The sum of the first signal value, the first compensation value, and the second compensation value is determined as the third signal value.

[0248] Here, the steps for determining the first compensation value based on the number of failed bits are as described above, so they will not be repeated here.

[0249] In some embodiments, the memory controller stores a second correspondence, which indicates the relationship between the second compensation value and the position of the second page.

[0250] In some embodiments, the step of determining the second compensation value based on the positional relationship of the second page relative to the first page includes:

[0251] Obtain the second correspondence;

[0252] Obtain the position of the second page, and based on the position of the second page, match the second compensation value corresponding to the second page in the second correspondence.

[0253] Here, the steps of obtaining the second correspondence and determining the second compensation value based on the second correspondence and the position of the second page can be performed by the memory controller.

[0254] In some embodiments, the step of obtaining the second correspondence relationship is further included before determining the second correspondence relationship.

[0255] For example, a non-volatile memory device may include at least one test block, each test block including a plurality of third test pages, which can be tested to determine a second correspondence. Specifically, determining the second correspondence includes the following steps:

[0256] A programming test pulse with the same signal value is applied to each third test page in the same test block;

[0257] Obtain the gate signal values ​​(V) of each memory cell in the third test page. g ) and threshold signal value (V t );

[0258] The characteristic signal values ​​of each third test page are determined based on the gate signal values ​​and threshold signal values ​​of multiple memory cells in each third test page;

[0259] Obtain the feature signal values ​​of each third test page in the test block to determine the second correspondence.

[0260] Here, the step of determining the second correspondence can be jointly performed by the memory controller and the non-volatile memory device. For example, the memory controller sends a sixth write command to the peripheral circuit, which includes the address of the test block and the signal value of the programming test pulse; after receiving the sixth write command, the peripheral circuit can apply programming test pulses with the same signal value to each third test page in the test block; the memory controller obtains the gate signal value and threshold signal value of each memory cell in the third test page, determines the characteristic signal value, and thereby determines the second correspondence.

[0261] For example, the gate signal value includes the gate voltage; the threshold signal value includes the threshold voltage. The gate voltage can be viewed as the voltage of the programming test pulse applied to the test page.

[0262] It is understandable that after applying the same signal value to each of the third test pages, the gate signal values ​​of each memory cell in the test page are basically the same, and the threshold signal value is related to the characteristics of each memory cell. Therefore, the characteristic signal value determined by the gate signal value and the threshold signal value can reflect the changing trend of the second compensation value.

[0263] For example, determining the characteristic signal value of each third test page based on the gate signal value and threshold signal value of a plurality of memory cells in each third test page includes:

[0264] Calculate the first difference between the gate signal value and the threshold signal value of each memory cell in each third test page;

[0265] The median of the multiple first differences corresponding to each memory cell in the third test page is determined and used as the characteristic signal value of the test page.

[0266] In some embodiments, the characteristic signal values ​​of each third test page in the test block are obtained to determine a second correspondence; including:

[0267] Obtain the characteristic signal values ​​of each third test page in the test block;

[0268] Select a third test page that is in the same position as the first page from among multiple third test pages. Use the difference between the feature signal values ​​of the other third test pages and the selected third test page that is in the same position as the first page as the second compensation value corresponding to the second page, and establish a second correspondence between the second compensation value and the position of the second page.

[0269] For example, an ISPP programming method can be used to apply a programmed test pulse with the same signal value to each third test page.

[0270] In some embodiments, a programming test pulse with the same signal value can be applied multiple times to each third test page in the same test block, with the signal value of the programming test pulse being different each time, in order to enrich the sample size and make the obtained second compensation value accurate.

[0271] In some embodiments, multiple test blocks are provided, and at least two of the test blocks have different number of erase / write cycles to enrich the sample size and make the obtained second compensation value accurate.

[0272] Figure 10 A diagram showing the relationship between page position and page feature signal values ​​provided in an embodiment of this disclosure. See also... Figure 10 , Figure 10 The horizontal axis represents the page position, and the vertical axis represents the page's characteristic signal value (V). g V t (median). Specifically, each block includes multiple stacked pages (i.e., word lines), each of which can be numbered from bottom to top or from top to bottom. Figure 10 The box plot at each point on the solid line shown is a distribution of the difference between the gate voltage and the threshold voltage of each memory cell in the page. Each point value is the median of the box plot (that is, the characteristic signal value of the page).

[0273] It should be noted that, Figure 10 The result was obtained by applying the same signal value to each page in the same block five times using the ISPP programming method, with each application having a different signal value. See also Figure 10 From top to bottom, the first curve is obtained after applying 6 programming pulses to each page in the same block, the second curve is obtained after applying 9 programming pulses, and the remaining curves are obtained after applying 12, 15, and 18 programming pulses respectively. The reason for this setting is that, with a fixed ISPP step voltage, as the programming voltage gradually increases, the memory cell will reach a stable programming efficiency. It is generally believed that the programming efficiency of the memory cell stabilizes under 6 to 18 programming pulses. Therefore, the measured V... g V t Relatively accurate.

[0274] like Figure 10 As shown, after applying the same signal value to each page in the same block, the characteristic signal values ​​of pages at different positions are different, indicating that the programming pulse signal values ​​for writing pages at different positions in the same block into the programming state are different.

[0275] based on Figure 10The page positions and characteristic signal values ​​shown can be used to determine the difference in characteristic signal values ​​between the second test page and the first test page in the test block. This difference serves as a second compensation value for the second page relative to the first page, establishing a second correspondence between multiple second compensation values ​​and multiple second page positions. This established second correspondence, with compensation values ​​adaptively set for each page position, achieves high accuracy.

[0276] It should be noted that the second compensation value can be positive, negative, or zero. This depends on the magnitudes of the first target programming pulse signal value on the first page and the second target programming pulse signal value on the second page. When the second target programming pulse signal value on the second page is greater than the first target programming pulse signal value on the first page, the second compensation value is positive. When the first target programming pulse signal value on the first page is equal to the second target programming pulse signal value on the second page, the second compensation value is zero. When the second target programming pulse signal value on the second page is less than the first target programming pulse signal value on the first page, the second compensation value is negative.

[0277] Here, it is understandable that the second compensation value is not necessary. When the second compensation value is zero or negative, the third signal value can still enable the second page to be programmed.

[0278] In some embodiments, the second compensation value may be the same for every few adjacent second pages. For example, the second compensation values ​​for pages 0 to 10 may be the same, and the second compensation values ​​for pages 11 to 20 may be the same. This simplifies the second correspondence and further improves programming speed.

[0279] It should be noted that in the above embodiments, the second correspondence was determined in multiple test blocks of the memory during the programming stage.

[0280] In some embodiments, the process of determining the second correspondence using test blocks can also be completed after the non-volatile memory device structure is fabricated but before the memory system is packaged and shipped. The determined second correspondence can be stored in the memory controller or the non-volatile memory device. Thus, when performing the above programming process, the second correspondence in the memory controller can be directly called, or the memory controller can call the second correspondence from the non-volatile memory device. This simplifies the programming process and saves programming time.

[0281] Here, the step of determining the second correspondence can be jointly performed by the non-volatile memory device and the test machine. For example, the test machine sends a sixth write command to the peripheral circuit, which includes the address of the test block and the signal value of the programming test pulse; after receiving the sixth write command, the peripheral circuit applies programming test pulses with the same signal value to each third test page in the test block; the test machine obtains the gate signal value and threshold signal value of each memory cell in the third test page, determines the characteristic signal value, and thereby determines the second correspondence.

[0282] In some embodiments, the step of determining the second correspondence can be jointly performed by the non-volatile memory device, the memory controller, and the test machine. For example, the test machine sends a sixth write command to the peripheral circuit through the memory controller, and obtains the gate signal value and threshold signal value through the memory controller. The test machine then determines the feature signal value based on the gate signal value and the threshold signal value, and thereby determines the second correspondence.

[0283] The first and second compensation values ​​provided in this embodiment are relatively accurate. Therefore, after applying the third programming pulse to the second page, the probability of the second page being programmed into the programming state is high. Thus, it is not necessary to perform programming verification on the second page to check whether the second page has been programmed into the programming state, which is beneficial to further shorten the programming time.

[0284] Figure 11 This is a schematic flowchart illustrating the programming of a block according to an embodiment of this disclosure. See also... Figure 11 The programming method provided in this embodiment includes the following steps:

[0285] S310: Obtain the first signal value of the first programming pulse applied to the first page of the block, as well as the first correspondence and the second correspondence;

[0286] S320: Apply a defined first programming pulse and programming verification pulse to the first page, and obtain the number of failure bits;

[0287] S330: The memory controller can calculate the first compensation value based on the number of failed bits and the first correspondence;

[0288] S340: The memory controller determines a second compensation value to be applied to the second page based on the location of the second page and the second correspondence; and applies a third programming pulse to the second page, wherein the third signal value of the third programming pulse is the sum of the first signal value of the first programming pulse, the first compensation value, and the second compensation value;

[0289] S350: The memory controller determines the second compensation value to be applied to the next second page based on the location of the next second page and the second correspondence; and applies a third programming pulse to the next second page;

[0290] S360: Following the above process, program each second page sequentially until all pages in the block have been programmed, then end the programming of the block.

[0291] In some embodiments, step S310 is performed before starting block programming.

[0292] In step S310, the memory controller stores a first correspondence, a second correspondence, and a first signal value. In some embodiments, the first correspondence, the second correspondence, and the first signal value may also be stored in the peripheral circuitry of a non-volatile memory device.

[0293] Step S320 can be performed by a non-volatile memory device.

[0294] In step S330, the memory controller can directly call the first correspondence stored in itself, or it can call the first correspondence stored in the peripheral circuit.

[0295] In step S340, the memory controller can directly call the first signal value and the second correspondence stored within itself, or it can call the first signal value and the second correspondence stored in the peripheral circuit. The memory controller determines the third signal value based on the first signal value, the first compensation value, and the second compensation value corresponding to the first second page.

[0296] The non-volatile memory device generates a third programming pulse to program the second page, the third programming pulse having a third signal value.

[0297] In step S350, the memory controller determines a third signal value to be applied to the next second page based on the first signal value, the first compensation value, and the second compensation value corresponding to the next second page. The non-volatile memory device executes a third programming pulse to be applied to the next second page, the third programming pulse having the third signal value.

[0298] The programming method provided in this embodiment pre-determines (e.g., during the memory fabrication stage) the first signal value, first correspondence, and second correspondence of the first programming pulse, thus minimizing programming time and improving programming efficiency. Furthermore, the first compensation value is determined through the first correspondence; the first compensation value differs for the first page at different erase / write cycles, enabling dynamic and refined programming based on the page's erase / write cycles. The second compensation value is determined by the position of the second page relative to the first page, enabling dynamic and refined programming within each block based on the page's position.

[0299] Figure 12 and Figure 13 The execution was listed for two blocks with different erase / write cycles (block 234 and block 80, respectively). Figure 6The programming method shown yields the threshold voltage distribution diagrams for the first page (WL0) and the second page (WL1). Block 234 is erased / written 10k times, and block 80 is erased / written 90k times. Figure 12 and Figure 13 The horizontal axis represents the threshold voltage, and the vertical axis represents the number of memory cells in a page. Curves 1-1 and 2-1 represent the threshold voltage distribution curves of the memory cells in the first page after the first programming pulse is applied; curves 1-2 and 2-2 represent the threshold voltage distribution curves of the memory cells in the second page after the first programming pulse is applied; curves 1-3 and 2-3 represent the threshold voltage distribution curves of the memory cells in the second page after the third programming pulse, whose signal value is equal to the sum of the first signal value, the first compensation value, and the second compensation value, is applied.

[0300] Figure 12 As can be seen from curve 1-1, after the first programming pulse is applied to the first page of block 234, the first page is not written to the programming state, and the number of failure bits obtained is 2210.

[0301] As can be seen from curve 1-2, after the first programming pulse is applied to the second page of block 234, the second page is not written to the programming state.

[0302] Based on the failure bit count of 2210 and the position of the second page, this experiment determined that the sum of the first and second compensation values ​​was 500mV. Next, a third programming pulse with a signal value equal to the sum of the first signal value, the first compensation value, and the second compensation value was applied to the second page.

[0303] As can be seen from curves 1-3, when the signal value of the third programming pulse is the sum of the first signal value, the first compensation value, and the second compensation value, the second page is programmed into the programming state. This demonstrates that the programming method provided in this embodiment is feasible and can precisely control the magnitude of the programming pulse signal value.

[0304] Figure 13 As can be seen from curve 2-1, after the first programming pulse is applied to the first page of block 80, the first page is not written to the programming state and the number of failure bits is 769.

[0305] As can be seen from curve 2-2, after the first programming pulse is applied to the second page of block 80, the second page is not programmed into the programming state.

[0306] Based on the first failure bit count of 769 and the position of the second page, this experiment determines that the sum of the first compensation value and the second compensation value is 300mV. Next, a third programming pulse with a signal value equal to the sum of the first signal value, the first compensation value, and the second compensation value is applied to the second page.

[0307] As can be seen from curves 2-3, when the signal value of the third programming pulse is the sum of the first signal value, the first compensation value, and the second compensation value, the second page is programmed into the programming state. This demonstrates that the programming method provided in this embodiment is feasible and can precisely control the magnitude of the programming pulse signal value.

[0308] pass Figure 12 and Figure 13 It can also be seen that the first compensation value is different for blocks with different erase / write cycles, indicating that this disclosure can adjust the first compensation value according to the number of erase / write cycles of the block, finely control the signal value of the programming pulse, and improve programming time and memory lifespan.

[0309] Figure 14 The threshold voltage distribution curve of the memory cells in the page (word line 64) after performing 100 erase / write cycles on two identical pages (word lines 64) of two blocks (blocks 234 and 236) using the DSLC method and the programming method provided in the embodiments of this disclosure. Figure 13 In the diagram, the horizontal axis represents the threshold voltage, and the vertical axis represents the number of memory cells. Block 234 employs the DSLC method, which applies a programming pulse of 20.7V throughout the 0 to 100k programming cycles. Block 236 employs the programming method provided in this embodiment, which applies a programming pulse of 20.7V during the 0 to 50k programming cycles and a programming pulse of 20.4V during the 50k to 100k programming cycles.

[0310] like Figure 14 As shown, in block 236, the threshold voltage shift of word line 64 in the programming state is less, the degradation of the erase state is less, the margin between the erase and programming states is wider, and the memory reliability is higher.

[0311] Figure 15 This is a cumulative distribution function (CDF) diagram showing the tolerances between the erase state threshold voltage and a specific voltage for word line 64 in blocks 234 and 236. Here, the specific voltage is the read voltage of a single-level memory cell. Figure 15 In the graph, the horizontal axis represents the tolerance, and the vertical axes represent the σ quantile and percentage of the cumulative probability, respectively. The left vertical axis represents the σ quantile of the cumulative probability, and the right vertical axis represents the percentage. For example... Figure 15As shown, the probability that the tolerance between the erase state threshold voltage and the specific voltage of word line 64 in block 236 is less than or equal to 1300mV is about 5% to 10%, while the probability that the tolerance between the erase state threshold voltage and the specific voltage of word line 64 in block 234 is less than or equal to 1300mV is about 25%. This indicates that the tolerance corresponding to word line 64 in block 236 is generally larger than that corresponding to word line 64 in block 234. The larger the tolerance, the smaller the degree of degradation in the erase state. Therefore, it can be concluded that the degree of degradation in the erase state of word line 64 in block 236 is smaller, that is, the crosstalk of word line 64 in the erase state is lower, and the reliability of the memory is higher. Figure 14 and Figure 15 This demonstrates that the programming method provided in the embodiments of this disclosure can improve the reliability of the memory.

[0312] Figure 16 This is a schematic flowchart illustrating a method for fabricating a memory system according to an embodiment of this disclosure. Figure 16 As shown, the preparation method includes the following steps:

[0313] S410: Execute a programming loop on multiple test pages of multiple test blocks, the programming loop including:

[0314] S411: Multiple programming test pulses are applied sequentially to the test page; wherein the signal values ​​of the multiple programming test pulses change in a step-like manner;

[0315] S412: After each programming test pulse is applied, the test page is programmed and verified to obtain the number of failure bits of the test page;

[0316] The preparation method further includes:

[0317] S420: Based on the acquired signal values ​​of multiple programming test pulses applied to multiple test pages, and the corresponding number of failure bits obtained after applying each programming test pulse, a first correspondence is determined; wherein, the first correspondence includes fitting functions for multiple programming pulse signal values ​​and failure bit numbers, the multiple fitting functions are different, and the multiple fitting functions are applied to pages with different erase / write cycles; or, the first correspondence includes a fitting function for a programming pulse signal value and failure bit number, the fitting function being applicable to pages with different erase / write cycles;

[0318] S430: Write a first correspondence to the memory controller; wherein, when programming a non-volatile memory device by executing the programming method as described in the embodiments of the present disclosure, a first compensation value is determined based on the first number of failure bits and the first correspondence.

[0319] In some embodiments, the above-described preparation method can be completed after the structure of the non-volatile memory device is prepared and before the memory system is packaged and shipped.

[0320] In some embodiments, the method for fabricating a memory system further includes the following steps:

[0321] A programming test pulse with the same signal value is applied to each test page in the same test block;

[0322] Obtain the gate signal value and threshold signal value of each memory cell in the test page;

[0323] The characteristic signal values ​​of the test page are determined based on the gate signal values ​​and threshold signal values ​​of each memory cell in the test page;

[0324] The feature signal values ​​of each test page in the block are obtained to determine the second correspondence; wherein, the second correspondence is used to indicate the positional relationship between the second compensation value and the second page;

[0325] A second correspondence is written to the memory controller; wherein, when programming a non-volatile memory device using the programming method as described in the embodiments of the present disclosure, a second compensation value for the second page is determined based on the positional relationship between the second page and the first page, and the second correspondence.

[0326] In some embodiments, the method for fabricating the memory further includes the following steps:

[0327] The step of determining the first test signal value of the first programming test pulse is performed on multiple test pages of multiple test blocks; the step of determining the first test signal value of the first programming test pulse includes:

[0328] Apply the first programming test pulse and the programming verification pulse to the test page, and obtain the first test failure bit count of the test page;

[0329] When the number of first test failure bits is greater than the target number of failure bits, a second programming test pulse and a programming verification pulse are applied to the test page to obtain the second number of test failure bits of the test page; wherein, the signal value of the second programming test pulse is greater than the signal value of the first programming test pulse;

[0330] When the number of second test failure bits is less than or equal to the target number of failure bits, the signal value of the first programming test pulse is determined to be the first test signal value of the first programming test pulse of the test page;

[0331] The first signal value of the first programming pulse is determined based on the first test signal values ​​of multiple first programming test pulses from multiple test pages of multiple test blocks.

[0332] A first signal value of a first programming pulse is written to a memory controller; wherein, when programming a non-volatile memory device using the programming methods of the embodiments of the present disclosure, the stored first signal value can be directly obtained.

[0333] By using the memory preparation method described above, the first correspondence, the second correspondence, and / or the first signal value of the first programming pulse are written into the memory controller or non-volatile memory device, and can be directly called during programming, which can save programming time.

[0334] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A programming method for a non-volatile memory device, characterized in that, The non-volatile memory device includes multiple pages, each page including multiple single-level memory cells, and the programming method includes: The first page of the plurality of pages is programmed using a signal including a first programming pulse, a programming verification pulse, and a second programming pulse. The first programming pulse is a start programming pulse, and the second signal value of the second programming pulse is greater than the first signal value of the first programming pulse. The programming verification pulse is used to obtain the number of failure bits of the first page after the first programming pulse and before the second programming pulse is applied. The verification result after programming the first page using the first programming pulse with the first signal value is a failure. The second page of the plurality of pages is programmed using only a third programming pulse, wherein the third signal value of the third programming pulse is determined based at least on the first signal value and the number of failure bits.

2. The programming method for the non-volatile memory device according to claim 1, characterized in that, The first programming pulse, the second programming pulse, and the third programming pulse are all voltage pulse signals.

3. The programming method for a non-volatile memory device according to claim 1, characterized in that, The first page is one, and the number of the second pages is greater than or equal to 2.

4. The programming method for a non-volatile memory device according to claim 1, characterized in that, The third signal value of the third programming pulse is equal to the sum of the first signal value and the first compensation value; Wherein, the first compensation value is the difference between the first target programming pulse signal value and the first signal value of the first page, the second target programming pulse signal value of the second page is equal to the first target programming pulse signal value, and the first compensation value is obtained based on the number of failure bits of the first page.

5. The programming method for a non-volatile memory device according to claim 1, characterized in that, The third signal value of the third programming pulse is determined based on the first signal value, the number of failure bits, and the positional relationship of the second page relative to the first page.

6. The programming method for a non-volatile memory device according to claim 5, characterized in that, The third signal value of the third programming pulse is equal to the sum of the first signal value, the first compensation value, and the second compensation value; The first compensation value is obtained based on the number of failure bits of the first page, and the second compensation value is obtained based on the positional relationship of the second page relative to the first page.

7. The programming method for a non-volatile memory device according to claim 4 or 6, characterized in that, The first compensation value is obtained based on the number of failure bits on the first page and the first correspondence. The first correspondence may include multiple fitting functions for programming pulse signal values ​​and failure bit counts, wherein the multiple fitting functions are different and are applied to pages with different erase / write cycles; or, the first correspondence may include a single fitting function for programming pulse signal values ​​and failure bit counts, wherein the fitting function is applicable to pages with different erase / write cycles.

8. The programming method for a non-volatile memory device according to claim 6, characterized in that, The second compensation value is obtained based on the position of the second page and the second correspondence. The second correspondence is used to indicate the relationship between the second compensation value and the position of the second page.

9. The programming method for a non-volatile memory device according to claim 1, characterized in that, After programming the second page of the plurality of pages using only the third programming pulse, the programming method further includes: Perform a programmatic verification on the second page.

10. A non-volatile memory device, characterized in that, include: A memory cell array comprising multiple pages, each page comprising multiple single-level memory cells; Peripheral circuitry coupled to the memory cell array, the peripheral circuitry being configured as follows: The first page of the plurality of pages is programmed using a signal including a first programming pulse, a programming verification pulse, and a second programming pulse. The first programming pulse is a start programming pulse, and the second signal value of the second programming pulse is greater than the first signal value of the first programming pulse. The programming verification pulse is used to obtain the number of failure bits of the first page after the first programming pulse and before the second programming pulse is applied. The verification result after programming the first page using the first programming pulse with the first signal value is a failure. The second page of the plurality of pages is programmed using only a third programming pulse, wherein the third signal value of the third programming pulse is determined based at least on the first signal value and the number of failure bits.

11. The non-volatile memory device according to claim 10, characterized in that, The first programming pulse, the second programming pulse, and the third programming pulse are all voltage pulse signals.

12. The non-volatile memory device according to claim 10, characterized in that, The first page is one, and the number of the second pages is greater than or equal to 2.

13. The non-volatile memory device according to claim 10, characterized in that, The third signal value of the third programming pulse is equal to the sum of the first signal value and the first compensation value; Wherein, the first compensation value is the difference between the first target programming pulse signal value and the first signal value of the first page, the second target programming pulse signal value of the second page is equal to the first target programming pulse signal value, and the first compensation value is obtained based on the number of failure bits of the first page.

14. The non-volatile memory device according to claim 10, characterized in that, The third signal value of the third programming pulse is determined based on the first signal value, the number of failure bits, and the positional relationship of the second page relative to the first page.

15. The non-volatile memory device according to claim 14, characterized in that, The third signal value of the third programming pulse is equal to the sum of the first signal value, the first compensation value, and the second compensation value; The first compensation value is obtained based on the number of failure bits of the first page, and the second compensation value is obtained based on the position of the second page relative to the first page.

16. The non-volatile memory device according to claim 13 or 15, characterized in that, The first compensation value is obtained based on the number of failure bits on the first page and the first correspondence. The first correspondence may include multiple fitting functions for programming pulse signal values ​​and failure bit counts, wherein the multiple fitting functions are different and are applied to pages with different erase / write cycles; or, the first correspondence may include a single fitting function for programming pulse signal values ​​and failure bit counts, wherein the fitting function is applicable to pages with different erase / write cycles.

17. The non-volatile memory device according to claim 15, characterized in that, The second compensation value is obtained based on the position of the second page and the second correspondence. The second correspondence is used to indicate the relationship between the second compensation value and the position of the second page.

18. The non-volatile memory device according to claim 10, characterized in that, The peripheral circuit is configured as follows: Perform a programmatic verification on the second page.

19. The non-volatile memory device according to claim 10, characterized in that, The non-volatile memory device includes a three-dimensional NAND flash memory device.

20. A memory system, characterized in that, include: One or more non-volatile memory devices as described in any one of claims 10 to 19; A memory controller, coupled to the non-volatile memory device and configured to control the non-volatile memory device.

21. The memory system according to claim 20, characterized in that, The non-volatile memory device includes multiple pages, and each page includes multiple single-level memory cells; The non-volatile memory device is configured to: sequentially program a first page of the plurality of pages using a first programming pulse, a programming verification pulse, and a second programming pulse; wherein the first programming pulse is a start programming pulse, the second signal value of the second programming pulse is greater than the first signal value of the first programming pulse, and the programming verification pulse is used to obtain the number of failure bits of the first page after the first programming pulse and before the second programming pulse is applied; The memory controller is configured to: determine a third signal value for a third programming pulse applied to a second page based on the first signal value and the number of failure bits; wherein the second page is different from the first page; The non-volatile memory device is configured to program the second page using only the third programming pulse.

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