Encoder self-test circuit and related methods applied to flash memory controllers

Abstract

This invention discloses an encoder self-test circuit for a flash memory controller, comprising a control circuit and an encoder. During operation of the encoder self-test circuit, without accessing any flash memory, the control circuit generates input data to the encoder. The encoder encodes the input data to generate a checksum, which is then sent to the control circuit to determine whether the encoder is functioning correctly. This self-test circuit can perform functional tests on the encoder in the flash memory controller without requiring connection to the flash memory module, accurately determining whether the encoder is malfunctioning. This avoids the inconvenience of prior art where the flash memory controller must be connected to the flash memory module before testing, leading to the need for additional stripping of the connected flash memory module when the flash memory controller malfunctions.

Description

[0001] This application is a divisional application of Chinese invention application filed on February 25, 2019, with application number 201910137901.8 and title "Encoder Self-Test Circuit and Related Method Applied to Flash Controller". Technical Field

[0002] This invention relates to flash memory controllers, and more particularly to an encoder self-test circuit used in flash memory controllers. Background Technology

[0003] At least one encoder is designed into the flash memory controller to encode the input data and generate a corresponding checksum before writing it along with the input data into the flash memory chip. However, considering the correctness of the encoder's function, during the factory testing phase, the flash memory controller is connected to the flash memory chip. The flash memory controller is then controlled to continuously encode and write data into the flash memory chip, and then read the data from the flash memory chip and decode it to determine whether the encoding and decoding functions of the flash memory controller are normal. However, the above approach encounters at least two problems. The first problem is that when the encoding and decoding functions of the flash memory controller are found to be abnormal, the flash memory chip connected to the flash memory controller is wasted, or a debonding process is required to make the flash memory chip reusable. The second problem is that when the encoding and decoding functions of the flash memory controller are found to be abnormal, it is impossible to correctly and quickly determine whether the problem lies with the encoder or the decoder, thus causing confusion for engineers. Summary of the Invention

[0004] Therefore, one of the objectives of this invention is to provide an encoder self-test circuit for a flash memory controller, which can test the encoder independently without the need for a flash memory chip, thereby solving the problems in the prior art.

[0005] In one embodiment of the present invention, an encoder self-test circuit for a flash memory controller is disclosed, comprising a control circuit and an encoder. During operation of the encoder self-test circuit, without accessing any flash memory, the control circuit generates input data to the encoder, and the encoder encodes the input data to generate a checksum, which is then sent to the control circuit to determine whether the encoder is functioning correctly.

[0006] In another embodiment of the present invention, an encoder self-testing method for a flash memory controller is disclosed, comprising the following steps: without accessing any flash memory: generating input data to an encoder; encoding the input data using the encoder to generate a check code; and determining whether the encoder is functioning correctly based on the check code. Attached Figure Description

[0007] Figure 1 This is a schematic diagram of a flash memory controller according to an embodiment of the present invention.

[0008] Figure 2 This is a schematic diagram of an encoder and control circuit according to an embodiment of the present invention.

[0009] Figure 3 This is a flowchart of an encoder self-testing method applied to a flash memory controller according to an embodiment of the present invention.

[0010] The reference numerals in the attached figures are explained as follows:

[0011] 110 Flash Controller

[0012] 112 microprocessor

[0013] 112C program code

[0014] 112M Read-Only Memory

[0015] 114 Control Logic

[0016] 116 Buffer memory

[0017] 118 Interface Logic

[0018] 120 Flash Module

[0019] 130 Main Unit

[0020] 132 encoder

[0021] 134 Control Circuit

[0022] 202, 204 pins

[0023] 210 Random Data Generation Circuit

[0024] 220 Multitasking

[0025] 230 Seed Data Generation Circuit

[0026] 240 Output Circuit

[0027] Steps 300-308

[0028] BIST_EN Self-Test Enable Signal

[0029] BIST_OUT judgment result Detailed Implementation

[0030] Figure 1 This is a schematic diagram of a flash memory controller 110 according to an embodiment of the present invention. The flash memory controller 110 is connected between a host device 130 and a flash memory module 120, and the flash memory controller 110 is used to access the flash memory module 120 according to read / write instructions from the host device 130. In this embodiment, the flash memory controller 110 includes a microprocessor 112, a read-only memory (ROM) 112M, a control logic 114, a buffer memory 116, and an interface logic 118. The read-only memory 112M is used to store program code 112C, and the microprocessor 112 is used to execute program code 112C to control access to the flash memory module 120. The control logic 114 includes an encoder 132 and a control circuit 134. The encoder 132 is used to encode the data written to the flash memory module 120 to generate a corresponding check code (or error correction code, ECC). The control circuit 134 is used to test the encoder 132, especially when the flash memory controller 110 is not yet connected to the flash memory module 120.

[0031] In a typical configuration, the flash memory module 120 includes multiple flash memory chips, and each flash memory chip includes multiple blocks. The flash memory controller 110 performs data erasure operations on the flash memory module 120 on a block-by-block basis. Additionally, a block can record a specific number of data pages, and the flash memory controller 110 performs data writing operations on the flash memory module 120 on a page-by-page basis. In this embodiment, the flash memory module 120 is a 3D NAND-type flash memory module.

[0032] In practice, the flash memory controller 110, which executes program code 112C via microprocessor 112, can utilize its internal components to perform various control operations, such as: using control logic 114 to control the access operations of flash memory module 120 (especially access operations to at least one block or at least one data page), using buffer memory 116 to perform necessary buffering operations, and using interface logic 118 to communicate with a host device 130. Buffer memory 116 is implemented as random access memory (RAM). For example, buffer memory 116 can be static random access memory (SRAM), but the invention is not limited thereto.

[0033] In one embodiment, the flash memory controller 110 may be located in a portable memory device (e.g., a memory card conforming to SD / MMC, CF, MS, or XD standards), and the main device 130 may be an electronic device that can be connected to the portable memory device, such as a mobile phone, laptop, desktop computer, etc. In another embodiment, the flash memory controller 110 may be applied to a solid-state drive or an embedded storage device conforming to Universal Flash Storage (UFS) or Embedded Multi Media Card (EMMC) specifications, and may be located in an electronic device, such as a mobile phone, laptop, or desktop computer, in which case the main device 130 may be a processor of the electronic device.

[0034] Figure 2 This is a schematic diagram of an encoder 132 and a control circuit 134 according to an embodiment of the present invention. Figure 2 As shown, the control circuit 134 includes a random data generation circuit 210, a multiplexer 220, a sub-data generation circuit 230, and an output circuit 240. In this embodiment, the control circuit 134 and the encoder 132 serve as an encoder self-test circuit, meaning that the operation of the control circuit 134 and the encoder 132 can detect and determine whether the encoder 132 is functioning correctly. Furthermore, the self-test operation of the control circuit 134 and the encoder 132 is performed in the chip probe (CP) stage of a wafer-level test or in the final test (FT) stage of a package-level test. That is, the self-test operation of the encoder 132 does not require any access to the flash memory module 120 (at this time, the flash memory controller 110 and the flash memory module 120 are not yet connected).

[0035] exist Figure 2 In the illustrated embodiment, firstly, during the chip probe stage of wafer-level testing or the final testing stage of post-packaging testing, the engineer inputs a self-test enable signal BIST_EN from the outside via a pad or pin 202 of the flash memory controller 110 to activate the encoder 132 and control circuit 134 for self-test operation. It should be noted that... Figure 2 The diagram illustrates that the self-test enable signal BIST_EN is directly input to the encoder 132 and the control circuit 134. However, the present invention is not limited thereto. In other embodiments, the flash memory controller 110 may include another circuit to receive the self-test enable signal BIST_EN and then start the encoder 132 and the control circuit 134 accordingly. These design variations are all within the scope of the present invention.

[0036] Next, the control circuit 134 generates the first input data to the encoder 132, which then encodes the data to generate a corresponding checksum. Specifically, the multiplexer 220 first switches to the upper channel to transmit a default input data as the first input data to the encoder 132. In this embodiment, the default input data is all logic values ​​"1" (0xFF) and is 2 kilobits (KB) in size, but this is not a limitation of the invention. The encoder 132 then encodes the default input data, for example, using a low-density parity-check code (LDPC code), to generate the first checksum. The size of the checksum depends on the design of the encoder 132 and may be, for example, 248 bits. Next, the seed data generation circuit 230 performs a cyclic redundancy check (CRC) operation or any other suitable hash operation on the first check code to compress the first check code into the first seed data (e.g., 16-bit seed data), which is used to provide the random data generation circuit 210 to generate the second input data of size 2 kilobytes.

[0037] The operations described above, including the multitasking unit 220 outputting the first input data to the encoder 132, the encoder 132 generating the first check code to the seed data generation circuit 230, and the seed data generation circuit 230 generating the first seed data to the random data generation circuit 210, can be regarded as the first loop operation.

[0038] Then, in the second loop operation, the multiplexer 220 switches to the lower channel to transmit the second input data generated by the random data generation circuit 210 to the encoder 132. The encoder 132 then encodes the second input data to generate a second check code, which is sent to the seed data generation circuit 230. The seed data generation circuit 230 then compresses the second check code into a second seed data, which is used to provide the random data generation circuit 210 to generate a third input data of size 2 kilobytes.

[0039] In the third cycle operation, the multiplexer 220 continues to maintain the lower channel to transmit the third input data generated by the random data generation circuit 210 to the encoder 132. The encoder 132 then encodes the third input data to generate a third check code, which is sent to the seed data generation circuit 230. The seed data generation circuit 230 then compresses the third check code into a third seed data, which is used to provide the random data generation circuit 210 to generate a fourth input data of size 2 kilobytes.

[0040] After a certain number of loop operations, for example, after N loop operations, the output circuit 240 will determine the correctness of the Nth seed data generated by the seed data generation circuit 230 to determine whether the encoder 132 is functioning normally. The determination result, BIST_OUT, will be output to other devices via a contact or pin 204 of the flash memory controller 110 for engineers' reference. Specifically, since engineers can first determine the correct value of the Nth seed data generated by the encoder 132 and control circuit 134 after N loop operations through simulation (this correct value can be pre-stored in the control circuit 134 or input separately by the engineer), the output circuit 240 can compare the Nth seed data generated by the seed data generation circuit 230 after N loop operations with this correct value. If the comparison result matches, it indicates that the encoder 132 is functioning normally; if the comparison result does not match, it indicates that the encoder 132 is malfunctioning.

[0041] In another embodiment of the present invention, the output circuit 240 can directly transmit the Nth seed data generated by the seed data generation circuit 230 to another electronic device through a contact or pin 204, so that an engineer can determine whether the encoder 132 is functioning properly.

[0042] exist Figure 2In the illustrated embodiment, the output circuit 240 is used to compare the Nth seed data with the correct value to determine whether the encoder 132 is functioning properly. However, in another embodiment, the output circuit 240 can also compare the Nth check code generated by the encoder 132 with a correct check code to determine whether the encoder 132 is functioning properly. These design variations should all fall within the scope of this invention.

[0043] As described above, the self-test operation can quickly and effectively determine whether the encoder 132 is functioning correctly. Furthermore, the self-test does not require access to any flash memory module 120; the flash memory controller 110 itself can be tested independently. This avoids the inconvenience of requiring additional stripping of the connected flash memory module 120 due to encoder 132 malfunction, as is present in existing technologies. In addition, since the encoder self-test in this embodiment does not involve decoding operations (it does not require the use of the decoder located in the control logic 114), the problem of separately determining whether the encoder or decoder is malfunctioning, as is present in existing technologies, can be avoided.

[0044] After completing the self-test operation, the engineer stops inputting the self-test enable signal BIST_EN to the flash controller 110, so that the encoder 132 and the control circuit 134 stop operating.

[0045] In the above embodiments, the number of cycles performed by the encoder 132 and control circuit 134 during self-testing (e.g., the aforementioned "N") can be any suitable value. However, considering that some circuits in the encoder 132 may require a longer testing time due to manufacturing process factors, the encoder 132 and control circuit 134 need a higher number of cycles, for example, N greater than 1000, or even N can be 100,000 or 1 million times, so that defects in the encoder 132 can be revealed in multiple cycles. On the other hand, in order to allow the encoder 132 and control circuit 134 to undergo more complete and comprehensive testing, engineers can design that these cycles do not generate the same seed data, that is, there will not be any two identical seed data from the first seed data to the Nth seed data.

[0046] Figure 3 This is a flowchart of an encoder self-test method applied to a flash memory controller according to an embodiment of the present invention. Also refer to the above... Figure 1 , 2 As described in the embodiments, Figure 3 The process is as follows.

[0047] Step 300: Process begins.

[0048] Step 302: Receive a self-test enable signal through a contact / pin of the flash memory controller to begin the self-test operation.

[0049] Step 304: Perform multiple cyclic operations using the control circuit and encoder, where each cyclic operation includes the following steps 304_1 to 304_3:

[0050] Step 304_1: The random data generation circuit generates the Kth input data;

[0051] Step 304_2: The encoder encodes the Kth input data to generate the Kth check code;

[0052] Step 304_3: The seed data generation circuit generates the Kth seed data according to the Kth check code and sends it to the random data generation circuit, then returns to step 304_1 to generate the (K+1)th input data;

[0053] Step 306: Determine whether the Nth seed data is correct to determine whether the encoder is functioning properly.

[0054] Step 308: End the self-test.

[0055] In summary, the encoder self-test circuit of this invention, applied to a flash memory controller, allows for functional testing of the encoder within the flash memory controller without requiring connection to the flash memory module, accurately determining whether the encoder is malfunctioning. This invention enables the flash memory controller to perform encoding function testing independently, avoiding the inconvenience of prior art where the flash memory controller must be connected to the flash memory module for testing, which necessitates additional stripping of the connected flash memory module when the flash memory controller malfunctions.

[0056] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. An encoder self-test circuit for application to a flash memory controller, the encoder self-test circuit comprising: Including: A control circuit; and One encoder; In the absence of any flash memory access, the control circuit generates input data to the encoder, and the encoder encodes the input data to generate a check code to the control circuit for determining whether the encoder is functioning properly. The control circuit performs multiple cyclic operations with the encoder, and each cyclic operation includes the following steps: (a) The control circuit generates the Kth input data to the encoder, where K is an arbitrary positive integer; and (b) The encoder encodes the Kth input data to generate the Kth check code and sends it to the control circuit to generate the (K+1)th input data; The Nth checksum generated by the encoder is used to determine whether the encoder is functioning correctly, where N is a default value. The control circuit includes: A random data generation circuit is used to generate the (K+1)th input data to the encoder, so that the encoder encodes the (K+1)th input data to generate the (K+1)th check code. as well as A sub-data generation circuit, coupled to the random data generation circuit, is used to generate a sub-data to the random data generation circuit based on the (K+1)th check code, so that the random data generation circuit can generate the (K+2)th input data.

2. The encoder self-test circuit of claim 1, wherein, The seed data generation circuit performs a cyclic redundancy check operation on the Kth check code to generate the seed data.

3. The encoder self-test circuit as described in claim 1, characterized in that, The control circuit also includes: A multitasking unit is used to selectively transmit either default input data or the (K+1)th input data generated by the random data generation circuit to the encoder, wherein the default input data is used as the first data generated by the control circuit to the encoder.

4. A method for encoder self-testing applied to flash memory controllers, characterized in that, Including: Without accessing any flash memory: Generate input data to an encoder; The input data is encoded using the encoder to generate a check code; as well as The verification code is used to determine whether the encoder is functioning properly. The input data is generated by a control circuit that performs multiple cyclic operations with the encoder, including the following steps: (a) The control circuit generates the Kth input data to the encoder, where K is an arbitrary positive integer; and (b) The encoder encodes the Kth input data to generate the Kth check code and sends it to the control circuit to generate the (K+1)th input data; (c) The encoder encodes the (K+1)th input data to generate the (K+1)th check code; (d) Generate a sub-data to the control circuit based on the (K+1)th check code, so that the control circuit can generate the (K+2)th input data; The Nth checksum generated by the encoder is used to determine whether the encoder is functioning properly, where N is a default value.

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