Semiconductor structure and method of forming the same

Abstract

The present disclosure relates to a semiconductor structure and a method for forming the same. The method for forming the semiconductor structure comprises the following steps: providing a substrate; forming a partition structure on a top surface of the substrate, the partition structure comprising a plurality of L-shaped stack structures arranged along a first direction, each of the L-shaped stack structures comprising a plurality of L-shaped semiconductor layers arranged along a second direction; forming word lines extending along the first direction, the word lines continuously covering all of the channel regions in each of the L-shaped stack structures in the partition structure; forming a capacitor structure on the L-shaped stack structures, the capacitor structure comprising a plurality of capacitors; and forming a bit line structure on the L-shaped stack structures, the bit line structure comprising a plurality of bit lines. Some embodiments of the present disclosure improve the performance of the semiconductor structure and enable higher storage density.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor device in computers and other electronic devices. It consists of multiple memory cells, each of which typically includes a transistor and a capacitor. The gate of the transistor is electrically connected to the word line, the source is electrically connected to the bit line, and the drain is electrically connected to the capacitor. The word line voltage on the word line can control the transistor to turn on and off, thereby allowing data information stored in the capacitor to be read or written to the capacitor via the bit line.

[0003] As semiconductor chips continue to evolve and their key dimensions shrink, the size of lithography patterns on semiconductor chips is limited by the structure of the lithography equipment itself. This has led to the development of semiconductor structures such as DRAM with three-dimensional structures. However, the storage density of these three-dimensional semiconductor structures, such as DRAM, is insufficient to meet the ever-growing demands of chip development, thus limiting the expansion of semiconductor structure applications.

[0004] Therefore, how to improve the storage density of semiconductor structures, thereby improving their performance and expanding their application areas, is a pressing technical problem that needs to be solved. Summary of the Invention

[0005] This disclosure provides semiconductor structures and methods for forming the same in some embodiments, which are used to solve the problem of low storage density in semiconductor structures, so as to improve the performance of semiconductor structures and expand the application fields of semiconductor structures.

[0006] According to some embodiments, this disclosure provides a method for forming a semiconductor structure, including the following steps:

[0007] Provide substrate;

[0008] A partitioned structure is formed on the top surface of the substrate. The partitioned structure includes a plurality of L-shaped stacked structures spaced apart along a first direction. The L-shaped stacked structures include a plurality of L-shaped semiconductor layers spaced apart along a second direction. The L-shaped semiconductor layers include a channel region and source and drain regions distributed on opposite sides of the channel region along a third direction. The first direction and the third direction are both parallel to the top surface of the substrate, the second direction is perpendicular to the top surface of the substrate, and the first direction intersects the third direction.

[0009] A word line is formed extending along the first direction, the word line continuously covering all the channel areas in each of the L-shaped stacked structures in the partition structure;

[0010] A capacitor structure is formed on the L-shaped stacked structure. The capacitor structure includes a plurality of capacitors, which extend along the second direction and are electrically connected to the drain region in the L-shaped semiconductor layer.

[0011] A bit line structure is formed on the L-shaped stacked structure. The bit line structure includes multiple bit lines that extend along the second direction and are electrically connected to the source region in the L-shaped semiconductor layer.

[0012] In some embodiments, the specific steps of forming a partitioned structure on the top surface of the substrate include:

[0013] Multiple partitioned structures are formed on the top surface of the substrate at intervals along the third direction, and the source regions of two adjacent partitioned structures are distributed relative to each other.

[0014] In some embodiments, the specific steps of forming a partitioned structure on the top surface of the substrate include:

[0015] A first dielectric layer is formed on the top surface of the substrate, and the first dielectric layer has a first groove;

[0016] An initial semiconductor layer and an initial interlayer insulating layer are alternately deposited along the second direction on the inner wall of the first groove and the top surface of the first dielectric layer to form an initial stacked layer;

[0017] The initial stacked layer is etched to form initial stacked structures spaced apart along the third direction, and a second groove located between adjacent initial stacked structures and exposing the first dielectric layer, the second groove extending along the first direction;

[0018] The initial stacked structure is etched to form a plurality of initial stacked structures spaced apart along the first direction, and a third groove located between adjacent initial stacked structures and exposing the first dielectric layer, the third groove extending along the third direction;

[0019] The initial stacked structure is etched to form an L-shaped stacked structure with its top surface flush with the top surface of the first dielectric layer. The remaining initial semiconductor layer serves as the L-shaped semiconductor layer, and the remaining initial interlayer insulating layer serves as the L-shaped interlayer insulating layer.

[0020] In some embodiments, the specific steps of forming initial stacked structures spaced apart along the third direction, and second grooves located between adjacent initial stacked structures and exposing the first dielectric layer, include:

[0021] The initial stacked layer is etched using a trimming-etching process to form the initial stacked structure with stepped ends and the second groove located between adjacent initial stacked structure layers.

[0022] In some embodiments, the L-shaped semiconductor layer comprises a first portion extending along the second direction and a second portion extending along the third direction and connected to the bottom of the first portion;

[0023] The drain region is located in the first part, and the channel region and the source region are located in the second part.

[0024] In some embodiments, the specific steps of forming word lines extending along the first direction include:

[0025] A second dielectric layer is formed covering the surface of the L-shaped laminated structure and the inner wall of the third groove;

[0026] A first conductive material is deposited on the surface of the second dielectric layer;

[0027] The first conductive material is etched to form word lines that extend along the first direction and continuously cover all the channel regions in each of the L-shaped stacked structures in the partitioned structure.

[0028] In some embodiments, the specific steps of forming a capacitor structure on the L-shaped stacked structure include:

[0029] A third dielectric layer is formed that fills the second and third grooves and covers the surface of the partition structure;

[0030] The third dielectric layer is etched to form multiple capacitor holes that expose multiple drain regions respectively;

[0031] A capacitor is formed within the capacitor hole.

[0032] In some embodiments, the specific steps of forming a capacitor within the capacitor hole include:

[0033] A lower electrode layer is formed that covers the sidewall of the capacitor hole and is in contact with and electrically connected to the drain region;

[0034] A dielectric layer is formed covering the surface of the lower electrode layer;

[0035] An upper electrode layer is formed that covers the surface of the dielectric layer and fills the capacitor holes.

[0036] In some embodiments, the specific steps of forming a bit line structure on the L-shaped stacked structure include:

[0037] A fourth dielectric layer is formed covering the third dielectric layer;

[0038] Etch the fourth dielectric layer, the third dielectric layer, and the L-shaped stacked structure to form bit line vias that expose the source region;

[0039] A second conductive material is filled into the bit line hole to form the bit line that is electrically connected to the source region.

[0040] In some embodiments, the following steps are also included:

[0041] The fourth dielectric layer, the third dielectric layer, and the L-shaped stacked structure are etched to form bit line holes that expose the source region, and simultaneously form plug holes that expose the upper electrode layer;

[0042] A second conductive material is filled into the bit line hole and the plug hole to form the bit line that is electrically connected to the source region, and at the same time to form the contact plug that is electrically connected to the upper electrode layer.

[0043] According to other embodiments, this disclosure also provides a semiconductor structure, including:

[0044] Substrate;

[0045] A partitioned structure is located on the top surface of the substrate. The partitioned structure includes a plurality of L-shaped stacked structures spaced apart along a first direction. The L-shaped stacked structures include a plurality of L-shaped semiconductor layers spaced apart along a second direction. The L-shaped semiconductor layers include a channel region and source and drain regions distributed on opposite sides of the channel region along a third direction. The first direction and the third direction are both parallel to the top surface of the substrate, the second direction is perpendicular to the top surface of the substrate, and the first direction intersects the third direction.

[0046] The character line extends along the first direction and continuously covers all the channel areas in each of the L-shaped stacked structures in the partition structure;

[0047] A capacitor structure is located on the L-shaped stacked structure. The capacitor structure includes a plurality of capacitors, which extend along the second direction and are electrically connected to the drain region in the L-shaped semiconductor layer.

[0048] A bit line structure is located on the L-shaped stacked structure. The bit line structure includes multiple bit lines that extend along the second direction and are electrically connected to the source region in the L-shaped semiconductor layer.

[0049] In some embodiments, the number of partition structures is multiple, the multiple partition structures are arranged at intervals along the third direction, and the source regions of two adjacent partition structures are relatively distributed.

[0050] In some embodiments, the L-shaped semiconductor layer comprises a first portion extending along the second direction and a second portion extending along the third direction and connected to the bottom of the first portion;

[0051] The drain region is located in the first part, and the channel region and the source region are located in the second part.

[0052] In some embodiments, in any two adjacent L-shaped semiconductor layers in the L-shaped stacked structure, the L-shaped semiconductor layer closer to the substrate protrudes from the other L-shaped semiconductor layer along the third direction.

[0053] In some embodiments, the capacitor includes a lower electrode layer electrically connected to the drain region, a dielectric layer covering the surface of the lower electrode layer, and an upper electrode layer covering the surface of the dielectric layer; the semiconductor structure further includes:

[0054] A contact plug, extending along the second direction and located above the capacitor, is electrically connected to the upper electrode layer of the capacitor.

[0055] The semiconductor structure and its formation method provided in some embodiments of this disclosure form a partitioned structure on the top surface of a substrate. The partitioned structure includes multiple L-shaped stacked structures spaced apart along a first direction. Each L-shaped stacked structure includes multiple L-shaped semiconductor layers spaced apart along a second direction. Each L-shaped semiconductor layer includes a channel region and source and drain regions distributed on opposite sides of the channel region along a third direction, forming an L-shaped channel. This extends the channel length, reduces quantum tunneling effects within the channel, and reduces leakage current, thereby improving the performance of the semiconductor structure. Furthermore, the L-shaped stacked structure in this disclosure enables higher storage density. The capacitors and bit lines in the semiconductor structure extend along a direction perpendicular to the top surface of the substrate and are located on the L-shaped stacked structure, which helps reduce the area occupied by a single memory cell, thereby further increasing the storage density of the semiconductor structure and expanding its application areas. Attached Figure Description

[0056] Appendix Figure 1 This is a flowchart of a method for forming a semiconductor structure according to a specific embodiment of this disclosure;

[0057] Appendix Figure 2A-2U This is a schematic diagram of the main process structure in the formation of the semiconductor structure according to the specific embodiments of this disclosure;

[0058] Appendix Figures 3A-3C This is a schematic diagram of the semiconductor structure in a specific embodiment of this disclosure. Detailed Implementation

[0059] The specific embodiments of the semiconductor structure and its formation method provided in this disclosure will be described in detail below with reference to the accompanying drawings.

[0060] This specific embodiment provides a method for forming a semiconductor structure, with appended... Figure 1 This is a flowchart illustrating the method for forming a semiconductor structure according to a specific embodiment of this disclosure, with appended... Figure 2A-2U This is a schematic diagram of the main process structure during the formation of the semiconductor structure in a specific embodiment of this disclosure. The semiconductor structure described in this embodiment can be, but is not limited to, DRAM. For example... Figure 1 , Figures 2A-2U As shown, the method for forming a semiconductor structure provided in this specific embodiment includes the following steps:

[0061] Step S11, provide substrate 20, such as Figure 2A As shown.

[0062] Specifically, the substrate 20 may be, but is not limited to, a silicon substrate. This specific embodiment uses a silicon substrate as an example for illustration. In other embodiments, the substrate 20 may also be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide, or SOI. The substrate 20 is used to support the device structure placed on it.

[0063] Step S12: A partition structure 40 is formed on the top surface of the substrate 20. The partition structure 40 includes a plurality of L-shaped stacked structures 25 spaced apart along a first direction D1. Each L-shaped stacked structure 25 includes a plurality of L-shaped semiconductor layers 261 spaced apart along a second direction D2. Each L-shaped semiconductor layer 261 includes a channel region PC and source regions PS and drain regions PD distributed on opposite sides of the channel region along a third direction D3. The first direction D1 and the third direction D3 are both parallel to the top surface of the substrate 20, and the second direction D2 is perpendicular to the top surface of the substrate 20. The first direction D1 intersects the third direction D3. Figure 2I As shown in Figure J, where, Figure 2I This is a top view of the structure after the partition structure 40 is formed on the top surface of the substrate 20. Figure 2J yes Figure 2I A schematic diagram of the cross-section along the CD direction.

[0064] In this specific embodiment, the L-shaped semiconductor layer 261 refers to a semiconductor layer in an L-shape. For example, such as... Figure 2RAs shown, the L-shaped semiconductor layer 261 includes a first portion P1 extending along the second direction D2 and a second portion P2 extending along the third direction D3 and connected to the bottom of the first portion P1. The L-shaped stacked structure 25 refers to a stacked structure in the shape of an L. For example, the L-shaped stacked structure 25 includes a third portion extending along the second direction D2 and a fourth portion extending along the third direction D3 and connected to the bottom of the third portion. In any two adjacent L-shaped semiconductor layers 261 in the L-shaped stacked structure 25, the L-shaped semiconductor layer 261 farther from the substrate 20 is located above the second portion P2 of the other L-shaped semiconductor layer 261.

[0065] In some embodiments, the specific steps of forming the partition structure 40 on the top surface of the substrate 20 include:

[0066] Multiple partition structures 40 are formed on the top surface of the substrate 20 at intervals along the third direction D3, and the source regions PS of two adjacent partition structures 40 are relatively distributed.

[0067] Specifically, by forming a plurality of partition structures 40 on the top surface of the substrate 20, a four-dimensional semiconductor structure is formed, which helps to increase the storage density of the semiconductor structure while further reducing its size.

[0068] In some embodiments, the specific steps of forming the partition structure 40 on the top surface of the substrate 20 include:

[0069] A first dielectric layer 21 is formed on the top surface of the substrate 20, and the first dielectric layer 21 has a first groove 211, such as... Figure 2A As shown;

[0070] An initial semiconductor layer 221 and an initial interlayer insulating layer 222 are alternately deposited along the second direction D2 on the inner wall of the first groove 211 and the top surface of the first dielectric layer 21 to form an initial stacked layer 22, as shown below. Figure 2B and Figure 2C As shown, where, Figure 2C yes Figure 2B A schematic diagram of the cross-section along the AB direction;

[0071] The initial stacked layer 22 is etched to form initial stacked structures 402 spaced along the third direction D3, and second grooves 23 located between adjacent initial stacked structures 402 and exposing the first dielectric layer 21. The second grooves 23 extend along the first direction D1, as shown below. Figure 2D and Figure 2E As shown, where, Figure 2EThis is a top view of the structure after the second groove 23 has been formed. Figure 2D yes Figure 2E A schematic diagram of the cross-section along the CD direction.

[0072] The initial stacked structure 402 is etched to form a plurality of initial stacked structures 251 spaced apart along the first direction D1, and a third groove 24 located between adjacent initial stacked structures 251 and exposing the first dielectric layer 21. The third groove 24 extends along the third direction D3, such as... Figure 2F , Figure 2G and Figure 2H As shown, where, Figure 2F This is a top view of the structure after the third groove 24 has been formed. Figure 2G yes Figure 2F A schematic diagram of the cross-section along the CD direction. Figure 2H yes Figure 2F Schematic diagram of the cross section along the EF direction;

[0073] The initial stacked structure 251 is etched to form an L-shaped stacked structure 25 with its top surface flush with the top surface of the first dielectric layer 21. The remaining initial semiconductor layer 221 serves as the L-shaped semiconductor layer 261, and the remaining initial interlayer insulating layer 222 serves as the L-shaped interlayer insulating layer 262. Figure 2I and Figure 2J As shown, where, Figure 2I This is a top view of the structure after the L-shaped laminated structure 25 has been formed. Figure 2J yes Figure 2I A schematic diagram of the cross-section along the CD direction.

[0074] Specifically, insulating materials such as TEOS (tetraethyl orthosilicate) can be deposited on the top surface of the substrate 20 using chemical vapor deposition, physical vapor deposition, or atomic layer deposition to form the first dielectric layer 21 covering the top surface of the substrate 20. Then, the first dielectric layer 21 is etched to form a first groove 211 that penetrates the first dielectric layer 21 along the first direction D1 but does not penetrate the dielectric layer 21 along the second direction D2 or the third direction D3. Figure 2A As shown. The first groove 211 is formed to facilitate the subsequent formation of the L-shaped semiconductor layer 261. After forming the first groove 211, the initial semiconductor layer 221 and the initial interlayer insulating layer 222 can be alternately deposited along the second direction D2 using chemical vapor deposition, physical vapor deposition, or atomic layer deposition to form an initial stacked layer 22, such as... Figure 2Band Figure 2C As shown. In some embodiments, the initial semiconductor layer 211 can be made of polycrystalline silicon including doped ions, thereby eliminating the need for subsequent doping processes and simplifying the fabrication process of the semiconductor structure. In some embodiments, the initial interlayer insulating layer 222 can be made of an oxide material (e.g., silicon dioxide). The specific number of alternating depositions of the initial semiconductor layer 221 and the initial interlayer insulating layer 222 in the initial stacked layer 22 can be selected by those skilled in the art according to actual needs. The more alternating depositions of the initial semiconductor layer 221 and the initial interlayer insulating layer 222 in the initial stacked layer 22, the greater the storage capacity of the formed semiconductor structure.

[0075] The initial stacked layer 22 is etched using photolithography to form a second groove 23 that penetrates the initial stacked layer 22 along the second direction D2 and exposes the first dielectric layer 21. For example... Figure 2D and Figure 2E As shown, the second groove 23 penetrates the initial stacked layer 22 along the first direction D1 to divide the initial stacked layer 22 into two initial stacked structures 402 spaced apart along the third direction D3. Then, a photolithography process is used again to simultaneously etch the two initial stacked structures 402 to form the third groove 24, which penetrates the initial stacked structure 402 along the second direction D2 and exposes the first dielectric layer 21. Figure 2F , Figure 2G and Figure 2H As shown. The third groove 24 extends along the third direction D3, thereby dividing the initial stacked structure 402 into a plurality of initial stacked structures 251 spaced apart along the first direction. The plurality of initial stacked structures 251 spaced apart along the first direction D1, and the third groove 24 between two adjacent initial stacked structures 251 along the first direction D1, together constitute the initial partitioning structure 401, as shown. Figure 2F As shown. Next, a first photoresist layer is formed on the surface of the initial stacked structure 251 and the inner wall of the third groove 24, and the first photoresist layer is patterned to form an opening in the first photoresist layer that exposes only the top surface of the first dielectric layer 21 of the initial stacked structure 251. The initial stacked structure 251 is etched along the opening to remove the initial stacked structure 251 on the top surface of the first dielectric layer 21, and the initial stacked structure 251 remaining inside the first groove 211 serves as the L-shaped stacked structure 25, as shown. Figure 2I and Figure 2JAs shown. The remaining initial semiconductor layer 221 serves as the L-shaped semiconductor layer 261, and the remaining initial interlayer insulating layer 222 serves as the L-shaped interlayer insulating layer 262. The plurality of L-shaped stacked structures 25 arranged at intervals along the first direction D1, and the third groove 24 between two adjacent L-shaped stacked structures 25 along the first direction D1, together serve as the partition structure 40.

[0076] In some embodiments, the specific steps of forming an initial stacked structure 402 spaced along the third direction D3, and a second groove 23 located between adjacent initial stacked structures 402 and exposing the first dielectric layer 21 include:

[0077] The initial stacked layer 22 is etched using a trimming-etching process to form the initial stacked structure 402 with stepped ends and the second groove 23 located between adjacent initial stacked structures 402.

[0078] Specifically, a second photoresist layer is formed on the surface of the initial stacked layer 22. Then, a trimming-etching process is used to etch the initial stacked layer 22, i.e., the initial stacked layer 22 is etched multiple times by trimming the second photoresist layer, forming two initial stacked structures 402 and a second groove 23 located between the two initial stacked structures 402. The opposite ends of the two initial stacked structures 402 are stepped (i.e., the sidewalls of the second groove 23 are stepped). The stepped ends of the initial stacked structures 402 mean that one initial semiconductor layer 221 and an initial interlayer insulating layer 222 located on its surface and adjacent to it form a sub-stacked layer. In any two adjacent sub-stacked layers along the second direction D2, the sub-stacked layer closer to the substrate 20 protrudes beyond the other sub-stacked layer along the third direction D3. By setting the ends of the initial stacked structure 402 in a stepped shape, it is easier to form bit line contacts at the stepped ends, thereby leading out each of the L-shaped semiconductor layers 261 in the L-shaped stacked structure 25, reducing the space occupied by the bit lines on the surface of the substrate 20, and further improving the integration of the semiconductor structure.

[0079] In some embodiments, the L-shaped semiconductor layer 261 has a first portion P1 extending along the second direction D2, and a second portion P2 extending along the third direction D3 and connected to the bottom of the first portion D1;

[0080] The drain region PD is located in the first part P1, and the channel region PC and the source region PS are located in the second part P2.

[0081] Step S13, forming a word line 28 extending along the first direction D1, the word line 28 continuously covering all the channel regions PC in each of the L-shaped stacked structures 25 in the partition structure 40, such as Figure 2L , Figure 2M and Figure 2N As shown, where, Figure 2L This is a top view of the structure after the character line 28 is formed. Figure 2M yes Figure 2L A schematic diagram of the cross-section along the CD direction. Figure 2N yes Figure 2L A schematic diagram of the cross-section along the EF direction.

[0082] In some embodiments, the specific steps of forming the word line 28 extending along the first direction D1 include:

[0083] A second dielectric layer 27 is formed, covering the surface of the L-shaped laminated structure 25 and the inner wall of the third groove 24, such as... Figure 2K As shown;

[0084] A first conductive material is deposited on the surface of the second dielectric layer 27;

[0085] The first conductive material is etched to form word lines 28 that extend along the first direction D1 and continuously cover all the channel regions PC in each of the L-shaped stacked structures 25 in the partition structure 40.

[0086] Specifically, a dielectric material such as an oxide (e.g., silicon dioxide) is deposited on the surface of the partition structure 40 to form a second dielectric layer 27 covering the L-shaped stacked structure 25, such as... Figure 2K As shown. The second dielectric layer 27 serves as the gate dielectric layer. Subsequently, a first conductive material, such as tungsten, is deposited on the surface of the second dielectric layer 27, and the word line 28 is formed by etching back the first conductive material. Each word line 28 extends along the first direction D1 and continuously covers all the channel regions PC in each of the L-shaped stacked structures 25 within a partition structure 40, so that all transistors in a partition structure 40 can be simultaneously turned on through a single word line 28. The transistor includes the channel region PC, the source region PS, and the drain region PD located in the same L-shaped semiconductor layer 261.

[0087] Step S14: A capacitor structure is formed on the L-shaped stacked structure 25. The capacitor structure includes a plurality of capacitors 31. The capacitors 31 extend along the second direction D2 and are electrically connected to the drain region PD in the L-shaped semiconductor layer 261. Figure 2Q , Figure 2R and Figure 2S As shown, where, Figure 2QThis is a top view of the structure after the capacitor structure is formed. Figure 2R yes Figure 2Q A schematic diagram of the cross-section along the CD direction. Figure 2S This is a schematic diagram showing the connection between the L-shaped semiconductor layer 261 and the capacitor 31.

[0088] In some embodiments, the specific steps of forming a capacitor structure on the L-shaped stacked structure 25 include:

[0089] A third dielectric layer 29 is formed, filling the second groove 23 and the third groove 24 and covering the surface of the partition structure 40, as shown in the example. Figure 2O As shown;

[0090] The third dielectric layer 29 is etched to form a plurality of capacitor vias 30 that expose a plurality of drain regions PD, such as Figure 2P As shown;

[0091] A capacitor 31 is formed within the capacitor hole 30, such as Figure 2Q , Figure 2R and Figure 2S As shown.

[0092] In some embodiments, the specific steps of forming the capacitor 31 within the capacitor hole 30 include:

[0093] A lower electrode layer 311 is formed that covers the sidewall of the capacitor hole 30 and is electrically connected to the drain region PD.

[0094] A dielectric layer 312 is formed covering the surface of the lower electrode layer 311;

[0095] An upper electrode layer 313 is formed that covers the surface of the dielectric layer 312 and fills the capacitor hole.

[0096] Specifically, a first sub-dielectric layer 291 and a second sub-dielectric layer 292 are alternately deposited along the second direction D2 to form a third dielectric layer 29 that fills the second groove 23 and the third groove 24 and covers the surface of the partition structure 40. The material of the first sub-dielectric layer 291 may be, but is not limited to, TEOS, and the material of the second sub-dielectric layer 292 may be, but is not limited to, a nitride material (e.g., silicon nitride). By forming the third dielectric layer 29 with the alternately arranged first sub-dielectric layers 291 and second sub-dielectric layers 292, on the one hand, the morphology of the subsequently formed capacitor hole 30 with a high aspect ratio can be ensured; on the other hand, the parasitic capacitance effect inside the third dielectric layer 29 can be reduced. After forming the capacitor hole 30, a selective atomic deposition process can be used to deposit the lower electrode layer 311 on the sidewall of the capacitor hole 30, making the lower electrode layer 311 electrically connected to the drain region PD. Subsequently, a dielectric layer 312 covering the surface of the lower electrode layer 311 and an upper electrode layer 313 covering the surface of the dielectric layer 312 and filling the capacitor holes are formed, as follows. Figure 2S As shown.

[0097] Step S15: A bit line structure is formed on the L-shaped stacked structure 25. The bit line structure includes multiple bit lines 33. The bit lines 33 extend along the second direction D2 and are electrically connected to the source region PS in the L-shaped semiconductor layer 261.

[0098] In some embodiments, the specific steps for forming a bit line structure on the L-shaped stacked structure 25 include:

[0099] Forming a fourth dielectric layer 32 covering the third dielectric layer 29, such as Figure 2T As shown;

[0100] The fourth dielectric layer 32, the third dielectric layer 29 and the L-shaped stacked structure 25 are etched to form bit line vias that expose the source region PS;

[0101] A second conductive material is filled into the bit line hole to form the bit line 33, which is electrically connected to the source region PS contact.

[0102] In some embodiments, the method for forming the semiconductor structure further includes the following steps:

[0103] The fourth dielectric layer 32, the third dielectric layer 29 and the L-shaped stacked structure 25 are etched to form bit line holes that expose the source region PS, and at the same time to form plug holes that expose the upper electrode layer 312.

[0104] A second conductive material is filled into the bit line hole and the plug hole to form the bit line 33, which is electrically connected to the source region PS, and simultaneously to form the contact plug 34, which is electrically connected to the upper electrode layer 312. Figure 2U As shown.

[0105] Specifically, a third sub-dielectric layer 321 is sequentially deposited on the surface of the third sub-dielectric layer 29, and a fourth sub-dielectric layer 322 is deposited on the surface of the third sub-dielectric layer 321, forming the fourth dielectric layer 32 comprising the third sub-dielectric layer 321 and the fourth sub-dielectric layer 322. Then, a deep-hole etching process can be used to etch the fourth dielectric layer 32, the third dielectric layer 29, and the L-shaped stacked structure 25 to form bit line vias exposing the source region PS, and simultaneously form plug vias exposing the upper electrode layer 312. Next, a second conductive material such as tungsten is deposited within the bit line vias and the plug vias, simultaneously forming the bit line 33 and the contact plug 34, further simplifying the semiconductor structure fabrication process.

[0106] This specific embodiment also provides a semiconductor structure, attached... Figures 3A-3C This is a schematic diagram of a semiconductor structure in a specific embodiment of this disclosure, wherein, Figure 3A This is a top view schematic diagram of the semiconductor structure. Figure 3B It is along Figure 3A A schematic diagram of the cross-section along the CD direction. Figure 3C It is along Figure 3A A schematic diagram of the cross-section along the EF direction. Figure 3A The dashed box only indicates the relative positional relationship between the partition structure 40 and the L-shaped stacked structure 25 on the substrate 20. The semiconductor structure provided in this specific embodiment can adopt, for example... Figure 1 , Figures 2A-2U The semiconductor structure shown is formed using the method described. Figures 2A-2U ,as well as Figures 3A-3C As shown, the semiconductor structure includes:

[0107] Substrate 20;

[0108] A partition structure 40 is located on the top surface of the substrate 20. The partition structure 40 includes a plurality of L-shaped stacked structures 25 spaced apart along a first direction D1. Each L-shaped stacked structure 25 includes a plurality of L-shaped semiconductor layers 261 spaced apart along a second direction D2. Each L-shaped semiconductor layer 261 includes a channel region PC and source regions PS and drain regions PD distributed on opposite sides of the channel region PC along a third direction D3. The first direction D1 and the third direction D3 are both parallel to the top surface of the substrate 20, and the second direction D2 is perpendicular to the top surface of the substrate 20. The first direction D1 intersects the third direction D3. Figure 2I , Figure 2J ,as well as Figures 3A-3C As shown;

[0109] The character line 28 extends along the first direction D1 and continuously covers all the channel areas PC in each of the L-shaped stacked structures 25 in the partition structure 40;

[0110] A capacitor structure is located on the L-shaped stacked structure 25. The capacitor structure includes a plurality of capacitors 31. The capacitors 31 extend along the second direction D2 and are electrically connected to the drain region PD in the L-shaped semiconductor layer 261.

[0111] The bit line structure is located on the L-shaped stacked structure 25. The bit line structure includes multiple bit lines 33, which extend along the second direction D2 and are electrically connected to the source region PS in the L-shaped semiconductor layer 261.

[0112] In some embodiments, there are multiple partition structures 40, which are arranged at intervals along the third direction D3, and the source pole regions PS of two adjacent partition structures 40 are relatively distributed.

[0113] In some embodiments, the L-shaped semiconductor layer 261 has a first portion P1 extending along the second direction D2, and a second portion P2 extending along the third direction D3 and connected to the bottom of the first portion P1;

[0114] The drain region PD is located in the first portion P1, and the channel region PC and the source region PS are located in the second portion P2. See below. Figure 2S .

[0115] In some embodiments, in any two adjacent L-shaped semiconductor layers 261 of the L-shaped stacked structure 25, the L-shaped semiconductor layer 261 closer to the substrate 20 protrudes from the other L-shaped semiconductor layer 261 along the third direction D3.

[0116] In some embodiments, the capacitor 31 includes a lower electrode layer 311 electrically connected to the drain region PD, a dielectric layer 312 covering the surface of the lower electrode layer 311, and an upper electrode layer 313 covering the surface of the dielectric layer 312; the semiconductor structure further includes:

[0117] Contact plug 34 extends along the second direction D2 and is located above the capacitor 31, and the contact plug 34 is electrically connected to the upper electrode layer 313 of the capacitor 31.

[0118] The semiconductor structure and its formation method provided in some embodiments of this specific implementation form a partitioned structure on the top surface of a substrate. The partitioned structure includes multiple L-shaped stacked structures spaced apart along a first direction. Each L-shaped stacked structure includes multiple L-shaped semiconductor layers spaced apart along a second direction. Each L-shaped semiconductor layer includes a channel region and source and drain regions distributed on opposite sides of the channel region along a third direction, forming an L-shaped channel. This extends the channel length, reduces the quantum tunneling effect within the channel, and reduces leakage current, thereby improving the performance of the semiconductor structure. Furthermore, the L-shaped stacked structure in this disclosure can achieve higher storage density. The capacitors and bit lines in the semiconductor structure extend along a direction perpendicular to the top surface of the substrate and are located on the L-shaped stacked structure, which helps to reduce the area occupied by a single memory cell, thereby further increasing the storage density of the semiconductor structure and expanding its application areas.

[0119] The above description is only a preferred embodiment of this disclosure. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principles of this disclosure, and these improvements and modifications should also be considered within the scope of protection of this disclosure.

Claims

1. A method for forming a semiconductor structure, characterized in that, Includes the following steps: Provide substrate; A partitioned structure is formed on the top surface of the substrate. The partitioned structure includes a plurality of L-shaped stacked structures spaced apart along a first direction. The L-shaped stacked structures include a plurality of L-shaped semiconductor layers spaced apart along a second direction. The L-shaped semiconductor layers include a channel region and source and drain regions distributed on opposite sides of the channel region along a third direction. The first direction and the third direction are both parallel to the top surface of the substrate, the second direction is perpendicular to the top surface of the substrate, and the first direction intersects the third direction. A word line is formed extending along the first direction, the word line continuously covering all the channel areas in each of the L-shaped stacked structures in the partition structure; A capacitor structure is formed on the L-shaped stacked structure. The capacitor structure includes a plurality of capacitors, which extend along the second direction and are electrically connected to the drain region in the L-shaped semiconductor layer. A bit line structure is formed on the L-shaped stacked structure. The bit line structure includes multiple bit lines that extend along the second direction and are electrically connected to the source region in the L-shaped semiconductor layer.

2. The method for forming a semiconductor structure according to claim 1, characterized in that, The specific steps for forming the partitioned structure on the top surface of the substrate include: Multiple partitioned structures are formed on the top surface of the substrate at intervals along the third direction, and the source regions of two adjacent partitioned structures are distributed relative to each other.

3. The method for forming a semiconductor structure according to claim 2, characterized in that, The specific steps for forming the partitioned structure on the top surface of the substrate include: A first dielectric layer is formed on the top surface of the substrate, and the first dielectric layer has a first groove; An initial semiconductor layer and an initial interlayer insulating layer are alternately deposited along the second direction on the inner wall of the first groove and the top surface of the first dielectric layer to form an initial stacked layer; The initial stacked layer is etched to form initial stacked structures spaced apart along the third direction, and a second groove located between adjacent initial stacked structures and exposing the first dielectric layer, the second groove extending along the first direction; The initial stacked structure is etched to form a plurality of initial stacked structures spaced apart along the first direction, and a third groove located between adjacent initial stacked structures and exposing the first dielectric layer, the third groove extending along the third direction; The initial stacked structure is etched to form an L-shaped stacked structure with its top surface flush with the top surface of the first dielectric layer. The remaining initial semiconductor layer serves as the L-shaped semiconductor layer, and the remaining initial interlayer insulating layer serves as the L-shaped interlayer insulating layer.

4. The method for forming a semiconductor structure according to claim 3, characterized in that, The specific steps for forming the initial stacked structures spaced apart along the third direction and the second grooves located between adjacent initial stacked structures and exposing the first dielectric layer include: The initial stacked layer is etched using a trimming-etching process to form the initial stacked structure with stepped ends and the second groove located between adjacent initial stacked structure layers.

5. The method for forming a semiconductor structure according to claim 3, characterized in that, The L-shaped semiconductor layer has a first portion extending along the second direction and a second portion extending along the third direction and connected to the bottom of the first portion; The drain region is located in the first part, and the channel region and the source region are located in the second part.

6. The method for forming a semiconductor structure according to claim 5, characterized in that, The specific steps for forming the character lines extending along the first direction include: A second dielectric layer is formed covering the surface of the L-shaped laminated structure and the inner wall of the third groove; A first conductive material is deposited on the surface of the second dielectric layer; The first conductive material is etched to form word lines that extend along the first direction and continuously cover all the channel regions in each of the L-shaped stacked structures in the partitioned structure.

7. The method for forming a semiconductor structure according to claim 5, characterized in that, The specific steps for forming a capacitor structure on the L-shaped stacked structure include: A third dielectric layer is formed that fills the second and third grooves and covers the surface of the partition structure; The third dielectric layer is etched to form multiple capacitor holes that expose multiple drain regions respectively; A capacitor is formed within the capacitor hole.

8. The method for forming a semiconductor structure according to claim 7, characterized in that, The specific steps for forming a capacitor within the capacitor hole include: A lower electrode layer is formed that covers the sidewall of the capacitor hole and is in contact with and electrically connected to the drain region; A dielectric layer is formed covering the surface of the lower electrode layer; An upper electrode layer is formed that covers the surface of the dielectric layer and fills the capacitor holes.

9. The method for forming a semiconductor structure according to claim 8, characterized in that, The specific steps for forming a bit line structure on the L-shaped stacked structure include: A fourth dielectric layer is formed covering the third dielectric layer; Etch the fourth dielectric layer, the third dielectric layer, and the L-shaped stacked structure to form bit line vias that expose the source region; A second conductive material is filled into the bit line hole to form the bit line that is electrically connected to the source region.

10. The method for forming a semiconductor structure according to claim 9, characterized in that, It also includes the following steps: The fourth dielectric layer, the third dielectric layer, and the L-shaped stacked structure are etched to form bit line holes that expose the source region, and simultaneously form plug holes that expose the upper electrode layer. A second conductive material is filled into the bit line hole and the plug hole to form the bit line that is electrically connected to the source region, and at the same time, a contact plug that is electrically connected to the upper electrode layer is formed.

11. A semiconductor structure, characterized in that, include: Substrate; A partitioned structure is located on the top surface of the substrate. The partitioned structure includes a plurality of L-shaped stacked structures spaced apart along a first direction. The L-shaped stacked structures include a plurality of L-shaped semiconductor layers spaced apart along a second direction. The L-shaped semiconductor layers include a channel region and source and drain regions distributed on opposite sides of the channel region along a third direction. The first direction and the third direction are both parallel to the top surface of the substrate, the second direction is perpendicular to the top surface of the substrate, and the first direction intersects the third direction. The character line extends along the first direction and continuously covers all the channel areas in each of the L-shaped stacked structures in the partition structure; A capacitor structure is located on the L-shaped stacked structure. The capacitor structure includes a plurality of capacitors, which extend along the second direction and are electrically connected to the drain region in the L-shaped semiconductor layer. A bit line structure is located on the L-shaped stacked structure. The bit line structure includes multiple bit lines that extend along the second direction and are electrically connected to the source region in the L-shaped semiconductor layer.

12. The semiconductor structure according to claim 11, characterized in that, The number of partition structures is multiple, and the multiple partition structures are arranged at intervals along the third direction, with the source regions of two adjacent partition structures being relatively distributed.

13. The semiconductor structure according to claim 12, characterized in that, The L-shaped semiconductor layer comprises a first portion extending along the second direction and a second portion extending along the third direction and connected to the bottom of the first portion; The drain region is located in the first part, and the channel region and the source region are located in the second part.

14. The semiconductor structure according to claim 13, characterized in that, In the L-shaped stacked structure, among any two adjacent L-shaped semiconductor layers, the L-shaped semiconductor layer closer to the substrate protrudes from the other L-shaped semiconductor layer along the third direction.

15. The semiconductor structure according to claim 11, characterized in that, The capacitor includes a lower electrode layer that is electrically connected to the drain region, a dielectric layer covering the surface of the lower electrode layer, and an upper electrode layer covering the surface of the dielectric layer. The semiconductor structure further includes a contact plug extending along the second direction and located above the capacitor, the contact plug being electrically connected to the upper electrode layer of the capacitor.

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