Semiconductor structure and method of forming the same, memory

Abstract

The present disclosure relates to the technical field of semiconductor technology, and relates to a semiconductor structure, a forming method thereof and a memory. The forming method comprises the following steps: providing a substrate; forming a first active layer on one side of the substrate, the first active layer comprising a plurality of spaced active regions; forming a first word line in each active region; forming a first bit line and a conductive contact plug on the top of the first active layer, the first bit line, the conductive contact plug and the first word line being insulated from each other; forming a gate dielectric layer on the side of the first active layer, the first bit line and the conductive contact plug away from the substrate; forming a second active layer on the side of the gate dielectric layer away from the substrate; and forming a second bit line and a second word line on the side of the second active layer away from the substrate, the second bit line and the second word line being respectively in contact with the second active layer. The forming method can reduce leakage and power consumption.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a semiconductor structure and a method for forming the same, and a memory. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is widely used in mobile devices such as mobile phones and tablets due to its advantages such as small size, high integration, and high transmission speed. Current DRAM mainly consists of transistors and capacitors. However, during data storage, the capacitor's charge retention time is short, requiring constant refreshing of the capacitor's charge to prevent data loss, resulting in high device power consumption and leakage current.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] In view of this, the present disclosure provides a semiconductor structure and a method for forming the same, as well as a memory, which can reduce leakage current and power consumption.

[0005] According to one aspect of this disclosure, a method for forming a semiconductor structure is provided, comprising:

[0006] Provide substrate;

[0007] A first active layer is formed on one side of the substrate, the first active layer comprising a plurality of spaced active regions;

[0008] A first word line is formed in each of the active regions;

[0009] A first bit line and a conductive contact plug are formed on the top of the first active layer, and the first bit line, the conductive contact plug and the first word line are insulated from each other;

[0010] A gate dielectric layer is formed on the side of the first active layer, the first bit line, and the conductive contact plug that is away from the substrate;

[0011] A second active layer is formed on the side of the gate dielectric layer opposite to the substrate;

[0012] A second bit line and a second word line are formed on the side of the second active layer away from the substrate, and the second bit line and the second word line are respectively connected to the second active layer.

[0013] In one exemplary embodiment of this disclosure, the first active layer is formed on one side of the substrate, including:

[0014] A first insulating layer is formed on the substrate;

[0015] A semiconductor layer is formed on the first insulating layer;

[0016] The semiconductor layer is etched to form a plurality of spaced isolation trenches in the semiconductor layer; the plurality of isolation trenches divide the semiconductor layer into a plurality of active regions.

[0017] In one exemplary embodiment of this disclosure, forming the first word line in each of the active regions includes:

[0018] Multiple first character line grooves are formed at intervals and extend along a first direction, each of the first character line grooves passing through multiple active regions;

[0019] A first dielectric layer is formed on the sidewall and bottom of the first character line groove;

[0020] The first word line is formed by filling the first word line trench in which the first dielectric layer is formed with conductive material.

[0021] In one exemplary embodiment of this disclosure, forming the first bit line includes:

[0022] A second insulating layer is formed, which covers the surface of the first active layer and the first word line;

[0023] The second insulating layer is patterned to form a plurality of spaced first bit line trenches extending along a second direction, each first bit line trench exposing the first ends of a plurality of said active regions, the second direction intersecting the first direction;

[0024] The first bit line is formed within the first bit line groove.

[0025] In one exemplary embodiment of this disclosure, forming the conductive contact plug includes:

[0026] A third insulating layer is formed, which covers the surfaces of the first bit line and the second insulating layer;

[0027] The second insulating layer and the third insulating layer are etched to form a plurality of conductive contact holes, each of the conductive contact holes exposing a second end of the active region, the first end and the second end being located on both sides of the first word line, respectively;

[0028] A conductive contact plug is formed inside the conductive contact hole.

[0029] In one exemplary embodiment of this disclosure, forming the gate dielectric layer includes:

[0030] A second dielectric layer is deposited on the surface of the structure formed by the conductive contact plug and the third insulating layer to form the gate dielectric layer.

[0031] In one exemplary embodiment of this disclosure, forming the second bit line and the second word line includes:

[0032] A fourth insulating layer is formed on the side of the second active layer that is away from the substrate;

[0033] The fourth insulating layer is etched with the second active layer as the etch stop layer to form a plurality of spaced second bit line trenches extending along the first direction and a plurality of spaced second word line trenches extending along the first direction in the fourth insulating layer; the orthographic projection of each second bit line trench on the substrate overlaps with the orthographic projection of the active region on the substrate, and the orthographic projection of each second word line trench on the substrate does not overlap with the orthographic projection of the active region on the substrate;

[0034] A second bit line is formed in each of the second bit line grooves, and a second word line is formed in each of the second word line grooves.

[0035] In one exemplary embodiment of this disclosure, forming the second bit line and the second word line includes:

[0036] A fourth insulating layer is formed on the side of the second active layer that is away from the substrate;

[0037] The fourth insulating layer is etched with the second active layer as the etch stop layer to form a plurality of spaced second bit line trenches extending along the first direction in the fourth insulating layer. The orthographic projection of each second bit line trench on the substrate overlaps with the orthographic projection of the active region on the substrate.

[0038] A second bit line is formed in each of the second bit line grooves;

[0039] A fifth insulating layer is formed covering the second bit line and the fourth insulating layer;

[0040] The fifth insulating layer and the fourth insulating layer are etched to form a plurality of spaced-apart vias and a plurality of spaced-apart second word line trenches extending along the second direction. Each second word line trench connects to a plurality of vias. Each via exposes the surface of the second active layer, and the orthographic projection of each via on the substrate does not overlap with the orthographic projection of the active region on the substrate.

[0041] The second letter line is formed in each of the through holes and in each of the second letter line grooves.

[0042] According to one aspect of this disclosure, a semiconductor structure is provided, comprising:

[0043] Substrate;

[0044] The first active layer is located on one side of the substrate and includes a plurality of spaced active regions.

[0045] The first character line structure includes multiple spaced-apart first character lines, each of which extends along a first direction and passes through multiple active regions.

[0046] The first bit line structure includes multiple spaced first bit lines, each first bit line extending along a second direction, and each first bit line connecting the first ends of multiple active regions, wherein the first direction and the second direction intersect.

[0047] A conductive contact structure includes a plurality of conductive contact plugs, each of the conductive contact plugs being connected to a second end of an active region, the first end and the second end being located on both sides of the first word line;

[0048] A gate dielectric layer is located on the side of the first active layer, the first bit line structure, and the conductive contact structure that is away from the substrate.

[0049] The second active layer is located on the side of the gate dielectric layer that is away from the substrate;

[0050] The second word line structure is located on the side of the second active layer away from the substrate and includes multiple second word lines, each of which connects to a first region of the second active layer.

[0051] The second bit line structure is located on the side of the second active layer away from the substrate, and includes multiple second bit lines, each of which connects to a second region of the second active layer.

[0052] The orthographic projection of each of the conductive contact plugs onto the second active layer is located between the first region and the second region.

[0053] In an exemplary embodiment of this disclosure, both the second word line and the second bit line extend along the first direction, and the orthographic projection of each second bit line on the substrate overlaps with the orthographic projection of the active region on the substrate, while the orthographic projection of each second word line on the substrate does not overlap with the orthographic projection of the active region on the substrate.

[0054] In one exemplary embodiment of this disclosure, the second bit line extends along the first direction, and the orthographic projection of each second bit line on the substrate overlaps with the orthographic projection of the active region on the substrate;

[0055] Each of the second word lines also includes a first conductive structure and a second conductive structure that are interconnected. The first conductive structure extends along the second direction, and the second conductive structure includes a plurality of conductive plugs. Each conductive plug is in contact with the second active layer, and the orthographic projection of each conductive plug on the substrate does not overlap with the orthographic projection of the active region on the substrate.

[0056] In one exemplary embodiment of this disclosure, a first insulating layer and an isolation structure are further included, wherein the first insulating layer is located between the substrate and the active region, and the isolation structure is located between the plurality of active regions.

[0057] In one exemplary embodiment of this disclosure, the conductive contact structure is in contact with the surface of the gate dielectric layer, and the first bit line structure is spaced apart from the surface of the gate dielectric layer.

[0058] In one exemplary embodiment of this disclosure, the first word line includes a first dielectric layer and a conductive layer, the first dielectric layer being located between the conductive layer and the active region, and the top surface of the conductive layer being lower than the top surface of the active region.

[0059] According to one aspect of this disclosure, a memory is provided, comprising the semiconductor structure described in any one of the foregoing claims.

[0060] In one exemplary embodiment of this disclosure, there are multiple semiconductor structures, and the multiple semiconductor structures are stacked and distributed along a direction perpendicular to the substrate.

[0061] The semiconductor structure and its formation method disclosed herein, and the memory, wherein the first bit line and the conductive contact plug can serve as the source and drain, respectively, and together with the first word line constitute a 6F. 2 The embedded transistor improves device integration. This transistor can serve as a write transistor for DRAM, controlling data writing. Simultaneously, the second bit line and second word line can serve as the source and drain, respectively, and together with the conductive contact plug (as the gate), form a planar transistor. This transistor can serve as a read transistor for DRAM, reading data. The parasitic capacitance of the read transistor can be used as a storage cell to complete charge storage. Furthermore, the planar transistor and 6F... 2Combining this with the DRAM architecture improves device integration and facilitates integrated design. In this process, on the one hand, because the charge retention time of transistors is longer than that of conventional capacitors, more frequent refreshes are unnecessary, resulting in lower device power consumption. On the other hand, since the second active layer is located between the gate dielectric layer and the second word line, the physical size between the second word line and the conductive contact is increased, reducing the electric field between the drain and the gate, thereby reducing drain current. Simultaneously, the increased physical size effectively prevents the gate dielectric layer from breaking down, effectively reducing standby power consumption and improving device reliability. Furthermore, since the read transistor and write transistor share a single electrode (conductive contact), with the former's gate and the latter's drain being the same electrode, the charge in the read transistor's gate capacitance can be changed by the write transistor to complete data writing and reading.

[0062] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0063] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0064] Figure 1 This is a flowchart of a method for forming a semiconductor structure according to an embodiment of the present disclosure;

[0065] Figure 2 This is a schematic diagram of the first active layer in the embodiments of this disclosure;

[0066] Figure 3 This is a flowchart of step S120 in the embodiment of this disclosure;

[0067] Figure 4 This is a flowchart of step S130 in the embodiment of this disclosure;

[0068] Figure 5 This is a schematic diagram showing the result after step S310 is completed in this embodiment of the present disclosure;

[0069] Figure 6 This is a schematic diagram showing the result after step S320 is completed in this embodiment of the present disclosure;

[0070] Figure 7 This is a top view after step S330 is completed in the embodiment of this disclosure;

[0071] Figure 8 For along Figure 7A schematic diagram showing a section cut along the AA direction.

[0072] Figure 9 This is a top view after step S140 is completed in this embodiment of the present disclosure;

[0073] Figure 10 For along Figure 9 A schematic diagram showing a section cut along the AA direction.

[0074] Figure 11 This is a flowchart illustrating the formation of the first line in this embodiment of the disclosure;

[0075] Figure 12 This is a schematic diagram of the first line in the embodiments of this disclosure;

[0076] Figure 13 For along Figure 12 A schematic diagram showing a section cut along the AA direction.

[0077] Figure 14 This is a flowchart illustrating the formation of the conductive contact plug in this embodiment of the present disclosure;

[0078] Figure 15 This is a schematic diagram showing the result after step S510 is completed in this embodiment of the present disclosure;

[0079] Figure 16 This is a schematic diagram showing the result after step S160 is completed in this embodiment of the present disclosure;

[0080] Figure 17 This is a top view after step S170 is completed in the first embodiment of this disclosure;

[0081] Figure 18 For along Figure 17 A schematic diagram showing a section cut along the AA direction.

[0082] Figure 19 This is a flowchart of step S170 in the first embodiment of this disclosure;

[0083] Figure 20 This is a schematic diagram of the second character line in the second embodiment of this disclosure;

[0084] Figure 21 This is a schematic diagram showing the result after step S170 is completed in the second embodiment of this disclosure;

[0085] Figure 22 This is a flowchart of step S170 in the second embodiment of this disclosure;

[0086] Figure 23 This is a schematic diagram of the memory in the first embodiment of this disclosure;

[0087] Figure 24This is a schematic diagram of the memory in the second embodiment of this disclosure.

[0088] Explanation of reference numerals in the attached figures:

[0089] 1. Substrate; 101. First insulating layer; 102. Isolation structure; 2. First active layer; 201. Active region; 3. First word line; 31. First conductive layer; 32. Second conductive layer; 301. First dielectric layer; 302. Passivation layer; 303. First word line trench; 4. First bit line; 41. Third conductive layer; 42. Fourth conductive layer; 401. Second insulating layer; 5. Conductive contact plug; 501. Third insulating layer; 6. Gate dielectric layer; 7. Second active layer; 8. Second bit line; 801. Fourth insulating layer; 9. Second word line; 901. Fifth insulating layer; 91. First conductive structure; 92. Second conductive structure. Detailed Implementation

[0090] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0091] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0092] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the existence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” … “fifth,” etc. are used only as markers and are not a limitation on the number of objects.

[0093] This disclosure provides a method for forming a semiconductor structure, such as... Figure 1 As shown, the forming method may include steps S110-S170, wherein:

[0094] Step S110: Provide a substrate;

[0095] Step S120: A first active layer is formed on one side of the substrate, the first active layer comprising a plurality of spaced active regions;

[0096] Step S130: Form a first word line in each of the active regions;

[0097] Step S140: A first bit line and a conductive contact plug are formed on the top of the first active layer, wherein the first bit line, the conductive contact plug and the first word line are insulated from each other.

[0098] Step S150: A gate dielectric layer is formed on the side of the first active layer, the first bit line, and the conductive contact plug that is away from the substrate.

[0099] Step S160: A second active layer is formed on the side of the gate dielectric layer opposite to the substrate;

[0100] Step S170: A second bit line and a second word line are formed on the side of the second active layer away from the substrate, and the second bit line and the second word line are respectively connected to the second active layer.

[0101] In the method for forming the semiconductor structure disclosed herein, the first word line and the conductive contact plug can serve as the source and drain, respectively, and together with the first word line, form a 6F structure. 2 The embedded transistor improves device integration. This transistor can serve as a write transistor for DRAM, controlling data writing. Simultaneously, the second bit line and second word line can serve as the source and drain, respectively, and together with the conductive contact plug (as the gate), form a planar transistor. This transistor can serve as a read transistor for DRAM, reading data. The parasitic capacitance of the read transistor can be used as a storage cell to complete charge storage. Furthermore, the planar transistor and 6F... 2 Combining this with the DRAM architecture improves device integration and facilitates integrated design. In this process, on the one hand, because the charge retention time of transistors is longer than that of conventional capacitors, more frequent refreshes are unnecessary, resulting in lower device power consumption. On the other hand, since the second active layer is located between the gate dielectric layer and the second word line, the physical size between the second word line and the conductive contact is increased, reducing the electric field between the drain and the gate, thereby reducing drain current. Simultaneously, the increased physical size effectively prevents the gate dielectric layer from breaking down, effectively reducing standby power consumption and improving device reliability. Furthermore, since the read transistor and write transistor share a single electrode (conductive contact), with the former's gate and the latter's drain being the same electrode, the charge in the read transistor's gate capacitance can be changed by the write transistor to complete data writing and reading.

[0102] The specific details of the method for forming a semiconductor structure according to the embodiments of this disclosure are described in detail below:

[0103] like Figure 1 As shown, in step S110, a substrate is provided.

[0104] like Figure 2 As shown, the substrate 1 can be a flat plate structure, which can be rectangular, circular, elliptical, polygonal or irregular shape, and its material can be a semiconductor material, for example, silicon, but not limited to silicon or other semiconductor materials. No special limitation is made on the shape and material of the substrate 1 here.

[0105] like Figure 1 As shown, in step S120, a first active layer is formed on one side of the substrate, the first active layer comprising a plurality of spaced active regions.

[0106] In one embodiment, the material of the first active layer 2 can be an amorphous material, such as indium gallium zinc oxide (IGZO), indium gallium zinc tin oxide (IGZTO), indium tin oxide (ITO), indium titanium oxide (ITiO), etc. Preferably, the material of the first active layer 2 can be indium gallium zinc oxide (IGZO). Multiple active regions 201 can be formed in the first active layer 2 by a patterning process, and the active regions 201 can be distributed at intervals.

[0107] In one exemplary embodiment of this disclosure, forming a first active layer 2 on one side of the substrate 1 may include steps S210-S230, such as... Figure 3 As shown, where:

[0108] Step S210: A first insulating layer is formed on the substrate.

[0109] In one exemplary embodiment of this disclosure, the first insulating layer 101 may be located on the surface of the substrate 1. The first insulating layer 101 can separate the substrate 1 from other film layers to prevent impurities in the substrate 1 from diffusing into other film layers, which helps to ensure the stability of the device.

[0110] The first insulating layer 101 may be a thin film or a coating formed on the surface of the substrate 1, and there is no particular limitation. In one embodiment, the first insulating layer 101 may be formed on the surface of the substrate 1 by means of chemical vapor deposition, physical vapor deposition, atomic layer deposition, thermal evaporation, vacuum evaporation or magnetron sputtering, etc. Of course, the first insulating layer 101 may also be formed by other means, and there is no particular limitation.

[0111] The material of the first insulating layer 101 can be an insulating material, such as silicon dioxide, a high-k dielectric material, or other dielectric materials, or any combination thereof. The thickness of the first insulating layer 101 can be set according to actual needs.

[0112] Step S220: A semiconductor layer is formed on the first insulating layer.

[0113] A semiconductor layer can be formed on the surface of the first insulating layer 101 opposite to the substrate 1. The semiconductor layer can be a thin film or a coating formed on the surface of the first insulating layer 101, and no particular limitation is made here. In one embodiment, the semiconductor layer can be formed on the surface of the first insulating layer 101 by means of chemical vapor deposition, physical vapor deposition, atomic layer deposition, thermal evaporation, vacuum evaporation or magnetron sputtering, etc. Of course, other means can also be used to form the semiconductor layer, and no particular limitation is made here.

[0114] In one embodiment, the semiconductor layer may be made of an amorphous material, such as indium gallium zinc oxide (IGZO), indium gallium zinc tin oxide (IGZTO), indium tin oxide (ITO), indium titanium oxide (ITiO), etc. Preferably, the semiconductor layer may be made of indium gallium zinc oxide (IGZO). The thickness of the semiconductor layer can be set according to actual needs.

[0115] Step S230: Etch the semiconductor layer to form a plurality of spaced isolation trenches in the semiconductor layer; the plurality of isolation trenches divide the semiconductor layer into a plurality of active regions.

[0116] Anisotropic etching can be used to etch the semiconductor layer to form multiple spaced isolation trenches. Each isolation trench can penetrate the semiconductor layer and expose the first insulating layer 101. The isolation trenches can divide the semiconductor layer into multiple active regions 201, that is, the active regions 201 can be separated by the isolation trenches to prevent coupling or short circuits between structures in adjacent active regions 201. The active regions 201 can be spaced apart in rows and / or columns. The cross-section of each active region 201 can be oval or rectangular, or other shapes; no specific limitation is made to the cross-sectional shape of the active regions 201 here.

[0117] For example, a photoresist layer can be formed on the surface of the semiconductor layer by spin coating or other methods. The material of the photoresist layer can be positive or negative photoresist, without special limitation. The shape of the surface of the photoresist layer away from the semiconductor layer can be the same as the shape of the semiconductor layer surface. A mask can be used to expose the photoresist layer, and the pattern of the mask can match the pattern required for the isolation trench. Subsequently, the exposed photoresist layer can be developed to form a developed area, which exposes the semiconductor layer, and the pattern of the developed area can be the same as the pattern required for the isolation trench, and the size of the developed area can be the same as the size of the required isolation trench. The semiconductor layer can be etched in the developed area using a dry etching process, with the first insulating layer 101 as the etch stop layer, to expose the first insulating layer 101.

[0118] In one exemplary embodiment of this disclosure, an isolation structure 102 may be formed by filling the isolation trench with an isolation material. The material of the isolation structure 102 may include silicon nitride, silicon oxide, or a combination of both, and is not specifically limited herein. The cross-sectional shape of the isolation structure 102 may be set according to actual needs.

[0119] In other embodiments, when forming the first active layer 2 on one side of the substrate 1, a thicker insulating layer can be formed on the substrate 1. The insulating layer is then etched to form multiple spaced active trenches. Active material is filled into each active trench to form the active region 201. It should be noted that the insulating layer does not need to be etched through during the etching process, so that a portion of the insulating layer remains between the substrate 1 and the active material to prevent impurities in the substrate 1 from diffusing into the active region 201.

[0120] like Figure 1 As shown, in step S130, a first word line is formed in each of the active regions.

[0121] The active region can be etched to form first word line trenches, and first word lines can be formed within each first word line trench. For example, two spaced-apart first word line trenches can be etched in each active region, and the two first word line trenches can be distributed in parallel. The two first word line trenches in two adjacent active regions can be interconnected, and first word lines can be formed in both first word line trenches.

[0122] In one exemplary embodiment of this disclosure, forming a first word line in each active region 201 may include steps S310-S330, such as... Figure 4 As shown, where:

[0123] Step S310: A plurality of first word line grooves are formed, spaced apart and extending along a first direction, each of the first word line grooves passing through a plurality of the active regions.

[0124] like Figure 5As shown, each active region 201 and the isolation material between each active region 201 can be etched to form a plurality of first word line trenches 303 penetrating each active region 201. Each first word line trench 303 can extend along a first direction and be arranged at intervals along a second direction. In the first direction, the first word line trenches 303 can be through at both ends and can be strip-shaped, and the strip-shaped first word line trenches 303 can be distributed in parallel.

[0125] In some embodiments, a photoresist layer can be formed on the surface of the first active layer 2 and the isolation material away from the substrate 1 by spin coating or other methods. The photoresist layer material can be positive photoresist or negative photoresist, and no special limitation is made here.

[0126] A photomask can be used to expose the photoresist layer, and the pattern of the photomask can match the pattern required for the first word line trench 303. Subsequently, the exposed photoresist layer can be developed to form multiple developed areas, each of which exposes the first active layer 2 and the isolation material. The pattern of the developed area can be the same as the pattern required for the first word line trench 303, and the size of each developed area can match the size of the required first word line trench 303.

[0127] The first active layer 2 and the isolation material can be etched in the developing area using a plasma etching process, thereby forming the first word line trench 303 within the first active layer 2 and the isolation material. After completing the above etching process, the photoresist layer can be removed by cleaning with a cleaning solution or by ashing or other processes.

[0128] It should be noted that the first direction can be any direction in the lateral extension direction of the substrate 1, and no special limitation is made to the first direction here. The second direction can intersect with the first direction; for example, the first direction can be perpendicular to the second direction. It should be noted that perpendicularity can be absolute or approximately perpendicular. Deviations are inevitable during the manufacturing process. In this disclosure, angular deviations may occur due to manufacturing process limitations, resulting in a certain deviation in the angle between the first and second directions. As long as the angular deviation between the first and second directions is within a preset range, the first direction can be considered perpendicular to the second direction. For example, the preset range can be 10°, that is, the first direction and the second direction can be considered perpendicular when the angle between them is greater than or equal to 80° and less than or equal to 100°.

[0129] Step S320: A first dielectric layer is formed on the sidewall and bottom of the first character groove.

[0130] like Figure 6As shown, the first dielectric layer 301 can be a thin film formed on the sidewalls and bottom of the first word line trench 303, or it can be a coating formed on the sidewalls and bottom of the first word line trench 303, without any particular limitation. The first dielectric layer 301 can be made of an insulating material, for example, silicon oxide. The first dielectric layer 301 can be formed on the sidewalls and bottom of the first word line trench 303 by chemical vapor deposition, physical vapor deposition, atomic layer deposition, thermal evaporation, vacuum evaporation, or magnetron sputtering. Of course, the first dielectric layer 301 can also be formed on the sidewalls and bottom of the first word line trench 303 by other methods, which will not be listed here.

[0131] In one embodiment, the thickness of the first dielectric layer 301 can be 2nm to 5nm. For example, its thickness can be 2nm, 3nm, 4nm or 5nm. Of course, the first dielectric layer 301 can also have other thicknesses, which will not be listed here.

[0132] Step S330: Fill the first word line trench where the first dielectric layer is formed with conductive material to form the first word line.

[0133] like Figure 7 and Figure 8 As shown, after the first dielectric layer 301 is formed, conductive material can be filled into each first word line trench 303 to form a first word line 3 in each first word line trench 303. In one embodiment, the first word line 3 may include a first conductive layer 31 and a second conductive layer 32, which can be formed sequentially in the first word line trench 303.

[0134] For example, the first conductive layer 31 may be a thin film formed at the bottom of the first word line trench 303. Its material may be titanium nitride. The first conductive layer 31 may be formed at the bottom of the first word line trench 303 by atomic layer deposition. The first conductive layer 31 may be in conformal contact with the first dielectric layer 301 on the sidewall and bottom of the first word line trench 303, and its surface away from the substrate 1 may be lower than the top surface of the first word line trench 303.

[0135] The second conductive layer 32 can be a thin film formed on the side of the first conductive layer 31 away from the substrate 1. Its material can be tungsten. The second conductive layer 32 can be formed on the side of the first conductive layer 31 away from the substrate 1 by vacuum evaporation, magnetron sputtering or atomic layer deposition. The second conductive layer 32 can be in contact with the first conductive layer 31, and its surface away from the first conductive layer 31 can be lower than the top surface of the first word line trench 303.

[0136] In one exemplary embodiment of this disclosure, the first word line 3 may further include a passivation layer 302. The passivation layer 302 may be a thin film formed on the side of the second conductive layer 32 opposite to the first conductive layer 31, which can be used to protect the surface of the second conductive layer 32. Its material may be silicon oxide or silicon nitride. The passivation layer 302 may be formed on the side of the second conductive layer 32 opposite to the first conductive layer 31 by chemical vapor deposition or physical vapor deposition. It should be noted that the surface of the passivation layer 302 opposite to the second conductive layer 32 may be flush with the surface of the first active layer 2.

[0137] like Figure 1 As shown, in step S140, a first bit line and a conductive contact plug are formed on the top of the first active layer, and the first bit line, the conductive contact plug and the first word line are insulated from each other.

[0138] like Figure 9 and Figure 10 As shown, a first bit line 4 and a conductive contact plug 5 can be formed on the top of the first active layer 2, respectively. The first bit line 4 and the conductive contact plug 5 can serve as the source and drain, respectively, and together with the first word line 3, they form a 6F. 2 The embedded transistor can improve device integration and can be used as a write transistor for DRAM to control data writing.

[0139] For example, a first bit line 4 and a conductive contact plug 5 can be formed on the top of the first active layer 2 on both sides of the first bit line groove 303, respectively. The first bit line 4, the first bit line 3, and the conductive contact plug 5 can be separated by an insulating material to prevent coupling or short circuit between the structures. For example, the first bit line 4, the first bit line 3, and the conductive contact plug 5 can be separated by a first dielectric layer 301 and / or a passivation layer 302.

[0140] In one exemplary embodiment of this disclosure, forming the first line 4 may include steps S410-S430, such as... Figure 11 As shown, where:

[0141] Step S410: A second insulating layer is formed, which covers the surface of the first active layer and the first word line.

[0142] like Figure 12 and Figure 13 As shown, a second insulating layer 401 can be formed on the surface of the structure jointly formed by the first word line 3 and the first active layer 2. The orthographic projections of the first word line 3 and the first active layer 2 on the substrate 1 can be within the orthographic projection of the second insulating layer 401 on the substrate 1. For example, the second insulating layer 401 can cover the surfaces of the first active layer 2 on both sides of the first word line trench 303 and the surface of the passivation layer 302.

[0143] In one embodiment, for ease of manufacturing, the second insulating layer 401 can simultaneously cover the top of the isolation structure 102. That is, the second insulating layer 401 can simultaneously cover the surfaces of the first active layer 2 on both sides of the first word trench 303, the surface of the passivation layer 302, and the top of the isolation structure 102.

[0144] In one exemplary embodiment of this disclosure, the material of the second insulating layer 401 may be the same as that of the first insulating layer 101, for example, it may be silicon oxide. The second insulating layer 401 may be formed on top of the first active layer 2 and the first word line 3 using processes such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition. Of course, the second insulating layer 401 may also be formed by other processes, and no particular limitation is made here on the formation method of the second insulating layer 401.

[0145] Step S420: The second insulating layer is patterned to form a plurality of spaced first bit line trenches extending along a second direction, each first bit line trench exposing the first ends of a plurality of active regions, the second direction intersecting the first direction.

[0146] The second insulating layer 401 can be patterned using an etching process to form a first line trench. There can be multiple first line trenches, each of which can extend along the second direction y, and the multiple first line trenches can be arranged at intervals along the first direction x.

[0147] The first line trench can penetrate multiple active regions 201, and the orthographic projection of the first end of the active region 201 on the substrate 1 at least partially overlaps with the orthographic projection of the first line trench on the substrate 1. In one embodiment, in a direction perpendicular to the substrate 1, the first line trench can penetrate the second insulating layer 401 and expose the top of the first active layer 2 located below the second insulating layer 401 at the first end of the active region 201.

[0148] For example, a photoresist layer can be formed on the surface of the second insulating layer 401 by spin coating or other methods. The photoresist layer material can be positive or negative photoresist, and no special limitation is made here.

[0149] A photomask can be used to expose the photoresist layer, and the pattern of the photomask can be matched with the pattern required for the first line trench. Subsequently, the exposed photoresist layer can be developed to form multiple development areas, each of which exposes the second insulating layer 401, and the pattern of the development area can be the same as the pattern required for the first line trench, and the size of each development area can be matched with the size of the required first line trench.

[0150] The second insulating layer 401 can be etched in the developing area using an anisotropic etching process, thereby forming the first line trench within the second insulating layer 401. After completing the above etching process, the photoresist layer can be removed by cleaning with a cleaning solution or by ashing or other processes.

[0151] Step S430: The first bit line is formed in the first bit line groove.

[0152] In one embodiment of this disclosure, the first line 4 may include a third conductive layer 41 and a fourth conductive layer 42. The third conductive layer 41 may be conformally attached to the bottom and sidewalls of the first line trench and is in contact with the first active layer 2 at the bottom of the first line trench. The fourth conductive layer 42 may fill the first line trench in which the third conductive layer 41 is formed and is flush with the top surface of the second insulating layer 401. Both the third conductive layer 41 and the fourth conductive layer 42 may be made of conductive materials. For example, the material of the third conductive layer 41 may be titanium nitride, and the material of the fourth conductive layer 42 may be tungsten.

[0153] The third conductive layer 41 and the fourth conductive layer 42 can be formed sequentially using methods such as atomic layer deposition, chemical vapor deposition, physical vapor deposition, vacuum evaporation, or magnetron sputtering. Of course, other methods can also be used to form the third conductive layer 41 and the fourth conductive layer 42, which will not be listed here. It should be noted that the formation methods of the third conductive layer 41 and the fourth conductive layer 42 can be the same or different; no specific limitations are placed on the formation methods of the third conductive layer 41 and the fourth conductive layer 42.

[0154] In one exemplary embodiment of this disclosure, forming the conductive contact plug 5 may include steps S510-S530, such as... Figure 14 As shown, where:

[0155] Step S510: A third insulating layer is formed, which covers the surfaces of the first bit line and the second insulating layer.

[0156] like Figure 5 As shown, after the first line 4 is formed, a third insulating layer 501 can be formed on the surface of the structure jointly formed by the first line 4 and the second insulating layer 401. The material of the third insulating layer 501 can be the same as that of the first insulating layer 101, for example, it can be silicon oxide. The third insulating layer 501 can be formed on the surface of the structure jointly formed by the first line 4 and the second insulating layer 401 using processes such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition. Of course, the third insulating layer 501 can also be formed by other processes. No special limitation is made here on the formation method of the third insulating layer 501.

[0157] Step S520: Etch the second insulating layer and the third insulating layer to form a plurality of conductive contact holes, each of the conductive contact holes exposing the second end of the active region, the first end and the second end being located on both sides of the first word line, respectively.

[0158] The second insulating layer 401 and the third insulating layer 501 can be etched using photolithography to form multiple spaced conductive contact holes. The conductive contact holes can be circular, rectangular, or irregularly shaped, and no special limitation is made here.

[0159] Multiple conductive contact holes can be arranged in a row and spaced apart along the extension direction of the first line 4. In one embodiment, each first line 4 can form a group with each column of conductive contact holes, forming multiple groups of first lines 4 and conductive contact holes arranged side by side. In adjacent groups, the columns formed by the first lines 4 and conductive contact holes are alternately distributed, that is, each conductive contact hole is distributed on both sides of the first line 4 and can be spaced apart along the extension direction of the first line 4.

[0160] Each conductive contact hole exposes the first active layer 2 located at the second end of the active region 201. To ensure the connectivity between the structure subsequently formed in the conductive contact hole and the first active layer 2, etching can be performed into the first active layer 2 during the etching process. That is, during the etching process, the second insulating layer 401 and the third insulating layer 501 can be etched through, while a portion of the first active layer 2 is etched.

[0161] It should be noted that the first end and the second end of the active area 201 can be located on both sides of the first word line 3, respectively. When the active area 201 includes two word lines, the active area 201 between the two word lines can be defined as the first end of the active area 201, and the active area 201 on the side of one word line away from the other word line can be defined as the second end of the active area 201.

[0162] Step S530: A conductive contact plug is formed inside the conductive contact hole.

[0163] Conductive material can be filled into the conductive contact hole to form a conductive contact plug 5, which then connects to the first active layer 2 through the conductive contact hole, allowing the collected charge to be stored. The conductive material can be polycrystalline silicon or tungsten, or other materials with good conductivity, which will not be listed here.

[0164] In one exemplary embodiment of this disclosure, a conductive contact plug 5 can be formed in a conductive contact hole by means of atomic layer deposition, vacuum evaporation, magnetron sputtering, chemical vapor deposition or physical vapor deposition. Of course, the conductive contact plug 5 can also be formed by other means. No special limitation is made here on the formation method of the conductive contact plug 5.

[0165] like Figure 1 As shown, in step S150, a gate dielectric layer is formed on the side of the first active layer, the first bit line, and the conductive contact plug that is away from the substrate.

[0166] The gate dielectric layer 6 can be formed on the side of the first active layer 2, the first first line 4 and the conductive contact plug 5 away from the substrate 1. It can be a thin film formed on the side of the first active layer 2, the first first line 4 and the conductive contact plug 5 away from the substrate 1, or it can be a coating formed on the side of the first active layer 2, the first first line 4 and the conductive contact plug 5 away from the substrate 1. No special limitation is made here.

[0167] In one embodiment, the gate dielectric layer 6 can be formed on the side of the first active layer 2, the first line 4 and the conductive contact plug 5 away from the substrate 1 by processes such as chemical vapor deposition, thermal oxidation, physical vapor deposition, atomic layer deposition or in-situ water oxidation. Of course, the gate dielectric layer 6 can also be formed by other means, and no special limitation is made here.

[0168] The gate dielectric layer 6 can be made of an insulating material, such as silicon dioxide, a high-k dielectric material, or other dielectric materials, or any combination thereof. The thickness of the gate dielectric layer 6 can be set according to actual needs. For example, its thickness can be 2nm to 5nm, such as 2nm, 3nm, 4nm, or 5nm. Of course, the gate dielectric layer 6 can also have other thicknesses, which will not be listed here.

[0169] In one exemplary embodiment of this disclosure, the gate dielectric layer 6 can be formed on the surface of the structure jointly formed by the conductive contact plug 5 and the third insulating layer 501. A second dielectric layer can be deposited on the surface of the structure jointly formed by the conductive contact plug 5 and the third insulating layer 501 using processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, thermal oxidation, or in-situ water oxidation. The material of the second dielectric layer can be the same as the material of the first dielectric layer 301; therefore, its material can be referenced to the material of the first dielectric layer 301, and will not be described further here. The second dielectric layer can be defined as the gate dielectric layer 6.

[0170] like Figure 1 As shown, in step S160, a second active layer is formed on the side of the gate dielectric layer opposite to the substrate.

[0171] like Figure 16 As shown, the second active layer 7 can be a thin film formed on the surface of the gate dielectric layer 6, or it can be a coating formed on the surface of the gate dielectric layer 6, without any particular limitation. In one embodiment, the second active layer 7 can be formed on the surface of the gate dielectric layer 6 by means of chemical vapor deposition, physical vapor deposition, atomic layer deposition, thermal evaporation, vacuum evaporation or magnetron sputtering, etc. Of course, the second active layer 7 can also be formed by other means, without any particular limitation.

[0172] In one embodiment, the material of the second active layer 7 can be the same as that of the first active layer 2, which will not be described in detail here. The thickness of the second active layer 7 can be set according to actual needs. For example, its thickness can be 5nm to 20nm, such as 5nm, 10nm, 15nm or 20nm. Of course, the second active layer 7 can also have other thicknesses, which will not be listed here.

[0173] like Figure 1 As shown, in step S170, a second bit line and a second word line are formed on the side of the second active layer away from the substrate, and the second bit line and the second word line are respectively connected to the second active layer.

[0174] Both the second bit line and the second word line can be formed on the surface of the second active layer 7 and can be in contact with and connected to the second active layer 7. The second bit line and its specific details are described in detail below using two embodiments:

[0175] In the first embodiment of this disclosure, such as Figure 17 As shown, the second bit line 8 can be made of a conductive material, for example, titanium nitride. The second bit line 9 can also be made of a conductive material, for example, tungsten.

[0176] The second bit line 8 and the second word line 9 can be located on both sides of the conductive contact plug 5, and can be connected to the second active layer 7. The second bit line 8 and the second word line 9 can serve as the source and drain, respectively, and together with the conductive contact plug 5, form a planar transistor. This transistor can serve as the read transistor for DRAM, used for reading data. The parasitic capacitance of the read transistor can be used as a storage cell to complete charge storage. The second bit line 8 and the second word line 9 can be separated by an insulating material to prevent coupling or short circuits between the structures.

[0177] The second bit line 8 may be strip-shaped and may extend along the first direction x. There may be multiple second bit lines 8, and multiple second bit lines 8 may be distributed at intervals along the second direction y. The orthographic projection of each second bit line 8 on the substrate 1 and the orthographic projection of the active region 201 on the substrate 1 shall at least partially overlap.

[0178] The second word line 9 can also be strip-shaped and can extend along the first direction x. There can be multiple second word lines 9, and multiple second word lines 9 can be distributed at intervals along the second direction y. The orthographic projection of each second word line 9 on the substrate 1 does not overlap with the orthographic projection of the active region 201 on the substrate 1.

[0179] For example, two second bit lines 8 may be distributed above each active region 201. The two second bit lines 8 may be distributed in parallel, and the orthogonal projections of the two second bit lines 8 onto the substrate 1 may pass through the orthogonal projections of multiple active regions 201 distributed at intervals along the first direction x onto the substrate 1. At the same time, in the second direction y, a second word line 9 may be distributed on both sides of each active region 201. The two second word lines 9 may be distributed in parallel, and the two second word lines 9 may also be parallel to the two second bit lines 8. That is, the second bit lines 8 and the second word lines 9 distributed around any active region 201 may extend along the first direction x, and the second word lines 9 and the second bit lines 8 may be arranged at intervals along the second direction y.

[0180] In the first embodiment of this disclosure, forming the second bit line 8 and the second word line 9 may include steps S610-S630, such as... Figure 19 As shown, where:

[0181] Step S610: A fourth insulating layer is formed on the side of the second active layer away from the substrate.

[0182] A fourth insulating layer 801 can be formed on the surface of the second active layer 7. The material of the fourth insulating layer 801 can be the same as that of the first insulating layer 101, for example, it can be silicon oxide. The fourth insulating layer 801 can be formed on the surface of the second active layer 7 using processes such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition. Of course, other processes can also be used to form the fourth insulating layer 801. No special limitation is made here on the formation method of the fourth insulating layer 801.

[0183] Step S620: Etch the fourth insulating layer using the second active layer as the etch stop layer to form a plurality of spaced second bit line trenches extending along the first direction and a plurality of spaced second word line trenches extending along the first direction in the fourth insulating layer; the orthographic projection of each second bit line trench on the substrate overlaps with the orthographic projection of the active region on the substrate, and the orthographic projection of each second word line trench on the substrate does not overlap with the orthographic projection of the active region on the substrate.

[0184] A photoresist layer can be formed on the surface of the fourth insulating layer 801 by spin coating or other methods. The photoresist layer material can be positive or negative photoresist, and no special limitation is made here.

[0185] A photomask can be used to expose the photoresist layer, and the pattern of the photomask can be matched with the required patterns for the second bit line trench and the second word line trench. Subsequently, the exposed photoresist layer can be developed to form multiple developed areas, each of which exposes the fourth insulating layer 801. The pattern of the developed area can be the same as the required patterns for the second bit line trench and the second word line trench, and the size of each developed area can be matched with the required size of the second bit line trench and the second word line trench.

[0186] The fourth insulating layer 801 can be etched in the developing area using an anisotropic etching process, thereby forming the second bit line trench and the second word line trench within the fourth insulating layer 801. After completing the above etching process, the photoresist layer can be removed by cleaning with a cleaning solution or by ashing or other processes.

[0187] It should be noted that the second bit line trench can be strip-shaped and can extend along the first direction x. There can be multiple second bit line trenches. Multiple second bit line trenches can be distributed at intervals along the second direction y. The orthographic projection of each second bit line trench on the substrate 1 and the orthographic projection of the active region 201 on the substrate 1 at least partially overlap.

[0188] The second word line trench can also be strip-shaped and can extend along the first direction x. There can be multiple second word line trenches. Multiple second word line trenches can be distributed at intervals along the second direction y. The orthographic projection of each second word line trench on the substrate 1 does not overlap with the orthographic projection of the active region 201 on the substrate 1.

[0189] Step S630: A second bit line is formed in each of the second bit line grooves, and a second word line is formed in each of the second word line grooves.

[0190] In this embodiment, a second bit line 8 can be formed first in a second bit line trench, and then a second word line 9 can be formed in a second word line trench. During the formation of the second bit line 8, the second word line trench can be shielded to ensure that the second bit line 8 is formed only in the second bit line trench. Alternatively, for process convenience, conductive material can be filled into the second word line trench, and then the conductive material can be removed by etching or other processes to facilitate the subsequent formation of the second word line 9. Conversely, the second word line 9 can be formed first in the second word line trench, and then the second bit line 8 can be formed in the second bit line trench. No specific limitation is made on the formation order of the second bit line 8 and the second word line 9. If the second word line 9 is formed before the second bit line 8, the second bit line trench can be shielded during the formation of the second word line 9 to ensure that the second word line 9 is formed only in the second word line trench. Alternatively, for process convenience, conductive material can be filled into the second bit line trench, and then the conductive material can be removed by etching or other processes to facilitate the subsequent formation of the second bit line 8 in the second word line trench.

[0191] The following example, which shows the formation process of the second position line 8 first and then the second character line 9, will be explained in detail:

[0192] The second bit line 8 can be formed in the second bit line trench by filling the first conductive material with processes such as atomic layer deposition, chemical vapor deposition, physical vapor deposition, vacuum evaporation, or magnetron sputtering. The first conductive material can be titanium nitride, or other materials with strong conductivity, which will not be listed here.

[0193] It should be noted that, for the sake of process convenience, during the formation of the second bit line 8, the first conductive material can be deposited simultaneously on the surface of the structure jointly formed by the second bit line trench, the second word line trench and the fourth insulating layer 801 until the first conductive material fills each second bit line trench and the deposition is stopped. Then the first conductive material located outside the second bit line trench can be removed, and the surface of the first conductive material located in the second bit line trench is made flush with the surface of the fourth insulating layer 801, thereby forming the second bit line 8 in the second bit line trench.

[0194] The second conductive material can be filled into the second word line trench using processes such as atomic layer deposition, chemical vapor deposition, physical vapor deposition, vacuum evaporation, or magnetron sputtering, thereby forming the second word line 9 in the second word line trench. The second conductive material can be tungsten, or other materials with strong conductivity, which will not be listed here.

[0195] It should be noted that, for process convenience, during the formation of the second word line 9, a second conductive material can be deposited simultaneously on the surface of the structure jointly formed by the second word line trench, the second bit line 8, and the fourth insulating layer 801 until the second conductive material fills each second word line trench. Then, the second conductive material located outside the second word line trench can be removed, and the surface of the second conductive material located in the second word line trench is made flush with the surface of the fourth insulating layer 801, thereby forming the second word line 9 in the second word line trench. Each second word line 9 and each second bit line 8 can be isolated by the fourth insulating layer 801 to avoid coupling or short circuit between adjacent second bit lines 8, between adjacent second word lines 9, and between adjacent second word lines 9 and second bit lines 8, which can improve product yield.

[0196] The process of forming the second character line 9 first and then the second position line 8 is similar to the process of forming the second position line 8 first and then the second character line 9, so it will not be described again here.

[0197] In the second embodiment of this disclosure, the arrangement and specific details of the second bit line 8 are the same as those of the second bit line 8 in the first embodiment described above. Therefore, the specific details can be referred to the first embodiment, and will not be repeated here.

[0198] The second embodiment of this disclosure differs from the first embodiment in the arrangement of the second character line 9. The specific details of the second character line 9 in the second embodiment of this disclosure are as follows:

[0199] The second digit 9 can be made of a conductive material, for example, tungsten. Figure 20 and Figure 21 As shown, each second word line 9 may include a first conductive structure 91 and a second conductive structure 92, wherein: the first conductive structure 91 may be strip-shaped and extend along the second direction y; the second conductive structure 92 may include a plurality of spaced conductive plugs; the cross-section of the second conductive structure 92 in the direction parallel to the substrate 1 may be circular, elliptical, rectangular, or irregular in shape, and the shape of the conductive plugs is not specifically limited here. One end of each conductive plug may be in contact with the second active layer 7, and the other end may be in contact with the first conductive structure 91.

[0200] In one embodiment, the orthographic projection of each conductive plug on the substrate 1 does not overlap with the orthographic projection of the active region 201 on the substrate 1. For example, around any active region 201, the orthographic projection of the conductive plug on the substrate 1 may be located on the side where the orthographic projection of the conductive contact plug 5 on the substrate 1 is far from the orthographic projection of the second bit line 8 on the substrate 1, and the orthographic projection of the conductive plug on the substrate 1 may be within the orthographic projection of the isolation structure 102 on the substrate 1.

[0201] There can be multiple second word lines 9, and the first conductive structures 91 of each second word line 9 can be distributed at intervals along the first direction x. Each second word line 9 can be in contact with and connected to the second active layer 7. For example, each conductive plug of each second word line 9 is in contact with and connected to the second active layer 7.

[0202] In a second embodiment of this disclosure, forming the second bit line 8 and the second word line 9 may include steps S710-S760, such as... Figure 22 As shown, where:

[0203] Step S710: A fourth insulating layer is formed on the side of the second active layer away from the substrate.

[0204] Step S720: The fourth insulating layer is etched with the second active layer as the etch stop layer to form a plurality of spaced second bit line trenches extending along the first direction in the fourth insulating layer. The orthographic projection of each second bit line trench on the substrate overlaps with the orthographic projection of the active region on the substrate.

[0205] Step S730: Form a second bit line in each of the second bit line trenches.

[0206] In the second embodiment of this disclosure, the formation of the second bit line 8 is similar to that in the first embodiment of this disclosure, so it will not be described again here.

[0207] Step S740: A fifth insulating layer is formed covering the second bit line and the fourth insulating layer.

[0208] A fifth insulating layer 901 can be formed on the surface of the structure jointly formed by the second insulating line 8 and the fourth insulating layer 801. The material of the fifth insulating layer 901 can be the same as that of the first insulating layer 101, for example, it can be silicon oxide. The fifth insulating layer 901 can be formed on the surface of the structure jointly formed by the second insulating line 8 and the fourth insulating layer 801 using processes such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition. Of course, the fifth insulating layer 901 can also be formed by other processes. No special limitation is made here on the formation method of the fifth insulating layer 901.

[0209] Step S750: Etch the fifth insulating layer and the fourth insulating layer to form a plurality of spaced-apart vias and a plurality of spaced-apart second word line trenches extending along the second direction. Each second word line trench connects to the plurality of vias. Each via exposes the surface of the second active layer, and the orthographic projection of each via on the substrate does not overlap with the orthographic projection of the active region on the substrate.

[0210] The vias can be used to form the second conductive structure 92. Each via can expose the surface of the second active layer 7, and the orthographic projection of each via on the substrate 1 does not overlap with the orthographic projection of the active region 201 on the substrate 1. The second word line trenches can be used to form the first conductive structure 91. Each second word line trench can connect multiple vias so that the first conductive structure 91 subsequently formed inside it can contact and connect with the second conductive structure 92 subsequently formed inside the via.

[0211] In one embodiment, a photoresist layer can be formed on the surface of the fifth insulating layer 901 by spin coating or other methods. The photoresist layer material can be positive or negative photoresist, without special limitation. A first mask can be used to expose the photoresist layer, and the pattern of the first mask can match the pattern required for each via. Subsequently, the exposed photoresist layer can be developed to form a plurality of first developing areas, each of which exposes the fifth insulating layer 901, and the pattern of the first developing area can be the same as the pattern required for the via. The size of each first developing area can match the size of the required via. The second active layer 7 can be used as an etch stop layer, and the fifth insulating layer 901 and the fourth insulating layer 801 can be etched in the first developing area by an anisotropic etching process, thereby forming a plurality of spaced vias within the fifth insulating layer 901 and the fourth insulating layer 801.

[0212] Subsequently, a second photomask can be used to expose the photoresist layer. The pattern of this second photomask can match the pattern required for each second word line trench. The exposed photoresist layer can then be developed to form multiple second developing areas. Each second developing area exposes the fifth insulating layer 901, and the pattern of the second developing area can be the same as the pattern required for the second word line trenches. The size of each second developing area can match the size of the required second word line trench. An isotropic etching process can be used to etch the fifth insulating layer 901 and the fourth insulating layer 801 in the second developing areas, thereby forming multiple spaced-apart second word line trenches within the fifth insulating layer 901 and the fourth insulating layer 801.

[0213] It should be noted that the second character line groove can be strip-shaped and can extend along the second direction y. There can be multiple second character line grooves, and multiple second character line grooves can be distributed at intervals along the first direction x.

[0214] Step S760: A second letter line is formed in each of the through holes and in each of the second letter line grooves.

[0215] The second conductive material can be filled into each through-hole and each second word line trench using processes such as atomic layer deposition, chemical vapor deposition, physical vapor deposition, vacuum evaporation, or magnetron sputtering, thereby forming the second word line 9 in the through-hole and the second word line trench. The second conductive material can be tungsten, or other materials with strong conductivity, which will not be listed here.

[0216] It should be noted that, for process convenience, during the formation of the second word line 9, a second conductive material can be deposited simultaneously on the surface of the structure formed by the through-hole, the second word line trench, and the fifth insulating layer 901. Deposition is stopped when the second conductive material fills each through-hole and each second word line trench. Subsequently, the second conductive material on the surface of the fifth insulating layer 901 can be removed, and the surface of the second conductive material in the second word line trench is made flush with the surface of the fifth insulating layer 901, thereby forming the second word line 9 in the through-hole and the second word line trench. Each second word line 9 and each second bit line 8 can be isolated by the fourth insulating layer 801 and the fifth insulating layer 901 to avoid coupling or short circuits between adjacent second bit lines 8, between adjacent second word lines 9, and between adjacent second word lines 9 and second bit lines 8, which can improve product yield.

[0217] It should be noted that although the steps of the semiconductor structure formation method in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that these steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0218] This disclosure also provides a semiconductor structure, such as Figure 18 and Figure 21 The semiconductor structure may include a substrate 1, a first active layer 2, a first word line structure, a second bit line structure, a conductive contact structure, a gate dielectric layer 6, a second active layer 7, a second word line structure, and a second bit line structure, wherein:

[0219] The first active layer 2 is located on one side of the substrate 1 and includes a plurality of spaced active regions 201.

[0220] The first character line structure includes multiple spaced first character lines 3, each first character line 3 extending along a first direction x, and each first character line 3 passing through multiple active regions 201;

[0221] The first line structure includes multiple spaced first lines 4, each first line 4 extending along the second direction y, and each first line 4 connecting the first ends of multiple active regions 201, with the first direction x intersecting the second direction y.

[0222] The conductive contact structure includes multiple conductive contact plugs 5, each conductive contact plug 5 is connected to the second end of an active region 201, and the first end and the second end are located on both sides of the first word line 3, respectively.

[0223] The gate dielectric layer 6 is located on the side of the first active layer 2, the first line structure, and the conductive contact structure that is away from the substrate 1.

[0224] The second active layer 7 is located on the side of the gate dielectric layer 6 that is away from the substrate 1;

[0225] The second word line structure is located on the side of the second active layer 7 away from the substrate 1, and includes multiple second word lines 9, each second word line 9 connecting to the first region of the second active layer 7;

[0226] The second bit line structure is located on the side of the second active layer 7 away from the substrate 1, and includes multiple second bit lines 8, each second bit line 8 connecting to a second region of the second active layer 7.

[0227] The orthographic projection of each conductive contact structure onto the second active layer 7 is located between the first and second regions.

[0228] In the semiconductor structure disclosed herein, the first word line 4 and the conductive contact plug 5 can serve as the source and drain, respectively, and together with the first word line 3, form a 6F. 2The embedded transistor improves device integration. This transistor can serve as a write transistor for DRAM, controlling data writing. Simultaneously, the second bit line 8 and the second word line 9 can serve as the source and drain, respectively, and together with the conductive contact plug 5, form a planar transistor. This transistor can serve as a read transistor for DRAM, reading data. The parasitic capacitance of the read transistor can be used as a storage cell to complete charge storage. Furthermore, the planar transistor and 6F... 2 Combining this with the DRAM architecture improves device integration and facilitates integrated design. In this process, on the one hand, because the charge retention time of transistors is longer than that of conventional capacitors, more frequent refreshes are unnecessary, resulting in lower device power consumption. On the other hand, since the second active layer 7 is located between the gate dielectric layer 6 and the second word line 9, the physical size between the second word line 9 and the conductive contact 5 is increased, reducing the electric field between the drain and the gate, thereby reducing drain current. Simultaneously, the increased physical size effectively prevents the gate dielectric layer 6 from being broken down, effectively reducing standby power consumption and improving device reliability. Furthermore, since the read transistor and write transistor share a single electrode (conductive contact 5), with the former's gate and the latter's drain being the same electrode, the charge in the gate capacitance of the read transistor can be changed by the write transistor to complete data writing and reading.

[0229] The semiconductor structure in the embodiments of this disclosure will be described in detail below:

[0230] like Figure 2 As shown, the substrate 1 can be a flat plate structure, which can be rectangular, circular, elliptical, polygonal or irregular shape, and its material can be a semiconductor material, for example, silicon, but not limited to silicon or other semiconductor materials. No special limitation is made on the shape and material of the substrate 1 here.

[0231] The first active layer 2 may be formed on one side of the substrate 1, and may include a plurality of spaced active regions 201, which may be spaced in rows and / or columns. For example, the cross-section of each active region 201 may be oval or rectangular, or of course, other shapes. No special limitation is made here on the cross-sectional shape of the active region 201.

[0232] The material of the first active layer 2 can be an amorphous material, such as indium gallium zinc oxide (IGZO), indium gallium zinc tin oxide (IGZTO), indium tin oxide (ITO), indium titanium oxide (ITiO), etc. Preferably, the material of the first active layer 2 can be indium gallium zinc oxide (IGZO).

[0233] In one embodiment, the first active layer 2 has a plurality of first word line trenches 303. For example, each active region 201 may have two spaced-apart first word line trenches 303, the two first word line trenches 303 may be distributed in parallel, and the two first word line trenches 303 in two adjacent active regions 201 may be interconnected.

[0234] In one exemplary embodiment of this disclosure, the semiconductor structure may further include a first insulating layer 101 and an isolation structure 102, wherein:

[0235] The first insulating layer 101 may be located between the substrate 1 and the first active layer 2. For example, the first insulating layer 101 may be located between the substrate 1 and the active region 201. For example, the first insulating layer 101 may be located on the surface of the substrate 1. The first insulating layer 101 can separate the substrate 1 and the first active layer 2 to prevent impurities in the substrate 1 from diffusing into the first active layer 2, which helps to ensure the stability of the device.

[0236] The first insulating layer 101 can be a thin film or a coating formed on the surface of the substrate 1, without any particular limitation. The material of the first insulating layer 101 can be an insulating material, such as silicon dioxide, a high-k dielectric material, or other dielectric materials, or any combination thereof. The thickness of the first insulating layer 101 can be set according to actual needs.

[0237] The isolation structure 102 can be located between multiple active regions 201, that is, the isolation structure 102 can be located between two adjacent active regions 201 in the second active layer 7. The isolation structure 102 can be made of insulating material. For example, its material can include silicon nitride, silicon oxide, or a combination of both, without special limitation. The cross-sectional shape of the isolation structure 102 can be set according to actual needs. The isolation structure 102 can be used to insulate and isolate adjacent active regions 201, avoiding coupling or short circuits between structures in adjacent active regions 201.

[0238] like Figure 7 As shown, the first character line structure may include multiple spaced-apart first character lines 3, each of which may penetrate multiple active regions 201. Each first character line 3 may extend along a first direction x and may be spaced-apart along a second direction y. In the first direction x, the first character line 3 may be continuous at both ends and may be in the form of strips, with each strip of first character line 3 being distributed in parallel.

[0239] It should be noted that the first direction x can be any direction in the lateral extension direction of the substrate 1, and no special limitation is made to the first direction x here. The second direction y can intersect with the first direction x; for example, the first direction x can be perpendicular to the second direction y. It should be noted that perpendicularity can be absolute or approximately perpendicular. Deviations are inevitable during the manufacturing process. In this disclosure, angular deviations may occur due to manufacturing process limitations, resulting in a certain deviation in the angle between the first direction x and the second direction y. As long as the angular deviation between the first direction x and the second direction y is within a preset range, the first direction x and the second direction y can be considered perpendicular. For example, the preset range can be 10°, that is, the first direction x and the second direction y can be considered perpendicular when the angle between the first direction x and the second direction y is greater than or equal to 80° and less than or equal to 100°.

[0240] For example, each first character line 3 can be formed in a corresponding first character line groove 303. When each active region 201 has two spaced first character line grooves 303, two spaced first character lines 3 can be formed in each active region 201. The two first character lines 3 can be distributed in parallel. The two first character lines 3 in two adjacent active regions 201 can be interconnected.

[0241] In one exemplary embodiment of this disclosure, the first word line 3 may include a first dielectric layer 301 and a conductive layer, such as Figure 6 As shown, the first dielectric layer 301 may be located between the conductive layer and the active region 201, with the top surface of the conductive layer lower than the top surface of the active region 201. The first dielectric layer 301 may be a thin film formed on the sidewalls and bottom of the first word line trench 303, or it may be a coating formed on the sidewalls and bottom of the first word line trench 303; no particular limitation is made here. The first dielectric layer 301 may be made of an insulating material, for example, silicon oxide.

[0242] In one embodiment, the thickness of the first dielectric layer 301 can be 2nm to 5nm. For example, its thickness can be 2nm, 3nm, 4nm or 5nm. Of course, the first dielectric layer 301 can also have other thicknesses, which will not be listed here.

[0243] After the first dielectric layer 301 is formed, a conductive layer can be formed within each first word line trench 303. For example... Figure 8 As shown, the conductive layer may include a first conductive layer 31 and a second conductive layer 32, which may be formed sequentially within the first word line trench 303.

[0244] For example, the first conductive layer 31 may be a thin film formed at the bottom of the first word line trench 303, and its material may be titanium nitride. The first conductive layer 31 may be in conformal contact with the first dielectric layer 301 on the sidewall and bottom of the first word line trench 303, and its surface away from the substrate 1 may be lower than the top surface of the first word line trench 303.

[0245] The second conductive layer 32 may be a thin film formed on the side of the first conductive layer 31 away from the substrate 1, and its material may be tungsten. The second conductive layer 32 may be in contact with the first conductive layer 31, and its surface away from the first conductive layer 31 may be lower than the top surface of the first word line trench 303.

[0246] In one exemplary embodiment of this disclosure, the first word line 3 may further include a passivation layer 302. The passivation layer 302 may be a thin film formed on the side of the second conductive layer 32 opposite to the first conductive layer 31, and may be used to protect the surface of the second conductive layer 32. The material of the passivation layer 302 may be silicon oxide or silicon nitride. It should be noted that the surface of the passivation layer 302 opposite to the second conductive layer 32 may be flush with the surface of the first active layer 2.

[0247] A second insulating layer 401 can be formed on the surface of the structure jointly formed by the first word line 3 and the first active layer 2. The orthographic projections of the first word line 3 and the first active layer 2 on the substrate 1 can be within the orthographic projection of the second insulating layer 401 on the substrate 1. For example, the second insulating layer 401 can cover the surfaces of the first active layer 2 on both sides of the first word line trench 303 and the surface of the passivation layer 302.

[0248] In one exemplary embodiment of this disclosure, the material of the second insulating layer 401 may be the same as that of the first insulating layer 101, for example, it may be silicon oxide. The second insulating layer 401 may have a plurality of spaced first line trenches, each of which may extend along the second direction y, and the plurality of first line trenches may be spaced along the first direction x.

[0249] The first line trench can penetrate multiple active regions 201, and the orthographic projection of the first end of the active region 201 on the substrate 1 at least partially overlaps with the orthographic projection of the first line trench on the substrate 1. In one embodiment, the first line trench can penetrate the second insulating layer 401 and expose the top of the first active layer 2 located below the second insulating layer 401 at the first end of the active region 201.

[0250] The first line 4 may be located within a first line trench. The first line 4 may include a third conductive layer 41 and a fourth conductive layer 42. The third conductive layer 41 may be conformally attached to the bottom and sidewalls of the first line trench and be in contact with the first active layer 2 at the bottom of the first line trench. The fourth conductive layer 42 may fill the first line trench in which the third conductive layer 41 is formed and be flush with the top surface of the second insulating layer 401. Both the third conductive layer 41 and the fourth conductive layer 42 may be made of conductive materials. For example, the material of the third conductive layer 41 may be titanium nitride, and the material of the fourth conductive layer 42 may be tungsten.

[0251] In one exemplary embodiment of this disclosure, such as Figure 10 As shown, after the first line 4 is formed, a third insulating layer 501 can be formed on the surface of the structure jointly formed by the first line 4 and the second insulating layer 401. The material of the third insulating layer 501 can be the same as the material of the first insulating layer 101, for example, it can be silicon oxide.

[0252] The semiconductor structure disclosed herein may further include a plurality of conductive contact holes penetrating the second insulating layer 401 and the third insulating layer 501, and each conductive contact hole may be spaced apart. The conductive contact holes may be circular holes, rectangular holes, or irregularly shaped hole structures, and no particular limitation is made herein.

[0253] Multiple conductive contact holes can be arranged in a row and spaced apart along the extension direction of the first line 4. In one embodiment, each first line 4 can form a group with each column of conductive contact holes, forming multiple groups of first lines 4 and conductive contact holes arranged side by side. In adjacent groups, the columns formed by the first lines 4 and conductive contact holes are alternately distributed, that is, each conductive contact hole is distributed on both sides of the first line 4 and can be spaced apart along the extension direction of the first line 4.

[0254] Each conductive contact hole can expose the first active layer 2 located at the second end of the active region 201. It should be noted that the first end and the second end of the active region 201 can be located on both sides of the first word line 3, respectively. When the active region 201 includes two word lines, the active region 201 between the two word lines can be defined as the first end of the active region 201, and the active region 201 on the side of one word line away from the other word line can be defined as the second end of the active region 201.

[0255] A conductive contact structure can be formed within a conductive contact hole and can be connected to the first active layer 2 through the conductive contact hole, so as to store the collected charge through the conductive contact plug 5. The material of the conductive contact plug 5 can be polycrystalline silicon or tungsten, or other materials with good conductivity, which will not be listed here.

[0256] For example, each conductive contact hole can be correspondingly formed with a conductive contact plug 5, and multiple spaced conductive contact plugs 5 can be formed. Each conductive contact plug 5 can be connected to the second end of an active region 201.

[0257] The gate dielectric layer 6 may be located on the side of the first active layer 2, the first first line structure and the conductive contact structure away from the substrate 1. It may be a thin film formed on the side of the first active layer 2, the first first line structure and the conductive contact structure away from the substrate 1, or it may be a coating formed on the side of the first active layer 2, the first first line structure and the conductive contact structure away from the substrate 1. No special limitation is made here.

[0258] The gate dielectric layer 6 can be made of an insulating material, such as silicon dioxide, a high-k dielectric material, or other dielectric materials, or any combination thereof. The thickness of the gate dielectric layer 6 can be set according to actual needs. For example, its thickness can be 2nm to 5nm, such as 2nm, 3nm, 4nm, or 5nm. Of course, the gate dielectric layer 6 can also have other thicknesses, which will not be listed here.

[0259] In one exemplary embodiment of this disclosure, the gate dielectric layer 6 may be located on the surface of the structure jointly formed by the conductive contact structure and the third insulating layer 501, that is, the conductive contact structure may be in contact with the surface of the gate dielectric layer 6, and the first line structure is spaced apart from the surface of the gate dielectric layer 6.

[0260] The second active layer 7 may be located on the side of the gate dielectric layer 6 away from the substrate 1. For example, the second active layer 7 may be a thin film formed on the surface of the gate dielectric layer 6 or a coating formed on the surface of the gate dielectric layer 6, without any particular limitation.

[0261] In one embodiment, the material of the second active layer 7 can be amorphous silicon, for example, indium gallium zinc oxide (IGZO), indium gallium zinc tin oxide (IGZTO), indium tin oxide (ITO), indium titanium oxide (ITiO), etc. Preferably, the material of the second active layer 7 can be indium gallium zinc oxide (IGZO). The thickness of the second active layer 7 can be set according to actual needs. For example, its thickness can be 5nm to 20nm, for example, its thickness can be 5nm, 10nm, 15nm or 20nm. Of course, the second active layer 7 can also have other thicknesses, which will not be listed here.

[0262] The second active layer 7 may include multiple first regions arranged side by side and multiple second regions arranged side by side, and the first regions and the second regions may also be spaced apart. Both the first regions and the second regions may be strip-shaped regions.

[0263] In a first embodiment of this disclosure, each first region and each second region may extend along a first direction x and be spaced apart along a second direction y. For example, two first regions and two second regions may be distributed around an active region 201, wherein each of the two second regions may be located between the two first regions, and the orthographic projection of each second region on the substrate 1 overlaps with the orthographic projection of the active region 201 on the substrate 1, while the orthographic projection of each first region on the substrate 1 does not overlap with the orthographic projection of the active region 201 on the substrate 1. Furthermore, the orthographic projection of each conductive contact plug 5 on the second active layer 7 is located between the first region and the second region.

[0264] Both the second word line structure and the second bit line structure can be located on the side of the second active layer 7 away from the substrate 1. The second word line structure may include multiple second word lines 9, each of which can be connected to the first region of the second active layer 7 in a one-to-one correspondence. The second bit line structure may include multiple second bit lines 8, each of which can be connected to the second region of the second active layer 7 in a one-to-one correspondence.

[0265] In a first embodiment of this disclosure, the second bit line 8 may be made of a conductive material, for example, titanium nitride. The second word line 9 may also be made of a conductive material, for example, tungsten.

[0266] The second bit line 8 and the second word line 9 can be located on both sides of the conductive contact plug 5, and can be connected to the second active layer 7. The second bit line 8 and the second word line 9 can serve as the source and drain, respectively, and together with the conductive contact plug 5, form a planar transistor. This transistor can serve as the read transistor for DRAM, used for reading data. The parasitic capacitance of the read transistor can be used as a storage cell to complete charge storage. The second bit line 8 and the second word line 9 can be separated by an insulating material to prevent coupling or short circuits between the structures.

[0267] The second bit line 8 may be strip-shaped and may extend along the first direction x. There may be multiple second bit lines 8, and multiple second bit lines 8 may be distributed at intervals along the second direction y. The orthographic projection of each second bit line 8 on the substrate 1 and the orthographic projection of the active region 201 on the substrate 1 shall at least partially overlap.

[0268] The second word line 9 can also be strip-shaped and can extend along the first direction x. There can be multiple second word lines 9, and multiple second word lines 9 can be distributed at intervals along the second direction y. The orthographic projection of each second word line 9 on the substrate 1 does not overlap with the orthographic projection of the active region 201 on the substrate 1. That is, each second bit line 8 is distributed in parallel with each second word line 9.

[0269] For example, two second bit lines 8 may be distributed above each active region 201. The two second bit lines 8 may be distributed in parallel, and the orthogonal projections of the two second bit lines 8 onto the substrate 1 may pass through the orthogonal projections of multiple active regions 201 distributed at intervals along the first direction x onto the substrate 1. At the same time, in the second direction y, a second word line 9 may be distributed on both sides of each active region 201. The two second word lines 9 may be distributed in parallel, and the two second word lines 9 may also be parallel to the two second bit lines 8. That is, the second bit lines 8 and the second word lines 9 distributed around any active region 201 may extend along the first direction x, and the second word lines 9 and the second bit lines 8 may be arranged at intervals along the second direction y.

[0270] In a second embodiment of this disclosure, each first region may extend along the second direction y and be distributed at intervals along the first direction x; each second region may extend along the first direction x and be arranged at intervals along the second direction y.

[0271] In this embodiment, the arrangement and specific details of the second bit line 8 are the same as those of the second bit line 8 in the first embodiment described above. Therefore, the specific details can be referred to in the first embodiment, and will not be repeated here.

[0272] The second embodiment of this disclosure differs from the first embodiment in the arrangement of the second character line 9. The specific details of the second character line 9 in the second embodiment of this disclosure are as follows:

[0273] The second word line 9 may be made of a conductive material, such as tungsten. Each second word line 9 may include a first conductive structure 91 and a second conductive structure 92, wherein: the first conductive structure 91 may be strip-shaped and extend along the second direction y; the second conductive structure 92 may include a plurality of spaced conductive plugs; the cross-section of the second conductive structure 92 in the direction parallel to the substrate 1 may be circular, elliptical, rectangular, or irregular in shape, and the shape of the conductive plugs is not specifically limited here. One end of each conductive plug may be in contact with the second active layer 7, and the other end may be in contact with the first conductive structure 91.

[0274] In one embodiment, the orthographic projection of each conductive plug on the substrate 1 does not overlap with the orthographic projection of the active region 201 on the substrate 1. For example, around any active region 201, the orthographic projection of the conductive plug on the substrate 1 may be located on the side where the orthographic projection of the conductive contact plug 5 on the substrate 1 is far from the orthographic projection of the second bit line 8 on the substrate 1, and the orthographic projection of the conductive plug on the substrate 1 may be within the orthographic projection of the isolation structure 102 on the substrate 1.

[0275] There can be multiple second word lines 9, and the first conductive structures 91 of each second word line 9 can be distributed at intervals along the first direction x. Each second word line 9 can be in contact with and connected to the second active layer 7. For example, each conductive plug of each second word line 9 is in contact with and connected to the second active layer 7.

[0276] This disclosure also provides a memory, which may include the semiconductor structure described in any of the above embodiments. The specific details, formation process and beneficial effects of the memory have been described in detail in the corresponding semiconductor structure formation method and semiconductor structure, and will not be repeated here.

[0277] In one implementation, such as Figure 23 and Figure 24 As shown, the memory may include multiple semiconductor structures as described in any of the above embodiments, and each semiconductor structure may be stacked and distributed along a direction perpendicular to the substrate 1.

[0278] In one exemplary embodiment of this disclosure, the semiconductor structure near the substrate 1 can serve as the substrate 1 of the semiconductor structure adjacent to it on the side away from the substrate 1.

[0279] For example, the memory can be Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), etc. Of course, it can also be other storage devices, which will not be listed here.

[0280] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: Provide substrate; A first active layer is formed on one side of the substrate, the first active layer comprising a plurality of spaced active regions; A first word line is formed in each of the active regions; A first bit line and a conductive contact plug are formed on the top of the first active layer, and the first bit line, the conductive contact plug and the first word line are insulated from each other; A gate dielectric layer is formed on the side of the first active layer, the first bit line, and the conductive contact plug that is away from the substrate; A second active layer is formed on the side of the gate dielectric layer opposite to the substrate; A second bit line and a second word line are formed on the side of the second active layer away from the substrate, and the second bit line and the second word line are respectively connected to the second active layer. The first bit line connects to the first end of the plurality of active regions, and each conductive contact plug connects to the second end of an active region. The first end and the second end are located on both sides of the first word line, respectively. The second word line connects to the first region of the second active layer, and the second bit line connects to the second region of the second active layer. The orthographic projection of each conductive contact plug on the second active layer is located between the first region and the second region.

2. The forming method according to claim 1, characterized in that, The first active layer is formed on one side of the substrate, including: A first insulating layer is formed on the substrate; A semiconductor layer is formed on the first insulating layer; The semiconductor layer is etched to form a plurality of spaced isolation trenches in the semiconductor layer; the plurality of isolation trenches divide the semiconductor layer into a plurality of active regions.

3. The forming method according to claim 2, characterized in that, Forming the first word line in each of the active regions includes: Multiple first character line grooves are formed at intervals and extend along a first direction, each of the first character line grooves passing through multiple active regions; A first dielectric layer is formed on the sidewall and bottom of the first character line groove; The first word line is formed by filling the first word line trench in which the first dielectric layer is formed with conductive material.

4. The forming method according to claim 3, characterized in that, Forming the first bit line includes: A second insulating layer is formed, which covers the surface of the first active layer and the first word line; The second insulating layer is patterned to form a plurality of spaced first bit line trenches extending along a second direction, each first bit line trench exposing the first ends of a plurality of said active regions, the second direction intersecting the first direction; The first bit line is formed within the first bit line groove.

5. The forming method according to claim 4, characterized in that, Forming the conductive contact plug includes: A third insulating layer is formed, which covers the surfaces of the first bit line and the second insulating layer; The second insulating layer and the third insulating layer are etched to form a plurality of conductive contact holes, each of the conductive contact holes exposing the second end of the active region, the first end and the second end being located on both sides of the first word line, respectively; A conductive contact plug is formed inside the conductive contact hole.

6. The forming method according to claim 5, characterized in that, Forming the gate dielectric layer includes: A second dielectric layer is deposited on the surface of the structure formed by the conductive contact plug and the third insulating layer to form the gate dielectric layer.

7. The forming method according to claim 3, characterized in that, Forming the second bit line and the second word line includes: A fourth insulating layer is formed on the side of the second active layer that is away from the substrate; The fourth insulating layer is etched with the second active layer as the etch stop layer to form a plurality of spaced second bit line trenches extending along the first direction and a plurality of spaced second word line trenches extending along the first direction in the fourth insulating layer; the orthographic projection of each second bit line trench on the substrate overlaps with the orthographic projection of the active region on the substrate, and the orthographic projection of each second word line trench on the substrate does not overlap with the orthographic projection of the active region on the substrate; A second bit line is formed in each of the second bit line grooves, and a second word line is formed in each of the second word line grooves.

8. The forming method according to claim 3, characterized in that, Forming the second bit line and the second word line includes: A fourth insulating layer is formed on the side of the second active layer that is away from the substrate; The fourth insulating layer is etched with the second active layer as the etch stop layer to form a plurality of spaced second bit line trenches extending along the first direction in the fourth insulating layer. The orthographic projection of each second bit line trench on the substrate overlaps with the orthographic projection of the active region on the substrate. A second bit line is formed in each of the second bit line grooves; A fifth insulating layer is formed covering the second bit line and the fourth insulating layer; The fifth insulating layer and the fourth insulating layer are etched to form a plurality of spaced-apart vias and a plurality of spaced-apart second word line trenches extending along the second direction. Each second word line trench connects to a plurality of vias. Each via exposes the surface of the second active layer, and the orthographic projection of each via on the substrate does not overlap with the orthographic projection of the active region on the substrate. The second letter line is formed in each of the through holes and in each of the second letter line grooves.

9. A semiconductor structure, characterized in that, include: Substrate; The first active layer is located on one side of the substrate and includes a plurality of spaced active regions. The first character line structure includes multiple spaced-apart first character lines, each of which extends along a first direction and passes through multiple active regions. The first bit line structure includes multiple spaced first bit lines, each first bit line extending along a second direction, and each first bit line connecting the first ends of multiple active regions, wherein the first direction and the second direction intersect. A conductive contact structure includes a plurality of conductive contact plugs, each of the conductive contact plugs being connected to a second end of an active region, the first end and the second end being located on both sides of the first word line; A gate dielectric layer is located on the side of the first active layer, the first bit line structure, and the conductive contact structure that is away from the substrate. The second active layer is located on the side of the gate dielectric layer that is away from the substrate; The second word line structure is located on the side of the second active layer away from the substrate and includes multiple second word lines, each of which connects to a first region of the second active layer. The second bit line structure is located on the side of the second active layer away from the substrate, and includes multiple second bit lines, each of which connects to a second region of the second active layer. The orthographic projection of each conductive contact plug onto the second active layer is located between the first region and the second region.

10. The semiconductor structure according to claim 9, characterized in that, Both the second word line and the second bit line extend along the first direction, and the orthographic projection of each second bit line on the substrate overlaps with the orthographic projection of the active region on the substrate, while the orthographic projection of each second word line on the substrate does not overlap with the orthographic projection of the active region on the substrate.

11. The semiconductor structure according to claim 9, characterized in that, The second bit line extends along the first direction, and the orthographic projection of each second bit line on the substrate overlaps with the orthographic projection of the active region on the substrate; Each of the second word lines also includes a first conductive structure and a second conductive structure that are interconnected. The first conductive structure extends along the second direction, and the second conductive structure includes a plurality of conductive plugs. Each conductive plug is in contact with the second active layer, and the orthographic projection of each conductive plug on the substrate does not overlap with the orthographic projection of the active region on the substrate.

12. The semiconductor structure according to claim 9, characterized in that, It also includes a first insulating layer and an isolation structure, wherein the first insulating layer is located between the substrate and the active region, and the isolation structure is located between the plurality of active regions.

13. The semiconductor structure according to claim 9, characterized in that, The conductive contact structure is in contact with the surface of the gate dielectric layer, and the first bit line structure is spaced apart from the surface of the gate dielectric layer.

14. The semiconductor structure according to claim 9, characterized in that, The first word line includes a first dielectric layer and a conductive layer, wherein the first dielectric layer is located between the conductive layer and the active region, and the top surface of the conductive layer is lower than the top surface of the active region.

15. A memory, characterized in that, Includes the semiconductor structure described in any one of claims 9-14.

16. The memory according to claim 15, characterized in that, The number of semiconductor structures is multiple, and the multiple semiconductor structures are stacked and distributed along a direction perpendicular to the substrate.

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