Package and method of forming the same

Abstract

A method includes bonding a first-layer device die to a carrier, forming a first gap-fill region to seal the first-layer device die, forming a first redistribution structure over the first-layer device die and electrically connecting the first redistribution structure to the first-layer device die, and bonding a second-layer device die to the first-layer device die. The second-layer device die is located over the first-layer device die and extends laterally beyond a corresponding edge of the first-layer device die. The method further includes forming a second gap-fill region to seal the second-layer device die, removing the carrier, and forming a dielectric via penetrating the first gap-fill region. The dielectric via overlaps with and is electrically connected to the second-layer device die. A second redistribution structure is formed, wherein the first redistribution structure and the second redistribution structure are located on opposite sides of the first-layer device die. Embodiments of the invention also relate to a package and a method of forming the same.

Description

Technical Field

[0001] Embodiments of the present invention relate to packages and methods of forming the same. Background Technology

[0002] Integrated circuit packages are becoming increasingly complex, with more device dies packed into a single package to achieve more functions. For example, package structures have been developed to include multiple device dies, such as processor and memory cubes, within the same package. Package structures can include device dies formed using different technologies and have different functions bonded to the same device die, thus forming a system. This can save manufacturing costs and optimize device performance. Some device dies in a die stack may include through-silicon vias (TSVs) for electrical interconnection purposes. Summary of the Invention

[0003] Embodiments of the present invention provide a method for forming a package, comprising: bonding a first layer device die to a first carrier; forming a first gap-filling region to seal the first layer device die; forming a first redistribution structure above the first layer device die, and the first redistribution structure being electrically connected to the first layer device die; bonding a first second layer device die to the first layer device die, wherein the first second layer device die is located above the first layer device die and the first second layer device die extends laterally beyond a corresponding edge of the first layer device die; forming a second gap-filling region to seal the first second layer device die; removing the first carrier; forming a first dielectric via penetrating the first gap-filling region, wherein the first dielectric via overlaps with and is electrically connected to the first second layer device die; and forming a second redistribution structure, wherein the first redistribution structure and the second redistribution structure are located on opposite sides of the first layer device die.

[0004] Another embodiment of the present invention provides a package comprising: a first redistribution structure; a first layer device die located above the first redistribution structure, wherein the first layer device die includes: a first semiconductor substrate; and a first semiconductor via penetrating the first semiconductor substrate; a first gap-filling region sealing the first layer device die; a second redistribution structure located above the first layer device die and the first semiconductor via and electrically connected to the first layer device die and the first semiconductor via; a first second layer device die located above the first layer device die and coupled to the first layer device die, wherein the first second layer device die extends laterally beyond a corresponding edge of the first layer device die; a second gap-filling region sealing the first second layer device die; and a first dielectric via penetrating the first gap-filling region, wherein the first dielectric via electrically connects the first second layer device die to the first redistribution structure.

[0005] Another embodiment of the present invention provides a package comprising: a first redistribution structure; a first device die located above the first redistribution structure; a first gap-filling region sealing the first device die; a second device die located above the first device die, wherein the second device die extends laterally beyond a first edge of the first device die; a second gap-filling region sealing the second device die; a third device die located above the second device die, wherein the third device die extends laterally beyond a second edge of the second device die; a third gap-filling region sealing the third device die; a first dielectric via located in the first gap-filling region, wherein the first dielectric via overlaps with and is electrically connected to the second device die; and a second dielectric via overlapping with the third device die, wherein the second dielectric via penetrates both the first gap-filling region and the second gap-filling region. Attached Figure Description

[0006] The various aspects of the invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0007] Figures 1 to 7 A cross-sectional view of an intermediate stage in the formation of a package according to some embodiments is shown.

[0008] Figures 8 to 14 A cross-sectional view of an intermediate stage in the formation of a package according to some embodiments is shown.

[0009] Figures 15 to 19A cross-sectional view of an intermediate stage in the formation of a package according to some embodiments is shown.

[0010] Figure 20 A cross-sectional view of the package according to some embodiments is shown.

[0011] Figures 21 to 24 A cross-sectional view of an intermediate stage in the formation of a package according to some embodiments is shown.

[0012] Figure 25 A cross-sectional view of the package according to some embodiments is shown.

[0013] Figures 26 to 31 A cross-sectional view of an intermediate stage in the formation of a package according to some embodiments is shown.

[0014] Figure 32 A cross-sectional view of the package according to some embodiments is shown.

[0015] Figure 33 and Figure 34 Top-view and cross-sectional views of a package comprising an array of device dies, according to some embodiments, are shown respectively.

[0016] Figure 35 A process flow for forming a package is shown according to some embodiments. Detailed Implementation

[0017] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the individual embodiments and / or configurations discussed.

[0018] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or component and another, as shown in the figures. In addition to the orientations shown in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0019] Packages and methods of forming thereof are provided according to some embodiments. The package includes stacked device dies, some of which include substrate vias. The device dies may be surrounded by gap-filled regions, and dielectric vias pass through these gap-filled regions to directly interconnect two device dies, such that the connection between the two device dies does not pass through substrate vias or metal wires in the device dies. This reduces RC delay. The embodiments discussed herein are intended to provide examples enabling the manufacture or use of the subject matter of the invention, and modifications that can be made while remaining within the intended scope of the different embodiments will be readily understood by those skilled in the art. In the various views and illustrative embodiments, the same reference numerals are used to denote the same elements. While method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

[0020] Figures 1 to 7 A cross-sectional view is shown of an intermediate stage in the formation of a package according to some embodiments of the present invention. The corresponding process is also... Figure 35 The process flow shown is schematically illustrated.

[0021] refer to Figure 1 A carrier 110 is provided. According to some embodiments, the carrier 110 is a blanket carrier formed of a homogeneous material, and the entire carrier 110 is formed of the same material. The carrier 110 can be a silicon carrier, a glass carrier, etc. According to some embodiments in which the carrier 110 is a silicon carrier, a dielectric layer 112 formed of or including silicon oxide can be formed on the top surface of the carrier 110 for bonding. The dielectric layer 112 can be formed by thermal oxidation, deposition processes, etc., of the surface layer of the carrier 110. According to alternative embodiments, the dielectric layer 112 is not formed.

[0022] Device die 210 is placed above carrier 110 and bonded to carrier 110 via die-to-wafer bonding. The corresponding process is shown as follows. Figure 35Process 602 is shown in process flow 600. Bonding can be at the wafer level. Therefore, multiple device dies 210 (which may be the same as or different from each other) are bonded to carrier 110, but only one device die 210 is shown. Throughout the description, the device die 210 and other device dies shown in the figure can be logic dies, memory dies, I / O dies, etc. For example, logic dies can include application processor (AP) dies, graphics processing unit (GPU) dies, field-programmable gate array (FPGA) dies, application-specific integrated circuit (ASIC) dies, input-output (I / O) dies, network processing unit (NPU) dies, tensor processing unit (TPU) dies, artificial intelligence (AI) engine dies, etc. The memory die can be or may include static random access memory (SRAM) dies, dynamic random access memory (DRAM) dies, wide I / O memory dies, NAND memory dies, resistive random access memory (RRAM) dies, magnetoresistive random access memory (MRAM) dies, phase change random access memory (PCRAM) dies, or other types of volatile or non-volatile memory dies.

[0023] Device die 210 includes a substrate 212. According to some embodiments, substrate 212 is a semiconductor substrate, which may be a crystalline silicon substrate, but may also include or be formed of other semiconductor materials, such as silicon germanium, silicon carbon, etc. According to some embodiments, device die 210 includes active circuitry, including active devices such as transistors (not shown) formed on the shown bottom (front) surface of semiconductor substrate 212. According to some embodiments, through-holes (sometimes referred to as substrate vias (TSVs)) 214 may be formed to extend into substrate 212. When substrate 212 is a silicon substrate, TSV 214 is sometimes also referred to as a through-silicon via. Each TSV 214 may be surrounded by an isolation pad (not shown) formed of a dielectric material such as silicon oxide, silicon nitride, etc. The isolation pad isolates the respective TSV 214 from semiconductor substrate 212. TSV 214 extends to an intermediate level between the top and bottom surfaces of semiconductor substrate 212. According to some embodiments, the bottom surface of TSV 214 is flush with the bottom surface of the illustrated semiconductor substrate 212. According to alternative embodiments, TSV 214 further extends downward into one of the dielectric layers 216. Conductive components 218 are schematically shown to represent front-end conductive components, including contact plugs, metal lines, vias, metal pads, metal pillars, etc.

[0024] According to some embodiments, the first device die 210 is bonded to the carrier 110 by fusion bonding. For example, the bottom dielectric layer in the device die 210 can be a silicon-containing dielectric layer formed of silicon oxide, silicon oxynitride, silicon oxycarbide, etc. When the dielectric layer 112 is not formed, the device die 210 can be directly bonded to the carrier 110 by fusion bonding. Fusion bonding can result in the formation of Si-O-Si bonds to bond the device die 210 to the carrier 10. According to alternative embodiments, the carrier 110 can be formed of materials other than silicon, such as glass, organic materials, etc. Therefore, the dielectric layer 112 can also be an adhesive layer, which can be a photothermal conversion (LTHC) film.

[0025] Figure 2 The gap filling process for the sealing device die 210 is shown. The corresponding process is shown as follows: Figure 35 Process 604 in the illustrated process flow 600. According to some embodiments, the gap-filling region 220 is formed of or includes an inorganic material. For example, the formation of the gap-filling region 220 may include depositing a dielectric pad (which is also an etch stop layer) and depositing a dielectric material over the dielectric pad. The dielectric pad may be a conformal layer extending to the top surface of the dielectric layer 112 and the sidewalls and top surface of the device die 210. The etch stop layer is formed of a dielectric material having good adhesion to the sidewalls of the device die 210 and the top surface of the dielectric layer 112. According to some embodiments of the invention, the etch stop layer is formed of a nitride-containing material such as silicon nitride. Deposition may include conformal deposition processes such as atomic layer deposition (ALD) or chemical vapor deposition (CVD). The dielectric material deposited on the etch stop layer may be formed of or include silicon oxide. According to alternative embodiments, the gap-filling region 220 is formed of molding compound, epoxy resin, resin, etc. A planarization process, such as chemical mechanical polishing (CMP) or mechanical polishing, is performed to make the back surface of device die 210 (the top surface shown) flush with the top surface of gap-filling region 220. The planarization process stops after the through-hole 214 is exposed. When viewed in the top view of the structure shown, gap-filling region 220 (and subsequently gap-filling regions formed in the upper layer) surrounds the respective device die.

[0026] In the subsequent process, an etching process is performed to recess the back side of substrate 212, forming a groove through which the sidewalls of gap-filled region 220 are exposed. Through-hole 214 is not recessed, such that its end protrudes beyond the recessed back side of substrate 212. Next, a dielectric material (such as silicon oxide, silicon nitride, etc.) is filled into the groove, followed by a polishing process to remove excess dielectric layer, leaving dielectric layer 226 in the groove. Throughout the description, dielectric layer 216 is considered part of device die 210.

[0027] The through-hole 225 (a dielectric via) is also formed as a through gap filling region 220. The corresponding process is shown as follows. Figure 35 Process 606 in the illustrated process flow 600. According to some embodiments, the forming process may include etching the gap-filling region 220 to form an opening penetrating the gap-filling region 220. A conductive material (such as titanium nitride, copper, tungsten, or multilayers thereof) is then filled into the opening. A planarization process, such as a CMP process or a mechanical polishing process, is then performed to remove excess portions of the conductive material, leaving a through-hole 225 in the opening.

[0028] Figure 2 It is also shown that a back-side interconnect structure 230 is formed on the back side of the device die 210. The corresponding process is shown as follows. Figure 35 Process 608 in the illustrated process flow 600. One or more dielectric layers 224 are deposited over the device die 210 and the gap-fill region 220. The dielectric layer 224 may also be formed of inorganic materials (such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, low-k materials, etc.) or organic materials (such as polyimide, polybenzoxazole (PBO), etc.). The back-side interconnect structure 230 may include RDLs and bonding pads 228 in the dielectric layers. Although a single-layer interconnect structure 230 is shown as an example, one or more dielectric layers and corresponding RDL / metal pads 228 may be present therein. The device die 210, the gap-fill region 220, and the interconnect structure 230 together form a reconstructed wafer 232.

[0029] refer to Figure 3 The second-layer device die 310 is placed above the reconstructed wafer 232 and bonded to the reconstructed wafer 232 via on-wafer bonding. The corresponding process is shown as follows. Figure 35 Process 610 in the illustrated process flow 600. The shown bonding scheme is also face-to-back bonding, but other bonding schemes, such as face-to-face bonding or back-to-back bonding, can be used. Bonding can be at the wafer level. Thus, although one device die 310 is shown, multiple identical device dies 310 are suitable for bonding to a reconstructed wafer 232. Device die 310 includes a substrate 312. According to some embodiments, device die 310 includes active circuitry located at the illustrated bottom surface of semiconductor substrate 312. Through-holes 314 can be formed as an intermediate layer extending between the top and bottom surfaces of substrate 312. Conductive components 318 are formed in dielectric layer 316 to connect to the active circuitry.

[0030] Device die 310 is bonded to reconstructed wafer 232 via hybrid bonding, which includes direct metal-to-metal bonding and fusion bonding. For example, the bottom dielectric layer in device die 310 is bonded to the top dielectric layer 224 via fusion bonding, and the bonding pad 322 in device die 310 is bonded to bonding pad 228 via direct metal-to-metal bonding.

[0031] Figure 4 The gap filling of device die 310 is shown. The corresponding process is shown as follows. Figure 35 Process 612 in the process flow 600 shown. The materials and forming processes can be selected from the corresponding candidate materials and candidate forming processes for the gap-filling region 220, and details will not be repeated here. A planarization process, such as CMP or mechanical polishing, is performed to make the back side of the device die 310 (the top surface shown) flush with the top surface of the gap-filling region 320. The planarization process is stopped after the through-hole 314 is exposed.

[0032] In the subsequent process, an etching process is performed to recess the back side of the substrate 312. A dielectric layer 226 is formed in the recess to surround the top portion of the through-hole 314. A back-side interconnect structure 330 is then formed on the back side of the device die 210. The corresponding process is shown as follows. Figure 35 Process 614 in the illustrated process flow 600. The back-side interconnect structure 330 may include one or more dielectric layers 324, which may be formed of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, polyimide, PBO, etc. RDL / bonding pads 328 are formed in the dielectric layer 324. Throughout the description, the device die 310, the gap fill region 320, and the interconnect structure 330 together form the reconstructed wafer 332.

[0033] refer to Figure 5 The third-layer device die 410 is placed on top of the reconstructed wafer 332 and bonded to the reconstructed wafer 332 via wafer-on-wafer bonding. The corresponding process is shown as follows. Figure 35 Process 616 in the illustrated process flow 600. The shown bonding scheme is also face-to-back bonding, but other bonding schemes, such as face-to-face bonding or back-to-back bonding, can be used. Bonding can be at the wafer level. Therefore, although a set of device dies 410 is shown, multiple sets of device dies 410 are suitable for bonding to the reconstructed wafer 332. Some device dies 410 may be identical to each other and may be the same as or different from other device dies 410. Device die 410 includes a semiconductor substrate 412. According to some embodiments, device die 410 includes active circuitry located on the surface of the semiconductor substrate 412. Conductive components 418 are formed to connect to the active circuitry and are formed in a dielectric layer 416.

[0034] Device die 410 is bonded to reconstructed wafer 332 via hybrid bonding, which includes direct metal-to-metal bonding and fusion bonding. For example, the bottom dielectric layer in device die 410 is bonded to the top dielectric layer 324 via fusion bonding, and the bonding pad 422 in device die 410 is bonded to bonding pad 328 via direct metal-to-metal bonding.

[0035] Figure 6 The gap filling of device die 410 is shown. The corresponding process is shown as follows. Figure 35 Process 618 in the process flow 600 shown. The materials and forming processes can be selected from the corresponding candidate materials and candidate forming processes for the gap filling region 220, and details will not be repeated here. A planarization process such as CMP or mechanical polishing is performed to make the back side of the device die 410 (the top surface shown) flush with the top surface of the gap filling region 420.

[0036] In subsequent processes, a bonding layer 424 is deposited on top of the gap-filling region 420 and the device die 410. The bonding layer 424 may be a silicon-containing dielectric layer, which may be formed of or include silicon oxide, silicon oxynitride, silicon carbonitride, etc.

[0037] Next, the carrier replacement process will be performed, such as... Figure 7 As shown. The corresponding process is shown as follows. Figure 35 Process 620 in the illustrated process flow 600. The carrier replacement process includes attaching a carrier 510 to a reconstructed wafer 432. According to some embodiments, the carrier 510 is formed of or comprises a silicon carrier, and a dielectric / bonding layer 512 is formed on the carrier 510. The dielectric layer 512 may be formed of or comprise silicon oxide or another silicon-containing dielectric material. The bonding can therefore be fused bonding. In a subsequent process, the carrier 110 is removed from the reconstructed wafer 232. For example, when the carrier 110 is formed of silicon, the carrier 110 can be separated from the reconstructed wafer 232 by laser lifting, or it can be removed by grinding. When the carrier 110 is a glass carrier and the dielectric layer 112 comprises LTHC, this debonding can be performed by projecting a laser beam onto the dielectric layer 112 to cause layer decomposition.

[0038] Further reference Figure 7 The through-hole 125 (a dielectric via) is formed to penetrate the gap-filled region 220, the interconnect structure 230, and the gap-filled region 320. The corresponding process is shown as follows: Figure 35Process 622 in the illustrated process flow 600. According to some embodiments, the formation process may include etching gap-filling regions 220, dielectric layers 224, and gap-filling regions 320 to form an opening through which bonding pads 328 are exposed. A conductive material, such as titanium nitride, copper, tungsten, or a multilayer thereof, is then filled into the opening. A planarization process, such as CMP or mechanical polishing, is then performed to remove excess conductive material, leaving through-holes 125 in the opening. It should be understood that by forming through-holes 125 that directly penetrate the two gap-filling regions, the connection from the device die 410 to the subsequently formed interconnect structure 244 does not need to traverse multiple layers of RDL and metal pads. The resistance of the electrical path is therefore lower, and RC delay and voltage drop are reduced.

[0039] According to an optional embodiment, instead of forming through-holes 125 that penetrate the gap-fill region 220, the interconnect structure 230, and the gap-fill region 320, each through-hole 125 is divided into a first through-hole in the first gap-fill region 220 and a second through-hole penetrating the gap-fill region 320. The first through-hole and the corresponding second through-hole are electrically interconnected via bonding pads / RDL 228 in the redistribution structure 230.

[0040] After forming the through-hole 125, an interconnect structure 244 is formed, which includes a dielectric layer 240 and an RDL 242 within the dielectric layer 240. Then, an electrical connector 246 is formed on the bottom surface of the interconnect structure 244, and the electrical connector 246 is electrically connected to the device die 210 and the through-holes 125 and 225. The corresponding process is shown as follows. Figure 35 Process 624 in the process flow 600 shown.

[0041] Figure 7 The structures within are collectively referred to as reconstructed wafer 20. A dicing process can be performed to divide the reconstructed wafer 20 into multiple identical packages 20'. The corresponding process is shown below. Figure 35 Process 626 in the illustrated process flow 600. According to some embodiments, the reconstructed wafer 20 is sawn without removing the carrier 510, and the sawn portion of the carrier 510 remains within the package 20'. According to an alternative embodiment, the carrier 510 is removed prior to the dicing process. Therefore, the top surface of the resulting package 20' can be located at the top level of the dielectric layer 512, or, if the dielectric layer 512 is removed, at the top level of the device die 410.

[0042] like Figure 7As shown, device die 310 extends laterally beyond the corresponding edge of the underlying device die 210. Therefore, via 225 can overlap with device die 310. Via 225 directly connects bonding pad 228 (and device die 310) to interconnect structure 244 without passing through via 214 in device die 210 and metal lines and vias. Via 125 can also be formed to directly connect bonding pad 328 (and device die 410) to interconnect structure 244 without passing through vias 214 and 314 in devices dies 210 and 310 and metal lines and vias. Therefore, the resistance of the connection path is reduced, and RC delay and voltage drop are reduced. According to some embodiments, vias 125 and 225 can have a larger lateral dimension than vias inside the device die, and can therefore be used to provide power supplies such as VDD and VSS, while signal connections between devices on different layers can be provided by vias inside the device die. For example, according to some embodiments, all power connections from interconnect structure 244 to second-layer device die 310 and third-layer device die 410 can be through dielectric vias such as 125 and 225, and all signal connections can be through semiconductor vias such as 214 and 314.

[0043] Device die 310 is connected to two device dies 410. Therefore, device die 310 can be used as a bridging die and provides lateral transmission of signals and / or power between device dies 410. The signal path may include metal wires as well as vias and bonding pads in device dies 310 and 410. Furthermore, the signal path may include digital devices such as switches, routers, etc., or an all-metal connection including metal wires / pads and vias.

[0044] Figures 8 to 14 The formation of a package according to an alternative embodiment of the present invention is illustrated. These embodiments are similar to... Figures 1 to 7 In the embodiments shown, in addition to two or more second-layer device dies 310 being bonded to a first-layer device die 210, a third-layer device die 410 may be bonded to two second-layer device dies 310. Unless otherwise stated, these embodiments (and) Figures 15 to 32 The materials and forming processes of the components in the illustrated embodiment are similar to those in... Figures 1 to 7 The same components referred to by the same reference numerals in the foregoing embodiments shown are substantially the same. Therefore, information about the foregoing embodiments can be found in the discussion of the foregoing embodiments. Figures 8 to 32 Details of the manufacturing process and materials of the components shown.

[0045] refer to Figure 8 For example, the first layer of device die 210 is attached to the carrier 110 by melt bonding or by adhesive. Next, as... Figure 9As shown, a gap-filling region 220 is formed to seal the device die 210. A planarization process is then performed to make the top surface of the device die 210, the top surface of the through-hole 214, and the top surface of the gap-filling region 220 flush. According to some embodiments, different... Figure 2 In the illustrated embodiment, no through-hole is formed in the gap-filling region 220 at this stage. According to an alternative embodiment, with... Figure 2 Similarly, through-holes 225 can also be formed at this stage to penetrate the gap-filled region 220. A dielectric layer 226 is then formed by recessing the semiconductor substrate 212 and filling the resulting groove with dielectric material. Next, an interconnect structure 230, including a dielectric layer 224 and bonding pads / RDLs 228, is formed over the gap-filled region 220 and the device die 210. This results in the formation of a reconstructed wafer 232.

[0046] refer to Figure 10 For example, the second-layer device die 310 can be bonded to the reconstructed wafer 232 via hybrid bonding. The bonding can also be face-to-back bonding, or other bonding schemes can be employed. According to some embodiments, two or more device dies 310 are bonded to the same device die 210. Therefore, the device die 210 can also be used as a bridging die (in addition to its other functions) to provide lateral connectivity between device dies 310. One or more device dies 310 may extend laterally beyond the corresponding edges of the device die 210, wherein some bonding pads 322 of the device die 310 are also vertically offset from the device die 210.

[0047] Next, as Figure 11 As shown, gap-fill regions 320 are formed, and then planarized such that their back surfaces are coplanar with the back surface of the substrate 312. Through-holes 325 (dielectric vias) are then formed to penetrate the gap-fill regions 320 and connect to the bonding pads 228. A dielectric layer 326 is also formed to surround the top portion of the through-holes 314. An interconnect structure 330 is then formed, comprising a dielectric layer 324 and RDL / bonding pads 328. Thus, a reconstructed wafer 332 is formed.

[0048] Figure 12 The bonding of a third-layer device die 410 is shown, which is bonded to two device dies 310. Therefore, according to some embodiments, device die 410 can also be used as a bridging die to interconnect the two device dies 310. Device die 410 is electrically connected to device die 210 through a through-hole 325, without through any semiconductor vias in device die 310.

[0049] Figure 13The sealing of the device die 410 in the gap-filling region 420 and the formation of the bonding layer 424 are shown. This forms a reconstructed wafer 432. Next, a carrier 510 is attached or bonded to the reconstructed wafer 432, for example by fusion bonding, with a dielectric layer 512 on the surface of the carrier 510 bonded to the bonding layer 424. The carrier 510 can be a silicon carrier, a glass wafer, etc. The carrier 510 can also be attached to the reconstructed wafer 432 by adhesive rather than by fusion bonding.

[0050] In subsequent processes, the carrier 110 is detached from the reconstructed wafer 232, and a through-hole 225 is subsequently formed. Figure 14 The resulting structure is shown in the figure. Next, an interconnect structure 244 is formed, which includes a dielectric layer 240 and forms RDL / bonding pads 242. Electrical connectors 246 are also formed to electrically connect to the through-hole 225 and the device die 210 through the interconnect structure 244. Thus, a reconstructed wafer 20 is formed.

[0051] In subsequent processes, the wafer 20 is diced and reconstructed to form multiple identical packages 20'. Again, packages 20' may or may not include the remainder of the carrier 510, and may or may not include the remainder of the bonding layers 424 and 512.

[0052] Figures 15 to 19 The formation of a package according to an alternative embodiment of the present invention is illustrated. These embodiments are similar to... Figures 1 to 14 The embodiment shown has two layers (instead of three layers) of device die. Reference Figure 15 The first-layer device die 210 is attached to the carrier 110. Next, as... Figure 16 As shown, a gap-filling region 220 is formed to seal the device die 210, followed by the formation of a dielectric layer 226. An interconnect structure 230 is then formed, comprising a dielectric layer 224 and bonding pads / RDLs 228 within the dielectric layer 224. This results in the formation of a reconstructed wafer 232.

[0053] refer to Figure 17 For example, the second-layer device die 310 can be bonded to the reconstructed wafer 232 via hybrid bonding. The bonding can be face-to-back bonding, but other bonding schemes are also possible. According to some embodiments, two or more device dies 310 are bonded to the same device die 210. Therefore, the device die 210 can also be used as a bridging die (in addition to its other functions) to provide lateral connectivity between device dies 310. One or more device dies 310 may extend laterally beyond the corresponding edges of the device die 210, wherein some bonding pads 322 of the device die 310 are also vertically offset from the device die 210.

[0054] Next, as Figure 18 As shown, gap-filling regions 320 are formed and then planarized such that their back surfaces are coplanar with the back surface of the substrate 312. When viewed in a top view, the gap-filling regions 320 surround the device die 310. A bonding layer 324, which is a dielectric layer, is then formed. Thus, a reconstructed wafer 332 is formed. Next, a carrier 510 is attached to the reconstructed wafer 332, for example, by fusion bonding, with the dielectric layer 512 on the surface of the carrier 510 bonded to the bonding layer 324. The carrier 510 can be a silicon carrier or a glass wafer. The carrier 510 can also be attached to the reconstructed wafer 332 by adhesive rather than by fusion bonding.

[0055] In subsequent processes, the carrier 110 is detached from the reconstructed wafer 232, subsequently forming the through-hole 225. Figure 19 The resulting structure is shown in the figure. Next, an interconnect structure 244 is formed, which includes a dielectric layer 240 and forms RDL / bonding pads 242. Electrical connectors 246 are also formed to electrically connect to the through-hole 225 and the device die 210 through the interconnect structure 244. Thus, a reconstructed wafer 20 is formed.

[0056] In subsequent processes, the wafer 20 is diced and reconstructed to form multiple identical packages 20'. Again, packages 20' may or may not include the remainder of the carrier 510, and may or may not include the remainder of dielectric layers 324 and 512.

[0057] Figure 20 A reconstructed wafer 20 and a corresponding package 20' according to an optional embodiment are shown. These embodiments are similar to... Figure 19 In the embodiment shown, in addition to a single second-layer device die 310 being bonded to device die 210, device die 310 extends laterally beyond the edge of device die 210, allowing through-hole 225 to be formed directly below device die 310 and interconnecting device die 310 and interconnect structure 244.

[0058] Figures 21 to 24 The formation of a package according to an alternative embodiment of the present invention is illustrated. These embodiments are similar to the foregoing embodiments, except that the carrier 110 is replaced by a device wafer 110'. Reference Figure 21 The second-layer device die 210 is bonded to the device die 110” in the device wafer 110” via hybrid bonding. The bonding can be surface-to-surface bonding, but other bonding schemes can also be used. The device die 110” also includes a semiconductor substrate 112 and active circuitry (not shown) located on the top surface of the semiconductor substrate 112. In addition, the device die 110” includes a dielectric layer 116, conductive components 118, a surface dielectric layer 124, and bonding pads 128.

[0059] Next, as Figure 22 As shown, a gap-fill region 220 is formed to seal the device die 210, followed by the formation of a dielectric layer 226. A through-hole 325 is also formed in the gap-fill region 220 and electrically connected to the bonding pad 128. An interconnect structure 230 is then formed, comprising a dielectric layer 224 and bonding pads / RDLs 228 within the dielectric layer 224. This results in the formation of a reconstructed wafer 232.

[0060] refer to Figure 23 For example, the second-layer device die 310 can be bonded to the reconstructed wafer 232 via hybrid bonding. The bonding can be face-to-back bonding, but other bonding schemes are also possible. According to some embodiments, two or more device dies 310 are bonded to the same device die 210. Therefore, the device die 210 can also be used as a bridging die (in addition to its other functions) to provide lateral connectivity for the device die 310. One or more device dies 310 may extend laterally beyond the corresponding edges of the device die 210, wherein some bonding pads 322 of the device die 310 are also vertically offset from the device die 210.

[0061] Next, as Figure 24 As shown, a gap-filling region 320 is formed to seal the device die 310, and then planarized so that their back surfaces are coplanar with the back surface of the substrate 312. The semiconductor substrate 312 and the gap-filling region 320 can be recessed, and then a dielectric layer 326 is formed to surround the top portion of the through-hole 314 in the device die 310.

[0062] Next, an interconnect structure 244, including a dielectric layer 240 and RDL / bonding pads 242, is formed over and electrically connected to the device die 410. Electrical connections 246 are also formed to be electrically connected to the device die 310 via the interconnect structure 244. Thus, a reconstructed wafer 20 is formed. In subsequent processes, the reconstructed wafer 20 is diced to form multiple identical packages 20'.

[0063] Figure 25 A reconstructed wafer 20 and a corresponding package 20' according to an optional embodiment are shown. These embodiments are similar to... Figure 24 In the embodiment shown, in addition to a single device die 310 being bonded to device die 210, device die 310 extends laterally beyond the edge of device die 210, allowing through-hole 225 to be formed directly below device die 310 and interconnecting device die 310 and interconnect structure 244.

[0064] Figures 26 to 31 The formation of a package according to an alternative embodiment of the present invention is illustrated. These embodiments are similar to those shown below. Figures 21 to 25The illustrated embodiment (device wafer used to replace the carrier) differs from the previous one, where three layers of device dies are stacked on top of the bottom wafer 110'. Reference Figure 26 The second-layer device die 210 is stacked on the device die 110” in the device wafer 110’ through hybrid bonding. The bonding can be surface-to-surface bonding, but other bonding schemes can also be used.

[0065] Next, as Figure 27 As shown, a gap-fill region 220 is formed to seal the device die 210, followed by the formation of a dielectric layer 226. A through-hole 225 is also formed in the gap-fill region 220 and electrically connected to the bonding pad 128. An interconnect structure 230 is then formed, comprising a dielectric layer 224 and bonding pads / RDLs 228 within the dielectric layer 224. This results in the formation of a reconstructed wafer 232.

[0066] refer to Figure 28 For example, the second-layer device die 310 can be bonded to the reconstructed wafer 232 via hybrid bonding. The bonding can also be face-to-back bonding, but other bonding schemes are also possible. According to some embodiments, two or more device dies 310 are bonded to the same device die 210. Therefore, device die 210 can also be used as a bridging die (in addition to its other functions) to provide lateral interconnects for device dies 310. One or more device dies 310 may extend laterally beyond the corresponding edges of device die 210, wherein some bonding pads 322 of device die 310 are also vertically offset from device die 210.

[0067] Next, as Figure 29 As shown, gap-filling regions 320 are formed and then planarized so that their back surfaces are coplanar with the back surface of the substrate 312. Through-holes 325 are formed in the gap-filling regions 320. The semiconductor substrate 312 and the gap-filling regions 320 can be recessed, and then a dielectric layer 226 is formed to surround the top portion of the through-holes 314 in the device die 310.

[0068] Figure 30 The diagram illustrates the bonding of device die 410 to two device dies 310. Therefore, according to some embodiments, device die 410 can also be used as a bridging die to interconnect the two device dies 310. Device die 410 is electrically connected to device die 210 via through-hole 325, without through any semiconductor vias in device die 310.

[0069] Figure 31This illustrates the sealing of the device die 410 within the gap-fill region 420. A reconstructed wafer 432 is thus formed. The semiconductor substrate 412 and the gap-fill region 420 can be recessed, and then a dielectric layer 426 is formed to surround the top portion of the through-hole 414 in the device die 410.

[0070] Next, an interconnect structure 244, including a dielectric layer 240 and RDL / bonding pads 242, is formed over and electrically connected to the device die 410. Electrical connections 246 are also formed. Thus, a reconstructed wafer 20 is formed. In subsequent processes, the reconstructed wafer 20 is diced to form multiple identical packages 20'.

[0071] Figure 32 A reconstructed wafer 20 and a corresponding package 20' according to an optional embodiment are shown. These embodiments are similar to... Figure 31 In the embodiment shown, in addition to a single device die 310 being bonded to device die 210, two device dies 410 are bonded to one device die 310. Furthermore, a through-hole 425 is formed in the gap-filled region 420. Figure 31 and Figure 32 In one embodiment, device die 310 extends laterally beyond the edge of device die 210, such that through-hole 225 can be formed directly below device die 310 and interconnect device dies 310 and 110.

[0072] Figure 33 and Figure 34 Top and cross-sectional views of portions of the example package 20' are shown, respectively. According to some embodiments, a plurality of second-layer device dies 210 are arranged in an array. A plurality of third-layer device dies 310A and 310B are located above and bonded to the second-layer device dies. The third-layer device die 310B is a bridging die, each bridging die bonded to two adjacent device dies 210.

[0073] In the embodiments shown above, some processes and components for forming three-dimensional (3D) packages were discussed according to some embodiments of the present invention. Other components and processes may also be included. For example, test structures may be included to assist in verification testing of 3D packaged or 3DIC devices. Test structures may include, for example, test pads formed in a redistribution layer or on a substrate, which allow testing of the 3D package or 3DIC using probes and / or probe cards, etc. Verification testing can be performed on intermediate structures as well as the final structure. Furthermore, the structures and methods disclosed herein can be combined with test methods that incorporate intermediate verification of known good dies to increase yield and reduce costs.

[0074] In the embodiments discussed above, two to four layers of device dies are shown. According to alternative embodiments, more layers of device dies may be employed. According to some example embodiments, the bottom layer may include logic device dies, such as CPU dies, GPU dies, etc., while the upper layer may include memory device dies.

[0075] Embodiments of the present invention have several advantageous features. By forming dielectric vias in the gap-filling regions, the dielectric vias replace some of the semiconductor vias, and therefore have a lower resistivity. The RC delay and voltage drop caused by the semiconductor vias and the corresponding metal lines and vias are correspondingly reduced.

[0076] According to some embodiments of the present invention, a method includes bonding a first-layer device die to a first carrier; forming a first gap-fill region to seal the first-layer device die; forming a first redistribution structure over the first-layer device die and electrically connected to the first-layer device die; bonding a first and second-layer device die to the first-layer device die, wherein the first and second-layer device dies are located over the first-layer device die and extend laterally beyond corresponding edges of the first-layer device die; forming a second gap-fill region to seal the first and second-layer device dies; removing the first carrier; forming a first dielectric via penetrating the first gap-fill region, wherein the first dielectric via overlaps with and is electrically connected to the first and second-layer device die; and forming a second redistribution structure, wherein the first and second redistribution structures are located on opposite sides of the first-layer device die. In an embodiment, the first redistribution structure includes a dielectric layer and a first bonding pad and a second bonding pad, wherein a third bonding pad of the first and second-layer device die is bonded to the first bonding pad, and the first dielectric via is physically connected to the second bonding pad. In one embodiment, a first dielectric via is formed before forming the first redistribution structure. In another embodiment, the first dielectric via is formed after forming the first redistribution structure and after removing the first carrier. In yet another embodiment, the method further includes bonding a second carrier over the first second-layer device die before removing the first carrier. In yet another embodiment, the method further includes bonding a second second-layer device die to a first-layer device die, wherein the second second-layer device die is located above the first-layer device die, and the first-layer device die electrically bridges the first second-layer device die to the second second-layer device die. In yet another embodiment, the first redistribution structure is a single-layer redistribution structure, including a single-layer dielectric; and bonding pads, wherein a first top surface and a first bottom surface of the bonding pads are coplanar with corresponding second top and second bottom surfaces of the single-layer dielectric. In yet another embodiment, the method further includes bonding a third-layer device die to the first second-layer device die, wherein the third-layer device die is located above the first second-layer device die, and the third-layer device die extends laterally beyond corresponding edges of the first second-layer device die; and forming a third gap-filling region to seal the third-layer device die. In one embodiment, the method further includes forming a second dielectric via to penetrate the first gap-fill region, the first redistribution structure, and the second gap-fill region. In another embodiment, the second dielectric via lands on a metal pad in the second redistribution structure.

[0077] According to some embodiments of the present invention, the package includes a first redistribution structure; a first device die located above the first redistribution structure, wherein the first device die includes: a first semiconductor substrate; and a first semiconductor via penetrating the first semiconductor substrate; a first gap-filling region sealing the first device die; a second redistribution structure located above the first device die and the first semiconductor via and electrically connected to the first device die and the first semiconductor via; a first and second device die located above the first device die and bonded to the first device die, wherein the first and second device dies extend laterally beyond corresponding edges of the first device die; a second gap-filling region sealing the first and second device dies; and a first dielectric via penetrating the first gap-filling region, wherein the first dielectric via electrically connects the first and second device dies to the first redistribution structure. In an embodiment, the first dielectric via overlaps with the first and second device dies. In one embodiment, the package further includes a third device die located above and bonded to the first and second device dies, wherein the third device die further extends laterally beyond the corresponding edges of the first and second device dies; and a third gap-filling region sealing the third device die. In another embodiment, the package further includes a second dielectric via penetrating the first gap-filling region, the second redistribution structure, and the second gap-filling region. In another embodiment, the second dielectric via includes a portion continuously extending into the first gap-filling region, the second redistribution structure, and the second gap-filling region, and has no interface in this portion. In yet another embodiment, the package further includes a second dielectric via penetrating the second gap-filling region, wherein the second dielectric via overlaps with and is electrically connected to the first device die.

[0078] According to some embodiments of the present invention, a package includes a first redistribution structure; a first device die located above the first redistribution structure; a first gap-filling region sealing the first device die; a second device die located above the first device die, wherein the second device die extends laterally beyond a first edge of the first device die; a second gap-filling region sealing the second device die; a third device die located above the second device die, wherein the third device die extends laterally beyond a second edge of the second device die; a third gap-filling region sealing the third device die; a first dielectric via located in the first gap-filling region, wherein the first dielectric via overlaps with and is electrically connected to the second device die; and a second dielectric via overlapping with the third device die, wherein the second dielectric via penetrates both the first gap-filling region and the second gap-filling region. In an embodiment, the second dielectric via includes a portion continuously extending through the first gap-filling region and the second gap-filling region, in which there is no interface. In an embodiment, the second dielectric via has a first top end and a first bottom end wider than the first top end. In an embodiment, the first dielectric via has a second top end and a second bottom end narrower than the second top end.

[0079] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a base to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent configurations do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made to them herein without departing from the spirit and scope of the invention.

Claims

1. A method of forming a package, comprising: Bond the first-layer device die to the first carrier; A first gap-filling region is formed to seal the first layer of the device die; A first redistribution structure is formed above the first layer device die, and the first redistribution structure is electrically connected to the first layer device die; The first and second layer device dies are bonded to the first layer device die, wherein the first and second layer device dies are located above the first layer device die, and the first and second layer device dies extend laterally beyond the corresponding edges of the first layer device die; A second gap-filling region is formed to seal the first and second layer device die; Remove the first carrier; A first dielectric via is formed that penetrates the first gap filling region, wherein the first dielectric via overlaps with and is electrically connected to the first and second layer device die; A second dielectric via is formed to penetrate the first gap-filling region, the first redistribution structure, and the second gap-filling region, wherein the first dielectric via and the second dielectric via are formed from different directions; and A second redistribution structure is formed, wherein the first redistribution structure and the second redistribution structure are located on opposite sides of the first layer device die.

2. The method of claim 1, wherein, The first redistribution structure includes a dielectric layer and a first bonding pad and a second bonding pad, wherein a third bonding pad of the first second layer device die is bonded to the first bonding pad, and the first dielectric via is physically connected to the second bonding pad.

3. The method of claim 1, wherein, The first dielectric via is formed before the first redistribution structure is formed.

4. The method of claim 1, wherein, After the first redistribution structure is formed, and after the first carrier is removed, the first dielectric via is formed.

5. The method of claim 1, further comprising bonding a second carrier over the first second-layer device die before removing the first carrier.

6. The method of claim 1, further comprising bonding a second second-tier device die to the first-tier device die, wherein, The second layer device die is located above the first layer device die, and the first layer device die electrically bridges the first layer device die to the second layer device die.

7. The method of claim 1, wherein, The first redistribution structure is a single-layer redistribution structure, comprising: Single-layer dielectric; and The bonding pads have a first top surface and a first bottom surface that are coplanar with the corresponding second top surface and second bottom surface of the monolayer dielectric.

8. The method according to claim 1, further comprising: A third-layer device die is bonded to a first and second-layer device die, wherein the third-layer device die is located above the first and second-layer device die, and the third-layer device die extends laterally beyond the corresponding edge of the first and second-layer device die; and A third gap filling region is formed to seal the third layer device die.

9. The method of claim 1, wherein, The first dielectric via has a top end and a bottom end that is narrower than the top end.

10. The method of claim 9, wherein, The second dielectric via lands on a metal pad in the second redistribution structure.

11. A package comprising: First redistribution structure; The first layer of device die is located above the first redistribution structure, wherein the first layer of device die includes: First semiconductor substrate; and A first semiconductor via penetrates the first semiconductor substrate; The first gap filling area seals the first layer of the device die; The second redistribution structure is located above the first layer device die and the first semiconductor via and is electrically connected to the first layer device die and the first semiconductor via. First and second layer device dies are located above and attached to the first layer device die, wherein the first and second layer device dies extend laterally beyond the corresponding edges of the first layer device die. The second gap filling area seals the first and second layer device dies; and A first dielectric via penetrates the first gap-filling region, wherein the first dielectric via electrically connects the first second-layer device die to the first redistribution structure. A third-layer device die is located above and bonded to the first and second-layer device dies, wherein the third-layer device die includes a die edge that forms part of the outermost edge of the package.

12. The package of claim 11, wherein, The first dielectric via overlaps with the first and second layer device die.

13. The package of claim 11, wherein, The first dielectric via has a top end and a bottom end that is narrower than the top end.

14. The package of claim 11, further comprising a second dielectric via penetrating the first gap-filling region, the second redistribution structure, and the second gap-filling region.

15. The package of claim 14, wherein, The second dielectric via includes a portion that extends continuously into the first gap-filling region, the second redistribution structure, and the second gap-filling region, wherein there is no interface in the portion.

16. The package of claim 11, further comprising a second dielectric via that penetrates the second gap-fill region, wherein, The second dielectric via overlaps with and is electrically connected to the first layer device die.

17. A package comprising: First redistribution structure; The first device die is located above the first redistribution structure; The first gap filling area seals the die of the first device. The second device die is located above the first device die, wherein the second device die extends laterally beyond the first edge of the first device die. The second gap filling area seals the second device die; A third device die is located above the second device die, wherein the third device die extends laterally beyond the second edge of the second device die, and wherein the third device die includes a die edge that forms part of the outermost edge of the package; The third gap filling area seals the die of the third device. A first dielectric via is located in the first gap-filling region, wherein the first dielectric via overlaps with and is electrically connected to the second device die; and The second dielectric via overlaps with the third device die, wherein the second dielectric via penetrates the first gap-filling region and the second gap-filling region.

18. The package of claim 17, wherein, The second dielectric via includes a portion that extends continuously through the first gap-filling region and the second gap-filling region, in which there is no interface.

19. The package of claim 17, wherein, The second dielectric via has a first top end and a first bottom end that is wider than the first top end.

20. The package of claim 19, wherein, The first dielectric via has a second top end and a second bottom end that is narrower than the second top end.

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