Semiconductor structure and method of fabricating the same

Abstract

The embodiments of the present disclosure disclose a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises: a plurality of transistors in a semiconductor layer; each transistor comprises a semiconductor body extending along a first direction and a gate structure covering at least one side of the semiconductor body; the first direction is a thickness direction of the semiconductor layer; a plurality of conductive columns; each conductive column is located on a top surface of a corresponding one of the semiconductor bodies and directly contacts the corresponding one of the semiconductor bodies; and a storage structure covering the plurality of conductive columns.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a semiconductor structure and a method for fabricating the same. Background Technology

[0002] The memory array architecture of Dynamic Random Access Memory (DRAM) consists of an array of memory cells (i.e., 1T1C memory cells) each containing one transistor and one capacitor. The gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor.

[0003] As the size of dynamic random access memory (DRAM) continues to shrink, the size of capacitors also shrinks. Ensuring the performance of capacitors in DRAM has become a pressing issue. Summary of the Invention

[0004] In view of this, the present disclosure provides a semiconductor structure and a method for fabricating the same.

[0005] According to one aspect of this disclosure, a semiconductor structure is provided, comprising:

[0006] Multiple transistors are located in a semiconductor layer; each transistor includes a semiconductor body extending along a first direction and a gate structure covering at least one side of the semiconductor body; the first direction is the thickness direction of the semiconductor layer;

[0007] Multiple conductive pillars; each conductive pillar is located on the top surface of a corresponding semiconductor body and is in direct contact with the corresponding semiconductor body;

[0008] The storage structure covers the plurality of conductive pillars.

[0009] In the above scheme, each conductive pillar includes N sub-conductive pillars stacked along the first direction, where N is a positive integer greater than or equal to 1; correspondingly, the storage structure includes N sub-storage structures stacked along the first direction.

[0010] In the above scheme, the three sub-memory structures stacked in the first direction include the following semiconductor structures:

[0011] A first sub-conductive pillar located on the top surface of each of the semiconductor bodies; a first sub-memory structure covering the sidewalls of the first sub-conductive pillar;

[0012] A second sub-conductive pillar located on the top surface of each of the first sub-conductive pillars; a second sub-storage structure covering the sidewalls of the second sub-conductive pillars;

[0013] A third sub-conductive pillar located on the top surface of each of the second sub-conductive pillars; a third sub-storage structure covering the top surface and sidewalls of the third sub-conductive pillars;

[0014] The first sub-conductive pillar, the second sub-conductive pillar, and the third sub-conductive pillar are in direct contact with each other, as are the first sub-storage structure, the second sub-storage structure, and the third sub-storage structure.

[0015] In the above scheme, the first sub-memory structure includes: a plurality of lower electrode conductive layers covering the sidewall of each of the first sub-conductive pillars, a plurality of dielectric layers covering each of the lower electrode conductive layers, an upper electrode conductive layer covering the top surface of the plurality of dielectric layers and the semiconductor layer between two adjacent dielectric layers, and a conductive material layer and a dielectric material layer sequentially stacked in the upper electrode conductive layer.

[0016] The second sub-storage structure includes: a plurality of lower electrode conductive layers covering the sidewalls of each of the second sub-conductive pillars, a plurality of dielectric layers covering each of the lower electrode conductive layers, an upper electrode conductive layer covering the top surface of the plurality of dielectric layers and the dielectric material layer, and a conductive material layer and a dielectric material layer sequentially stacked in the upper electrode conductive layer.

[0017] The third sub-storage structure includes: a plurality of upper electrode conductive layers covering the sidewalls and top surface of each of the third sub-conductive pillars; a plurality of dielectric layers covering each of the upper electrode conductive layers; a lower electrode conductive layer covering the plurality of dielectric layers and the top surface of the dielectric material layer; and a conductive material layer located in and on the top surface of the lower electrode conductive layer.

[0018] In the first, second, and third sub-memory structures, the upper and lower electrode conductive layers are interconnected to form complete upper and lower electrode layers;

[0019] The media layers in the first, second, and third sub-storage structures are interconnected to form a complete media layer.

[0020] In the above scheme, the transistor further includes a source and a drain respectively disposed at two ends of the semiconductor body in the first direction.

[0021] In the above scheme, the semiconductor structure further includes: multiple bit lines;

[0022] Each of the bit lines is in direct contact with the bottom surface of the plurality of semiconductor bodies.

[0023] In the above scheme, the conductive pillar is formed by an epitaxial growth process; the storage structure is formed at least by a selective deposition process.

[0024] According to another aspect of this disclosure, a memory is provided, comprising: a semiconductor structure as described in any of the foregoing embodiments of this disclosure.

[0025] According to another aspect of this disclosure, a method for fabricating a semiconductor structure is provided, the method comprising:

[0026] Provides a semiconductor layer;

[0027] A plurality of transistors are formed in the semiconductor layer, each transistor including a semiconductor body extending along a first direction and a gate structure covering at least one side of the semiconductor body; the first direction is the thickness direction of the semiconductor layer;

[0028] Conductive pillars are formed on the exposed top surface of each of the semiconductor bodies;

[0029] A storage structure is formed covering the conductive pillars.

[0030] In the above scheme, each conductive pillar includes N sub-conductive pillars stacked along the first direction, where N is a positive integer greater than or equal to 1; correspondingly, the storage structure includes N sub-storage structures stacked along the first direction.

[0031] Forming the conductive pillars and the storage structure includes:

[0032] A sub-conducting pillar and a corresponding sub-memory structure are formed on the semiconductor body;

[0033] Along the first direction, (N-1) sub-conductive pillars and corresponding (N-1) sub-storage structures are formed sequentially.

[0034] In the above scheme, N=3, and the formation of the conductive pillar and the storage structure includes:

[0035] A first sub-conductive pillar is formed on the exposed top surface of each of the semiconductor bodies;

[0036] A first sub-memory structure is formed covering the first sub-conductive pillar;

[0037] A second sub-conductive post is formed on the exposed top surface of each of the first sub-conductive posts; the first sub-conductive post is in direct contact with the corresponding second sub-conductive post;

[0038] A second sub-memory structure is formed to cover the second sub-conductive pillar; the first sub-memory structure is in direct contact with the second sub-memory structure.

[0039] A third sub-conductive post is formed on the exposed top surface of each of the second sub-conductive posts; the third sub-conductive post is in direct contact with the corresponding second sub-conductive post;

[0040] A third sub-memory structure is formed that covers the third sub-conductive pillar; the third sub-memory structure is in direct contact with the second sub-memory structure.

[0041] In the above scheme, forming the first sub-memory structure covering the first sub-conductive pillar includes:

[0042] Multiple lower electrode conductive layers are formed by selective deposition process, covering the top surface and sidewalls of each of the first sub-conductive pillars;

[0043] A plurality of dielectric layers covering each of the lower electrode conductive layers are formed by a selective deposition process; a first gap is formed between two adjacent dielectric layers.

[0044] An upper electrode conductive layer is formed covering the plurality of dielectric layers and the bottom of the plurality of first gaps.

[0045] The method in the above scheme further includes:

[0046] Before forming a second sub-conductive pillar on the exposed top surface of each of the first sub-conductive pillars, a conductive material layer and a dielectric material layer are sequentially formed in a plurality of first gaps where the upper electrode conductive layer is formed;

[0047] Remove the lower electrode conductive layer, dielectric layer and upper electrode conductive layer from the top surface of the first sub-conductive post to expose the top surface of the first sub-conductive post; wherein the top surface of the dielectric material layer is substantially flush with the exposed top surface of the first sub-conductive post.

[0048] In the above scheme, the material of the conductive pillar may be the same as or different from the material of the conductive material layer.

[0049] In the above scheme, forming a second sub-memory structure covering the second sub-conductive pillar includes:

[0050] Multiple lower electrode conductive layers are formed by selective deposition process, covering the top surface and sidewalls of each of the second sub-conductive pillars;

[0051] A plurality of dielectric layers covering each of the upper electrode conductive layers are formed by a selective deposition process; a second gap is formed between two adjacent dielectric layers.

[0052] A top electrode sub-conductive layer is formed covering the bottom of the plurality of dielectric layers and the plurality of second gaps; the top electrode conductive layer of the second sub-memory structure is in direct contact with the top electrode conductive layer of the first sub-memory structure.

[0053] The method in the above scheme further includes:

[0054] Before forming a third sub-conductive pillar on the exposed top surface of each of the second sub-conductive pillars, a conductive material layer and a dielectric material layer are sequentially formed in a plurality of second gaps in which the upper electrode conductive layer is formed;

[0055] Remove the lower electrode conductive layer, dielectric layer, and upper electrode conductive layer from the top surface of the second sub-conductive pillar to expose the top surface of the second sub-conductive pillar; wherein the top surface of the dielectric material layer is substantially flush with the exposed top surface of the upper electrode conductive pillar.

[0056] In the above scheme, forming a third sub-memory structure covering the third sub-conductive pillar includes:

[0057] Multiple lower electrode conductive layers are formed by selective deposition process, covering the top surface and sidewalls of each of the third sub-conductive pillars;

[0058] A plurality of dielectric layers covering each of the lower electrode conductive layers are formed by a selective deposition process; a third gap is formed between two adjacent dielectric layers.

[0059] An upper electrode conductive layer is formed covering the bottom of the plurality of dielectric layers and the plurality of third gaps;

[0060] The method further includes:

[0061] A third conductive material layer is formed in the plurality of third gaps in which the upper electrode conductive layer is formed and on the top of the upper electrode conductive layer;

[0062] In the first, second, and third sub-memory structures, the upper and lower electrode conductive layers are interconnected to form complete upper and lower electrode layers;

[0063] The media layers in the first, second, and third sub-storage structures are interconnected to form a complete media layer.

[0064] In the above scheme, multiple transistors are formed in the semiconductor layer, including:

[0065] The semiconductor layer is etched from its surface along a first direction to form the semiconductor body of the transistor;

[0066] A gate structure of a transistor is formed on at least one side of the semiconductor body;

[0067] The source and drain of a transistor are formed at opposite ends of the semiconductor body along the first direction.

[0068] The method in the above scheme further includes:

[0069] Multiple bit lines are formed in the semiconductor layer;

[0070] Each of the bit lines is in direct contact with the bottom surface of the plurality of semiconductor bodies.

[0071] The semiconductor structure fabrication method provided in this disclosure can form multiple transistors in a semiconductor layer and form conductive pillars on each transistor that are in direct contact with the semiconductor body in the transistor. In this way, conductive pillars can be formed only at the locations that are in direct contact with the semiconductor body, reducing the difficulty of aligning the transistors and conductive pillars, increasing the process window, and improving the reliability of the semiconductor structure. At the same time, a memory structure is formed on the surface of the conductive pillars, so that the size of the memory structure can change with the size of the conductive pillars. This allows the size of the memory structure to be set according to actual needs, thereby improving the storage capacity of the semiconductor structure. Attached Figure Description

[0072] Figure 1a This is a schematic diagram of the circuit connection of a DRAM transistor provided in an embodiment of this disclosure;

[0073] Figure 1b This is a schematic diagram of the structure of a memory provided in an embodiment of this disclosure;

[0074] Figure 2a This is a schematic diagram of the buried gate structure arrangement provided in an embodiment of the present disclosure;

[0075] Figure 2b This is a schematic diagram of the ring gate structure arrangement provided in an embodiment of the present disclosure;

[0076] Figure 2c A schematic diagram of a hexagonal close-packed structure provided in an embodiment of this disclosure;

[0077] Figure 2d This is a schematic diagram of a square stacking structure provided in an embodiment of the present disclosure;

[0078] Figure 3 A schematic flowchart illustrating a method for manufacturing a semiconductor structure according to an embodiment of this disclosure;

[0079] Figures 4a to 4d A cross-sectional schematic diagram of the manufacturing process of a semiconductor structure provided in an embodiment of this disclosure;

[0080] Figures 5a to 5i A cross-sectional schematic diagram of the manufacturing process of another semiconductor structure provided in this disclosure embodiment;

[0081] Figure 6 This is a cross-sectional schematic diagram of a semiconductor structure provided in an embodiment of this disclosure.

[0082] Explanation of reference numerals in the attached figures:

[0083] 30 - Semiconductor layer; 301 - Bit line; 302 - Transistor; 3021 - Source; 3022 - Drain; 3023 - Channel region; 3024 - Gate structure; 3024a - Gate; 3024b - Gate oxide layer; 303 - Insulating layer; 304 - Conductive pillar; 305 - Gap; 306 - Storage structure; 3061 - Lower electrode conductive layer; 3062 - Dielectric layer; 3063 - Upper electrode conductive layer; 307 - Conductive material layer; 50 - Semiconductor layer; 502 - Transistor; 5041 - First sub-conductive pillar; 5042 5043 - Second sub-conductive pillar; 505 - Gap; 5061 - First sub-storage structure; 5062 - Second sub-storage structure; 5063 - Third sub-storage structure; 5061a - Lower electrode conductive layer; 5061b - Dielectric layer; 5061c - Upper electrode conductive layer; 507 - First support layer; 5071 - First conductive material layer; 5072 - First dielectric material layer; 508 - Second support layer; 5081 - Second conductive material layer; 5082 - Second dielectric material layer; 509 - Third conductive material layer.

[0084] In the above figures (which are not necessarily drawn to scale), similar reference numerals may describe similar parts in different views. Similar reference numerals with different letter suffixes may indicate different examples of similar parts. The figures illustrate, by way of example and not limitation, the various embodiments discussed herein. Detailed Implementation

[0085] To make the technical solutions and advantages of the embodiments of this disclosure clearer, the technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary implementation methods of this disclosure are shown in the accompanying drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the implementation methods set forth herein. Rather, these implementation methods are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art.

[0086] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.

[0087] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.

[0088] Furthermore, for ease of description, spatial relative terms such as “on,” “above,” “above,” “upper,” “above,” “upper,” etc., may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figures. In addition to the orientations depicted in the figures, the spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0089] In embodiments of this disclosure, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include various semiconductor materials, such as silicon, silicon germanide, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafer.

[0090] In embodiments of this disclosure, the term "layer" refers to a portion of material including a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers. For example, an interconnect layer may include one or more conductor and contact sublayers (where interconnect lines and / or via contacts are formed), and one or more dielectric sublayers.

[0091] In the embodiments of this disclosure, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0092] The semiconductor structure disclosed herein is at least a portion of the structure that will be used in subsequent processes to form the final device structure. Here, the final device may include a memory, including but not limited to dynamic random access memory (DRAM). The following description uses DRAM as an example only.

[0093] However, it should be noted that the following description of dynamic random access memory is only for illustrating this disclosure and is not intended to limit the scope of this disclosure.

[0094] With the development of dynamic random access memory technology, the size of memory cells is getting smaller and smaller, and their array architecture has increased from 8F. 2 Go to 6F 2 Then go to 4F 2Furthermore, based on the requirements for ions and leakage current in dynamic random access memory, the memory architecture has evolved from planar array transistors to recessed gate array transistors, then from recessed gate array transistors to buried channel array transistors, and finally from buried channel array transistors to vertical channel array transistors.

[0095] In some embodiments of this disclosure, whether planar transistors or buried transistors, dynamic random access memory is composed of multiple memory cell structures. Each memory cell structure is mainly composed of a transistor and a memory cell (storage capacitor) controlled by the transistor. That is, dynamic random access memory includes an architecture of 1 transistor (T) and 1 capacitor (C) (1T1C).

[0096] Figure 1a This is a schematic diagram of a control circuit using a 1T1C architecture provided in an embodiment of this disclosure. Figure 1b This is a schematic diagram of a DRAM memory array formed by transistors using a 1T1C architecture, as provided in an embodiment of this disclosure; Figure 1a , Figure 1b As shown, the drain of transistor T is electrically connected to the bit line (BL), the source region of transistor T is electrically connected to one of the electrode plates of capacitor C, and the other electrode plate of capacitor C can be connected to a reference voltage, which can be ground voltage or other voltages. The gate of transistor T is connected to the word line (WL). The transistor T is turned on or off by applying a voltage through the word line WL. The bit line BL is used to perform read or write operations on transistor T when it is turned on.

[0097] As electronic products become increasingly integrated, the size of dynamic random access memory (DRAM) is constantly shrinking, and its memory cell arrays are being arranged from buried gate (BWL) structures (see reference). Figure 2a The technology has evolved to include a smaller gate all-around (GAA) arrangement (see reference). Figure 2b Simultaneously, the capacitor size in the DRAM was also adjusted, from the densest hexagonal packing (see reference). Figure 2c It evolved into a quadrilateral stack (see reference) Figure 2d ); among them, the radius of the capacitor also becomes smaller, and it reverts from a cup-shaped structure to a columnar structure.

[0098] To increase the size of capacitors, i.e., to increase the surface area between the capacitor electrodes and the dielectric layer, and thus improve the storage capacity of the memory, one approach is to increase the capacitor height. However, increasing the capacitor height results in a higher aspect ratio, which increases the manufacturing difficulty and limits the capacitor height. Another approach is to stack multiple capacitors. However, aligning multiple capacitors is quite difficult during the stacking process.

[0099] In view of this, in order to solve one or more of the above problems, this disclosure provides a method for fabricating a semiconductor structure to increase the capacitor height while reducing the process difficulty and increasing the storage capacity of the memory. Figure 3 This is a schematic flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this disclosure. Figure 3 As shown, the method for fabricating a semiconductor structure provided in this embodiment includes the following steps:

[0100] S100: Provides a semiconductor layer;

[0101] S200: A plurality of transistors are formed in the semiconductor layer, each transistor including a semiconductor body extending along a first direction and a gate structure covering at least one side of the semiconductor body; the first direction is the thickness direction of the semiconductor layer;

[0102] S300: Conductive pillars are formed on the exposed top surface of each of the semiconductor bodies;

[0103] S400: Form a storage structure covering the conductive pillars.

[0104] It should be understood that Figure 3 The steps shown are not exclusive; other steps may be performed before, after, or between any of the steps shown. Figure 3 The steps shown can be adjusted in order according to actual needs. Figures 4a to 4d This is a cross-sectional schematic diagram illustrating the fabrication process of a semiconductor structure according to an embodiment of this disclosure. The following is in conjunction with... Figure 3 , Figures 4a to 4d The method for fabricating the semiconductor structure provided in the embodiments of this disclosure will be described in detail.

[0105] In step S100, refer to Figure 4a Provides a semiconductor layer 30.

[0106] The semiconductor layer may be made of silicon (Si), germanium (Ge), silicon germanide (SiGe), etc.; in some specific embodiments, the semiconductor layer may also be silicon-on-insulator (SOI) or germanium-on-insulator (GOI).

[0107] In some embodiments, the method further includes: providing a substrate; forming a semiconductor layer on the substrate.

[0108] Here, the substrate may include various semiconductor materials, such as silicon, silicon germanide, germanium, gallium arsenide, indium phosphide, etc. In some specific examples, the substrate material includes silicon, and the semiconductor layer includes silicon germanide.

[0109] In some embodiments, the semiconductor layer can be formed by processes such as physical vapor deposition (PVD), chemical vapor deposition (CVD), and atomic layer deposition (ALD).

[0110] In some embodiments, reference Figure 4a The method further includes forming a plurality of bit lines 301 in the semiconductor layer before forming a plurality of transistors.

[0111] Here, bit line 301 is used to perform read or write operations on transistor 302 when transistor 302 is turned on.

[0112] The material of bit line 301 includes, but is not limited to, tungsten.

[0113] The bit line 301 can be formed by processes such as PVD, CVD or ALD.

[0114] In step S200, a plurality of transistors 302 are formed in the semiconductor layer 30.

[0115] Here, transistor 302 is in direct contact with bit line 301.

[0116] In some embodiments, the transistor type includes one of the following:

[0117] Columnar gate transistor;

[0118] Semi-surround gate transistor;

[0119] All-around gate transistor.

[0120] Among them, in a pillar-type gate transistor, the gate is formed in a pillar shape on one side of the channel region; in a semi-surround gate transistor, the gate partially surrounds the channel region; and in a fully surrounding gate transistor, the gate fully surrounds the channel region.

[0121] The transistor types in the embodiments of this disclosure may include, but are not limited to, the types described above. For clarity and conciseness, the following embodiments use a fully all-around gate transistor as an example. However, it should be noted that the descriptions of transistor types in the following embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0122] In some embodiments, a plurality of transistors 302 are formed in the semiconductor layer 30, including:

[0123] The semiconductor layer 30 is etched from its surface along a first direction to form the semiconductor body of the transistor. Figure 4a (Not marked in the text).

[0124] Here, the source (S, Source) 3021 and drain (D, Drain) 3022 of the transistor are formed at opposite ends of the semiconductor body along the first direction, respectively. The region between the source and drain in the semiconductor body is the channel region 3023.

[0125] The first direction is the direction in which the semiconductor body extends, and it is also perpendicular to the semiconductor layer 30. In some specific examples, the first direction may be... Figure 4a The Z-axis direction is shown in the figure.

[0126] In some embodiments, the source and drain are the two ends of the channel region disposed opposite each other in the Z-axis direction, and the positions of the source and drain can be interchanged. In this embodiment, the drain is described as being located at the bottom of the semiconductor body and connected to the bit line; in other words, in this embodiment, the bit line 301 is in direct contact with the bottom surface (i.e., drain 3022) of the semiconductor body among the plurality of transistors 302. The top surface (i.e., source 3021) of the semiconductor body is exposed.

[0127] In some embodiments, the source 3021 and drain 3022 can be formed by doping or diffusion processes, or by other suitable methods.

[0128] For example, doping is achieved through an ion implantation process to form source 3021 and drain 3022.

[0129] For example, a drain 3022 can be formed first at one end close to bit line 301, and then a source 3021 can be formed at the other end away from bit line 301.

[0130] In this embodiment of the disclosure, the method further includes forming a gate structure 3024 of a surround transistor on the side of the semiconductor body.

[0131] It should be noted that the gate structure 3024 here includes a gate (G) 3024a and a gate oxide layer 3024b; wherein, the gate oxide layer 3024b is located between the gate 3024a and the channel region 3023, and is used to electrically isolate the channel region 3023 and the gate 3024a, thereby reducing the hot carrier effect of the transistor.

[0132] Here, the material of the gate 3024a may include metal or polysilicon, etc. The material of the gate oxide layer 3024b may include, but is not limited to, silicon oxide.

[0133] In some embodiments, the method for forming the gate 3024a includes, but is not limited to, PVD, CVD, or ALD. The method for forming the gate oxide layer 3024b includes, but is not limited to, in-situ oxidation.

[0134] It should be noted that the position of the gate 3024a varies depending on the type of transistor; in other words, the gate 3024a can be located on one side of the channel region 3023; it can be located on opposite sides of the channel region 3023; or it can be located around the channel region 3023. The specific position depends on the type of transistor; in a fully all-around gate transistor, the gate 3024a is located around the channel region 3023.

[0135] In this embodiment of the disclosure, the method further includes forming an insulating layer 303 in the gaps between a plurality of transistors 302 in the semiconductor layer.

[0136] The insulating layer 303 can be used to electrically isolate multiple transistors 302; it can also be used to provide support.

[0137] Here, the material of the insulating layer 303 includes, but is not limited to, silicon nitride (SiN).

[0138] Methods for forming the insulating layer include, but are not limited to, PVD, CVD, or ALD processes.

[0139] In step S300, refer to Figure 4b Conductive pillars 304 are formed on the exposed top surface of each of the semiconductor bodies.

[0140] In some embodiments, the material of the conductive post 304 may be other conductive materials that can grow unidirectionally along the first direction.

[0141] For example, the material of the conductive pillar 304 includes silicon germanide.

[0142] In some embodiments, the conductive pillar 304 can be formed by an epitaxial growth process.

[0143] Here, epitaxial growth refers to growing a material layer with certain requirements on the exposed top surface of the semiconductor substrate, which has the same crystal orientation as the semiconductor substrate.

[0144] It is understood that in the embodiments of this disclosure, during the process of forming multiple conductive pillars through epitaxial growth, self-alignment between the conductive pillars and the source electrode can be achieved; that is, the problem of difficulty in aligning the conductive pillars 304 with the top surface (i.e., the source electrode) of the semiconductor body is reduced or avoided.

[0145] In this embodiment of the disclosure, reference is made to Figure 4b There is a gap of 305 between the multiple conductive pillars arranged along the second direction.

[0146] Here, the second direction is perpendicular to the first direction and also perpendicular to the surface of the semiconductor layer. For example, the second direction could be... Figure 4b The X-axis direction is shown in the figure.

[0147] It should be noted that, in some embodiments, the plurality of transistors 302 formed in the semiconductor layer 30 can be arranged in an array along the second direction and the third direction (here, the third direction is perpendicular to both the first direction and the second direction). In this case, correspondingly, the plurality of conductive pillars 304 are arranged in an array along the second direction and the third direction.

[0148] In step S400, refer to Figure 4c A storage structure 306 covering the conductive pillar is formed in the gap 305.

[0149] Here, the storage structure 306 is used to store data. For example, the storage structure 306 includes a capacitor.

[0150] In some embodiments, forming the storage structure 306 includes:

[0151] A selective deposition process is used to form a lower electrode conductive layer 3061 covering the conductive pillar;

[0152] A dielectric layer 3062 is formed covering the surface of the lower electrode conductive layer by a selective deposition process;

[0153] An upper electrode conductive layer 3063 is formed covering the top surface of the dielectric layer 3062 and the insulating layer 303.

[0154] Here, the lower electrode conductive layer 3061 is used as the lower electrode of the capacitor; the dielectric layer 3062 is used as the dielectric of the capacitor; and the upper electrode conductive layer 3063 is used as the upper electrode of the capacitor.

[0155] Here, selective deposition process refers to selectively depositing the lower electrode conductive layer on the surface of the conductive pillar; and selectively depositing the dielectric layer on the surface of the lower electrode conductive layer.

[0156] In some embodiments, the material of the conductive pillar 304 may be the same as or different from the material of the lower electrode conductive layer 3061 or the upper electrode conductive layer 3063. In some specific embodiments, the materials of both the lower electrode conductive layer 3061 and the upper electrode conductive layer 3063 may include, but are not limited to, titanium nitride (TiN).

[0157] The dielectric layer 3062 is made of a high-k dielectric material, which generally refers to a material with a dielectric constant higher than 3.9, and is typically significantly higher than that value. In some specific examples, the material of the dielectric layer 3062 may include, but is not limited to, hafnium oxide (HfO2).

[0158] It should be noted that, in the embodiments of this disclosure, during the selective deposition process to form the lower electrode conductive layer 3061, the material used to form the lower electrode conductive layer 3061 can be grown only on the surface of the conductive pillar 304, or formed on other selected materials, and not formed on the top surface of the insulating layer 303. (Refer to...) Figure 4c Similarly, during the selective deposition process to form the dielectric layer 3062, the material used to form the dielectric layer 3062 can be formed only on the surface of the lower electrode conductive layer 3061, and not on the top surface of the insulating layer 303. (Refer to...) Figure 4c This avoids forming the lower electrode conductive layer 3061 and dielectric layer 3062 in gaps with high aspect ratios, reducing process difficulty and increasing the process window. On the other hand, it also avoids the void problem that occurs when forming the lower electrode conductive layer, dielectric layer and upper electrode conductive layer using other processes, thereby improving the reliability of the semiconductor structure.

[0159] In addition, the present invention employs an epitaxial growth process to form the conductive pillar 304 and a selective deposition process to form the memory structure 306, which can avoid the problem of multiple overlapping photolithography that occurs during the process of forming etching holes (for forming memory structures) in the semiconductor layer using photomask technology.

[0160] It should be noted that the dielectric layer 3062 and the upper electrode conductive layer 3063 located on the top surface of the insulating layer 303 are connected as a whole. In this way, the surface area of ​​the upper electrode conductive layer 3063 can be increased, thereby improving the storage capacity of the storage structure.

[0161] In some embodiments, the method for forming the upper electrode conductive layer 3063 includes, but is not limited to, processes such as PVD, CVD, or ALD. It is understood that the upper electrode conductive layer 3063 does not necessarily require a selective deposition process.

[0162] In some embodiments, reference Figure 4d The upper electrode conductive layer 3063 can directly fill the gap between two adjacent dielectric layers 3062.

[0163] In some embodiments, after the upper electrode conductive layer 3063 is formed, a conductive material layer 307 is filled in the gaps between the upper electrode conductive layer 3063. In some specific examples, the material of the conductive material layer 307 may include, but is not limited to, silicon germanide.

[0164] It is understandable that directly filling the gaps between two adjacent dielectric layers 3062 through a deposition process to form the upper electrode conductive layer 3063 may be difficult and prone to voids. However, forming a conductive material layer 307 in the gaps above the upper electrode conductive layer 3063 can reduce the process difficulty and form a higher quality upper electrode conductive layer 3063. Here, the conductive material layer 307 also serves to improve the stability of the semiconductor structure.

[0165] In the embodiments disclosed above, conductive pillars can be formed only at locations directly in contact with the semiconductor substrate using epitaxial growth processes, reducing the difficulty of aligning transistors with conductive pillars, increasing the process window, and improving the reliability of the semiconductor structure. At the same time, selective deposition processes can be used to form memory structures in gaps with a large aspect ratio, increasing the process window, reducing process difficulty, and improving the reliability of the semiconductor structure.

[0166] It is understood that the height of the conductive pillars determines the size and storage capacity of the memory structure; based on this, in some embodiments of this disclosure, in order to increase the storage capacity of the memory structure by increasing the height of the conductive pillars, another semiconductor structure and its fabrication method are proposed.

[0167] In other embodiments, each of the conductive pillars includes N sub-conductive pillars stacked along the first direction, where N is a positive integer greater than or equal to 1; correspondingly, the storage structure includes N sub-storage structures stacked along the first direction.

[0168] Forming the conductive pillars and the storage structure includes:

[0169] A sub-conducting pillar and a corresponding sub-memory structure are formed on the semiconductor body;

[0170] Along the first direction, (N-1) sub-conductive pillars and corresponding (N-1) sub-storage structures are formed sequentially.

[0171] Here, by forming multiple sub-conductive pillars and stacking them together to form a conductive pillar, the total height of the conductive pillars is increased, thereby increasing the surface area of ​​the storage structure and improving the storage capacity of the memory.

[0172] In other words, multiple sub-conductive pillars are stacked on top of the semiconductor layer (i.e., the side of the source electrode furthest from the channel region) through an epitaxial growth process, and multiple sub-memory structures are covered on the surface of the corresponding sub-conductive pillars.

[0173] Each sub-conducting pillar corresponds one-to-one with a sub-storage structure.

[0174] It should be noted that in the embodiments of this disclosure, N stacked sub-conductive pillars can be formed above the semiconductor layer; and in order to reduce the difficulty of forming the sub-memory structure, a corresponding sub-memory structure is formed after each sub-conductive pillar is formed.

[0175] Correspondingly, N sub-conductive pillars stacked along the Z-axis correspond to N sub-storage structures stacked along the Z-axis.

[0176] It should be noted that the top sub-memory structure (the Nth sub-memory structure) is different from the non-top sub-memory structures (the first to the Nth sub-memory structures). Specifically, the non-top sub-memory structures only cover the sidewalls of the corresponding sub-conductive pillars, while the top sub-memory structures cover both the top and sidewalls of the corresponding sub-conductive pillars.

[0177] In some embodiments, after forming the first to the Nth sub-conductive pillars and their corresponding sub-storage structures, a partial sub-storage structure is formed on the top of the Nth sub-conductive pillar so that the sub-storage structure located on the top of the Nth sub-conductive pillar is connected to the storage structure on the sidewall to form a complete Nth sub-storage structure.

[0178] In other embodiments, the first to N-1 sub-conductive pillars and their corresponding first to N-1 sub-memory structures are first formed; then the Nth sub-conductive pillar is formed; and then a sub-memory structure covering the top and sidewalls of the Nth sub-conductive pillar is formed simultaneously.

[0179] Understandably, forming a sub-storage structure that simultaneously covers the sidewalls and top of the Nth sub-conductive pillar can save on process steps and reduce manufacturing costs.

[0180] For example, forming conductive pillars and storage structures includes sequentially forming (N-1) sub-conductive pillars and corresponding (N-1) sub-storage structures stacked along the Z-axis direction; wherein, after each sub-conductive pillar is formed, a corresponding sub-storage structure is formed.

[0181] Next, the Nth sub-conductive pillar is formed on the (N-1)th sub-conductive pillar; and the Nth sub-storage structure is formed covering the top and sidewalls of the Nth sub-conductive pillar.

[0182] Here, during the formation of the Nth sub-memory structure, the timing of forming the sub-memory structure located on top of the Nth sub-conductive pillar can be selected according to actual needs.

[0183] To better understand the intent of this disclosure, the following detailed explanation will be based on the example of each conductive pillar comprising three sub-conductive pillars and each storage structure comprising three sub-storage structures.

[0184] That is, N=3, the conductive pillar includes a first sub-conductive pillar, a second sub-conductive pillar located on the first sub-conductive pillar, and a third sub-conductive pillar located on the second sub-conductive pillar.

[0185] Accordingly, the storage structure includes a first sub-storage structure covering the first sub-conductive post, a second sub-storage structure covering the second sub-conductive post, and a third sub-storage structure covering the third sub-conductive post.

[0186] In some embodiments, forming the conductive pillars and the storage structure includes:

[0187] A first sub-conductive pillar is formed on the exposed top surface of each of the semiconductor bodies;

[0188] A first sub-memory structure is formed covering the first sub-conductive pillar;

[0189] A second sub-conductive post is formed on the exposed top surface of each of the first sub-conductive posts; the first sub-conductive post is in direct contact with the corresponding second sub-conductive post;

[0190] A second sub-memory structure is formed to cover the second sub-conductive pillar; the first sub-memory structure is in direct contact with the second sub-memory structure.

[0191] A third sub-conductive post is formed on the exposed top surface of each of the second sub-conductive posts; the third sub-conductive post is in direct contact with the corresponding second sub-conductive post;

[0192] A third sub-memory structure is formed that covers the third sub-conductive pillar; the third sub-memory structure is in direct contact with the second sub-memory structure.

[0193] Here, for reference Figure 5a A semiconductor layer 50 is provided, which is the same as the semiconductor layer 30 in the foregoing embodiments;

[0194] The semiconductor layer 50 includes a plurality of transistors 502; one end of the transistor 502 (i.e. the exposed end face of the semiconductor body) is substantially flush with the top surface of the semiconductor layer 50; as previously mentioned, it will not be repeated here.

[0195] In this embodiment of the disclosure, a first sub-conductive pillar 5041 is formed on the exposed top surface of each of the semiconductor bodies by epitaxial growth.

[0196] Here, there is a gap 505 between multiple first sub-conducting pillars.

[0197] Next, refer to Figure 5b A first sub-storage structure 5061 is formed in the gap 505, covering the first sub-conductive post 5041. The first sub-storage structure 5061 includes a lower electrode conductive layer 5061a, a dielectric layer 5061b, and an upper electrode conductive layer 5061c.

[0198] Specifically, in some embodiments, forming the first sub-memory structure covering the first sub-conductive pillar includes:

[0199] Multiple lower electrode conductive layers 5061a are formed by selective deposition process, covering the top surface and sidewalls of each of the first sub-conductive pillars 5041.

[0200] A plurality of dielectric layers 5061b are formed by selective deposition process, covering each of the lower electrode conductive layers 5061a; a first gap is formed between two adjacent dielectric layers 5061b. Figure 5b (Not shown in the text);

[0201] An upper electrode conductive layer 5061c is formed covering the plurality of dielectric layers 5061b and the bottom of the plurality of first gaps.

[0202] Here, by selective deposition process, the lower electrode conductive layer 5061a can be formed only on the top surface and sidewall of the first sub-conductive pillar 5041, and not at the bottom of the first gap.

[0203] Similarly, a dielectric layer 5061b can be formed only on the sidewall of the lower electrode conductive layer 5061a using a selective deposition process.

[0204] In this way, the lower electrode conductive layer 5061a and dielectric layer 5061b can be formed in the gap 505 with a depth-to-width ratio, increasing the process window, reducing the process difficulty, and improving the reliability of the device.

[0205] It is understood that the upper electrode conductive layer 5061c does not need to be formed using a selective deposition process. Exemplary methods for forming the upper electrode conductive layer 5061c include, but are not limited to, PVD, CVD, or ALD processes.

[0206] Here, the dielectric layer 5061b covering the dielectric layer and the upper electrode conductive layer 5061c located on the top surface of the insulating layer are connected as a whole, which can increase the storage capacity of the sub-storage structure.

[0207] Next, the method further includes:

[0208] A first support layer 507 is formed in a plurality of first gaps in which an upper electrode conductive layer is formed.

[0209] Here, the first support layer 507 includes a first conductive material layer 5071 and a first dielectric material layer 5072 located above the first conductive material layer 5071.

[0210] refer to Figure 5c A first conductive material layer 5071 is formed in multiple first gaps between the first sub-memory structures 5061 and on the top surface of the upper electrode conductive layer 5061c through processes such as PVD or CVD.

[0211] In some embodiments, the materials of the first conductive material layer 5071 and the conductive pillar 504 may be the same or different; the choice can be made according to actual needs. For example, the constituent materials of the first conductive material layer 5071 include, but are not limited to, silicon germanide.

[0212] refer to Figure 5d The first conductive material layer 5071 is etched to remove the first conductive material layer 5071 located on the top surface of the upper electrode conductive layer 5061c, as well as a portion of the first conductive material layer 5071 located in the first gap.

[0213] Here, the top surface of the remaining first conductive material layer 5071 in the first gap is lower than the top surface of the upper electrode conductive layer 5061c.

[0214] refer to Figure 5e A first dielectric material layer 5072 is formed on the top surface of the upper electrode conductive layer 5061c and the top surface of the first conductive material layer 5071.

[0215] In some specific examples, the material of the first dielectric material layer 5072 includes, but is not limited to, silicon nitride (SiN).

[0216] Methods for forming the first dielectric material layer 5072 include, but are not limited to, PVD, CVD, or ALD processes.

[0217] It should be noted that the first dielectric material layer here is silicon nitride, which ensures that in subsequent processes, when the second sub-conductive pillar 5042 is formed by epitaxial growth, the second sub-conductive pillar 5042 is not formed on the first dielectric material layer (silicon nitride), and when the lower electrode conductive layer and dielectric layer in the second sub-memory structure are formed by selective deposition, the lower electrode conductive layer and dielectric layer of the second sub-memory structure are not formed on the first dielectric material layer (silicon nitride).

[0218] refer to Figure 5f The method further includes:

[0219] Remove the lower electrode conductive layer 5061a, dielectric layer 5061b, upper electrode conductive layer 5061c, and first dielectric material layer 5072 from the top surface of the first sub-conductive post 5041 to expose the top surface of the first sub-conductive post 5041; at this time, the top surface of the remaining first dielectric material layer 5072 in the first gap is basically flush with the exposed top surface of the first sub-conductive post 5041.

[0220] In some embodiments, the removal process includes, but is not limited to, chemical mechanical polishing (CMP).

[0221] Next, refer to Figure 5g A second sub-conductive post 5042 is formed on the exposed top surface of each of the first sub-conductive posts 5041.

[0222] Here, the second sub-conductive post 5042 is made of the same material and is formed in the same way as the first sub-conductive post 5041, as previously mentioned, and will not be repeated here.

[0223] Next, refer to Figure 5h This forms a second sub-storage structure 5062 covering the second sub-conductive pillar 5042. The second sub-storage structure 5062 includes a lower electrode conductive layer 5061a, a dielectric layer 5061b, and an upper electrode conductive layer 5061c.

[0224] Here, the materials of the lower electrode conductive layer 5061a and the upper electrode conductive layer 5061c can be including, but not limited to, titanium nitride.

[0225] Specifically, in some embodiments, forming the second sub-memory structure 5062 covering the second sub-conductive pillar 5042 includes:

[0226] A plurality of lower electrode conductive layers 5061a are formed by selective deposition process, covering the top surface and sidewalls of each of the second sub-conductive pillars 5042; the lower electrode conductive layer 5061a of the second sub-memory structure 5062 is in direct contact with the lower electrode conductive layer 5061a of the first sub-memory structure 5061.

[0227] A plurality of dielectric layers 5061b are formed by selective deposition process to cover the upper electrode conductive layer of each second sub-conductive pillar 5042; wherein the dielectric layer 5061b of the second sub-memory structure 5062 is in direct contact with the dielectric layer 5061b of the first sub-memory structure 5061; and a second gap is formed between two adjacent dielectric layers.

[0228] An upper electrode conductive layer 5061c is formed, covering the bottom of multiple dielectric layers and multiple second gaps; the upper electrode conductive layer 5061c of the second sub-memory structure 5062 is in direct contact with the upper electrode conductive layer 5061c of the first sub-memory structure 5061. It should be noted that, through selective deposition, a lower electrode conductive layer 5061a is formed only on the top surface and sidewalls of the second sub-conductive pillar 5042; and a dielectric layer 5061b is formed only on the sidewalls of the lower electrode conductive layer 5061a. This allows sub-memory structures to be formed within gaps with a high aspect ratio; increases the process window, reduces process difficulty, and improves the reliability of the semiconductor structure.

[0229] Next, after forming the second sub-memory structure 5062, in order to increase the stability of the semiconductor structure and improve the reliability of the memory device, a second support layer 508 is formed in the multiple second gaps where the upper electrode conductive layer is formed.

[0230] Here, the second support layer 508 includes a second conductive material layer 5081 and a second dielectric material layer 5082 located above the second conductive material layer 5081.

[0231] In actual operation, a second conductive material layer 5081 can be formed first, and then a second dielectric material layer 5082 can be formed on top of the second conductive material layer 5081.

[0232] It should be noted that the second support layer 508 is the same as the first support layer 507; the second conductive material layer 5081 is the same as the first conductive material layer 5071; the second dielectric material layer 5082 is the same as the first dielectric material layer 5072; their materials and formation methods have been described previously and will not be repeated here.

[0233] In some embodiments, the method further includes:

[0234] Remove the lower electrode conductive layer 5061a, dielectric layer 5061b and upper electrode conductive layer 5061c from the top surface of the second sub-conductive pillar 5042 to expose the top surface of the second sub-conductive pillar 5042; wherein the top surface of the second dielectric material layer 5082 is substantially flush with the exposed top surface of the upper electrode conductive layer 5061c.

[0235] Next, refer to Figure 5h A third sub-conductive post 5043 is formed on the exposed top surface of each of the second sub-conductive posts 5042.

[0236] Here, the third sub-conductive post 5043 is made of the same material and is formed in the same way as the first sub-conductive post 5041 and the second sub-conductive post 5042, as previously mentioned, and will not be repeated here.

[0237] Next, refer to Figure 5i This forms a third sub-storage structure 5063 covering the third sub-conductive pillar 5043. The third sub-storage structure 5063 includes a lower electrode conductive layer 5061a, a dielectric layer 5061b, and an upper electrode conductive layer 5061c.

[0238] In some embodiments, a third sub-memory structure 5063 is formed covering the third sub-conductive post 5043, including:

[0239] A plurality of lower electrode conductive layers 5061a are formed by selective deposition process, covering the top surface and sidewalls of each of the third sub-conductive pillars 5043; the lower electrode conductive layer 5061a of the third sub-memory structure 5063 is in direct contact with the lower electrode conductive layer 5061a of the second sub-memory structure 5062.

[0240] Multiple dielectric layers are formed by selective deposition processes, covering the lower electrode conductive layer of each of the third sub-conductive pillars 5043; the dielectric layer 5061b of the third sub-memory structure 5063 is in direct contact with the dielectric layer 5061b of the second sub-memory structure 5062; wherein a third gap is formed between the dielectric layers 5061b of two adjacent third sub-memory structures 5063 along the X-axis direction. Figure 5f (Not marked in the text);

[0241] A dielectric layer 5061b covering multiple third sub-memory structures 5063 and an upper electrode conductive layer 5061c at the bottom of multiple third gaps are formed; wherein, the lower electrode conductive layer 5061a of the third sub-memory structure 5063 located on the sidewall of the third sub-conductive pillar 5043 is in direct contact with the lower electrode conductive layer 5061a of the second sub-memory structure 5062.

[0242] In some embodiments of this disclosure, the method further includes:

[0243] A third conductive material layer 509 is formed in the plurality of third gaps in which the upper electrode conductive layer is formed and on top of the upper electrode conductive layer.

[0244] Here, filling the third gap with a third conductive material layer 509 reduces the process difficulty compared to filling the third gap with other materials; in addition, the third conductive material layer 509 can also be used to fix multiple third sub-memory structures, thereby enhancing the reliability of the semiconductor structure.

[0245] In this embodiment of the disclosure, the upper and lower electrode conductive layers in the first sub-memory structure, the second sub-memory structure, and the third sub-memory structure are interconnected to form complete upper and lower electrode layers;

[0246] The media layers in the first sub-storage structure, the second sub-storage structure, and the third sub-storage structure are interconnected to form a complete media layer.

[0247] In some embodiments, reference Figure 6 In order to increase the height of the memory structure and increase the memory capacity of the semiconductor structure, a fourth sub-conductive pillar, a fifth sub-conductive pillar, etc. can be formed on the third sub-conductive pillar in the semiconductor structure; correspondingly, a fourth sub-memory structure covering the fourth sub-conductive pillar and a fifth sub-memory structure covering the fifth sub-conductive pillar are formed, etc.

[0248] In the embodiments disclosed above, conductive pillars can be formed only at locations directly in contact with the semiconductor substrate using epitaxial growth processes. This reduces the difficulty of aligning transistors with conductive pillars, increases the process window, and improves the reliability of the semiconductor structure. Simultaneously, selective deposition processes allow memory structures to be formed within gaps with a large aspect ratio, further increasing the process window and reducing process complexity. Furthermore, in other embodiments, by sequentially forming multiple directly contacting sub-conductive pillars and corresponding sub-memory structures, the size of the memory structure within the semiconductor structure can increase with the size of the conductive pillars. This allows the size of the memory structure to be set according to actual needs, thereby increasing the storage capacity of the memory structure.

[0249] This disclosure also provides a semiconductor structure, the semiconductor structure comprising:

[0250] Multiple transistors are located in a semiconductor layer; each transistor includes a semiconductor body extending along a first direction and a gate structure covering at least one side of the semiconductor body; the first direction is the thickness direction of the semiconductor layer;

[0251] Multiple conductive pillars; each conductive pillar is located on the top surface of a corresponding semiconductor body and is in direct contact with the corresponding semiconductor body;

[0252] The storage structure covers the plurality of conductive pillars.

[0253] In some embodiments, each of the conductive pillars includes N sub-conductive pillars stacked along the first direction, where N is a positive integer greater than or equal to 1; correspondingly, the storage structure includes N sub-storage structures stacked along the first direction.

[0254] In some embodiments, where N = 3, the semiconductor structure includes:

[0255] A first sub-conductive pillar located on the top surface of each of the semiconductor bodies; a first sub-memory structure covering the sidewalls of the first sub-conductive pillar;

[0256] A second sub-conductive pillar located on the top surface of each of the first sub-conductive pillars; a second sub-storage structure covering the sidewalls of the second sub-conductive pillars;

[0257] A third sub-conductive pillar located on the top surface of each of the second sub-conductive pillars; a third sub-storage structure covering the top surface and sidewalls of the third sub-conductive pillars;

[0258] The first sub-conductive pillar, the second sub-conductive pillar, and the third sub-conductive pillar are in direct contact with each other, as are the first sub-storage structure, the second sub-storage structure, and the third sub-storage structure.

[0259] In some embodiments, the first sub-memory structure includes: a plurality of lower electrode conductive layers covering the sidewall of each first sub-conductive pillar, a plurality of dielectric layers covering each of the lower electrode conductive layers, an upper electrode conductive layer covering the top surface of the plurality of dielectric layers and the semiconductor layer between two adjacent dielectric layers, and a conductive material layer and a dielectric material layer sequentially stacked in the upper electrode conductive layer.

[0260] The second sub-storage structure includes: a plurality of lower electrode conductive layers covering the sidewalls of each of the second sub-conductive pillars, a plurality of dielectric layers covering each of the lower electrode conductive layers, an upper electrode conductive layer covering the top surface of the plurality of dielectric layers and the dielectric material layer, and a conductive material layer and a dielectric material layer sequentially stacked in the upper electrode conductive layer.

[0261] The third sub-storage structure includes: a plurality of upper electrode conductive layers covering the sidewalls and top surface of each of the third sub-conductive pillars; a plurality of dielectric layers covering each of the upper electrode conductive layers; a lower electrode conductive layer covering the plurality of dielectric layers and the top surface of the dielectric material layer; and a conductive material layer located in and on the top surface of the lower electrode conductive layer.

[0262] In the first, second, and third sub-memory structures, the upper and lower electrode conductive layers are interconnected to form complete upper and lower electrode layers;

[0263] The media layers in the first, second, and third sub-storage structures are interconnected to form a complete media layer.

[0264] In some embodiments, the transistor further includes a source and a drain disposed at two ends of the semiconductor body in the first direction.

[0265] In some embodiments, the semiconductor structure further includes: multiple bit lines;

[0266] Each of the bit lines is in direct contact with the bottom surface of the plurality of semiconductor bodies.

[0267] In some embodiments, the conductive pillars are formed by an epitaxial growth process; the storage structure is formed at least by a selective deposition process.

[0268] This disclosure also provides a memory comprising a semiconductor structure as described in any of the foregoing embodiments.

[0269] The scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, Includes: Multiple transistors are located in a semiconductor layer; each transistor includes a semiconductor body extending along a first direction and a gate structure covering at least one side of the semiconductor body; the first direction is the thickness direction of the semiconductor layer; Multiple conductive pillars; Each conductive pillar is located on the top surface of a corresponding semiconductor body and is in direct contact with the corresponding semiconductor body. Each conductive pillar includes three sub-conductive pillars stacked along the first direction, including: a first sub-conductive pillar located on the top surface of each semiconductor body, a second sub-conductive pillar located on the top surface of each first sub-conductive pillar, and a third sub-conductive pillar located on the top surface of each second sub-conductive pillar. A storage structure covers the plurality of conductive pillars; correspondingly, the storage structure includes three sub-storage structures stacked along the first direction, including: a first sub-storage structure covering the sidewall of the first sub-conductive pillar, a second sub-storage structure covering the sidewall of the second sub-conductive pillar, and a third sub-storage structure covering the top surface and sidewall of the third sub-conductive pillar; The first sub-conductive pillar, the second sub-conductive pillar, and the third sub-conductive pillar are in direct contact with each other, as are the first sub-storage structure, the second sub-storage structure, and the third sub-storage structure.

2. The semiconductor structure according to claim 1, characterized in that, The first sub-memory structure includes: a plurality of lower electrode conductive layers covering the sidewall of each first sub-conductive pillar, a plurality of dielectric layers covering each lower electrode conductive layer, an upper electrode conductive layer covering the top surface of the plurality of dielectric layers and the semiconductor layer between two adjacent dielectric layers, and a conductive material layer and a dielectric material layer sequentially stacked in the upper electrode conductive layer. The second sub-storage structure includes: a plurality of lower electrode conductive layers covering the sidewalls of each of the second sub-conductive pillars, a plurality of dielectric layers covering each of the lower electrode conductive layers, an upper electrode conductive layer covering the top surface of the plurality of dielectric layers and the dielectric material layer, and a conductive material layer and a dielectric material layer sequentially stacked in the upper electrode conductive layer. The third sub-storage structure includes: a plurality of upper electrode conductive layers covering the sidewalls and top surface of each of the third sub-conductive pillars; a plurality of dielectric layers covering each of the upper electrode conductive layers; a lower electrode conductive layer covering the plurality of dielectric layers and the top surface of the dielectric material layer; and a conductive material layer located in and on the top surface of the lower electrode conductive layer. In the first, second, and third sub-memory structures, the upper and lower electrode conductive layers are interconnected to form complete upper and lower electrode layers; The media layers in the first, second, and third sub-storage structures are interconnected to form a complete media layer.

3. The semiconductor structure according to claim 1, characterized in that, The transistor further includes a source and a drain respectively disposed at two ends of the semiconductor body in the first direction.

4. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure also includes: multiple bit lines; Each of the bit lines is in direct contact with the bottom surface of the plurality of semiconductor bodies.

5. The semiconductor structure according to claim 1, characterized in that, The conductive pillars are formed by an epitaxial growth process; the storage structure is formed at least by a selective deposition process.

6. A memory, characterized in that, include: The semiconductor structure as described in any one of claims 1 to 5.

7. A method for fabricating a semiconductor structure, characterized in that, The method includes: Provides a semiconductor layer; A plurality of transistors are formed in the semiconductor layer, each transistor including a semiconductor body extending along a first direction and a gate structure covering at least one side of the semiconductor body; the first direction is the thickness direction of the semiconductor layer; A conductive pillar is formed on the exposed top surface of each of the semiconductor bodies, and each conductive pillar includes three sub-conductive pillars stacked along the first direction; A storage structure is formed covering the conductive pillars, and correspondingly, the storage structure includes three sub-storage structures stacked along the first direction; The formation of the conductive pillars and the memory structure includes: forming a first sub-conductive pillar on the exposed top surface of each of the semiconductor bodies; forming a first sub-memory structure covering the first sub-conductive pillars; forming a second sub-conductive pillar on the exposed top surface of each of the first sub-conductive pillars; the first sub-conductive pillars being in direct contact with the corresponding second sub-conductive pillars; forming a second sub-memory structure covering the second sub-conductive pillars; the first sub-memory structure being in direct contact with the second sub-memory structure; forming a third sub-conductive pillar on the exposed top surface of each of the second sub-conductive pillars; the third sub-conductive pillar being in direct contact with the corresponding second sub-conductive pillar; forming a third sub-memory structure covering the third sub-conductive pillar; the third sub-memory structure being in direct contact with the second sub-memory structure.

8. The method for fabricating a semiconductor structure according to claim 7, characterized in that, The formation of the first sub-memory structure covering the first sub-conductive pillar includes: Multiple lower electrode conductive layers are formed by selective deposition process, covering the top surface and sidewalls of each of the first sub-conductive pillars; A plurality of dielectric layers covering each of the lower electrode conductive layers are formed by a selective deposition process; a first gap is formed between two adjacent dielectric layers. An upper electrode conductive layer is formed covering the plurality of dielectric layers and the bottom of the plurality of first gaps.

9. The method for fabricating a semiconductor structure according to claim 8, characterized in that, The method further includes: Before forming a second sub-conductive pillar on the exposed top surface of each of the first sub-conductive pillars, a conductive material layer and a dielectric material layer are sequentially formed in a plurality of first gaps where the upper electrode conductive layer is formed; Remove the lower electrode conductive layer, dielectric layer and upper electrode conductive layer from the top surface of the first sub-conductive post to expose the top surface of the first sub-conductive post; wherein the top surface of the dielectric material layer is substantially flush with the exposed top surface of the first sub-conductive post.

10. The method for fabricating a semiconductor structure according to claim 9, characterized in that, The material of the conductive pillar may be the same as or different from the material of the conductive material layer.

11. The method for fabricating a semiconductor structure according to claim 9, characterized in that, Forming a second sub-memory structure covering the second sub-conductive pillar includes: Multiple lower electrode conductive layers are formed by selective deposition process, covering the top surface and sidewalls of each of the second sub-conductive pillars; A plurality of dielectric layers covering each of the upper electrode conductive layers are formed by a selective deposition process; a second gap is formed between two adjacent dielectric layers. A top electrode sub-conductive layer is formed covering the bottom of the plurality of dielectric layers and the plurality of second gaps; the top electrode conductive layer of the second sub-memory structure is in direct contact with the top electrode conductive layer of the first sub-memory structure.

12. The method for fabricating a semiconductor structure according to claim 11, characterized in that, The method further includes: Before forming a third sub-conductive pillar on the exposed top surface of each of the second sub-conductive pillars, a conductive material layer and a dielectric material layer are sequentially formed in a plurality of second gaps in which the upper electrode conductive layer is formed; Remove the lower electrode conductive layer, dielectric layer, and upper electrode conductive layer from the top surface of the second sub-conductive pillar to expose the top surface of the second sub-conductive pillar; wherein the top surface of the dielectric material layer is substantially flush with the exposed top surface of the upper electrode conductive pillar.

13. The method for fabricating a semiconductor structure according to claim 11, characterized in that, Forming a third sub-memory structure covering the third sub-conductive pillar includes: Multiple lower electrode conductive layers are formed by selective deposition process, covering the top surface and sidewalls of each of the third sub-conductive pillars; A plurality of dielectric layers covering each of the lower electrode conductive layers are formed by a selective deposition process; a third gap is formed between two adjacent dielectric layers. An upper electrode conductive layer is formed covering the bottom of the plurality of dielectric layers and the plurality of third gaps; The method further includes: A third conductive material layer is formed in the plurality of third gaps in which the upper electrode conductive layer is formed and on the top of the upper electrode conductive layer; In the first, second, and third sub-memory structures, the upper and lower electrode conductive layers are interconnected to form complete upper and lower electrode layers; The media layers in the first, second, and third sub-storage structures are interconnected to form a complete media layer.

14. The method for fabricating a semiconductor structure according to claim 7, characterized in that, Multiple transistors are formed in the semiconductor layer, including: The semiconductor layer is etched from its surface along a first direction to form the semiconductor body of the transistor; A gate structure of a transistor is formed on at least one side of the semiconductor body; The source and drain of a transistor are formed at opposite ends of the semiconductor body along the first direction.

15. The method for fabricating a semiconductor structure according to claim 7, characterized in that, The method further includes: Multiple bit lines are formed in the semiconductor layer; Each of the bit lines is in direct contact with the bottom surface of the plurality of semiconductor bodies.

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