Semiconductor structure and method of manufacturing the same

Abstract

The embodiment of the present disclosure relates to the technical field of semiconductor, and provides a semiconductor structure and a manufacturing method thereof, the semiconductor structure comprising: a substrate and an initial bit line on the surface of the substrate, the initial bit line extending along a first direction; a semiconductor column, the semiconductor column being located on the side of the initial bit line away from the substrate, and along the direction perpendicular to the surface of the initial bit line, the semiconductor column comprising a first region, a channel region and a second region arranged in sequence, the first region being in contact with the initial bit line, and along the direction perpendicular to the first direction, the width of the initial bit line being greater than the width of the first region, and the material forming the first region being the same as the material forming the initial bit line; and a word line structure, the word line structure surrounding the channel region, and the word line structure extending along a second direction, the second direction intersecting the first direction. The embodiment of the present disclosure is at least beneficial to improving the electrical performance of the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and its manufacturing method. Background Technology

[0002] As the integration density of dynamic memory continues to increase, while researching the arrangement of transistors in dynamic memory array structures and how to reduce the size of individual functional devices in dynamic memory array structures, it is also necessary to improve the electrical performance of small-sized functional devices.

[0003] When using a vertical gate-all-around (GAA) transistor structure as a dynamic memory select transistor (access transistor), its area can reach 4F. 2 (F: Minimum pattern size achievable under given process conditions) In principle, higher density efficiency can be achieved. However, due to the small size of the transistor structure itself, the electrical connection performance when the transistor structure is electrically connected to other electrical devices is affected by the size of the transistor structure, thus affecting the electrical performance of the semiconductor structure. Summary of the Invention

[0004] This disclosure provides a semiconductor structure and a method for manufacturing the same, which at least helps to improve the electrical performance of the semiconductor structure.

[0005] According to some embodiments of this disclosure, one aspect of this disclosure provides a semiconductor structure, including: a substrate and an initial bit line located on the surface of the substrate, the initial bit line extending along a first direction; a semiconductor pillar located on the side of the initial bit line away from the substrate, along a direction perpendicular to the surface of the initial bit line, the semiconductor pillar including a first region, a channel region, and a second region arranged sequentially, the first region contacting the initial bit line, and along a direction perpendicular to the first direction, the width of the initial bit line being greater than the width of the first region, the material forming the first region being the same as the material forming the initial bit line; and a word line structure surrounding the channel region, the word line structure extending along a second direction, the second direction intersecting the first direction.

[0006] In some embodiments, the ratio of the height of the initial bit line to the height of the first region is 1 / 3 to 2 / 3 along a direction perpendicular to the surface of the initial bit line.

[0007] In some embodiments, the semiconductor structure further includes: a first metal-semiconductor compound layer, the first metal compound layer being located on the side of the initial bit line away from the substrate, the first metal compound layer and the initial bit line together constituting a bit line.

[0008] In some embodiments, the semiconductor structure further includes: a first metal layer located on the side of the first metal-semiconductor compound layer away from the initial bit line, wherein the first metal layer, the first metal-semiconductor compound layer, and the initial bit line together constitute the bit line.

[0009] In some embodiments, the semiconductor structure further includes a second metal-semiconductor compound layer located on the side of the second region away from the channel region.

[0010] In some embodiments, the semiconductor structure further includes: an isolation structure located between the word line structure and the initial bit line, and the isolation structure also located between the word line structure and the semiconductor pillar; and a capacitor structure located on the side of the second region away from the channel region.

[0011] In some embodiments, the semiconductor structure further includes a capacitor contact structure located between the capacitor structure and the second region.

[0012] According to some embodiments of this disclosure, another aspect of this disclosure provides a method for manufacturing a semiconductor structure, comprising: providing a substrate; forming an initial bit line and a semiconductor pillar on the surface of the substrate, the initial bit line extending along a first direction, the semiconductor pillar located on the side of the initial bit line away from the substrate, along a direction perpendicular to the surface of the initial bit line, the semiconductor pillar comprising a first region, a channel region, and a second region arranged sequentially, the first region contacting the initial bit line, and along a direction perpendicular to the first direction, the width of the initial bit line being greater than the width of the first region, the material forming the first region being the same as the material forming the initial bit line; forming a word line structure, the word line structure surrounding the channel region, and the word line structure extending along a second direction, the second direction intersecting the first direction.

[0013] In some embodiments, the step of forming the initial bit line and the semiconductor pillar on the substrate surface includes: forming an initial semiconductor layer on the substrate, the initial semiconductor layer including a stacked initial first region, an initial channel region, and an initial second region; patterning the initial semiconductor layer to form a semiconductor layer and the semiconductor pillar located on the semiconductor layer, wherein the semiconductor layer covers the substrate surface, wherein the remaining initial second region after patterning serves as the second region, the remaining initial channel region after patterning serves as the channel region, and the remaining initial first region after patterning serves as the first region and the semiconductor layer; and patterning the semiconductor layer to form the initial bit line.

[0014] In some embodiments, the ratio of the height of the initial bit line to the height of the first region is 1 / 3 to 2 / 3 along a direction perpendicular to the substrate surface.

[0015] In some embodiments, after patterning the semiconductor layer and before forming the word line structure, the method further includes: forming a second metal layer on the side of the initial bit line exposed away from the substrate, and using the second metal layer to perform a first metallization process on the initial bit line to form a first metal semiconductor compound layer, the first metal semiconductor compound layer being located on the side of the remaining initial bit line away from the substrate, the first metal semiconductor compound layer and the remaining initial bit line together constituting a bit line.

[0016] In some embodiments, after forming the first metal-semiconductor compound layer and before forming the word line structure, the method further includes forming a first metal layer located on the side of the first metal-semiconductor compound layer away from the remaining initial bit lines.

[0017] In some embodiments, the manufacturing method further includes: performing a second metallization process on the side of the second region away from the channel region to form a second metal semiconductor compound layer, the second metal semiconductor compound layer being located on the side of the second region away from the channel region.

[0018] In some embodiments, the manufacturing method further includes forming a capacitive contact structure on the side of the second region away from the channel region.

[0019] The technical solutions provided in this disclosure have at least the following advantages:

[0020] On the one hand, along the direction perpendicular to the first direction, the width of the initial bit line is greater than the width of the first region. This ensures that all areas on the bottom surface of the first region are in contact with the initial bit line, thus guaranteeing a larger contact area between the initial bit line and the first region. This improves the conductivity between the first region and the initial bit line, thereby enhancing the electrical performance of the semiconductor structure. On the other hand, the material forming the first region is the same as the material forming the initial bit line, meaning the first region and the initial bit line are an integral structure. This helps to mitigate interface state defects between the first region and the initial bit line, further improving the conductivity and thus enhancing the electrical performance of the semiconductor structure. Furthermore, forming a vertical GAA transistor on the substrate, with the bit line located below the semiconductor pillar, allows for a 3D stacked semiconductor structure, which is beneficial for increasing the integration density of the semiconductor structure. Attached Figure Description

[0021] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings represent similar elements. Unless otherwise stated, the figures in the drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a partial top view of a semiconductor structure provided in an embodiment of the present disclosure;

[0023] Figures 2 to 4 for Figure 1 Schematic diagrams of three cross-sectional structures of the semiconductor structure along the AA1 and BB1 directions;

[0024] Figures 5 to 13 This is a cross-sectional structural diagram corresponding to each step of a method for manufacturing a semiconductor structure according to another embodiment of this disclosure. Detailed Implementation

[0025] As can be seen from the background technology, the electrical performance of semiconductor structures needs to be improved.

[0026] This disclosure provides a semiconductor structure and its manufacturing method. In the semiconductor structure, on the one hand, along a direction perpendicular to a first direction, the width of the initial bit line is greater than the width of the first region. This is beneficial in ensuring that all areas of the bottom surface of the first region are in contact with the initial bit line, thereby ensuring a large contact area between the initial bit line and the first region, improving the conductivity between the first region and the initial bit line, and thus enhancing the electrical performance of the semiconductor structure. On the other hand, the material forming the first region is the same as the material forming the initial bit line, i.e., the first region and the initial bit line are an integral structure. This is beneficial in improving interface state defects between the first region and the initial bit line, thereby improving the conductivity between the first region and the initial bit line, and further enhancing the electrical performance of the semiconductor structure. Furthermore, by forming a vertical GAA transistor on the substrate, and with the bit line located below the semiconductor pillar, a 3D stacked semiconductor structure can be formed, which is beneficial in increasing the integration density of the semiconductor structure.

[0027] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the embodiments. However, the technical solutions claimed in the embodiments of this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0028] This disclosure provides a semiconductor structure according to an embodiment. The semiconductor structure provided by this disclosure will be described in detail below with reference to the accompanying drawings. Figure 1 This is a partial top view of a semiconductor structure provided in an embodiment of the present disclosure; Figures 2 to 4 for Figure 1 Schematic diagrams of three cross-sectional structures of the semiconductor structure along the AA1 and BB1 directions.

[0029] refer to Figures 1 to 4 The semiconductor structure includes: a substrate 100 and an initial bit line 101 located on the surface of the substrate 100, the initial bit line 101 extending along a first direction X; a semiconductor pillar 102 located on the side of the initial bit line 101 away from the substrate 100, the semiconductor pillar 102 including a first region I, a channel region II and a second region III arranged sequentially along a direction perpendicular to the surface of the initial bit line 101, the first region I contacting the initial bit line 101, and the width of the initial bit line 101 being greater than the width of the first region I along a direction perpendicular to the first direction X, the material forming the first region I being the same as the material forming the initial bit line 101; and a word line structure 103 surrounding the channel region II, the word line structure 103 extending along a second direction Y, the second direction Y intersecting the first direction X.

[0030] The semiconductor pillar 102 extends along a direction perpendicular to the surface of the initial bit line 101, and along a direction perpendicular to the first direction X, the width of the initial bit line 101 is greater than the width of the first region I. Thus, all areas of the bottom surface of the first region I are in contact with the initial bit line 101, which helps to ensure a large contact area between the initial bit line 101 and the first region I, reduce the contact resistance between the initial bit line 101 and the first region I, improve the conductivity between the first region I and the initial bit line 101, and enhance the electrical performance of the semiconductor structure.

[0031] Moreover, the material forming the first region I is the same as the material forming the initial bit line 101, that is, the first region I and the initial bit line 101 are an integral structure, which is beneficial to improve the interface state defects between the first region I and the initial bit line 101, thereby improving the conductivity between the first region I and the initial bit line 101, so as to improve the electrical performance of the semiconductor structure.

[0032] It should be noted that the first direction X and the second direction Y can be orthogonal. The following explanation will use the orthogonality of the first direction X and the second direction Y as an example. In practical applications, it is only necessary to ensure that the angle between the first direction X and the second direction Y is not zero. Furthermore, Figure 1The example only shows 4 initial bit lines 101, 3 word line structures 103, 3 spaced semiconductor pillars 102 on one initial bit line 101, and 4 spaced semiconductor pillars 102 on one word line structure 103. In practical applications, there are no restrictions on the number of initial bit lines 101, the number of word line structures 103, the number of spaced semiconductor pillars 102 on one initial bit line, or the number of spaced semiconductor pillars 102 on one word line structure 103.

[0033] The following will combine Figures 1 to 4 A more detailed explanation of the semiconductor structure is provided.

[0034] In some embodiments, the material of the substrate 100 can be an elemental semiconductor material or a crystalline inorganic compound semiconductor material. The elemental semiconductor material can be silicon or germanium; the crystalline inorganic compound semiconductor material can be silicon carbide, silicon germanide, gallium arsenide, or indium gallium, etc.

[0035] It should be noted that the specific structure of the semiconductor pillar 102 includes at least the following two embodiments.

[0036] In some embodiments, the semiconductor pillar 102 is a stacked structure, which includes a first region I, a channel region II, and a second region III, that is, the first region I, the channel region II, and the second region III are layered structures, and the first region I, the channel region II, and the second region III all contain the same semiconductor element, wherein the first region I and the initial bit line 101 are an integral structure; in other embodiments, the semiconductor pillar 102 is a monolithic structure, that is, the first region I, the channel region II, and the second region III are an integral structure.

[0037] The semiconductor element may include at least one of silicon, carbon, germanium, arsenic, gallium, and indium. The following description will exemplify that both the initial bit line 101 and the semiconductor pillar 102 include silicon.

[0038] Furthermore, in the two embodiments described above, channel region II may be doped with a first type of ion, and first region I and second region III may be doped with a second type of ion. The second type of ion is different from the first type of ion, and both the first type of ion and the second type of ion are either N-type ions or P-type ions. Alternatively, channel region II, first region I and second region III may be doped with the same type of ion, either N-type ions or P-type ions, but the doping concentration of the ion in channel region II is higher than the doping concentration in first region I and second region III.

[0039] In some embodiments, along a direction perpendicular to the surface of the initial bit line 101, the ratio of the height of the initial bit line 101 to the height of the first region I is 1 / 3 to 2 / 3. If the ratio of the height of the initial bit line 101 to the height of the first region I is less than 1 / 3, it is not conducive to ensuring good conductivity of the initial bit line 101 itself; if the ratio of the height of the initial bit line 101 to the height of the first region I is greater than 2 / 3, it is not conducive to ensuring good conductivity of the first region I itself. Both the conductivity of the initial bit line 101 and the conductivity of the first region I will affect the conductivity between the first region I and the initial bit line 101. Therefore, setting the ratio of the height of the initial bit line 101 to the height of the first region I within the range of 1 / 3 to 2 / 3 is beneficial to ensuring that both the initial bit line 101 and the first region I have good conductivity, thereby helping to ensure good conductivity between the semiconductor pillar 102 and the bit line 121.

[0040] It should be noted that the variation in the cross-sectional area of ​​the semiconductor pillar 102 mentioned above includes at least the following two embodiments.

[0041] In some embodiments, along the direction perpendicular to the surface of the initial bit line 101, the cross-sectional area of ​​the semiconductor pillar 102 gradually decreases as the height of the semiconductor pillar 102 decreases, that is, the cross-sectional area of ​​the first region I is smaller than the cross-sectional area of ​​the channel region II, and the cross-sectional area of ​​the channel region II is smaller than the cross-sectional area of ​​the second region III; in other embodiments, along the direction perpendicular to the surface of the initial bit line 101, the semiconductor pillar 102 is dumbbell-shaped, that is, the cross-sectional area of ​​the channel region II is smaller than the cross-sectional area of ​​the first region I, and the cross-sectional area of ​​the channel region II is smaller than the cross-sectional area of ​​the second region III.

[0042] Both of the above embodiments are advantageous in forming a channel region II with a smaller cross-sectional area, which is beneficial to improving the control capability of the word line structure 103 surrounding the sidewall of the channel region II over the channel region II, thereby making it easier to control the conduction or turn-off of the GAA transistor.

[0043] In some embodiments, continue to refer to Figure 1 and Figure 2 The semiconductor structure may further include: a first metal semiconductor compound layer 111, the first metal semiconductor compound layer 111 being located on the side of the initial bit line 101 away from the substrate 100, and the first metal semiconductor compound layer 111 and the initial bit line 101 together forming bit line 121.

[0044] The first metal-semiconductor compound layer 111 has a relatively lower resistivity compared to the unmetallized semiconductor material, i.e., the initial bit line 101. Therefore, the bit line 121 containing the first metal-semiconductor compound layer 111 has a lower resistivity compared to the initial bit line 101, which helps to reduce the resistance of the bit line 121 itself and reduce the contact resistance between the bit line 121 and the first region I, thereby further improving the electrical performance of the semiconductor structure.

[0045] Furthermore, the resistivity of bit line 121 can be less than that of substrate 100.

[0046] In some embodiments, reference Figure 3 The semiconductor structure may further include: a first metal layer 131, which is located on the side of the first metal semiconductor compound layer 111 away from the initial bit line 101, and the first metal layer 131, the first metal semiconductor compound layer 111 and the initial bit line 101 together constitute bit line 121.

[0047] The first metal layer 131 has a relatively lower resistivity compared to the unmetallized semiconductor material, i.e., the initial bit line 101, and the first metal layer 131 also has a relatively lower resistivity compared to the first metal semiconductor compound layer 111. Therefore, compared to the initial bit line 101, the bit line 121, which includes the first metal semiconductor compound layer 111 and the first metal layer 131, has a lower resistivity, which helps to reduce the resistance of the bit line 121 itself and reduce the contact resistance between the bit line 121 and the first region I, further improving the electrical performance of the semiconductor structure.

[0048] The first metal layer 131 and the first metal semiconductor compound layer 111 may have the same metal element, which may be at least one of cobalt, nickel, molybdenum, titanium, tungsten, tantalum or platinum.

[0049] In some embodiments, reference Figure 2 and Figure 3 Along the direction away from the sidewall of the semiconductor pillar 102, the word line structure 103 includes a first diffusion barrier layer 113 and a first conductive layer 123 arranged sequentially. Thus, the first diffusion barrier layer 113 can be used to block the diffusion of conductive elements in the first conductive layer 123 into the channel region II, avoiding affecting the conductivity of the first conductive layer 123 itself and the conduction and shutdown performance of the channel region II. The material of the first diffusion barrier layer 113 can be titanium nitride, and the material of the first conductive layer 123 can be at least one of polycrystalline silicon, titanium nitride, tantalum nitride, copper, or tungsten.

[0050] In some embodiments, the thickness of the first diffusion barrier layer 113 can be 3 nm to 5 nm along the direction perpendicular to the sidewall of the channel region II.

[0051] In some embodiments, in conjunction with reference Figures 2 to 4 The semiconductor structure may further include: an isolation structure 104, located between the word line structure 103 and the initial bit line 101, and also located between the word line structure 103 and the semiconductor pillar 102; and a capacitor structure 105, located on the side of the second region III away from the channel region II. It should be noted that the isolation structure 104 may include: a first isolation layer 114, located between the word line structure 103 and the semiconductor pillar 102, i.e., the first isolation layer 114 surrounds the sidewall of the first region I and the sidewall of the channel region II, used to isolate the word line structure 103 from the first region I and the channel region II, so that the word line structure 103 can control the conduction and shutdown of the channel region II; and a second isolation layer 124, located between the word line structure 103 and the initial bit line 101. It should be noted that, referring to... Figure 2 In addition to the initial bit line 101, bit line 121 also includes a first metal-semiconductor compound layer 111. The second isolation layer 124 is specifically located between the first metal-semiconductor compound layer 111 and the initial bit line 101. (Refer to...) Figure 3 In addition to the initial bit line 101, the bit line 121 also includes a first metal semiconductor compound layer 111 and a first metal layer 131. The second isolation layer 124 is specifically located between the first metal layer 131 and the initial bit line 101. The second isolation layer 124 is used to achieve insulation between the word line structure 103 and the bit line 121. The third isolation layer 134 is located between adjacent second regions III arranged along the first direction X, and is also located between adjacent word line structures 103. It is used to achieve insulation between adjacent second regions III and insulation between adjacent word line structures 103.

[0052] The first isolation layer 114 can be made of silicon oxide, the second isolation layer 124 can be made of silicon nitride, and the third isolation layer 134 can be made of silicon oxide.

[0053] In some embodiments, reference Figure 4 The semiconductor structure may further include: a second metal semiconductor compound layer 106, wherein the second metal semiconductor compound layer 106 is located on the side of the second region III away from the channel region II.

[0054] It should be noted that the second metal-semiconductor compound layer 106 is also located between the capacitor structure 105 and the second region III. Furthermore, the second metal-semiconductor compound layer 106 has a relatively lower resistivity compared to the unmetallized semiconductor material, i.e., the second region III. Therefore, the second metal-semiconductor compound layer 106 has a lower resistivity than the second region III. The second metal-semiconductor compound layer 106 can serve as a connection region between the capacitor structure 105 and the second region III, which helps to reduce the contact resistance between the capacitor structure 105 and the second region III, thereby improving the accuracy and efficiency of electrical signal transmission between the capacitor structure 105 and the second region III, and thus further improving the electrical performance of the semiconductor structure.

[0055] In some embodiments, the semiconductor structure may further include a capacitor contact structure 107, which is located between the capacitor structure 105 and the second region III.

[0056] It should be noted that the capacitor contact structure 107 is also located between the capacitor structure 105 and the second region III. The capacitor contact structure 107 can also serve as a connection area between the capacitor structure 105 and the second region III, which helps to reduce the contact resistance between the capacitor structure 105 and the second region III, thereby improving the accuracy and efficiency of electrical signal transmission between the capacitor structure 105 and the second region III, and thus further improving the electrical performance of the semiconductor structure.

[0057] It should be noted that, in some embodiments, the semiconductor structure may only include the second metal-semiconductor compound layer 106, and the second metal-semiconductor compound layer 106 is located between the capacitor structure 105 and the second region III; in other embodiments, the semiconductor structure may only include the capacitor contact structure 107, and the capacitor contact structure 107 is located between the capacitor structure 105 and the second region III; in still other embodiments, the semiconductor structure may include the second metal-semiconductor compound layer 106 and the capacitor contact structure 107, the second metal-semiconductor compound layer 106 being contacted and connected to the side of the second region III away from the channel region II, and the capacitor contact structure 107 being contacted and connected to the side of the second metal-semiconductor compound layer 106 away from the second region III.

[0058] The materials of the first metal semiconductor compound layer 111 and the second metal semiconductor compound layer 106 may each include at least one of cobalt silicide, nickel silicide, molybdenum silicide, titanium silicide, tungsten silicide, tantalum silicide, or platinum silicide.

[0059] In some embodiments, the capacitor contact structure 107 may include a second diffusion barrier layer (not shown) and a second conductive layer (not shown). The second diffusion barrier layer is located near the second region III, and the second conductive layer is located near the capacitor structure 105. The second diffusion barrier layer can be used to block the diffusion of conductive elements in the second conductive layer into the second region III, thereby avoiding affecting the conductivity of the second conductive layer itself and the conductivity of the second region III. The material of the second diffusion barrier layer may be titanium nitride, and the material of the second conductive layer may be at least one of polycrystalline silicon, titanium nitride, tantalum nitride, copper, or tungsten.

[0060] It should be noted that the third isolation layer 134 may also be located between adjacent second metal semiconductor compound layers 106 and between adjacent capacitive contact structures 107, so as to achieve insulation between adjacent second metal semiconductor compound layers 106 and insulation between adjacent capacitive contact structures 107.

[0061] In some embodiments, the capacitor structure 105 may include a lower electrode 115, a dielectric layer 125, and an upper electrode 135. The lower electrode 115 is a columnar structure and extends in the same direction as the semiconductor pillar 102. The bottom of the lower electrode 115 contacts the capacitor contact structure 107. The dielectric layer 125 is located on the outer surface of the lower electrode 115, and the upper electrode 135 is located on the outer surface of the dielectric layer 125.

[0062] In some embodiments, continue to refer to Figures 2 to 4 The substrate 100 includes a plurality of mutually discrete initial bit lines 101; the semiconductor structure may further include a shallow trench isolation structure 108, which is located between adjacent initial bit lines 101 and within the substrate 100. The top end of the shallow trench isolation structure 108 is flush with the top end of the initial bit lines 101, and a second isolation layer 124 is located between the word line structure 103 and the shallow trench isolation structure 108. The material of the shallow trench isolation structure 108 may be at least one of silicon oxide, silicon nitride, and a silicon oxide-silicon nitride composition.

[0063] In summary, all areas on the bottom surface of the first region I are in contact with the initial bit line 101, which helps to ensure a large contact area between the initial bit line 101 and the first region I, thereby improving the conductivity between the first region I and the initial bit line 101 and improving the electrical performance of the semiconductor structure. Furthermore, the materials forming the first region I and the initial bit line 101 are the same, meaning the first region I and the initial bit line 101 are a single structure. This helps to improve interface state defects between the first region I and the initial bit line 101, thus improving the conductivity between the first region I and the initial bit line 101 and improving the electrical performance of the semiconductor structure.

[0064] Another embodiment of this disclosure also provides a method for manufacturing a semiconductor structure, used to prepare the semiconductor structure provided in the foregoing embodiments.

[0065] Figures 5 to 13 This is a cross-sectional structural diagram showing the steps of a semiconductor structure manufacturing method according to another embodiment of the present disclosure. The following will describe in detail the manufacturing method of the semiconductor structure according to another embodiment of the present disclosure, with reference to the accompanying drawings. The parts that are the same as or corresponding to those in the above embodiment will not be described in detail below.

[0066] refer to Figures 4 to 13 A method for manufacturing a semiconductor structure includes: providing a substrate 100; forming an initial bit line 101 and a semiconductor pillar 102 on the surface of the substrate 100, wherein the initial bit line 101 extends along a first direction X, and the semiconductor pillar 102 is located on the side of the initial bit line 101 away from the substrate 100. Along a direction perpendicular to the surface of the initial bit line 101, the semiconductor pillar 102 includes a first region I, a channel region II, and a second region III arranged sequentially, wherein the first region I is in contact with the initial bit line 101, and along a direction perpendicular to the first direction X, the width of the initial bit line 101 is greater than the width of the first region I, and the material forming the first region I is the same as the material forming the initial bit line 101; forming a word line structure 103, the word line structure 103 surrounding the channel region II, and the word line structure 103 extending along a second direction Y, the second direction Y intersecting the first direction X.

[0067] In some embodiments, the step of forming an initial bit line 101 and a semiconductor pillar 102 on the surface of a substrate 100 may include: forming an initial semiconductor layer 112 on the substrate 100, the initial semiconductor layer 112 including a stacked initial first region 122, an initial channel region 132 and an initial second region 142; patterning the initial semiconductor layer 112 to form a semiconductor layer 152 and semiconductor pillars 102 located on the semiconductor layer 152, and the semiconductor layer 152 covering the surface of the substrate 100, wherein the remaining initial second region 142 after patterning is designated as second region III, the remaining initial channel region 132 after patterning is designated as channel region II, the remaining initial first region 122 after patterning is designated as first region I and semiconductor layer 152; and patterning the semiconductor layer 152 to form the initial bit line 101.

[0068] In some embodiments, the step of forming an initial semiconductor layer 112 on the substrate 100 may include: forming an initial first region 122, an initial channel region 132 and an initial second region 142 sequentially on the substrate 100 along a direction perpendicular to the second direction Y, that is, the initial first region 122, the initial channel region 132 and the initial second region 142 are a layered structure.

[0069] The initial semiconductor layer 112 forming the layered structure includes at least the following two embodiments:

[0070] In some embodiments, forming an initial first region 122 may include the following steps: forming a first semiconductor layer (not shown) on the surface of a substrate 100, and implanting a first type of ions into the first semiconductor layer to form the initial first region 122; forming an initial channel region 132 may include the following steps: forming a second semiconductor layer (not shown) on the side of the initial first region 122 away from the substrate 100, and implanting a second type of ions into the second semiconductor layer to form the initial channel region 132; forming an initial second region 142 may include the following steps: forming a third semiconductor layer (not shown) on the side of the initial channel region 132 away from the initial first region 122, and implanting a first type of ions into the third semiconductor layer to form the initial second region 142. The second type of ions is different from the first type of ions, and both the first type of ions and the second type of ions are either N-type ions or P-type ions.

[0071] In other embodiments, forming the initial first region 122 may include the following steps: forming a first semiconductor layer (not shown) on the surface of the substrate 100, and implanting a first type of ions into the first semiconductor layer to form the initial first region 122; forming the initial channel region 132 may include the following steps: forming a second semiconductor layer (not shown) on the side of the initial first region 122 away from the substrate 100, and implanting a first type of ions into the second semiconductor layer to form the initial channel region 132; forming the initial second region 142 may include the following steps: forming a third semiconductor layer (not shown) on the side of the initial channel region 132 away from the initial first region 122, and implanting a first type of ions into the third semiconductor layer to form the initial second region 142. The first type of ions are either N-type ions or P-type ions, and the doping concentration of the first type of ions in the initial channel region 132 is higher than the doping concentration in the initial first region 122 and the initial second region 142.

[0072] In some embodiments, the step of forming an initial semiconductor layer 112 on the substrate 100 may include: forming a basic semiconductor layer (not shown in the figure) on the surface of the substrate 100, and sequentially performing different ion implantation processes on different regions of the basic semiconductor layer to form an initial first region 122, an initial channel region 132, and an initial second region 142, i.e., the initial first region 122, the initial channel region 132, and the initial second region 142 are an integral structure. The initial channel region 132 may be doped with a first type of ion, and the initial first region 122 and the initial second region 142 may be doped with a second type of ion, which is different from the first type of ion, and both the first type of ion and the second type of ion are either N-type or P-type ions; or, the initial channel region 132, the initial first region 122, and the initial second region 142 may be doped with the same type of ion, either N-type or P-type, but the doping concentration of this ion in the initial channel region 132 is higher than the doping concentration in the initial first region 122 and the initial second region 142.

[0073] In some embodiments, patterning an initial semiconductor layer 112 to form a semiconductor layer 152 and semiconductor pillars 102 located on the semiconductor layer 152 may include the following steps:

[0074] Continue to refer to Figure 5 An initial mask layer 109 is formed on the side of the initial second region 142 away from the initial channel region 132; Reference Figure 6 The initial mask layer 109 is patterned to form a mask layer 119, and the initial semiconductor layer 112 is etched using the mask layer 119 as a mask to form a semiconductor layer 152 and semiconductor pillars 102 located on the semiconductor layer 152. The sidewalls of adjacent semiconductor pillars 102 form an opening 129, and the bottom surface of the opening 129 is the semiconductor layer 152.

[0075] Both the initial mask layer 109 and the initial semiconductor layer 112 can be etched using a dry etching process. In one example, the height of the semiconductor pillar 102 can be 200 nm along a direction perpendicular to the surface of the substrate 100.

[0076] In some embodiments, the step of patterning the semiconductor layer 152 to form the initial bit line 101 may include: referencing Figure 7 The portion of the semiconductor layer 152 exposed by the opening 129 and the substrate 100 located below the portion of the semiconductor layer 152 are etched to form a first trench 139, which extends along a first direction X; Reference Figure 8 A shallow trench isolation structure 108 is formed in the first trench 139 to enhance the isolation effect between adjacent initial position lines 101.

[0077] It should be noted that the reference is... Figure 7Along the second direction Y, the width of the opening 129 is greater than the width of the first groove 139. Thus, along the second direction Y, it is beneficial to form an initial bit line 101 with a width greater than the width of the first region I.

[0078] In some embodiments, the ratio of the height of the initial bit line 101 to the height of the first region I along a direction perpendicular to the surface of the substrate 100 is 1 / 3 to 2 / 3. This helps to ensure that both the initial bit line 101 and the first region I have good conductivity, thereby ensuring good conductivity between the first region I and the initial bit line 101.

[0079] Continue to refer to Figure 8 An initial first isolation layer 144 is formed on the sidewalls of the semiconductor pillar 102 exposed by the opening 129 and the sidewalls of the mask layer 119. In one example, the thickness of the initial first isolation layer 144 along the direction perpendicular to the sidewalls of the semiconductor pillar 102 is [missing information].

[0080] In some embodiments, reference Figure 9 In the patterned semiconductor layer 152 (reference) Figure 6 Following this, before forming the word line structure 103, the semiconductor structure manufacturing method may further include: forming a second metal layer (not shown in the figure) on the side of the initial bit line 101 exposed away from the substrate 100; performing a first metallization treatment on the initial bit line 101 using the second metal layer to form a first metal semiconductor compound layer 111; the first metal semiconductor compound layer 111 is located on the side of the remaining initial bit line 101 away from the substrate 100; the first metal semiconductor compound layer 111 and the remaining initial bit line 101 together constitute bit line 121. Compared to the initial bit line 101, the bit line 121 containing the first metal semiconductor compound layer 111 has a lower resistivity, which helps to reduce the resistance of the bit line 121 itself and reduce the contact resistance between the bit line 121 and the first region I, further improving the electrical performance of the semiconductor structure.

[0081] It should be noted that after the initial bit line 101 is subjected to a first metallization process using the second metal layer to form the first metal semiconductor compound layer 111, the remaining unreacted second metal layer will be removed.

[0082] The semiconductor structure manufacturing method may further include, after forming the first metal-semiconductor compound layer 111 and before forming the word line structure 103, forming a first metal layer 131 located on the side of the first metal-semiconductor compound layer 111 away from the remaining initial bit line 101. Compared to the initial bit line 101, the bit line 121 containing the first metal-semiconductor compound layer 111 and the first metal layer 131 has a lower resistivity, which helps to reduce the resistance of the bit line 121 itself and reduce the contact resistance between the bit line 121 and the first region I, further improving the electrical performance of the semiconductor structure.

[0083] refer to Figure 11 At opening 129 (reference) Figure 9 The exposed first metal semiconductor compound layer 111 and the top surface of the shallow trench isolation structure 108 form a second isolation layer 124. In one example, the top surface of the second isolation layer 124 is flush with the top surface of the first region I.

[0084] In some embodiments, forming the word line structure 103 may include the following steps:

[0085] refer to Figure 12 In the remaining opening 129 (reference) Figure 9 An initial first diffusion barrier layer 133 is formed on the exposed sidewall of the first isolation layer 114, and the initial first diffusion barrier layer 133 surrounds the first groove to form an initial first conductive layer 143 that fills the first groove.

[0086] Reference Figure 12 and Figure 13 The initial first conductive layer 143 is patterned to form a second trench 149, and the second trench 149 extends along the second direction Y. Subsequently, the initial first diffusion barrier layer 133 and the remaining initial first conductive layer 143 are etched back so that the top height of the initial first conductive layer 143 is flush with the bottom height of the second region III, and the remaining initial first conductive layer 143 forms a word line structure 103.

[0087] In some embodiments, in conjunction with reference Figure 13 and Figure 4The method for manufacturing a semiconductor structure, after removing the mask layer 119, may further include: performing a second metallization process on the side of the second region III away from the channel region II to form a second metal-semiconductor compound layer 106, wherein the second metal-semiconductor compound layer 106 is located on the side of the second region III away from the channel region II. Compared to the second region III, the second metal-semiconductor compound layer 106 has a lower resistivity. The second metal-semiconductor compound layer 106 can serve as a connection region between the subsequently formed capacitor structure 105 and the second region III, which helps to reduce the contact resistance between the capacitor structure 105 and the second region III, thereby improving the accuracy and efficiency of electrical signal transmission between the capacitor structure 105 and the second region III, and thus further improving the electrical performance of the semiconductor structure.

[0088] Among them, continue to refer to Figure 4 The method for manufacturing the semiconductor structure may further include forming a capacitor contact structure 107 on the side of the second region III away from the channel region II. The capacitor contact structure 107 can serve as a connection region between the capacitor structure 105 and the second region III, which helps to reduce the contact resistance between the capacitor structure 105 and the second region III, thereby improving the accuracy and efficiency of electrical signal transmission between the capacitor structure 105 and the second region III, and thus further improving the electrical performance of the semiconductor structure.

[0089] In some embodiments, the step of forming the capacitive contact structure 107 may include: forming a second diffusion barrier layer (not shown) on the side of the second metal semiconductor compound layer 106 away from the second region III; forming a second conductive layer (not shown) on the side of the second diffusion barrier layer away from the second metal semiconductor compound layer 106. In this way, the second diffusion barrier layer can be used to block the diffusion of conductive elements in the second conductive layer into the second region III, thereby avoiding affecting the conductivity of the second conductive layer itself and the conductivity of the second region III.

[0090] Combination Figure 13 and reference Figure 4 The initial first isolation layer 144, the initial first diffusion barrier layer 133, and the remaining initial first conductive layer 143 are etched back to expose the sidewall of the second region III. The remaining initial first isolation layer 144 serves as the first isolation layer 114, the remaining initial first diffusion barrier layer 133 serves as the first diffusion barrier layer 113, and the remaining initial first conductive layer 143 serves as the first conductive layer 123. A third isolation layer 134 is formed, which fills the gaps between adjacent second region III, adjacent second metal semiconductor compound layer 106, and adjacent capacitor contact structure 107, and also fills the second trench 149. The first isolation layer 114, the second isolation layer 124, and the third isolation layer 134 together constitute the isolation structure 104.

[0091] Continue to refer to Figure 4 A capacitor structure 105 is formed on the side of the second region III away from the channel region II. Specifically, the capacitor structure 105 may be located on the side of the capacitor contact structure 107 away from the channel region II.

[0092] In summary, using the same semiconductor material to form the first region I and the initial bit line 101, making them an integral structure, helps to improve interface state defects between the first region I and the initial bit line 101, thereby improving the conductivity between them and enhancing the electrical performance of the semiconductor structure. Furthermore, all areas on the bottom surface of the formed first region I are in contact with the initial bit line 101, ensuring a large contact area between them, further improving conductivity and enhancing the electrical performance of the semiconductor structure.

[0093] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the embodiments of this disclosure. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of the embodiments of this disclosure; therefore, the scope of protection of the embodiments of this disclosure should be determined by the scope defined in the claims.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that, include: Provide a base; An initial bit line and a semiconductor pillar are formed on the surface of the substrate. The initial bit line extends along a first direction, and the semiconductor pillar is located on the side of the initial bit line away from the substrate. Along a direction perpendicular to the surface of the initial bit line, the semiconductor pillar includes a first region, a channel region, and a second region arranged sequentially. The first region is in contact with the initial bit line, and along a direction perpendicular to the first direction, the width of the initial bit line is greater than the width of the first region. The material forming the first region is the same as the material forming the initial bit line. A character line structure is formed, the character line structure surrounds the channel area, and the character line structure extends along a second direction, the second direction intersecting the first direction; The step of forming the initial bit line and the semiconductor pillar on the substrate surface includes: An initial semiconductor layer is formed on the substrate, the initial semiconductor layer comprising a stacked initial first region, an initial channel region, and an initial second region; The initial semiconductor layer is patterned to form a semiconductor layer and the semiconductor pillars located on the semiconductor layer, and the semiconductor layer covers the substrate surface, wherein the remaining initial second region after patterning is the second region, the remaining initial channel region after patterning is the channel region, and the remaining initial first region after patterning is the first region and the semiconductor layer; The semiconductor layer is patterned to form the initial bit line.

2. The manufacturing method as described in claim 1, characterized in that, Along a direction perpendicular to the substrate surface, the ratio of the height of the initial bit line to the height of the first region is 1 / 3 to 2 / 3.

3. The manufacturing method as described in claim 1, characterized in that, After patterning the semiconductor layer and before forming the word line structure, the method further includes: forming a second metal layer on the side of the initial bit line exposed away from the substrate, and performing a first metallization process on the initial bit line using the second metal layer to form a first metal semiconductor compound layer, the first metal semiconductor compound layer being located on the side of the remaining initial bit line away from the substrate, the first metal semiconductor compound layer and the remaining initial bit line together constituting a bit line.

4. The manufacturing method as described in claim 3, characterized in that, After forming the first metal-semiconductor compound layer and before forming the word line structure, the method further includes: forming a first metal layer located on the side of the first metal-semiconductor compound layer away from the remaining initial bit lines.

5. The manufacturing method as described in claim 1, characterized in that, Also includes: A second metallization process is performed on the side of the second region away from the channel region to form a second metal semiconductor compound layer, the second metal semiconductor compound layer being located on the side of the second region away from the channel region.

6. The manufacturing method as described in claim 1 or 5, characterized in that, Also includes: A capacitive contact structure is formed on the side of the second region away from the channel region.

7. A semiconductor structure, characterized in that, The semiconductor structure, manufactured by the manufacturing method according to any one of claims 1 to 6, comprises: A substrate and an initial bit line located on the surface of the substrate, the initial bit line extending along a first direction; A semiconductor pillar is located on the side of the initial bit line away from the substrate. Along a direction perpendicular to the surface of the initial bit line, the semiconductor pillar includes a first region, a channel region, and a second region arranged in sequence. The first region is in contact with the initial bit line and along a direction perpendicular to the first direction, the width of the initial bit line is greater than the width of the first region. The material forming the first region is the same as the material forming the initial bit line. A character line structure, the character line structure surrounding the channel area and the character line structure extending along a second direction, the second direction intersecting the first direction.

8. The semiconductor structure as described in claim 7, characterized in that, Along a direction perpendicular to the surface of the initial bit line, the ratio of the height of the initial bit line to the height of the first region is 1 / 3 to 2 / 3.

9. The semiconductor structure as described in claim 7, characterized in that, Also includes: A first metal-semiconductor compound layer is located on the side of the initial bit line away from the substrate, and the first metal-semiconductor compound layer and the initial bit line together constitute the bit line.

10. The semiconductor structure as described in claim 9, characterized in that, Also includes: A first metal layer is located on the side of the first metal-semiconductor compound layer away from the initial bit line, and the first metal layer, the first metal-semiconductor compound layer, and the initial bit line together constitute the bit line.

11. The semiconductor structure as claimed in claim 7, characterized in that, Also includes: A second metal-semiconductor compound layer is located on the side of the second region away from the channel region.

12. The semiconductor structure as claimed in claim 7, characterized in that, Also includes: An isolation structure is provided, wherein the isolation structure is located between the word line structure and the initial bit line, and the isolation structure is also located between the word line structure and the semiconductor pillar; A capacitor structure located on the side of the second region away from the channel region.

13. The semiconductor structure as described in claim 12, characterized in that, Also includes: A capacitor contact structure is located between the capacitor structure and the second region.

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