Ferroelectric memory, method of manufacturing the same, and application thereof

Abstract

The application relates to a ferroelectric memory and a preparation method and application thereof. The preparation method comprises the following steps: depositing a TiN bottom electrode on a substrate, then introducing NH3 into a CVD chamber to process the bottom electrode; depositing a hafnium oxide-based ferroelectric film on the surface of the bottom electrode; depositing a top electrode on the surface of the hafnium oxide-based ferroelectric film; patterning the top electrode by using a dry etching method; then performing annealing treatment; the annealing time is 20-40 s, and the temperature is 400-600 DEG C; and then performing metal interconnection. The ferroelectric memory integrated in a chip has improved residual polarization strength.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing processes, and in particular to a ferroelectric memory, its preparation method, and its applications. Background Technology

[0002] HfO2-based ferroelectric materials (HZO) are a novel type of ferroelectric material with excellent ferroelectric properties. Compared to traditional ferroelectric materials such as PZT and BST, they are compatible with CMOS processes, and their high dielectric constant allows for very thin film thickness control. They maintain stable ferroelectricity even at ultra-thin thicknesses below 10 nm, while PZT and SBT ferroelectric materials require thicker films to maintain their ferroelectricity. This effectively reduces the size of devices such as FeFETs, thereby improving chip integration. Furthermore, they do not contain Pb, reducing environmental pollution. HZO-based ferroelectric memories offer advantages such as high speed, low power consumption, fast read speed, and low operating voltage, making them a promising new type of non-volatile memory for solving the "memory wall" problem, with broad development prospects and potential.

[0003] In the electrode-ferroelectric layer-electrode (MFM) ferroelectric memory structure, how to integrate hafnium-based ferroelectric memory devices into CMOS integrated circuits while ensuring that the ferroelectric memory devices have a large residual polarization intensity is an urgent problem to be solved, which limits the progress of ferroelectric memory towards commercial application.

[0004] Therefore, this invention is proposed. Summary of the Invention

[0005] The main objective of this invention is to provide a method for fabricating ferroelectric memory, which improves the remanent polarization intensity of ferroelectric memory integrated into a chip.

[0006] To achieve the above objectives, the present invention provides the following technical solutions.

[0007] A first aspect of the present invention provides a method for fabricating a ferroelectric memory, comprising:

[0008] A TiN bottom electrode is deposited on a substrate, and then NH3 is introduced into the CVD chamber to treat the bottom electrode.

[0009] A hafnium oxide-based ferroelectric film is deposited on the surface of the bottom electrode;

[0010] A top electrode is deposited on the surface of the hafnium oxide-based ferroelectric film;

[0011] The top electrode was patterned using a dry etching method;

[0012] Then, annealing is performed: the annealing time is 20-40 seconds, and the temperature is 400-600℃.

[0013] Then, metal interconnects are performed.

[0014] A second aspect of the present invention provides a ferroelectric memory obtained by the above-described preparation method.

[0015] A third aspect of the present invention provides the application of the above-described ferroelectric memory in integrated circuits.

[0016] Compared with the prior art, the present invention achieves the following technical effects.

[0017] (1) The present invention uses a specific process sequence to form the bottom electrode, ferroelectric layer and top electrode and then anneal it. At the same time, the bottom electrode is treated with NH3 to reduce defects on the bottom electrode. Specific annealing conditions are used to achieve the crystallization of hafnium oxide-based ferroelectric film to promote the generation of ferroelectric phase. Based on these aspects, the residual polarization intensity of the ferroelectric memory integrated in the chip is improved.

[0018] (2) The process provided by the present invention is compatible with CMOS process, and the process is simple and low cost, and can be applied in large-scale production. Attached Figure Description

[0019] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention.

[0020] Figure 1 This is a structural diagram of the hafnium oxide-based ferroelectric film deposited in the preparation method provided in the embodiments of the present invention;

[0021] Figure 2 This is a structural diagram of the top electrode after deposition and patterning in the preparation method provided in the embodiments of the present invention;

[0022] Figure 3 This is a structural diagram of a memory cell after the metal interconnect structure is formed in the fabrication method provided in the embodiments of the present invention. Detailed Implementation

[0023] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0024] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0025] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0026] As described in the background section, existing fabrication processes for ferroelectric memory devices result in devices with relatively low remanent polarization. This invention discovers that the process sequence and conditions have a crucial impact on this polarization, and therefore provides the following fabrication method.

[0027] like Figure 1 As shown, a substrate 1 is provided; the substrate 1 can be any substrate known to those skilled in the art for carrying semiconductor integrated circuit components, such as silicon-on-insulator (SOI), bulk silicon, germanium, silicon germanium, gallium arsenide, or germanium-on-insulator, etc., with the corresponding top semiconductor material being silicon, germanium, silicon germanium, or gallium arsenide, etc., or it can be a carrier on which other structures have been fabricated, such as a carrier on which gate, transistor, or other structures have been fabricated. The carrier can be pre-cleaned.

[0028] Then, a TiN bottom electrode 2 is deposited on substrate 1, such as... Figure 1 As shown. Deposition methods include, but are not limited to, PVD, LPCVD, ALD, RTCVD, or PECVD, with PVD being the preferred method. The process conditions of PVD have a significant impact on the remanent polarization intensity of the memory. Studies have found that when the ion beam energy is 600–1100 eV and the current value is 30–50 mA, the deposited memory can achieve a higher remanent polarization intensity.

[0029] When depositing the TiN bottom electrode 2 using the above method, many defects may exist in the electrode itself due to particle bombardment effects during sputtering. Therefore, this invention transfers the electrode to a CVD chamber after deposition and introduces NH3 to treat the bottom electrode, thereby improving its electrical reliability. The NH3 treatment is preferably carried out in an inert atmosphere, such as N2. Furthermore, the process conditions of this treatment have a significant impact on the remanent polarization intensity of the memory. Studies have found that a higher remanent polarization intensity can be obtained when the pressure is 20–80 Pa, the power is 10–1000 W, the flow rate is 10–100 sccm, and the treatment time is 1–30 min.

[0030] The thickness of the bottom electrode 2 is preferably controlled between 20 nm and 50 nm to obtain good electrical performance.

[0031] Next, a hafnium oxide-based ferroelectric film 3 is deposited on the surface of the bottom electrode 2, such as... Figure 1 As shown. The membrane 3 can be deposited using methods such as LPCVD, ALD, RTCVD, or PECVD, with ALD (Atomic Layer Deposition) being preferred. ALD is a method of deposition using pulsed supply of reactive gas and precursor, i.e., pulsed supply of precursor and oxidant. Preferred ALD process conditions include: precursors Hf[N(C2H5)CH3]4 and Zr[N(C2H5)CH3]4, oxygen source O3 or H2O, and temperature 200℃~300℃, to minimize vacancy defects in the ferroelectric film.

[0032] The thickness of the hafnium oxide-based ferroelectric film 3 is preferably controlled between 5 nm and 13 nm to obtain good electrical properties.

[0033] Next, a top electrode 4 is deposited on the surface of the hafnium oxide-based ferroelectric film 3, such as... Figure 2 As shown, the type of top electrode is not limited; various common metals are acceptable, but it is preferred to use the same material as the bottom electrode, namely TiN. Similarly, the deposition method for the top electrode includes, but is not limited to, PVD, LPCVD, ALD, RTCVD, or PECVD, with PVD being the preferred method. The process conditions of the PVD method have a significant impact on the remanent polarization intensity of the memory. Studies have found that when the ion beam energy is 600–1100 eV and the current value is 30–50 mA, the deposited memory can achieve a higher remanent polarization intensity.

[0034] The top electrode 4 is then patterned using a dry etching method, which has advantages such as speed and low impurities. The preferred dry etching conditions are: etching gases of SF6 and C3F8, radio frequency power of 400-600W, and etching time of 20-30s.

[0035] The pattern of top electrode 4 depends on the period requirements.

[0036] Next, annealing is performed. The main purpose of annealing is to achieve crystallization of the hafnium oxide-based ferroelectric film to promote the formation of the ferroelectric phase. The preferred annealing conditions are: annealing time of 20-40 seconds and temperature of 400-600℃. These conditions, combined with the treatment of the bottom electrode, can significantly improve the remanent polarization intensity of the memory. Annealing is carried out in an inert atmosphere, preferably N2 atmosphere.

[0037] Finally, metal interconnects are performed to form interconnect structure 5, such as... Figure 3 As shown. Metal materials such as aluminum and tungsten can be used, with Al being the preferred choice.

[0038] In metal interconnect processes, through-holes and dielectric layers are typically formed by repeatedly depositing and etching dielectric layers. These processes can all be achieved using methods commonly found in the field.

[0039] The method described above in this invention is simple and achieves the effect of increasing the residual polarization intensity of ferroelectric memory integrated into a chip by using only specific process sequences and conditions.

[0040] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A method for fabricating a ferroelectric memory, characterized in that, include: A TiN bottom electrode is deposited on a substrate, and then NH3 is introduced into the CVD chamber to treat the bottom electrode. A hafnium oxide-based ferroelectric film is deposited on the surface of the bottom electrode; A top electrode is deposited on the surface of the hafnium oxide-based ferroelectric film; The top electrode was patterned using a dry etching method; Then, annealing is performed: the annealing time is 20-40 seconds, and the temperature is 400-600℃. Then, metal interconnects are performed; The annealing process serves to promote the formation of the ferroelectric phase by oxidizing the hafnium-based ferroelectric film; the annealing process performed after patterning the top electrode, together with the treatment of the bottom electrode by introducing NH3, synergistically enhances the residual polarization intensity of the ferroelectric memory in the integrated chip. The bottom electrode is formed by ion beam sputtering: the ion beam energy is 600-1100 eV and the current value is 30-50 mA. The conditions for treating the bottom electrode by introducing NH3 are as follows: The pressure is 20-80 Pa, the power is 10-1000 W, the flow rate is 10-100 sccm, and the processing time is 1-30 min.

2. The preparation method according to claim 1, characterized in that, The thickness of the bottom electrode is 20nm to 50nm.

3. The preparation method according to claim 1, characterized in that, The top electrode is TiN and is formed by ion beam sputtering: the ion beam energy is 600-1100 eV and the current value is 30-50 mA. And / or, The thickness of the top electrode is 20nm to 50nm.

4. The preparation method according to any one of claims 1-3, characterized in that, The hafnium oxide-based ferroelectric film was deposited using atomic layer deposition: the precursors were Hf[N(C2H5)CH3]4 and Zr[N(C2H5)CH3]4, the oxygen source was O3 or H2O, and the temperature was 200℃~300℃. And / or, The thickness of the hafnium oxide-based ferroelectric film is 5 nm to 13 nm.

5. The preparation method according to claim 1, characterized in that, The dry etching process uses SF6 and C3F8 as etching gases, has an RF power of 400-600W, and an etching time of 20-30s.

6. The preparation method according to claim 1, characterized in that, The annealing was performed in an N2 atmosphere.

7. The preparation method according to claim 1, characterized in that, The material of the metal interconnect is Al.

8. A ferroelectric memory, characterized in that, It is obtained by the preparation method according to any one of claims 1-7.

9. An application of the ferroelectric memory according to claim 8 in an integrated circuit.

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