Semiconductor structure, method of manufacturing the same, storage system, and electronic device

Abstract

The present disclosure provides a semiconductor structure, a preparation method thereof, a storage system and an electronic device, and relates to the technical field of semiconductor chips, so as to improve the structural stability of the semiconductor structure. The preparation method of the semiconductor structure comprises the following steps: forming an initial stack layer, the initial stack layer having an array region and a connection region; forming a contact hole, the contact hole extending into a target gate sacrificial layer, and the contact hole being located in the connection region; forming a set of sacrificial portions in the contact hole; forming an isolation groove, the isolation groove penetrating through the initial stack layer and dividing the initial stack layer into at least one initial storage block; and replacing the gate sacrificial layer located in the array region and the partial gate sacrificial layer located in the connection region with a gate layer via the isolation groove, forming a stack layer, and replacing the set of sacrificial portions with a contact portion; the contact portion being electrically connected with a target gate layer replacing the target gate sacrificial layer. The preparation method of the semiconductor structure is applied to the preparation of the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor chip technology, and in particular to a semiconductor structure and its fabrication method, a storage system, and an electronic device. Background Technology

[0002] As the feature size of memory cells approaches the lower limit of the process, planar processes and manufacturing technologies become challenging and costly, causing the storage density of 2D or planar NAND flash memory to approach its upper limit.

[0003] To overcome the limitations of 2D or planar NAND flash memory, the industry has developed memory with a three-dimensional structure (3D NAND), which increases storage density by arranging memory cells three-dimensionally on a substrate. Currently, improving the structural stability of 3D NAND is a problem that needs to be solved. Summary of the Invention

[0004] Embodiments of this disclosure provide a semiconductor structure and its fabrication method, a storage system, and an electronic device to improve the structural stability of the semiconductor structure.

[0005] To achieve the above objectives, the embodiments of this disclosure adopt the following technical solutions: On one hand, a method for fabricating a semiconductor structure is provided. The method includes: forming an initial stacked layer, the initial stacked layer comprising alternatingly stacked plurality of gate sacrificial layers and plurality of first dielectric layers; the initial stacked layer having an array region and a connection region; forming a contact hole extending into a target gate sacrificial layer; the contact hole being located in the connection region; the contact hole comprising a first portion and a second portion connected together; the first portion being disposed on the same layer as a layer of the target gate sacrificial layer; the second portion extending away from the target gate sacrificial layer and penetrating the initial stacked layer; forming a designated sacrificial portion within the contact hole; forming an isolation trench penetrating the initial stacked layer and dividing the initial stacked layer into at least one initial memory block; replacing the gate sacrificial layer located in the array region and a portion of the gate sacrificial layer located in the connection region with gate layers via the isolation trench to form a stacked layer, and replacing the designated sacrificial portion with a contact portion; the contact portion being electrically connected to a target gate layer that replaces the target gate sacrificial layer.

[0006] The semiconductor structure fabrication method provided in the above embodiments of this disclosure replaces the gate sacrificial layer located in the array region and a portion of the gate sacrificial layer located in the connection region with a gate layer, and replaces the set sacrificial portion with a contact portion. That is, the gate layer and the contact portion are formed simultaneously. In the embodiments of this disclosure, since the gate layer and the contact portion are formed simultaneously, damage to the first dielectric layer adjacent to the gate layer can be avoided during the etching of the contact hole where the contact portion is located, thereby improving the stability of the structure. Furthermore, when the gate layer includes a second dielectric layer, damage to the second dielectric layer of the gate layer can also be avoided during the etching of the contact hole where the contact portion is located, thereby preventing a decrease in the breakdown voltage between adjacent gate layers and improving the reliability of the structure.

[0007] In some embodiments, forming a designated sacrificial portion within the contact hole includes: forming a first filling layer on the sidewall and bottom wall of the contact hole; forming a second filling layer at the opening of the contact hole, the second filling layer sealing the opening of the contact hole; the first filling layer and the second filling layer are connected to form the designated sacrificial portion.

[0008] In some embodiments, the deposition rate for forming the first filling layer is less than the deposition rate for forming the second filling layer.

[0009] In some embodiments, the isolation trench includes a first portion extending through the array region and a second portion extending through the connection region. The process of replacing the gate sacrificial layer located in the array region and a portion of the gate sacrificial layer located in the connection region with gate layers via the isolation trench to form a stacked layer, and replacing the designated sacrificial portion with a contact portion, includes: A first sacrificial portion is formed within a first portion of the isolation trench. A portion of the gate sacrificial layer located within the connection region is removed via a second portion of the isolation trench, forming a second cavity; the second cavity exposes the portion of the designated sacrificial portion located within the target gate sacrificial layer. A second sacrificial portion is formed within the second cavity. The first sacrificial portion is removed, and the gate sacrificial layer located within the array region is removed via the first portion of the isolation trench, forming a first cavity. The second sacrificial portion and the designated sacrificial portion are removed, making the second cavity communicate with the contact hole at the location of the target gate sacrificial layer. A gate layer is formed within the first cavity and the second cavity via the first and second portions of the isolation trench, forming a stacked layer, and a contact portion is formed within the contact hole.

[0010] In some embodiments, forming the second sacrificial portion within the second cavity includes: forming a third filling layer on the sidewall and bottom wall of the second cavity; forming a fourth filling layer at the opening of the second cavity to seal the opening of the second cavity; the third filling layer is connected to the fourth filling layer to form the second sacrificial portion.

[0011] In some embodiments, the deposition rate for forming the third filler layer is less than the deposition rate for forming the fourth filler layer.

[0012] In some embodiments, the material of the second sacrificial part is the same as the material of the set sacrificial part.

[0013] In some embodiments, forming the first sacrificial portion within the first portion of the isolation trench includes: filling the first and second portions of the isolation trench with sacrificial material; forming a first mask layer having a first opening that exposes the sacrificial material in the second portion, and covering the top opening of the contact hole by the first mask layer; the portion of the first mask layer covering the top opening of the contact hole forms the top wall of the contact hole; etching the sacrificial material located in the second portion through the first opening; the sacrificial material retained in the first portion serves as the first sacrificial portion.

[0014] In some embodiments, removing the first sacrificial portion and removing the gate sacrificial layer located in the array region via a first portion of the isolation trench to form a first cavity includes: etching the first mask layer to form a second opening, the second opening exposing the first sacrificial portion; removing the first sacrificial portion via the second opening; and removing the gate sacrificial layer located in the array region via the first portion to form a first cavity.

[0015] In some embodiments, forming a contact portion within the contact hole includes: depositing a first target material within the contact hole via a connection between the second cavity and the contact hole; the first target material being deposited on the sidewalls and bottom wall of the contact hole to form a first sub-contact portion; and the first target material being deposited on the top wall of the contact hole to form a second sub-contact portion. The contact portion includes the first sub-contact portion and the second sub-contact portion, and the first sub-contact portion and the second sub-contact portion surround a third cavity.

[0016] In some embodiments, forming the isolation trench includes: forming a second mask layer having a plurality of third openings that expose a portion of the surface of the initial stacked layer; the top opening of the contact hole is also covered by the second mask layer, and the top wall of the contact hole includes a portion of the second mask layer that covers the top opening of the contact hole. The initial stacked layer is etched through the plurality of third openings to form the isolation trench.

[0017] In some embodiments, forming a contact hole includes: etching the initial stacked layers down to a first dielectric layer adjacent to and above the target gate sacrificial layer to form an initial contact hole; forming a third dielectric layer within the initial contact hole, the third dielectric layer covering the sidewalls and bottom wall of the initial contact hole; etching the third dielectric layer covering the bottom wall of the initial contact hole and the first dielectric layer below it to expose the target gate sacrificial layer; and etching the exposed portion of the target gate sacrificial layer and the portion surrounding the exposed portion to form the contact hole.

[0018] In some embodiments, prior to forming the contact hole, the fabrication method further includes forming a channel structure through the initial stacked layer. After replacing the gate sacrificial layer located in the array region and a portion of the gate sacrificial layer located in the connection region with a gate layer via the isolation trench to form a stacked layer, and replacing the designated sacrificial portion with a contact portion, the fabrication method further includes forming a first connection portion and a second connection portion, wherein the first connection portion is electrically connected to the channel structure and the second connection portion is electrically connected to the contact portion.

[0019] In some embodiments, forming the first connection portion and the second connection portion includes: forming a first protective layer covering the channel structure and the contact portion; forming a fourth opening and a fifth opening penetrating the first protective layer, the fourth opening exposing the channel structure and the fifth opening exposing the contact portion; forming the first connection portion within the fourth opening and forming the second connection portion at least within the fifth opening.

[0020] In some embodiments, the contact portion includes a first sub-contact portion and a second sub-contact portion, the first sub-contact portion and the second sub-contact portion forming a third cavity, the fifth opening further penetrating the top wall of the contact hole and the second sub-contact portion of the contact portion, and along a predetermined direction, the size of the fifth opening is smaller than the size of the second sub-contact portion; the predetermined direction is at least one direction parallel to the plane of the stacked layer. Forming a second connection portion located at least within the fifth opening includes: depositing a second target material into the third cavity of the contact portion via the fifth opening to form the second connection portion; the second connection portion includes a main body portion filling the third cavity and an extension portion filling the fifth opening.

[0021] In some embodiments, forming the fifth opening includes: removing a first protective layer located above the contact portion, the top wall of the contact hole, and a second sub-contact portion of the contact portion to form the fifth opening; the fifth opening exposes the first sub-contact portion of the contact portion. Forming a second connection portion located at least within the fifth opening includes: depositing a second target material into a third cavity of the contact portion via the fifth opening to form a conductive filling layer; the conductive filling layer covers the sidewalls of the first sub-contact portion and the sidewalls of the fifth opening, and the conductive filling layer has gaps. A protective filling layer is formed within the gaps; the second connection portion includes the conductive filling layer and the protective filling layer.

[0022] In some embodiments, the fifth opening further penetrates the top wall of the contact hole, exposing a second sub-contact of the contact portion. Forming a second connection portion, at least within the fifth opening, includes depositing a second target material into the fifth opening to form the second connection portion.

[0023] In some embodiments, forming the first connection and the second connection includes: removing a portion of the stacked layer to expose a first sub-contact of the contact portion and the channel structure; forming a second protective layer that fills a third cavity of the contact portion and covers the channel structure; forming a fourth opening and a fifth opening through the second protective layer, the fourth opening exposing the channel structure and the fifth opening exposing the first sub-contact; forming a first connection portion within the fourth opening and a second connection portion within the fifth opening.

[0024] In some embodiments, forming a gate layer, forming a stacked layer, and forming a contact portion within the contact hole via a first portion and a second portion of the isolation trench includes: sequentially forming a second dielectric layer, a metal compound layer, and a conductive layer within the first cavity, the second cavity, and the contact hole via the first portion and the second portion of the isolation trench. Specifically, portions of the second dielectric layer, the metal compound layer, and the conductive layer located within the first cavity and the second cavity form the gate layer, and portions of the second dielectric layer, the metal compound layer, and the conductive layer located within the contact hole form the contact portion.

[0025] On the other hand, a semiconductor structure is provided. The semiconductor structure includes a stacked layer, an isolation structure, and a contact portion. The stacked layer includes a plurality of alternately stacked gate layers and a plurality of first dielectric layers, the stacked layer having an array region and a connection region. The isolation structure extends through the stacked layer and divides the stacked layer into at least one memory block. The contact portion is located in the connection region; the contact portion extends from the upper surface of the stacked layer to a target gate layer and is electrically connected to the target gate layer; the contact portion and the gate layer are integrally formed.

[0026] In some embodiments, the contact portion includes a first sub-contact portion, which is a cylindrical structure. The axis of the first sub-contact portion is perpendicular to the plane of the stacked layer, and the bottom end of the first sub-contact portion is electrically connected to the target gate layer.

[0027] In some embodiments, the semiconductor structure further includes a second connection portion, a portion of which extends into the first sub-contact portion and is in electrical contact with the first sub-contact portion.

[0028] In some embodiments, the contact portion further includes a second sub-contact portion located on the side of the first sub-contact portion away from the target gate layer and connected to the first sub-contact portion. The semiconductor structure further includes a second mask layer, a first mask layer, and a first protective layer. The second mask layer is disposed on the stacked layer; the first mask layer is disposed on the side of the second mask layer away from the stacked layer; the first protective layer is disposed on the side of the first mask layer away from the stacked layer; wherein the second connection portion includes a main portion and an extension portion, the main portion being located within the first sub-contact portion, and the extension portion penetrating the first protective layer, the first mask layer, the second mask layer, and the second sub-contact portion, and connected to the main portion.

[0029] In some embodiments, the extension is smaller than the size of the second sub-contact portion along a predetermined direction; the predetermined direction is at least one direction parallel to the plane of the stacked layers; and / or, the main body portion has an air gap.

[0030] In some embodiments, the semiconductor structure further includes a second mask layer, a first mask layer, and a first protective layer. The second mask layer is disposed on the stacked layer; the first mask layer is disposed on the side of the second mask layer away from the stacked layer; the first protective layer is disposed on the side of the first mask layer away from the stacked layer. The second connection portion includes a conductive filling layer and the protective filling layer. The conductive filling layer penetrates the first protective layer, the first mask layer, and the second mask layer, and covers the inner sidewall and top wall of the first sub-contact portion. The conductive filling layer has a gap, and the protective filling layer fills the gap.

[0031] In some embodiments, the contact portion further includes a second sub-contact portion located on the side of the first sub-contact portion away from the target gate layer and connected to the first sub-contact portion. The semiconductor structure further includes a second mask layer, a first mask layer, a first protective layer, and a second connection portion. The second mask layer is disposed on the stacked layer; the first mask layer is disposed on the side of the second mask layer away from the stacked layer; the first protective layer is disposed on the side of the first mask layer away from the stacked layer; the second connection portion penetrates the first protective layer, the first mask layer, and the second mask layer, and is electrically connected to the second sub-contact portion.

[0032] In some embodiments, the size of the second connection portion is smaller than the size of the second sub-contact portion along a predetermined direction; the predetermined direction is at least one direction parallel to the plane of the stacked layer.

[0033] In some embodiments, the semiconductor structure further includes a second protective layer and a second connection portion. The second protective layer is disposed on the stacked layer and fills the first sub-contact portion. The second connection portion extends through the second protective layer and is electrically connected to the top end of the first sub-contact portion.

[0034] In another aspect, a storage system is provided. The storage system includes a semiconductor structure as described above and a controller, the controller being coupled to the semiconductor structure to control the semiconductor structure to store data.

[0035] In another aspect, an electronic device is provided. The electronic device includes the storage system described above.

[0036] It is understood that the beneficial effects of the semiconductor structure, memory system and electronic device provided in the above embodiments of this disclosure can be referred to the beneficial effects of the semiconductor structure preparation method described above, and will not be repeated here. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0038] Figure 1 A cross-sectional view of a semiconductor structure according to some embodiments; Figure 2A for Figure 1 A cross-sectional view of a string of storage cells in a three-dimensional memory. Figure 2B for Figure 2A Equivalent circuit diagram of the memory cell string; Figure 3A This is a top view of a semiconductor structure according to some embodiments during the formation of an isolation trench; Figure 3B This is a top view of a semiconductor structure according to some embodiments; Figures 4-8 In a method for fabricating a semiconductor structure according to some embodiments, the semiconductor structure along... Figure 3A Preparation steps at the mid-section line AA'; Figures 9-13 In a method for fabricating a semiconductor structure according to some embodiments, the semiconductor structure along... Figure 3B Preparation steps at the mid-section line AA'; Figure 14 and Figure 15 This is a diagram illustrating the fabrication steps of a semiconductor structure according to some embodiments; Figure 16 and Figure 17 This is a diagram illustrating the fabrication steps of a semiconductor structure according to some other embodiments; Figure 18 and Figure 19 This is a diagram illustrating the fabrication steps of a semiconductor structure according to some other embodiments; Figure 20 and Figure 21 This is a diagram illustrating the fabrication steps of a semiconductor structure according to some other embodiments; Figures 22-33 This is a flowchart of a method for fabricating a semiconductor structure according to some embodiments; Figure 34 This is a block diagram of a storage system according to some embodiments; Figure 35 This is a block diagram of a storage system according to some other embodiments. Detailed Implementation

[0039] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0040] In the description of this disclosure, it should be understood that the terms “center,” “upper,” “lower,” “front,” “rear,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” and “outer,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0041] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0042] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0043] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0044] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0045] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0046] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0047] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0048] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0049] In this disclosure, the meanings of “on,” “above,” and “above” should be interpreted in the broadest possible sense, such that “on” means not only “directly on” something, but also includes “on” something with intermediate features or layers in between, and “above” or “above” means not only “above” or “above” something, but also “above” or “above” something without intermediate features or layers in between (i.e., directly on something).

[0050] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0051] As used herein, the term "substrate" refers to a material on which subsequent material layers can be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0052] As used herein, the term “vertical / perpendicular” means nominally perpendicular to the main surface (i.e., the lateral surface) of the substrate or source layer.

[0053] Figure 1This is a cross-sectional view of a semiconductor structure according to some embodiments. Figure 2A for Figure 1 A cross-sectional view of a string of memory cells in a semiconductor structure. Figure 2B for Figure 2A Equivalent circuit diagram of the storage cell string.

[0054] See Figure 1 Some embodiments of this disclosure provide a semiconductor structure 200. The semiconductor structure 200 may include a memory cell string array 300. The semiconductor structure 200 may also include a source layer SL coupled to the memory cell string array 300, and peripheral devices 100 coupled to the memory cell string array 300. The peripheral devices 100 may be disposed on the side of the memory cell string array 300 away from the source layer SL.

[0055] The source layer SL can be made of semiconductor materials, such as single-crystal silicon, polycrystalline silicon, single-crystal germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, and other suitable semiconductor materials. The source layer SL can be partially or completely doped. For example, the source layer SL can include doped regions doped with p-type dopant. The source layer SL can also include undoped regions.

[0056] See Figure 1 and Figure 2A The semiconductor structure 200 may include arrays of memory cell transistor strings 400 (referred to herein as “memory cell strings”, such as NAND memory cell strings). A source layer SL may be coupled to the source ends of multiple memory cell strings 400.

[0057] Specifically, see Figure 2A and Figure 2B The storage cell string 400 may include multiple transistors T, one transistor T (e.g., Figure 2B Transistors T1 to T6 can be configured as a memory cell, and these transistors T are connected together to form a memory cell string 400. A transistor T (e.g., each transistor T) can be formed by a semiconductor channel 249 and a gate G surrounding the semiconductor channel 249. The gate G is configured to control the on-state of the transistor T.

[0058] It should be noted that, Figure 1 , Figure 2A and Figure 2B The number of transistors is merely illustrative. The memory cell string of the semiconductor structure provided in the embodiments of this disclosure may also include other numbers of transistors, such as 4, 16, 32, and 64.

[0059] Further, along the third direction Z, the lowermost gate among the multiple gates G (e.g., the gate closest to the source layer SL among the multiple gates G) is configured as a source select gate SGS. The source select gate SGS is configured to control the conduction state of transistor T6, thereby controlling the conduction state of one source channel in the memory cell string 400. The uppermost gate among the multiple gates G (e.g., the gate furthest from the source layer SL among the multiple gates G) is configured as a drain select gate SGD. The drain select gate SGD is configured to control the conduction state of transistor T1, thereby controlling the conduction state of one drain channel in the memory cell string 400. The middle gate among the multiple gates G can be configured as multiple word lines WL, such as word lines WL0, WL1, WL2, and WL3. By writing different voltages on the word lines WL, data writing, reading, and erasing of each memory cell (e.g., transistor T) in the memory cell string 400 can be completed.

[0060] It should be noted that the semiconductor structure 200 extends in the XY plane. The first direction X and the second direction Y are, for example, two orthogonal directions in the plane where the semiconductor structure 200 is located (e.g., the plane where the source layer SL is located): the first direction X is, for example, the extension direction of the word line, and the second direction Y is, for example, the extension direction of the bit line. The third direction Z is perpendicular to the plane where the semiconductor structure 200 is located, that is, perpendicular to the XY plane.

[0061] As used in this disclosure, whether a component (e.g., a layer, structure, or device) is "on," "above," or "below" another component of the memory cell string array 300 is determined relative to the substrate or source layer of the memory cell string array 300 in the third direction Z, when the substrate or source layer is located in the lowest plane of the memory cell string array 300 in the third direction Z. The same concepts are applied throughout this disclosure to describe spatial relationships.

[0062] See also Figure 1 In some embodiments, the semiconductor structure 200 may further include an array interconnect layer 290. The array interconnect layer 290 may be coupled to the memory cell string 400. The array interconnect layer 290 may include the drain (i.e., bit line) of the memory cell string 400, which may be coupled to the semiconductor channel of at least one transistor T in the memory cell string 400.

[0063] The array interconnect layer 290 may include one or more first interlayer insulating layers 292, and may also include a plurality of contact plugs 232 insulated from each other by these first interlayer insulating layers 292. The contact plugs 232 may include, for example, bit line contact plugs coupled to bit lines and drain select gate contact plugs coupled to drain select gates (SGD). The array interconnect layer 290 may also include one or more first interconnect conductor layers 291. The first interconnect conductor layer 291 may include a plurality of interconnect lines, such as bit lines, and word line interconnect lines coupled to word lines (WL). The materials of the first interconnect conductor layer 291 and the contacts may be conductive materials, such as tungsten, cobalt, copper, aluminum, and combinations of one or more metal silicides, or other suitable materials. The material of the first interlayer insulating layer 292 is an insulating material, including at least one of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organosilicon glass, dielectric metal oxides (e.g., aluminum oxide, hafnium dioxide, etc.) and their silicates, and organic insulating materials, and this disclosure is not limited thereto.

[0064] Peripheral device 100 may include peripheral circuitry. The peripheral circuitry is configured to control and sense the array device. The peripheral circuitry may be any suitable digital, analog, and / or mixed-signal control and sensing circuitry used to support the operation (or function) of the array device, including but not limited to page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive components of the circuitry (e.g., transistors, diodes, resistors, or capacitors). The peripheral circuitry may also include any other circuitry compatible with advanced logic processes, including logic circuitry (e.g., processors and programmable logic devices (PLDs)) or memory circuitry (e.g., static random-access memory (SRAM)).

[0065] Specifically, in some embodiments, the peripheral device 100 may include a substrate 110, a transistor 120 disposed on the substrate 110, and a peripheral interconnect layer 130 disposed on the substrate 110. The peripheral circuitry may include the transistor 120.

[0066] The substrate 110 can be made of single-crystal silicon or other suitable materials, such as silicon-germanium, germanium or silicon-on-insulator thin film.

[0067] The peripheral interconnect layer 130 is coupled to the transistor 120 to transmit electrical signals between the transistor 120 and the peripheral interconnect layer 130. The peripheral interconnect layer 130 may include one or more second interlayer insulating layers 131, and may also include one or more second interconnect conductor layers 132. Different second interconnect conductor layers 132 may be coupled to each other via contacts. The materials of the second interconnect conductor layers 132 and the contacts may be conductive materials, such as tungsten, cobalt, copper, aluminum, and combinations of one or more metal silicides, or other suitable materials. The material of the second interlayer insulating layer 131 is an insulating material, including at least one of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organosilicon glass, dielectric metal oxides (e.g., aluminum oxide, hafnium dioxide, etc.) and their silicates, and organic insulating materials, and this disclosure is not limited thereto.

[0068] The peripheral interconnect layer 130 can be coupled to the array interconnect layer 290, enabling coupling between the semiconductor structure 200 and the peripheral device 100. Specifically, since the peripheral interconnect layer 130 is coupled to the array interconnect layer 290, the peripheral circuitry in the peripheral device 100 can be coupled to the memory cell strings in the memory cell string array 300 to achieve the transmission of electrical signals between the peripheral circuitry and the memory cell strings. In some possible implementations, an bonding interface 500 can be provided between the peripheral interconnect layer 130 and the array interconnect layer 290, through which the peripheral interconnect layer 130 and the array interconnect layer 290 can be bonded and coupled to each other.

[0069] As the number of layers in 3D NAND increases, the etching process for the contact holes used to bring out the gate layer becomes increasingly difficult. To reduce this difficulty, a self-aligned contact (SCT) architecture for 3D NAND has been proposed. However, in the fabrication process of SCT architecture 3D NAND, since the contacts used to bring out the gate layer are fabricated after the gate layer is formed, the high-dielectric-constant layer within the gate layer is easily damaged during contact formation. This leads to a decrease in the breakdown voltage between adjacent gate layers, increasing the risk of voltage breakdown between adjacent gate layers; and the dielectric layer adjacent to the gate layer is also easily damaged, thus affecting the stability of the structure.

[0070] Based on this, embodiments of this disclosure provide a method for fabricating a semiconductor structure 200, such as... Figure 22 As shown, the preparation method includes steps S100 to S500.

[0071] S100: See Figure 4 This forms the initial stacked layer 210'.

[0072] In the above steps, the initial stacked layer 210' includes multiple gate sacrificial layers 212' and multiple first dielectric layers 211 stacked alternately. Wherein, combined with Figure 3A and Figure 4 The initial stacked layer 210' has an array region C and a connection region S, and the gate sacrificial layer 212' and the first dielectric layer 211 both extend from the array region C to the connection region S. Here, Figure 4 China has not formed Figure 3A The isolation slot GLS and the set sacrifice unit 240' are shown.

[0073] It should be noted that the material of the first dielectric layer 211 may include an insulating material, which includes at least one of silicon oxide, silicon nitride, doped silicon oxide, organosilicon glass, dielectric metal oxide (e.g., aluminum oxide, hafnium dioxide, etc.) and their silicates, and organic insulating materials. The material of the gate sacrificial layer 212' includes at least one of silicon, silicon oxide, silicon carbide, and silicon nitride, but this disclosure is not limited thereto.

[0074] Here, the material of the first dielectric layer 211 is different from the material of the gate sacrificial layer 212', so that the first dielectric layer 211 and the gate sacrificial layer 212' have different etching selectivity ratios for the same etchant. For example, the material of the first dielectric layer 211 is silicon dioxide, and the material of the gate sacrificial layer 212' is silicon nitride.

[0075] The initial stacked layer 210' can be formed on the substrate using any of the thin film deposition processes of CVD, PVD, or ALD.

[0076] Here, the aforementioned substrate can be used to support the initial stacked layer 210', which can be removed in subsequent processes. The substrate material includes monocrystalline silicon, polycrystalline silicon, monocrystalline germanium, and III... Group V compound semiconductor materials, II A group VI compound semiconductor material or at least one of other semiconductor materials known in the art.

[0077] In some embodiments, the substrate may be a composite substrate. Exemplarily, the substrate may include a base, and a sacrificial silicon oxide layer and a sacrificial polycrystalline silicon layer sequentially formed on the base. The material of the base may include monocrystalline silicon, polycrystalline silicon, monocrystalline germanium, or III... The material of the sacrificial silicon oxide layer may include silicon oxide; the material of the sacrificial polysilicon layer may include polysilicon.

[0078] S200: See also Figure 6 This forms contact hole 241.

[0079] In the above steps, the contact hole 241 extends from the upper side of the initial stacked layer 210' into the target gate sacrificial layer 2121'. The contact hole 241 includes a first portion and a second portion that are connected. The first portion is disposed in the same layer as the target gate sacrificial layer 2121', and the second portion extends away from the target gate sacrificial layer 2121', penetrating the initial stacked layer 210'. Figure 6 China has not formed Figure 3A The isolation slot GLS and the set sacrifice unit 240' are shown.

[0080] It should be noted that the specific process for forming contact hole 241 can be found in [reference needed]. Figure 33 The details of S210~S240 in this disclosure will not be elaborated here.

[0081] Understandably, in combination Figure 13 Each gate sacrificial layer 212' is at least partially replaced by a gate layer 212 in subsequent processes, and each gate layer 212 is electrically contacted with a contact portion 240 to be electrically connected to the corresponding word line connection. Here, the contact portion 240 is located in a contact hole 241, and the gate layer 212 electrically connected to each contact portion 240 is the target gate layer 2121. That is, the contact hole 241 extends to the target gate layer 2121, and the target gate sacrificial layer 2121' is the gate sacrificial layer 212' corresponding to the target gate layer 2121 exposed by the contact hole 241 before replacement.

[0082] S300: See Figure 6 , Figure 7A and Figure 7B A set sacrificial part 240' is formed inside the contact hole 241.

[0083] In the above steps, any of the thin film deposition processes of CVD, PVD, and ALD can be used to form the sacrificial portion 240'. The sacrificial portion 240' covers the sidewalls and bottom wall of the contact hole 241 and seals the opening of the contact hole 241 to avoid subsequent formation of the second mask layer 280 (see...). Figure 8 During the process, the second mask layer 280 is partially formed within the contact hole 241, thereby affecting the contact portion 240 formed within the contact hole 241 (see...). Figure 13 The conductivity of ). Here, Figure 7A and Figure 7B China has not formed Figure 3A The isolation slot GLS shown.

[0084] The material of the set sacrificial portion 240' is different from that of the gate sacrificial layer 212', so that the set sacrificial portion 240' and the gate sacrificial layer 212' have different etching rates for the same etchant. For example, the material of the set sacrificial portion 240' includes carbon, and the material of the gate sacrificial layer 212' can be silicon nitride, but this disclosure is not limited thereto.

[0085] It should be noted that the specific process for forming the sacrificial section 240' can be found in [reference needed]. Figure 23 The details of S310~S320 in this disclosure will not be elaborated here.

[0086] S400: See Figure 8 This forms the isolation groove GLS.

[0087] In the above steps, the isolation slot GLS penetrates the initial stack layer 210' and divides the initial stack layer 210' into at least one initial storage block B' (see...). Figure 3A The isolation trench GLS comprises a first part GLS1 passing through the array region C and a second part GLS2 passing through the connection region S. The isolation trench GLS, penetrating the initial stacked layer 210', can be formed using a dry / wet etching process.

[0088] It should be noted that the specific process for forming the GLS isolation trench can be found in [reference needed]. Figure 28 The details of S410~S420 in this disclosure will not be elaborated here.

[0089] S500: See Figure 8 and Figure 13 The gate sacrificial layer 212' located in the array region C and the partial gate sacrificial layer 212' located in the connection region S are replaced with gate layer 212 via the isolation trench GLS, and the set sacrificial part 240' is replaced with contact part 240.

[0090] In the above steps, the gate layer 212 may include a conductive layer 2122, and the material of the conductive layer 2122 may include a conductive material, such as at least one of tungsten, cobalt, copper, aluminum, doped silicon, and silicide.

[0091] In some embodiments, the gate layer 212 may further include a metal compound layer 2123, which is located between the conductive layer 2122, the channel structure 220, and the first dielectric layer 211. The metal compound layer 2123 is configured as an adhesive layer to improve the adhesion between the conductive layer 2122 and the first dielectric layer 211. The material of the metal compound layer 2123 includes at least one of titanium nitride, tantalum nitride, and tungsten carbide.

[0092] In some embodiments, the gate layer 212 may further include a second dielectric layer 2124, which is located between the metal compound layer 2123, the channel structure 220, and the first dielectric layer 211 to reduce the risk of charge flowing from the channel structure 220 to the conductive layer 2122. The dielectric constant of the second dielectric layer 2124 is greater than or equal to 7. Exemplarily, the material of the second dielectric layer 2124 includes at least one of aluminum oxide, hafnium oxide, and tantalum oxide.

[0093] Based on the above, such as Figure 8 and Figure 13 As shown, a stacked layer 210 can be formed, which includes a first dielectric layer 211 and a gate layer 212. The contact portion 240 is electrically connected to the conductive layer 2122 in the target gate layer 2121 that replaces the target gate sacrificial layer 2121'. Furthermore, after forming the gate layer 212, an isolation structure 235 can be formed in the isolation trench GLS.

[0094] It should be noted that the specific process of replacing the gate sacrificial layer 212' located in the array region C and part of the gate sacrificial layer 212' located in the connection region S with the gate layer 212 via the isolation trench GLS, and replacing the setting sacrificial part 240' with the contact part 240, can be found in [reference needed]. Figure 24 The S510~S560 components are not described in detail here.

[0095] As described above, the semiconductor structure fabrication method provided in some embodiments of this disclosure replaces the gate sacrificial layer 212' located in the array region C and the partial gate sacrificial layer 212' located in the connection region S with the gate layer 212, and replaces the set sacrificial portion with the contact portion 240. That is, the gate layer 212 and the contact portion 240 are formed simultaneously. In the embodiments of this disclosure, since the gate layer 212 and the contact portion 240 are formed simultaneously, damage to the first dielectric layer 211 adjacent to the gate layer 212 can be avoided during the etching of the contact hole where the contact portion is located, thereby improving the stability of the structure. Furthermore, when the gate layer 212 includes a second dielectric layer 2124, damage to the second dielectric layer 2124 of the gate layer 212 can also be avoided during the etching of the contact hole where the contact portion is located, thereby preventing a decrease in the breakdown voltage between adjacent gate layers 212 and improving the reliability of the structure.

[0096] In some embodiments, see Figure 23 The above S300 includes S310~S320.

[0097] S310: See also Figure 6 , Figure 7A and Figure 7B A first filling layer 2410' is formed on the sidewall and bottom wall of the contact hole 241.

[0098] In the above steps, any one of CVD, PVD, or ALD thin film deposition processes can be used to form the first filling layer 2410', which covers the sidewalls and bottom wall of the contact hole 241. Here, the deposition time can be controlled by stopping the deposition after covering the sidewalls and bottom wall of the contact hole 241 through the opening of the contact hole 241, thereby forming the first filling layer 2410'.

[0099] S320: See also Figure 6 , Figure 7A and Figure 7B A second filling layer 2420' is formed at the opening of the contact hole 241.

[0100] In the above steps, any one of CVD, PVD, or ALD thin film deposition processes can be used to form the second filler layer 2420'. The second filler layer 2420' seals the opening of the contact hole 241. The first filler layer 2410' is connected to the second filler layer 2420' to form the set sacrificial part 240'.

[0101] Here, the second filler layer 2420' seals the opening of the contact hole 241 to prevent subsequent formation of the second mask layer 280 (see...). Figure 8 During the process, the second mask layer 280 is partially formed within the contact hole 241, thereby affecting the contact portion 240 formed within the contact hole 241 (see...). Figure 13 The conductivity of the second mask layer 280, and to prevent the formation of isolation trenches GLS by etching with the second mask layer 280 as a mask (see Figure 8 During the process, the contact hole 241 was damaged.

[0102] Furthermore, by controlling the rate at which the material is deposited in S320 is greater than the rate at which the material is deposited in S310, that is, the deposition rate of forming the first filling layer 2410' is less than the deposition rate of forming the second filling layer 2420', a second filling layer 2420' can be formed to seal the opening of the contact hole 241.

[0103] For example, the material of the first filling layer 2410' is the same as that of the second filling layer 2420'. Based on this, the deposition rate of the deposited material can be controlled, for example, the deposition rate can be increased after the first filling layer 2410' is formed, so that the contact hole 241 can be sealed in advance to form the second filling layer 2420'.

[0104] It should be noted that the material of the first filling layer 2410' and the material of the second filling layer 2420' can be the same or different. Here, if the materials of the first filling layer 2410' and the second filling layer 2420' are different, such as... Figure 7BAs shown, the second filling layer 2420' also covers the inner wall of the first filling layer 2410'.

[0105] In some embodiments, see Figure 24 The above S500 includes S510 to S560.

[0106] S510: See also Figure 8 and Figure 9 A first sacrificial part 251 is formed in the first part GLS1 of the isolation groove GLS.

[0107] In the above steps, the first sacrificial portion 251 can be formed in the isolation trench GLS using any of the following thin film deposition processes: CVD, PVD, and ALD. The material of the first sacrificial portion 251 is different from the material of the first dielectric layer 211, so that the first sacrificial portion 251 and the first dielectric layer 211 have different etching rates for the same etchant. Here, the material of the first sacrificial portion 251 can be polysilicon, but this disclosure is not limited thereto. Figure 9 China has not formed Figure 3B The isolation structure 235 and the contact portion 240 are shown.

[0108] It should be noted that the specific process of forming the first sacrificial part 251 in the first part GLS1 of the isolation tank GLS can be referred to S511~S513, and will not be repeated here.

[0109] S520: See Figure 8 and Figure 9 The second cavity 260 is formed by removing part of the gate sacrificial layer 212' located in the connection region S via the second part GLS2 of the isolation groove GLS.

[0110] In the above steps, the second part GLS2 of the isolation trench GLS can be used as an etchant channel to remove part of the gate sacrificial layer 212' located in the connection region S by isotropic etching, thereby forming the second cavity 260. The second cavity 260 exposes the portion of the set sacrificial part 240' located in the target gate sacrificial layer 2121'.

[0111] It should be noted that the second cavity 260 includes the second part of the isolation groove GLS, GLS2.

[0112] S530: See also Figure 9 , Figure 10A and Figure 10B A second sacrificial part 261 is formed within the second cavity 260.

[0113] In the above steps, the second sacrificial portion 261 can be formed in the isolation tank GLS using any of the following thin film deposition processes: CVD, PVD, and ALD. The material of the second sacrificial portion 261 can be the same as the material of the initial sacrificial portion 240'. Here, Figure 10A and Figure 10B China has not formed Figure 3B The isolation structure 235 and the contact portion 240 are shown.

[0114] In some embodiments, such as Figure 10A and Figure 10B As shown, the second sacrificial part 261 is in contact with the set sacrificial part 240'.

[0115] It should be noted that the specific process for forming the second sacrificial part 261 within the second cavity 260 can be found in [reference needed]. Figure 25 The details of S531~S532 in this disclosure will not be elaborated here.

[0116] S540: See also Figure 8 , Figure 10A and Figure 11 The first sacrificial portion 251 is removed, and the gate sacrificial layer 212' located in the array region C is removed via the first part GLS1 of the isolation trench GLS to form the first cavity 250.

[0117] In the above steps, a dry / wet etching process can be used first to remove the first sacrificial portion 251 within the first part GLS1 of the isolation trench GLS. Then, using the first part GLS1 of the isolation trench GLS as an etchant channel, isotropic etching is used to remove the gate sacrificial layer 212' located in the array region C, forming the first cavity 250. Here, Figure 11 China has not formed Figure 3B The isolation structure 235 and the contact portion 240 are shown.

[0118] It should be noted that the specific process of removing the first sacrificial portion 251 and removing the gate sacrificial layer 212' located in the array region C through the first part of the isolation trench GLS to form the first cavity 250 can be found in [reference needed]. Figure 27 The details of S541~S543 in this disclosure will not be elaborated here.

[0119] S550: See also Figure 11 and Figure 12 Remove the second sacrificial part 261 and the set sacrificial part 240', so that the second cavity 260 and the contact hole 241 are connected at the position of the target gate sacrificial layer 2121'.

[0120] In the above steps, a dry / wet etching process can be used to remove the second sacrificial portion 261 within the second part GLS2 of the isolation trench GLS and to remove the designated sacrificial portion 240' located within the array region C. Here, Figure 12 China has not formed Figure 3B The isolation structure 235 and the contact portion 240 are shown.

[0121] S560: See also Figure 8 , Figure 12 and Figure 13 A gate layer 212 is formed in the first cavity 250 and the second cavity 260 via the first portion GLS1 and the second portion GLS2 of the isolation trench GLS, and combined with Figure 6 And a contact portion 240 is formed within the contact hole 241.

[0122] In the above steps, the isolation trench (GLS) can be used as the deposition channel, and any thin film deposition process of CVD, PVD, or ALD can be used to form a gate layer 212 in the first cavity 250 and the second cavity 260, and a contact portion 240 is formed in the contact hole 241. At this time, a stacked layer 210 is formed, which includes an alternately stacked first dielectric layer 211 and a gate layer 212.

[0123] In the case where the gate layer 212 includes a conductive layer 2122, a metal compound layer 2123, and a second dielectric layer 2124, the above-mentioned S560 specifically includes the formation of the second dielectric layer 2124, the metal compound layer 2123, and the conductive layer 2122 in the first cavity 250, the second cavity 260, and the contact hole 241 via the first part GLS1 and the second part GLS2 of the isolation trench GLS.

[0124] Here, the portions of the second dielectric layer 2124, the metal compound layer 2123, and the conductive layer 2122 located within the first cavity 250 and the second cavity 260 form a gate layer 212, and the portions of the second dielectric layer 2124, the metal compound layer 2123, and the conductive layer 2122 located within the contact hole 241 form a contact portion 240.

[0125] In some embodiments, see Figure 25 The above S530 includes S531 to S532.

[0126] S531: See also Figure 9 , Figure 10A and Figure 10B A third filling layer 2610 is formed on the sidewalls and bottomwalls of the second cavity 260.

[0127] In the above steps, any one of the thin film deposition processes, CVD, PVD, or ALD, can be used to form the third filler layer 2610, which covers the sidewalls and bottom wall of the contact hole 241. Here, by controlling the deposition time, the deposition can be stopped after covering the sidewalls and bottom wall of the second cavity 260 through the opening of the second cavity 260 (i.e., the opening on the upper side of the second part GLS2 of the isolation tank GLS), thereby forming the third filler layer 2610.

[0128] S532: See also Figure 9 , Figure 10A and Figure 10B A fourth filling layer 2620 is formed at the opening of the second cavity 260 to seal the opening of the second cavity 260.

[0129] In the above steps, any one of the thin film deposition processes of CVD, PVD, and ALD can be used to form the fourth filling layer 2620. The fourth filling layer 2620 seals the opening of the second cavity 260. The third filling layer 2610 is connected to the fourth filling layer 2620 to form the second sacrificial part 261.

[0130] Here, the fourth filler layer 2620 seals the opening of the contact hole 241 to prevent damage to the second sacrificial part 261 during the subsequent removal of the first sacrificial part 251 and the gate sacrificial layer 212' located in the array region C, which would cause the gate sacrificial layer 212' located in the connection region S to be removed, thereby resulting in insufficient support inside the semiconductor structure 200 and collapse.

[0131] Here, by controlling the rate of material deposition in S320, the rate of material deposition in S532 can be greater than the rate of material deposition in S531, that is, the deposition rate of forming the third filling layer 2610 is less than the deposition rate of forming the fourth filling layer 2620, thereby forming the fourth filling layer 2620 that seals the opening of the second cavity 260.

[0132] It should be noted that the material of the third filler layer 2610 can be the same as or different from the material of the fourth filler layer 2620. Here, in the case where the material of the third filler layer 2610 is different from the material of the fourth filler layer 2620, such as... Figure 10B As shown, the fourth filler layer 2620 also covers the inner wall of the third filler layer 2610.

[0133] In some embodiments, see Figure 26 The above S510 includes S511 to S513.

[0134] S511: See also Figure 8 Sacrificial material is filled in the first part GLS1 and the second part GLS2 of the isolation tank GLS.

[0135] In the above steps, any of the thin film deposition processes of CVD, PVD, and ALD can be used to fill the first part GLS1 and the second part GLS2 of the isolation tank GLS with sacrificial material.

[0136] S512: See also Figure 9 This forms the first mask layer 270.

[0137] In the above steps, the first mask layer 270 has a first opening 271, which exposes the sacrificial material in the second portion of GLS2. The first mask layer 270 can be formed on the upper side of the second mask layer 280 using any of the following thin film deposition processes: CVD, PVD, and ALD. Alternatively, the first mask layer 270 can be formed using a thin film deposition and etching process.

[0138] It should be noted that the material of the first mask layer 270 is different from the materials of the first dielectric layer 211 and the first sacrificial portion 251. The material of the first mask layer 270 includes at least one of silicon oxide, silicon oxynitride, doped silicon oxide, and silicon nitride, and this disclosure is not limited thereto.

[0139] S513: See also Figure 9 The sacrificial material located in the second part GLS2 is etched through the first opening 271.

[0140] In the above steps, a dry / wet etching process can be used to remove the sacrificial material located in the second part GLS2. The sacrificial material retained in the first part GLS1 serves as the first sacrificial portion 251.

[0141] Based on this, refer to Figure 27 The above S540 includes S541 to S543.

[0142] S541: See also Figure 10A and Figure 11 The first mask layer 270 is etched to form the second opening 272.

[0143] In the above steps, a dry / wet etching process can be used to etch the first mask layer 270 to form the second opening 272. The second opening 272 exposes the first sacrificial portion 251.

[0144] S542: See also Figure 11 The first sacrificial part 251 is removed through the second opening 272.

[0145] In the above steps, a dry / wet etching process can be used to remove the first sacrificial part 251, so that the first part GLS1 of the isolation trench GLS leaves a gap.

[0146] S543: As Figure 10A and Figure 11 As shown, the gate sacrificial layer 212' located in the array region C is removed via the first part GLS1 to form the first cavity 250.

[0147] In the above steps, the first portion GLS1 of the isolation trench GLS is used as the etchant channel, and isotropic etching is used to remove the gate sacrificial layer 212' located in the array region C, forming the first cavity 250. Here, the first cavity 250 includes the first portion GLS1 of the isolation trench GLS.

[0148] After S550, the top opening of the contact hole 241 is covered by the first mask layer 270, and the portion of the first mask layer 270 covering the top opening of the contact hole 241 forms the top wall of the contact hole 241. At this time, in S560, a contact portion 240 is formed within the contact hole 241. (See reference...) Figure 13 This includes: depositing a first target material in the contact hole 241 via the connection between the second cavity 260 and the contact hole 241.

[0149] In the above steps, the first target material is deposited on the sidewall and bottom wall of the contact hole 241 to form a first sub-contact portion 2401, and the first target material is deposited on the top wall of the contact hole 241 to form a second sub-contact portion 2402. The contact portion 240 includes the first sub-contact portion 2401 and the second sub-contact portion 2402, and the first sub-contact portion 2401 and the second sub-contact portion 2402 form a third cavity 242.

[0150] It should be noted that the first target material may include the material of the conductive layer 2122, the material of the metal compound layer 2123, and the material of the second dielectric layer 2124. Specifically, when the first target material includes the materials of the conductive layer 2122, the metal compound layer 2123, and the second dielectric layer 2124, the materials of the conductive layer 2122, the metal compound layer 2123, and the second dielectric layer 2124 are deposited sequentially.

[0151] In some embodiments, see Figure 28 The above S400 includes S410~S420.

[0152] S410: See also Figure 8 This forms a second mask layer 280.

[0153] In the above steps, the second mask layer 280 can be formed sequentially through coating, exposure, and development processes. The second mask layer 280 has a plurality of third openings 281, which expose a portion of the surface of the initial stacked layer 210'.

[0154] S420: See also Figure 8The initial stacked layer 210' is etched through multiple third openings 281 to form the isolation trench GLS.

[0155] In the above steps, the initial stacked layer 210' can be etched using a dry / wet etching process to form the isolation trench GLS. At this time, after S550, the top opening of the contact hole 241 is also covered by the second mask layer 280, and the top wall of the contact hole 241 also includes the portion of the second mask layer 280 that covers the top opening of the contact hole 241.

[0156] In some embodiments, see Figure 29 Before S200, the above preparation method also includes S110.

[0157] S110: See also Figure 4 This forms a channel structure 220 that penetrates the initial stacked layer 210'.

[0158] In the above steps, a channel hole penetrating the initial stacked layer 210' can be formed by a dry / wet etching process, and then a channel structure 220 is formed within the channel hole. The channel structure 220 includes a storage function layer 221 and a channel layer 222.

[0159] It should be noted that the storage functional layer 221 includes a barrier layer, a charge trapping layer, and a tunneling layer. The materials of the barrier layer, charge trapping layer, tunneling layer, and channel layer 222 can be silicon oxide, silicon nitride, silicon oxide, and polysilicon, respectively, to form a "SONP" structure.

[0160] Based on this, after S500, see [link / reference]. Figure 29 The above preparation method also includes S600.

[0161] S600: See also Figure 15 This forms the first connecting part 223 and the second connecting part 230.

[0162] In the above steps, the first connecting part 223 is electrically connected to the channel structure 220, and the second connecting part 230 is electrically connected to the contact part 240.

[0163] In some embodiments, see Figure 30 S600 includes S610 to S630.

[0164] S610: As Figure 14 As shown, the first protective layer 282 is formed.

[0165] In the above steps, the first protective layer 282 covers the channel structure 220 and the contact portion 240. The first protective layer 282 can be formed on the upper side of the first mask layer 270 using any of the thin film deposition processes selected from CVD, PVD, and ALD.

[0166] It should be noted that the material of the first protective layer 282 includes insulating materials, which include at least one of silicon oxide, silicon nitride, doped silicon oxide, organosilicon glass, dielectric metal oxide (e.g., aluminum oxide, hafnium dioxide, etc.) and their silicates, and organic insulating materials, and this disclosure is not limited thereto.

[0167] S620: such as Figure 14 As shown, a fourth opening 283 and a fifth opening 284 are formed that penetrate the first protective layer 282.

[0168] In the above steps, the first protective layer 282 can be formed sequentially through coating, exposure, and development processes. The fourth opening 283 exposes the channel structure 220, and the fifth opening 284 exposes the contact portion 240.

[0169] S630: A first connecting portion 223 is formed within the fourth opening 283, and a second connecting portion 230 is formed at least within the fifth opening 284.

[0170] In some embodiments, see 13 and Figure 14 The aforementioned fifth opening 284 also penetrates the top wall of the contact hole 241 and the second sub-contact portion 2402 of the contact portion 240, and along a set direction, the size of the fifth opening 284 is smaller than the size of the second sub-contact portion 2402. Here, the set direction is at least one direction parallel to the plane where the stacked layer 210 is located, for example, the set direction is the first direction X.

[0171] Based on this, a second connecting portion 230 is formed in S630, at least within the fifth opening 284, such as... Figure 14 and Figure 15 As shown, it may include depositing a second target material into the third cavity 242 of the contact portion 240 via the fifth opening 284 to form a second connection portion 230.

[0172] In the above steps, the second connecting portion 230 includes a main body portion that fills the third cavity 242 and an extension portion that fills the fifth opening 284.

[0173] It should be noted that the second target material may include conductive materials and also metallic compound materials that act as adhesives. Specifically, when the second target material includes both conductive and metallic compound materials, the conductive material and the metallic compound material are deposited sequentially.

[0174] In other embodiments, a fifth opening 284 penetrating the first protective layer 282 is formed in S620, see reference. Figure 13 and Figure 16This includes removing the first protective layer 282 located above the contact portion 240, the top wall of the contact hole 241, and the second sub-contact portion 2402 of the contact portion 240 to form a fifth opening 284.

[0175] In the above steps, the fifth opening 284 exposes the first sub-contact 2401 of the contact portion 240.

[0176] Based on this, refer to Figure 31 The second connecting portion 230 formed in S630 at least within the fifth opening 284 may include S632 to S633.

[0177] S632: See also Figure 16 and Figure 17 A second target material is deposited into the third cavity 242 of the contact portion 240 through the fifth opening 284 to form a conductive filling layer 233.

[0178] In the above steps, the conductive filling layer 233 covers the sidewalls of the first sub-contact portion 2401 and the fifth opening 284, and the conductive filling layer 233 has gaps. The second target material can be referred to above, and will not be repeated here.

[0179] S633: See also Figure 17 A protective filling layer 234 is formed within the gap.

[0180] At this time, the second connection portion 230 includes a conductive filling layer 233 and a protective filling layer 234.

[0181] In some other embodiments, such as Figure 13 and Figure 20 As shown, the fifth opening 284 also penetrates the top wall of the contact hole 241, exposing the second sub-contact portion 2402 of the contact portion 240.

[0182] Based on this, a second connecting portion 230 is formed in S630, at least within the fifth opening 284, such as... Figure 20 and Figure 21 As shown, it may include depositing a second target material into the fifth opening 284 to form a second connection 230.

[0183] The second target material mentioned above can be referred to in the above text, and will not be repeated here.

[0184] In some other embodiments, see [reference] Figure 32 S630 includes S635 to S638.

[0185] S635: See also Figure 13 and Figure 18 Remove part of the stacked layer 210 to expose the first sub-contact 2401 of the contact portion 240 and the channel structure 220.

[0186] In the above steps, chemical mechanical planarization (CMP) and / or dry / wet etching processes can be used to etch the stacked layer 210 so that the first sub-contact 2401 of the contact portion 240 and the channel structure 220 are exposed.

[0187] S636: See also Figure 18 This forms a second protective layer 285.

[0188] In the above steps, the second protective layer 285 can be formed on the upper side of the stacked layer 210 after step S635 using any of the thin film deposition processes of CVD, PVD, and ALD. The second protective layer 285 fills the third cavity 242 of the contact portion 240 and covers the channel structure 220.

[0189] It should be noted that the material of the second protective layer 285 includes insulating materials, which include at least one of silicon oxide, silicon nitride, doped silicon oxide, organosilicon glass, dielectric metal oxide (e.g., aluminum oxide, hafnium dioxide, etc.) and their silicates, and organic insulating materials, and this disclosure is not limited thereto.

[0190] S637: See also Figure 18 This forms a fourth opening 283 and a fifth opening 284 that penetrate the second protective layer 285.

[0191] In the above steps, the fourth opening 283 exposes the channel structure 220, and the fifth opening 284 exposes the first sub-contact portion 2401.

[0192] S638: See also Figure 18 and Figure 19 A first connecting portion 223 is formed in the fourth opening 283, and a second connecting portion 230 is formed in the fifth opening 284.

[0193] In some embodiments, see Figure 33 The above S200 includes S210 to S240.

[0194] S210: See also Figure 5 The initial stacked layer 210' is etched to the first dielectric layer 211, which is adjacent to and above the target gate sacrificial layer 2121', to form the initial contact hole 241'.

[0195] In the above steps, the initial stacked layer 210 can be etched using a dry / wet etching process to form the initial contact hole 241'. Exemplarily, an anisotropic etching process (any one of dry etching methods such as ion milling, plasma etching, reactive ion etching, and laser ablation) is used to form the initial contact hole 241'. Here, Figure 5 China has not formed Figure 3A The isolation slot GLS and the set sacrifice unit 240' are shown.

[0196] S220: See also Figure 5 and Figure 6 A third dielectric layer 243 is formed within the initial contact hole 241'.

[0197] In the above steps, the third dielectric layer 243 covers the sidewalls and bottom wall of the initial contact hole 241'. The material of the third dielectric layer 243 may include an insulating material, which may include at least one of silicon oxide, silicon nitride, doped silicon oxide, organosilicon glass, dielectric metal oxides (e.g., alumina, hafnium dioxide, etc.) and their silicates, and organic insulating materials.

[0198] S230: See also Figure 5 and Figure 6 The third dielectric layer 243 covering the bottom wall of the initial contact hole 241' and the first dielectric layer 211 below it are etched to expose the target gate sacrificial layer 2121'.

[0199] In the above steps, the material of the third dielectric layer 243 can be the same as that of the first dielectric layer 211. In this way, the third dielectric layer 243 covering the bottom wall of the initial contact hole 241' and the first dielectric layer 211 below it can be removed by the same etchant and a single etching process.

[0200] S240: As Figure 6 As shown, the exposed portion of the target gate sacrificial layer 2121' and the portion surrounding the exposed portion are etched to form a contact hole 241.

[0201] In the above steps, the sacrificial layer 212' exposed by the contact hole 241 can be etched by a dry / wet etching process, so that the target sacrificial layer 2121' is recessed relative to the first dielectric layer 211 to form the contact hole 241.

[0202] Some embodiments of this disclosure also provide a semiconductor structure 200, see reference. Figure 3B and Figure 15 It includes a stacked layer 210, an isolation structure 235, and a contact portion 240.

[0203] It should be noted that, as Figure 1As shown, the semiconductor structure 200 can be a memory cell string array 300, or it can be a device after the memory cell string array 300 is bound to the peripheral device 100. The embodiments disclosed herein are not specifically limited.

[0204] The stacked layer 210 includes a plurality of alternating first dielectric layers 211 and a plurality of gate layers 212, and the stacked layer 210 has an array region C and a connection region S. The gate layer 212 extends from the array region C to the connection region S.

[0205] like Figure 3B and Figure 15 As shown, the isolation structure 235 extends through the stack layer 210 and divides the stack layer 210 into at least one storage block B.

[0206] Among them, see Figure 13 The isolation structure 235 may include an insulating layer 2351 to prevent short circuits between different gate layers 212 and to prevent oxidation of the gate layers 212. The isolation structure 235 may also include an intermediate fill layer 2352 to provide mechanical support. Here, the insulating layer 2351 is located between the intermediate fill layer 2352 and the stacked layer 210.

[0207] It should be noted that the material of the intermediate filling layer 2352 can be a conductive material or an insulating material. When the source signal is led out through the isolation structure 235, the material of the intermediate filling layer 2352 can be a conductive material, for example, the material of the intermediate filling layer 2352 includes polysilicon, but this disclosure is not limited thereto.

[0208] like Figure 13 As shown, the contact portion 240 is located in the connection area S. The contact portion 240 is formed by the upper surface of the stacked layer 210 ( Figure 13 The contact portion 240 extends from the upper side of the stacked layer 210 to the target gate layer 2121 and is electrically connected to the target gate layer 2121. The contact portion 240 and the gate layer 212 are integrally formed. That is, the contact portion 240 and the gate layer 212 are continuous film layers, and there is no metal compound layer 2123 and a second dielectric layer 2124 between them.

[0209] Among them, see Figure 13 The aforementioned contact portion 240 may include a first sub-contact portion 2401, which has a cylindrical structure. The axis of the first sub-contact portion 2401 is perpendicular to the plane of the stacked layer 210, and the bottom end of the first sub-contact portion 2401 is electrically connected to the target gate layer 2121.

[0210] In some embodiments, such as Figure 13 and Figure 19As shown, the semiconductor structure 200 further includes a second protective layer 285 and a second connection portion 230. The second protective layer 285 is disposed on the stacked layer 210 and fills the first sub-contact portion 2401; the second connection portion 230 penetrates the second protective layer 285 and is electrically connected to the top end of the first sub-contact portion 2401.

[0211] In other embodiments, such as Figure 13 and Figure 17 As shown, the semiconductor structure 200 may include a second connection portion 230, a portion of which extends into the first sub-contact portion 2401 and is in electrical contact with the first sub-contact portion 2401.

[0212] Among them, see Figure 17 The semiconductor structure 200 includes a first mask layer 270, a second mask layer 280, a first protective layer 282, and a second connection portion 230. The second mask layer 280 is disposed on the stacked layer 210, the first mask layer 270 is disposed on the side of the second mask layer 280 away from the stacked layer 210, and the first protective layer 282 is disposed on the side of the first mask layer 270 away from the stacked layer 210.

[0213] For example, see Figure 17 The second connection portion 230 includes a conductive filling layer 233 and a protective filling layer 234. The conductive filling layer 233 penetrates the first protective layer 282, the first mask layer 270 and the second mask layer 280, and covers the inner sidewall and top wall of the first sub-contact portion 2401. The conductive filling layer 233 has gaps, and the protective filling layer 233 fills the gaps.

[0214] For example, see Figure 13 and Figure 15 The aforementioned contact portion 240 may further include a second sub-contact portion 2402, which is located on the side of the first sub-contact portion 2401 away from the target gate layer 2121 and is connected to the first sub-contact portion 2401. The second connecting portion 230 includes a main portion and an extension portion. The main portion is located within the first sub-contact portion 2401, and the extension portion penetrates the first protective layer 282, the first mask layer 270, the second mask layer 280, and the second sub-contact portion 2402, and is connected to the main portion. Furthermore, the main portion may have an air gap.

[0215] It should be noted that, along the set direction, the extension is smaller than the size of the second sub-contact portion 2402. The set direction is at least one direction parallel to the plane containing the stacked layer 210, for example, the set direction is the first direction X.

[0216] In some other embodiments, see [reference] Figure 13 and Figure 21The semiconductor structure 200 may include a second connection portion 230, a portion of which extends into the second sub-contact portion 2402 and is in electrical contact with the second sub-contact portion 2402.

[0217] Among them, see Figure 21 The semiconductor structure 200 includes a first mask layer 270, a second mask layer 280, a first protective layer 282, and a second connection portion 230. The second mask layer 280 is disposed on the stacked layer 210, the first mask layer 270 is disposed on the side of the second mask layer 280 away from the stacked layer 210, and the first protective layer 282 is disposed on the side of the first mask layer 270 away from the stacked layer 210.

[0218] Here, the second connecting portion 230 penetrates the first protective layer 282, the first mask layer 270 and the second mask layer 280, and the second connecting portion 230 is electrically connected to the second sub-contact portion 2402.

[0219] It should be noted that, along the set direction, the size of the second connecting portion 230 can be smaller than the size of the second sub-contact portion 2402. Here, the set direction is at least one direction parallel to the plane where the stacked layer 210 is located, for example, the set direction is the first direction X.

[0220] In some embodiments, such as Figure 3B and Figure 13 As shown, the semiconductor structure 200 may also include a virtual channel structure 224.

[0221] The virtual channel structure 224 extends through the stacked layer 210 and is configured to provide mechanical support for the semiconductor structure 200.

[0222] In addition, the dummy channel structure 224 may include an insulating material, such as one or more combinations of silicon oxide, silicon nitride, and high dielectric constant insulating materials, or other suitable materials.

[0223] In some embodiments, the aforementioned dummy channel structure 224 may be formed synchronously with the channel structure 220, and its structure is the same as that of the channel structure 220.

[0224] Figure 34 This is a block diagram of a storage system according to some embodiments. Figure 35 This is a block diagram of a storage system according to some other embodiments.

[0225] Please see Figure 34 and Figure 35Some embodiments of this disclosure also provide a storage system 1000. The storage system 1000 includes a controller 20 and a semiconductor structure 200 as described in some of the embodiments above, the controller 20 being coupled to the semiconductor structure 200 to control the semiconductor structure 200 to store data.

[0226] The storage system 1000 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an Embedded Multi Media Card (eMMC) package). In other words, the storage system 1000 can be applied to and packaged into different types of electronic products, such as mobile phones (e.g., cell phones), desktop computers, tablets, laptops, servers, in-vehicle devices, game consoles, printers, positioning devices, wearable devices, smart sensors, power banks, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic device containing storage.

[0227] In some embodiments, see Figure 34 The storage system 1000 includes a controller 20 and a semiconductor structure 200, and the storage system 1000 can be integrated into a three-dimensional memory card.

[0228] Among them, 3D memory cards include any one of the following: PC card (PCMCIA, the International Association for Personal Computer 3D Memory Cards), Compact Flash (CF) card, Smart Media (SM) card, 3D memory, Multimedia Card (MMC), Secure Digital Memory Card (SD) card, and UFS.

[0229] In other embodiments, see Figure 35 The storage system 1000 includes a controller 20 and multiple semiconductor structures 200, and the storage system 1000 is integrated into a solid state drive (SSD).

[0230] In some embodiments of the storage system 1000, the controller 20 is configured to operate in a low duty cycle environment, such as an SD card, CF card, Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, and mobile phones.

[0231] In other embodiments, controller 20 is configured to operate in a high duty cycle environment in an SSD or eMMC, which is used as data storage for mobile devices such as smartphones, tablets, and laptops, as well as enterprise storage arrays.

[0232] In some embodiments, controller 20 may be configured to manage data stored in semiconductor structure 200 and to communicate with external devices (e.g., a host). In some embodiments, controller 20 may also be configured to control operations of semiconductor structure 200, such as read, erase, and program operations. In some embodiments, controller 20 may also be configured to manage various functions relating to data stored or to be stored in semiconductor structure 200, including at least one of bad block management, garbage collection, logic-to-physical address translation, and wear leveling. In some embodiments, controller 20 is also configured to process error correction codes relating to data read from or written to semiconductor structure 200.

[0233] Of course, controller 20 can also perform any other suitable functions, such as formatting semiconductor structure 200; for example, controller 20 can communicate with external devices (e.g., hosts) through at least one of various interface protocols.

[0234] It should be noted that interface protocols include USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, and PCI High Speed ​​(PCI) protocol. E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronic Device (IDE) protocol, Firewire protocol, or at least one of these protocols.

[0235] Some embodiments of this disclosure also provide an electronic device. The electronic device can be any of the following: mobile phone, desktop computer, tablet computer, laptop computer, server, in-vehicle equipment, wearable device (e.g., smartwatch, smart bracelet, smart glasses, etc.), power bank, game console, digital multimedia player, etc.

[0236] The electronic device may include the storage system 1000 described above, and may also include at least one of a central processing unit (CPU) and a cache.

[0237] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: An initial stack layer is formed, the initial stack layer comprising a plurality of gate sacrificial layers and a plurality of first dielectric layers stacked alternately; The initial stacked layer has an array region and a connection region; A contact hole is formed, the contact hole extending into the target gate sacrificial layer; The contact hole is located in the connection area; the contact hole includes a first part and a second part that are connected; the first part is disposed in the same layer as the target gate sacrificial layer; the second part extends away from the target gate sacrificial layer and penetrates the initial stack layer; A sacrificial portion is formed within the contact hole; An isolation trench is formed, which penetrates the initial stack layer and divides the initial stack layer into at least one initial storage block; The gate sacrificial layer located in the array region and a portion of the gate sacrificial layer located in the connection region are replaced with gate layers via the isolation trench to form a stacked layer, and the designated sacrificial portion is replaced with a contact portion; wherein, one gate layer and one gate sacrificial layer are disposed on the same layer, at least one contact portion penetrates one or more gate sacrificial layers, and the contact portion is electrically connected to the target gate layer that replaces the target gate sacrificial layer.

2. The preparation method according to claim 1, characterized in that, The method of forming a set sacrificial portion within the contact hole includes: A first filling layer is formed on the sidewall and bottom wall of the contact hole; A second filling layer is formed at the opening of the contact hole, and the second filling layer seals the opening of the contact hole; the first filling layer and the second filling layer are connected to form the set sacrificial part.

3. The preparation method according to claim 2, characterized in that, The deposition rate for forming the first filling layer is less than the deposition rate for forming the second filling layer.

4. The preparation method according to claim 1, characterized in that, The isolation trench includes a first portion passing through the array region and a second portion passing through the connection region; The process of replacing the gate sacrificial layer located in the array region and a portion of the gate sacrificial layer located in the connection region with gate layers via the isolation trench to form a stacked layer, and replacing the designated sacrificial portion with a contact portion, includes: A first sacrificial portion is formed within the first part of the isolation groove; A portion of the gate sacrificial layer located within the connection area is removed via the second part of the isolation groove, forming a second cavity; the second cavity exposes the portion of the designated sacrificial portion located within the target gate sacrificial layer. A second sacrificial portion is formed within the second cavity; The first sacrificial portion is removed, and the gate sacrificial layer located in the array region is removed via the first portion of the isolation groove to form a first cavity; Remove the second sacrificial portion and the set sacrificial portion, so that the second cavity communicates with the contact hole at the location of the target gate sacrificial layer; A gate layer is formed in the first cavity and the second cavity via the first and second portions of the isolation trench, forming a stacked layer, and a contact portion is formed in the contact hole.

5. The preparation method according to claim 4, characterized in that, The formation of the second sacrificial portion within the second cavity includes: A third filling layer is formed on the sidewalls and bottom wall of the second cavity; A fourth filling layer is formed at the opening of the second cavity to seal the opening of the second cavity; the third filling layer is connected to the fourth filling layer to form the second sacrificial part.

6. The preparation method according to claim 5, characterized in that, The deposition rate for forming the third filling layer is less than the deposition rate for forming the fourth filling layer.

7. The preparation method according to claim 4, characterized in that, The material of the second sacrificial part is the same as the material of the set sacrificial part.

8. The preparation method according to claim 4, characterized in that, The formation of a first sacrificial portion within the first part of the isolation groove includes: Sacrificial material is filled into the first and second portions of the isolation groove; A first mask layer is formed, the first mask layer having a first opening that exposes the sacrificial material in the second portion, and the top opening of the contact hole is covered by the first mask layer; the portion of the first mask layer covering the top opening of the contact hole forms the top wall of the contact hole; The sacrificial material located in the second portion is etched through the first opening; the sacrificial material retained in the first portion serves as the first sacrificial part.

9. The preparation method according to claim 8, characterized in that, The step of removing the first sacrificial portion and removing the gate sacrificial layer located in the array region via the first portion of the isolation trench to form a first cavity includes: The first mask layer is etched to form a second opening, which exposes the first sacrificial portion. The first sacrificial part is removed through the second opening; The first cavity is formed by removing the gate sacrificial layer located in the array region via the first part.

10. The preparation method according to claim 8, characterized in that, The formation of a contact portion within the contact hole includes: A first target material is deposited in the contact hole through the communication between the second cavity and the contact hole. The first target material is deposited on the sidewall and bottom wall of the contact hole to form a first sub-contact portion. The first target material is deposited on the top wall of the contact hole to form a second sub-contact portion. The contact portion includes a first sub-contact portion and a second sub-contact portion, which together form a third cavity.

11. The preparation method according to claim 10, characterized in that, The formation of the isolation trench includes: A second mask layer is formed, the second mask layer having a plurality of third openings that expose a portion of the surface of the initial stacked layer; the top opening of the contact hole is also covered by the second mask layer, and the top wall of the contact hole also includes a portion of the second mask layer that covers the top opening of the contact hole; The initial stacked layer is etched through the plurality of third openings to form isolation trenches.

12. The preparation method according to any one of claims 1 to 11, characterized in that, The formation of the contact hole includes: The initial stacked layer is etched down to a first dielectric layer adjacent to and above the target gate sacrificial layer to form an initial contact hole; A third dielectric layer is formed within the initial contact hole, the third dielectric layer covering the sidewalls and bottom wall of the initial contact hole; The third dielectric layer covering the bottom wall of the initial contact hole and the first dielectric layer below it are etched to expose the target gate sacrificial layer; The exposed portion of the target gate sacrificial layer and the portion surrounding the exposed portion are etched to form the contact hole.

13. The preparation method according to any one of claims 1 to 11, characterized in that, Prior to forming the contact hole, the preparation method further includes: Forming a channel structure that penetrates the initial stacked layers; After replacing the gate sacrificial layer located in the array region and a portion of the gate sacrificial layer located in the connection region with gate layers via the isolation trench to form a stacked layer, and replacing the designated sacrificial portion with a contact portion, the fabrication method further includes: A first connecting portion and a second connecting portion are formed, wherein the first connecting portion is electrically connected to the channel structure and the second connecting portion is electrically connected to the contact portion.

14. The preparation method according to claim 13, characterized in that, The formation of the first connecting portion and the second connecting portion includes: A first protective layer is formed, which covers the channel structure and the contact portion; A fourth opening and a fifth opening are formed that penetrate the first protective layer, the fourth opening exposing the channel structure and the fifth opening exposing the contact portion; A first connecting portion is formed within the fourth opening, and a second connecting portion is formed at least within the fifth opening.

15. The preparation method according to claim 14, characterized in that, The contact portion includes a first sub-contact portion and a second sub-contact portion, which together form a third cavity. The fifth opening also penetrates the top wall of the contact hole and the second sub-contact portion of the contact portion. Along a predetermined direction, the size of the fifth opening is smaller than the size of the second sub-contact portion. The predetermined direction is at least one direction parallel to the plane of the stacked layer. The formation of the second connecting portion, at least within the fifth opening, includes: A second target material is deposited into the third cavity of the contact portion through the fifth opening to form a second connection portion; the second connection portion includes a main body portion filled in the third cavity and an extension portion filled in the fifth opening.

16. The preparation method according to claim 14, characterized in that, Forming the fifth opening includes: The first protective layer above the contact portion, the top wall of the contact hole, and the second sub-contact portion of the contact portion are removed to form the fifth opening; the fifth opening exposes the first sub-contact portion of the contact portion. The formation of the second connecting portion, at least within the fifth opening, includes: A second target material is deposited into the third cavity of the contact portion through the fifth opening to form a conductive filling layer; the conductive filling layer covers the sidewall of the first sub-contact portion and the sidewall of the fifth opening, and the conductive filling layer has gaps; A protective filling layer is formed within the gap; the second connection portion includes the conductive filling layer and the protective filling layer.

17. The preparation method according to claim 14, characterized in that, The fifth opening also penetrates the top wall of the contact hole, exposing the second sub-contact of the contact portion; The formation of the second connecting portion, at least within the fifth opening, includes: A second target material is deposited into the fifth opening to form a second connection.

18. The preparation method according to claim 13, characterized in that, The formation of the first connecting portion and the second connecting portion includes: Remove a portion of the stacked layers to expose the first sub-contact of the contact portion and the channel structure; A second protective layer is formed, which fills the third cavity of the contact portion and covers the channel structure; A fourth opening and a fifth opening are formed that penetrate the second protective layer, the fourth opening exposing the channel structure and the fifth opening exposing the first sub-contact portion; A first connecting portion is formed in the fourth opening, and a second connecting portion is formed in the fifth opening.

19. The preparation method according to claim 4, characterized in that, The process of forming a gate layer, a stacked layer, and a contact portion within the contact hole via the first and second portions of the isolation trench includes: A second dielectric layer, a metal compound layer, and a conductive layer are sequentially formed in the first cavity, the second cavity, and the contact hole via the first and second portions of the isolation groove. In this configuration, the portions of the second dielectric layer, the metal compound layer, and the conductive layer located within the first cavity and the second cavity form a gate layer, and the portions of the second dielectric layer, the metal compound layer, and the conductive layer located within the contact hole form a contact portion.

20. A semiconductor structure, characterized in that, include: The stacked layer includes multiple gate layers and multiple first dielectric layers that are alternately stacked; The stacked layer has an array region and a connection region; the stacked layer also includes a plurality of gate sacrificial layers, one of the gate sacrificial layers being disposed on the same layer as one of the gate layers, and the gate sacrificial layer being located in the connection region; An isolation structure extends through the stacked layer and divides the stacked layer into at least one storage block; A contact portion is located in the connection region; at least one of the contact portions penetrates one or more of the gate sacrificial layers, the contact portion extends from the upper surface of the stacked layers to the target gate layer, and is electrically connected to the target gate layer; the contact portion and the gate layer are integrally formed.

21. The semiconductor structure according to claim 20, characterized in that, The contact portion includes a first sub-contact portion, which has a cylindrical structure. The axis of the first sub-contact portion is perpendicular to the plane of the stacked layer, and the bottom end of the first sub-contact portion is electrically connected to the target gate layer.

22. The semiconductor structure according to claim 21, characterized in that, Also includes: The second connecting portion extends into the first sub-contact portion and makes electrical contact with the first sub-contact portion.

23. The semiconductor structure according to claim 22, characterized in that, The contact portion further includes a second sub-contact portion, which is located on the side of the first sub-contact portion away from the target gate layer and is connected to the first sub-contact portion; The semiconductor structure also includes: A second mask layer is disposed on the stacked layers; A first mask layer is disposed on the side of the second mask layer away from the stacked layers; A first protective layer is disposed on the side of the first mask layer away from the stacked layers; The second connecting portion includes a main body and an extension portion. The main body is located within the first sub-contact portion, and the extension portion penetrates the first protective layer, the first mask layer, the second mask layer, and the second sub-contact portion, and is connected to the main body.

24. The semiconductor structure according to claim 23, characterized in that, Along a set direction, the extension is smaller than the size of the second sub-contact portion; the set direction is at least one direction parallel to the plane of the stacked layer; and / or, the main body portion has an air gap.

25. The semiconductor structure according to claim 22, characterized in that, Also includes: A second mask layer is disposed on the stacked layers; A first mask layer is disposed on the side of the second mask layer away from the stacked layers; A first protective layer is disposed on the side of the first mask layer away from the stacked layers; The second connection portion includes a conductive filling layer and a protective filling layer. The conductive filling layer penetrates the first protective layer, the first mask layer, and the second mask layer, and covers the inner sidewall and top wall of the first sub-contact portion. The conductive filling layer has gaps, and the protective filling layer fills the gaps.

26. The semiconductor structure according to claim 21, characterized in that, The contact portion further includes a second sub-contact portion, which is located on the side of the first sub-contact portion away from the target gate layer and is connected to the first sub-contact portion; The semiconductor structure also includes: A second mask layer is disposed on the stacked layers; A first mask layer is disposed on the side of the second mask layer away from the stacked layers; A first protective layer is disposed on the side of the first mask layer away from the stacked layers; The second connecting portion penetrates the first protective layer, the first mask layer, and the second mask layer, and is electrically connected to the second sub-contact portion.

27. The semiconductor structure according to claim 26, characterized in that, Along a predetermined direction, the size of the second connecting portion is smaller than the size of the second sub-contact portion; the predetermined direction is at least one direction parallel to the plane of the stacked layer.

28. The semiconductor structure according to claim 21, characterized in that, Also includes: A second protective layer is disposed on the stacked layer and fills the first sub-contact portion; The second connecting part penetrates the second protective layer and is electrically connected to the top end of the first sub-contact part.

29. A storage system, characterized in that, include: A semiconductor structure, wherein the semiconductor structure is the semiconductor structure as described in any one of claims 20 to 28; A controller is coupled to the semiconductor structure to control the semiconductor structure to store data.

30. An electronic device, characterized in that, Including the storage system as described in claim 29.

Images