Three-dimensional memory, methods of making the same, and memory systems having the same

Abstract

The application provides a three-dimensional memory, a manufacturing method thereof, and a storage system with the same. The manufacturing method comprises the following steps: providing a substrate, a stack on the substrate comprises a plurality of layers of sacrificial layers and a plurality of layers of isolation layers which are alternately stacked in a direction away from the substrate, at least one end of the stack has a step structure, a side of the step structure away from the substrate has a plurality of first step surfaces, each layer of the sacrificial layers has a first surface away from the substrate, and each first step surface is located in the first surface in a one-to-one correspondence; forming a channel array in the stack except the step structure and penetrating to the substrate, and forming a pseudo channel hole penetrating to the substrate through each first step surface; forming a support layer at the bottom of the pseudo channel hole, an area of the pseudo channel hole except the support layer constitutes a contact hole, and each contact hole penetrates one layer of the sacrificial layers; replacing the sacrificial layers with a control gate structure, and forming a conductive channel in the contact hole, so that the control gate structure is electrically connected with the conductive channel. The above method reduces the process difficulty.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a three-dimensional memory, a method for manufacturing the same, and a storage system having the same. Background Technology

[0002] With the increasing demand for integration and storage capacity, 3D NAND flash memory emerged. 3D NAND flash memory significantly saves silicon wafer area, reduces manufacturing costs, and increases storage capacity.

[0003] In 3D NAND memory structures, a stacked 3D NAND memory structure is achieved by vertically stacking multiple layers of data storage cells. In the process of forming a 3D NAND memory array, a stack of alternating sacrificial layers and isolation layers is first formed. Then, the sacrificial layers are replaced with control gate structures to obtain a gate stack structure. The gate stack structure has contact holes (SSCTs) that communicate with different control gate structures and are filled with conductive material to bring out word lines.

[0004] However, as the number of layers in a 3D NAND memory structure increases, the difficulty of SSCT etching to stop in the gate stack structure increases, which in turn increases the manufacturing difficulty of the device. Summary of the Invention

[0005] The main objective of this application is to provide a three-dimensional memory, its fabrication method, and a storage system having the same, in order to solve the problem that the manufacturing difficulty of memory structures increases with the number of stacked layers in the prior art.

[0006] To achieve the above objectives, according to one aspect of this application, a method for fabricating a three-dimensional memory is provided, comprising the following steps: providing a substrate having a stack body on the substrate, the stack body including multiple sacrificial layers and multiple isolation layers alternately stacked in a direction away from the substrate, at least one end of the stack body having a stepped structure, the side of the stepped structure away from the substrate having a plurality of first stepped surfaces, each sacrificial layer having a first surface away from the substrate, the first stepped surfaces being located in the first surfaces corresponding to each other; forming an array of channels penetrating to the substrate in the region of the stack body other than the stepped structure, and forming pseudo-channel holes penetrating to the substrate through each first stepped surface; forming a support layer at the bottom of the pseudo-channel holes, the region of the pseudo-channel holes other than the support layer constituting contact holes, each contact hole penetrating a sacrificial layer; replacing the sacrificial layer with a control gate structure, and forming a conductive channel in the contact hole to electrically connect the control gate structure to the conductive channel.

[0007] Furthermore, prior to the step of forming the pseudo-channel via, the fabrication method further includes the following steps: forming an interlayer dielectric layer covering the stack; in the step of forming the pseudo-channel via, sequentially etching the interlayer dielectric layer and the step structure to form a pseudo-channel via communicating with the substrate.

[0008] Furthermore, the steps for forming the pseudo-channel via include: sequentially etching the interlayer dielectric layer and the step structure to form a pre-existing channel extending through the substrate; and performing lateral etching along the sidewall of the pre-existing channel to form the pseudo-channel via, wherein the sacrificial layer has an exposed end protruding from the sidewall of the pseudo-channel via.

[0009] Furthermore, the step of forming a support layer at the bottom of each pseudo-channel hole includes: depositing an insulating material in the pseudo-channel hole to cover the exposed end; etching the insulating material to form a contact hole, the remaining insulating material constituting the support layer, and the surface of the support layer away from the substrate being the bottom surface of the contact hole.

[0010] Furthermore, prior to the step of forming the interlayer dielectric layer covering the stack, the fabrication method further includes the following steps: covering each first step surface with an etch barrier layer one by one; and in the step of forming the pseudo-channel via, sequentially etching the interlayer dielectric layer, the etch barrier layer, and the step structure to form a pseudo-channel via connected to the substrate.

[0011] Further, replacing the sacrificial layer with a control gate structure and forming a conductive channel in the contact hole includes: filling the contact hole with a first conductive material to form a conductive channel, wherein a portion of the first conductive material is disposed through a sacrificial layer in a direction away from the substrate; forming a gate gap through the substrate in the stack to give the sacrificial layer an exposed end face located in the gate gap; etching away the sacrificial layer along the exposed end face; and filling the area where the sacrificial layer has been removed with a first gate material to make the first gate material contact the conductive channel.

[0012] Further, replacing the sacrificial layer with a control gate structure includes: filling a contact hole with sacrificial material such that the sacrificial material is disposed through a sacrificial layer in a direction away from the substrate; forming a gate slot through the substrate in the stack such that the sacrificial layer has an exposed end face located in the gate slot; etching away the sacrificial layer along the exposed end face to form a first channel; forming a high-k dielectric layer on the sidewall of the first channel; and filling the first channel with a second gate material such that the high-k dielectric layer encapsulates the second gate material.

[0013] Further, forming a conductive channel in the contact hole includes: removing the sacrificial material to expose a portion of the high-k dielectric layer; removing the exposed portion of the high-k dielectric layer; and filling the area where the sacrificial layer and the high-k dielectric layer have been removed with a second conductive material, the second conductive material being in contact with the second gate material to form a conductive channel.

[0014] According to another aspect of this application, a three-dimensional memory is provided, including a substrate and a memory array located on the substrate. The memory array includes: a gate stack structure disposed on the substrate, the gate stack structure including multiple layers of control gate structures and multiple layers of isolation layers alternating in a direction away from the substrate, the gate stack structure including a core memory region and a step region; a channel array disposed in the core memory region and extending to the substrate; a plurality of support layers extending to the substrate from the step region, the different support layers extending through a different number of isolation layers, and each support layer contacting a control gate structure on its side away from the substrate; and a plurality of conductive channels disposed one-to-one on the side of the support layers away from the substrate, and each conductive channel being connected to the support layer by respectively extending through a control gate structure.

[0015] Furthermore, the control gate structure includes a gate that is in contact with a conductive channel; or the control gate structure includes a high-k dielectric layer and a gate, wherein the high-k dielectric layer partially encloses the gate and the gate is in contact with the conductive channel.

[0016] According to another aspect of this application, a storage system is also provided, including a controller and a memory, the controller being coupled to a three-dimensional memory and controlling the three-dimensional memory to store data, the memory being prepared by the above-described method for manufacturing a three-dimensional memory, or the memory being the above-described three-dimensional memory.

[0017] This application provides a method for fabricating a three-dimensional memory. The method first forms a substrate with a stack, the stack comprising multiple sacrificial layers and multiple isolation layers alternately stacked along a direction away from the substrate. At least one end of the stack has a stepped structure, and the side of the stepped structure away from the substrate has multiple first step surfaces. Each sacrificial layer has a first surface away from the substrate, and each first step surface is located in a corresponding position within the first surface. A pseudo-channel is formed, passing through each first step surface to the substrate. Then, a support layer is formed at the bottom of the pseudo-channel, so that the area in the pseudo-channel except for the support layer constitutes a contact hole. Each contact hole penetrates a sacrificial layer, thereby providing a conductive channel in the contact hole, allowing the conductive channel to be directly electrically connected to the control gate structure formed after the sacrificial layer is replaced. Using the above fabrication method of this application, contact holes can be formed in the pseudo-channel, which not only simplifies the device structure but also avoids the increased etching difficulty caused by the small process window between the pseudo-channel and the contact hole, thus reducing the overall process complexity. Furthermore, the above-mentioned manufacturing method can avoid over-etching caused by directly etching to form channel holes, thus eliminating the need to set an etching stop layer to prevent over-etching of contact holes, thereby simplifying the process flow and reducing process costs. Attached Figure Description

[0018] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0019] Figure 1 This illustration shows a cross-sectional view of the substrate after providing a substrate with stacked bodies in a method for fabricating a three-dimensional memory according to an embodiment of this application.

[0020] Figure 2 It shows the formation through Figure 1 A schematic diagram of the cross-sectional structure of the substrate after the pre-drained channel of the substrate from each first surface of the stepped structure in the stacked body shown.

[0021] Figure 3 It shows along Figure 2 The diagram shows a cross-sectional structure of the substrate after the sidewalls of the pre-existing channel are laterally etched to form a pseudo-channel.

[0022] Figure 4 It shows in Figure 3 A schematic diagram of the cross-sectional structure of the substrate after the insulating material is deposited in the pseudo-channel hole to wrap the exposed end;

[0023] Figure 5 Etching is shown Figure 4 The diagram shows a cross-sectional structure of the substrate after the insulating material has formed contact holes.

[0024] Figure 6 It shows Figure 4 A schematic diagram of the cross-sectional structure of the local substrate on the first surface after the etch barrier layer is covered one-to-one;

[0025] Figure 7 It shows in Figure 6 A schematic diagram of the cross-sectional structure of the substrate after the contact hole is filled with the first conductive material to form a conductive channel;

[0026] Figure 8 It shows that Figure 7 The diagram shows a cross-sectional structure of the substrate after the sacrificial layer has been replaced with a control gate structure.

[0027] Figure 9 It shows in Figure 6 A schematic diagram of the cross-sectional structure of the substrate after the contact holes are filled with sacrificial material;

[0028] Figure 10 It shows that Figure 9 The diagram shows a cross-sectional view of the substrate after the sacrificial layer is replaced with a control gate structure. The control gate structure includes a high-k dielectric layer and a gate material, and the high-k dielectric layer encapsulates the gate material.

[0029] Figure 11 It shows Figure 10 Schematic diagram of the cross-sectional structure of region A in the middle;

[0030] Figure 12 It shows the removal Figure 10 The diagram shows a cross-sectional structure of the substrate behind the sacrificial material and part of the high-k dielectric layer.

[0031] Figure 13 It shows Figure 12 A schematic diagram of the cross-sectional structure of region A' in the middle;

[0032] Figure 14 It shows in Figure 12 A schematic diagram of the cross-sectional structure of the substrate after the area where the sacrificial layer and high-k dielectric layer have been removed is filled with a second conductive material to form a conductive channel;

[0033] Figure 15 It shows Figure 14 A schematic diagram of the cross-sectional structure of region A'' in the middle;

[0034] Figure 16 A schematic diagram of the connection relationship of a storage system provided according to an embodiment of this application is shown.

[0035] The above figures include the following reference numerals:

[0036] 10. Substrate; 20. Stack; 200. Gate stack structure; 210. Sacrificial layer; 220. Isolation layer; 230. Step structure; 240. Control gate structure; 241. High-k dielectric layer; 242. Second gate material; 30. Channel array; 310. Channel structure; 40. Interlayer dielectric layer; 50. Pseudo-channel via; 501. Pre-drilled via; 510. Contact via; 60. Support layer; 610. Insulating material; 70. Conductive channel; 80. Sacrificial material; 90. Etch barrier layer; 1000. 3D memory; 2000. Controller; 3000. Host; 20000. Memory system. Detailed Implementation

[0037] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0038] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0039] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0040] According to one embodiment of this application, a method for fabricating a three-dimensional memory is proposed, comprising the following steps: providing a substrate, wherein the substrate has a stack body, the stack body comprising multiple sacrificial layers and multiple isolation layers alternately stacked in a direction away from the substrate, at least one end of the stack body having a stepped structure, the side of the stepped structure away from the substrate having a plurality of first stepped surfaces, each sacrificial layer having a first surface away from the substrate, the first stepped surfaces being located in the first surfaces corresponding to each other; forming a channel array penetrating to the substrate in the region of the stack body other than the stepped structure, and forming pseudo-channel holes penetrating to the substrate through each first stepped surface; forming a support layer at the bottom of the pseudo-channel holes, the region of the pseudo-channel holes other than the support layer constituting a contact hole, each contact hole penetrating a sacrificial layer; replacing the sacrificial layer with a control gate structure, and forming a conductive channel in the contact hole to electrically connect the control gate structure with the conductive channel.

[0041] The fabrication method described in this application enables the formation of contact holes within pseudo-channel vias, simplifying the device structure and avoiding the increased etching difficulty caused by the small process window between the pseudo-channel via and the contact hole, thus reducing the overall fabrication complexity. Furthermore, this method avoids over-etching caused by directly forming channel vias through etching, eliminating the need for an etching stop layer to prevent over-etching of the contact hole, thereby simplifying the process flow and reducing costs.

[0042] Exemplary embodiments of the method for fabricating a three-dimensional memory according to this application will now be described in more detail. However, these exemplary embodiments may be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein. It should be understood that these embodiments are provided so that the disclosure of this application is thorough and complete, and that the concept of these exemplary embodiments is fully conveyed to those skilled in the art.

[0043] First, a substrate 10 is provided, on which a stack 20 is provided. The stack 20 includes multiple sacrificial layers 210 and multiple insulating layers 220 alternately stacked in a direction away from the substrate 10. At least one end of the stack 20 has a step structure 230. The side of the step structure 230 away from the substrate has a plurality of first step surfaces. Each sacrificial layer 210 has a first surface away from the substrate 10, and the first step surfaces are located in the first surface in a one-to-one correspondence. Figure 1 As shown.

[0044] The substrate 10 can be made of single-crystal silicon (Si), single-crystal germanium (Ge), or silicon-germanium (GeSi), silicon carbide (SiC); it can also be silicon-on-insulator (SOI), germanium-on-insulator (GOI); or it can be other materials, such as gallium arsenide or other III-V compounds.

[0045] The sacrificial layer 210 and the isolation layer 220 can be formed using a deposition process, such as chemical vapor deposition. Those skilled in the art can reasonably determine the number of layers in the sacrificial layer 210 and the isolation layer 220. The isolation layer 220 can be SiO2, and the sacrificial layer 210 can be SiN, but are not limited to these types. Those skilled in the art can also reasonably select the types of the sacrificial layer 210 and the isolation layer 220.

[0046] The step structure 230 in the stack 20 can be formed by dry etching. A channel array 30 is formed in the area of ​​the stack 20 other than the step structure 230. The side of the step structure 230 away from the substrate 10 has a plurality of first step surfaces, each of which is a part of the surface of a different sacrificial layer 210 away from the substrate 10.

[0047] After the step of forming the stack 20 with the stepped structure 230, a channel array 30 extending to the substrate 10 is formed in the region of the stack 20 other than the stepped structure 230, and pseudo-channel holes 50 are formed through each first stepped surface to the substrate 10, such as... Figure 2 and Figure 3 As shown.

[0048] The aforementioned channel array 30 includes channel structures 310 that extend through the substrate 10 and correspond one-to-one with channel vias, such as... Figure 2As shown, the step of forming the above-mentioned channel structure 310 in the channel hole may include: sequentially depositing a functional layer, a channel layer and a filling layer on the sidewall of the channel hole, filling with a dielectric material to obtain a channel structure 310 that extends through the substrate 10.

[0049] Optionally, the aforementioned functional layer includes a charge blocking layer, a charge trapping layer, and a tunneling layer sequentially stacked on the sidewall of the channel hole.

[0050] For example, the charge blocking layer is made of SiO2, the charge trapping layer is made of iN, the tunneling layer and the filling dielectric material are made of SiO2, and the channel layer is made of polysilicon.

[0051] After forming the aforementioned channel array 30, an interlayer dielectric layer 40 is formed covering the stack 20, and pseudo-channel vias 50 are formed sequentially through the interlayer dielectric layer 40 and each first step surface to the substrate 10, as shown below. Figure 3 As shown. The interlayer dielectric layer 40 can be an insulating dielectric material, such as SiO2.

[0052] In a preferred embodiment, the step of forming the aforementioned pseudo-channel via 50 includes: sequentially etching the interlayer dielectric layer 40 and the step structure 230 to form a pre-existing channel 501 penetrating the stack 20, the pre-existing via reaching the substrate 10, such as... Figure 2 As shown; transverse etching is performed along the sidewall of the pre-drilled channel 501 to form a pseudo-channel hole 50. The sacrificial layer 210 has an exposed end protruding from the sidewall of the pseudo-channel hole 50, as shown. Figure 3 As shown. The isolation layer has an exposed end face exposed in the wall of the pre-drain 501. The lateral etching can start from this exposed end face to etch the isolation layer, thereby exposing the sacrificial layer, which is alternately arranged with the isolation layer, at the middle end of the pseudo-channel hole 50, so that the subsequently formed conductive channel can contact the control gate structure obtained by replacing the sacrificial layer 210.

[0053] In the above embodiment, a mask layer can be covered on the side of the substrate 10 away from the stack 20, and the mask layer can be patterned so that it has hollow areas that correspond one-to-one with the first step surface of the stepped structure. Then, the interlayer dielectric layer 40 and the stack 20 are sequentially etched through the hollow areas until the etching stops at the substrate 10, so as to obtain a pre-existing channel 501 through the first step surface to the substrate 10, and then the mask layer is removed. The mask layer can be formed using conventional mask materials, such as SiN, and the patterning process of the mask layer can be a photolithography process, which will not be described in detail in this application.

[0054] In the above embodiment, in order to form the dummy channel hole 50, the spacer layer can be laterally etched using a dry etching process through the exposed end face of the spacer layer located in the pre-drilled channel 501, thereby giving the sacrificial layer 210 an exposed end protruding from the sidewall of the dummy channel hole 50, such as... Figure 3 As shown. The etching gas in the above dry etching process can be reasonably selected according to the type of spacer layer, and this application does not make specific limitations.

[0055] After forming the pseudo-channel vias 50 through each first step surface to the substrate 10, a support layer 60 is formed in the first via segment, such that the area of ​​the pseudo-channel via 50 excluding the support layer 60 constitutes a contact via 510, and each contact via 510 penetrates a sacrificial layer 210, such as Figures 4 to 6 As shown.

[0056] The step of forming a support layer 60 in each dummy channel hole 50 may include: filling the dummy channel hole 50 with an insulating material 610 to cover the exposed ends of the sacrificial layer 210, such as... Figure 4 As shown; the insulating material 610 is etched to form the contact hole 510, and the remaining insulating material 610 forms the support layer 60. The surface of the support layer 60 away from the substrate 10 serves as the bottom surface of the contact hole 510, as shown. Figure 5 As shown. Through the above etching process, the formed support layer 60 can be located at the bottom of the pseudo-channel hole 50 and penetrate to the substrate 10. Each support layer 60 penetrates a different number of isolation layers 220, and the side of each support layer 60 away from the substrate 10 is in contact with a sacrificial layer 210, so that each of the above support layers 60 can play the role of supporting the stepped structure.

[0057] Specifically, insulating material 610 can be deposited in the pseudo-channel via 50 using ALD (atomic layer deposition) or chemical vapor deposition (CVD) processes, such as... Figure 4 As shown, anisotropic etching is then performed on the insulating material 610 starting from the top of the dummy channel hole 50, so that only the end of the sacrificial layer 210 in each dummy channel hole 50 is exposed, and the remaining insulating material 610 forms the support layer 60. The side of the support layer 60 away from the substrate 10 forms the contact hole 510, and the surface of the support layer 60 away from the substrate 10 is the bottom surface of the contact hole 510, as shown. Figure 5 As shown. The anisotropic etching described above can be a conventional dry etching process. Those skilled in the art can reasonably select the etching gas according to the specific type of insulating material 610; this application does not impose specific limitations. The insulating material 610 described above can be SiO2.

[0058] In another alternative embodiment, the first step surface of the stepped structure is covered with an etch barrier layer 90. After the pre-existing channel 501 is laterally expanded to form a pseudo-channel hole 50, both the sacrificial layer 210 and the etch barrier layer 90 have exposed ends located in the pseudo-channel hole 50. Then, the pseudo-channel hole 50 is filled with an insulating material 610 to cover the exposed ends of the sacrificial layer 210 and the etch barrier layer 90, such as... Figure 6 As shown. The step of etching the insulating material 610 described above is to expose the uppermost sacrificial layer 210 located in the dummy channel hole 50. By providing the etching barrier layer 90, the distance between the surface of the insulating material 610 and the surface of the uppermost sacrificial layer can be increased, thereby increasing the etching window of the sacrificial layer 210 in the dummy channel hole 50. This helps to prevent over-etching and causing the contact hole 510 to penetrate multiple layers of sacrificial layer 210 in a direction away from the substrate 10. In order to facilitate the etching barrier layer 90 to be etched away together with the sacrificial layer 210 in the subsequent process, the material of the etching barrier layer 90 can also have a large etching selectivity ratio with the isolation layer 220. For example, the material of the etching barrier layer 90 is the same as that of the sacrificial layer 210, such as SiN.

[0059] After forming a support layer 60 in the first aperture segment to form a contact hole 510 on the side of the support layer 60 away from the substrate 10, the sacrificial layer 210 is replaced with a control gate structure 240, and a conductive channel 70 is formed in the contact hole 510 to electrically connect the control gate structure 240 to the conductive channel 70, such as... Figures 7 to 15 As shown.

[0060] To electrically connect the control gate structure 240 to the conductive channel 70, in the first example of this application, the sacrificial layer 210 is replaced with the control gate structure 240, and the conductive channel 70 is formed in the contact hole 510. This includes filling the contact hole 510 with a first conductive material to form the conductive channel 70, wherein a portion of the first conductive material is disposed through a sacrificial layer 210 in a direction away from the substrate 10, such as... Figure 7 As shown; a gate gap extending through the substrate 10 is formed in the stack 20 so that the sacrificial layer 210 has an exposed end face located in the gate gap; the sacrificial layer 210 is removed by etching along the exposed end face; a first gate material is filled in the area where the sacrificial layer 210 has been removed to form a gate layer, i.e., a control gate structure 240, so that the control gate structure 240 contacts the conductive channel 70, as shown. Figure 8 As shown.

[0061] In the first example above, those skilled in the art can make reasonable selections of the first conductive material, such as the second conductive material being tungsten metal or molybdenum metal.

[0062] In the first example above, the sacrificial layer 210 can be removed by an etching process. Exemplarily, by forming the gate gap, the sacrificial layer 210 can have an exposed end face, allowing wet etching of the sacrificial layer 210 starting from the exposed end face to remove it. Furthermore, by removing the sacrificial layer 210, a laterally extending channel can be formed at the location where the sacrificial layer 210 was removed, and then a first gate material can be deposited in the channel. The deposition process can be atomic layer deposition (ALD). The first gate material is typically a metal, and can be selected from one or more of W, Al, Cu, Ti, Ag, Au, Pt, and Ni.

[0063] In the second example of this application, the step of replacing the sacrificial layer 210 with the control gate structure 240 includes: as Figure 9 As shown, a sacrificial material 80 is filled into the contact hole 510 so that the sacrificial material 80 is disposed through a sacrificial layer 210 in a direction away from the substrate 10; a gate gap extending through the substrate 10 is formed in the stack 20 so that the sacrificial layer 210 has an exposed end face located in the gate gap; the sacrificial layer 210 is etched away along the exposed end face to form a first channel; a high-k dielectric layer 241 is formed on the sidewall of the first channel; a second gate material 242 is filled into the first channel so that the high-k dielectric layer 241 encapsulates the second gate material 242, as shown. Figure 10 and Figure 11 As shown.

[0064] In the second example above, in order to facilitate the removal of the sacrificial layer 210 while retaining the sacrificial material 80, the sacrificial layer 210 can have a large etching selectivity ratio with the sacrificial material 80. Those skilled in the art can make reasonable selections for the sacrificial material 80 based on the etching selectivity ratio of the two, such as polysilicon, carbon, etc.

[0065] In the second example above, by forming the gate gap, the sacrificial layer 210 can have an exposed end face, thereby enabling wet etching of the sacrificial layer 210 using an etchant starting from the exposed end face, thus removing the sacrificial layer 210. Furthermore, by removing the sacrificial layer 210, a laterally extending channel, i.e., the first channel, can be formed at the location where the sacrificial layer 210 was removed. Then, using the first channel as a deposition channel, a high-k dielectric material is first deposited on the inner surface to form a high-k dielectric layer 241. Then, a second gate material 242 is deposited to obtain the gate layer. A portion of the high-k dielectric layer 241 is disposed between the gate layer and the memory structure to form the gate dielectric layer, and another portion of the high-k dielectric layer 241 is disposed between the gate layer and the adjacent isolation layer 220, such as... Figure 10 and Figure 11 As shown. The above deposition process can be atomic layer deposition (ALD).

[0066] The high-K dielectric material mentioned above can be selected from one or more of HfO2, TiO2, HfZrO, HfSiNO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3 and BaSrTiO; the second gate material 242 mentioned above is usually a metal and can be selected from one or more of W, Al, Cu, Ti, Ag, Au, Pt and Ni.

[0067] In the second example above, to electrically connect the control gate structure 240 to the conductive channel 70, the step of forming the conductive channel 70 in the contact hole 510 may include: removing the sacrificial material 80 to expose a portion of the high-k dielectric layer 241, such as... Figure 12 and Figure 13 As shown; the exposed portion of the high-k dielectric layer 241 is removed; a second conductive material is filled in the area where the sacrificial layer 210 and the high-k dielectric layer 241 have been removed, and the second conductive material contacts the second gate material 242 to form a conductive channel 70, as shown. Figure 14 and Figure 15 As shown.

[0068] In the second example above, a wet etching process can be used to remove the sacrificial material 80 and part of the high-k dielectric layer 241. Those skilled in the art can rationally select the wet etching solvent based on the type of sacrificial material 80 and the material type of the high-k dielectric layer 241. Those skilled in the art can also rationally select the second conductive material, such as tungsten or molybdenum.

[0069] In an alternative embodiment, after forming the gate gap described above, a sidewall insulating layer is first deposited and formed in the gate gap, and then a common source electrode is formed in the gate gap covered with the sidewall insulating layer. The common source electrode is isolated from the control gate structure 240 by the sidewall insulating layer, and the memory structure forms a common source electrode connection via the substrate 10.

[0070] It should be noted that the process for forming the common source electrode is not limited to the optional embodiments described above. In another optional embodiment, the functional layer in the channel structure is made to directly contact the substrate, a gate gap extending through the substrate is formed in the stack, and the gate gap is filled with a second insulating material; the substrate is thinned or removed to expose the functional layer and the second insulating material at the bottom; a semiconductor layer is then covered on the exposed functional layer and the second insulating material to serve as the common source electrode. For example, the semiconductor layer described above is an N-type doped polysilicon layer.

[0071] According to another embodiment of this application, a three-dimensional memory is provided, such as... Figure 8 and Figure 14As shown, the device includes a substrate 10 and a memory array located on the substrate 10. The memory array includes a gate stack structure 200, a channel array 30, a plurality of support layers 60, and a plurality of conductive channels 70.

[0072] In the above embodiments, the gate stack structure 200 is disposed on the substrate 10. The gate stack structure 200 includes multiple layers of control gate structure 240 and multiple layers of isolation layer 220 alternating in a direction away from the substrate 10. The gate stack structure 200 includes a core memory region and a step region. The channel array 30 is disposed in the core memory region and extends through the substrate 10. Multiple support layers 60 extend through the step region to the substrate 10. Different support layers 60 extend through different numbers of isolation layers 220, and the side of each support layer 60 away from the substrate 10 is in contact with a control gate structure 240. Multiple conductive channels 70 are disposed one-to-one on the side of the support layer 60 away from the substrate, and each conductive channel 70 is connected to the support layer 60 by extending through a control gate structure 240.

[0073] In the three-dimensional memory of this embodiment, since multiple support layers 60 penetrate through the step region to the substrate 10, different support layers 60 penetrate different numbers of isolation layers 220, and the side of each support layer 60 away from the substrate 10 is in contact with a control gate structure 240, the conductive channel 70 does not need a separate contact hole and can be directly disposed on the side of the support layer 60 away from the substrate, thereby simplifying the device structure.

[0074] For example, the support layer 60 is a SiO2 layer, and the conductive channel 70 is tungsten or molybdenum.

[0075] In an optional implementation, the control gate structure 240 includes a gate, the gate layer being in contact with the conductive channel 70 to achieve electrical connection with the conductive channel 70, such as... Figure 8 As shown.

[0076] In another alternative embodiment, the control gate structure 240 includes a high-k dielectric layer 241 and a gate layer. The high-k dielectric layer 241 partially encloses the gate, and the gate contacts the portion of the gate layer not enclosed by the high-k dielectric layer 241, thereby achieving electrical connection with the conductive channel 70. Figure 14 and Figure 15 As shown.

[0077] According to one embodiment of this application, a storage system 20000 is also provided. Figure 16 This is an internal block diagram of a storage system 20000 according to an embodiment of this application. For example... Figure 16 As shown, the storage system 20000 may include a three-dimensional memory 1000 and a controller 2000.

[0078] The three-dimensional memory 1000 may be the same as the three-dimensional memory described in any of the embodiments above, or may be prepared by the manufacturing method of the three-dimensional memory in any of the embodiments above, and this application will not elaborate further on this.

[0079] The controller 2000 can control the three-dimensional memory 1000 via channel CH, and the three-dimensional memory 1000 can perform operations based on the control of the controller 2000 in response to requests from the host 3000. The three-dimensional memory 1000 can receive commands CMD and addresses ADDR from the controller 2000 via channel CH and access the region selected from the memory cell array in response to that address. In other words, the three-dimensional memory 1000 can perform internal operations corresponding to commands on the region selected by the address.

[0080] In some implementations, the aforementioned storage system may be implemented as a Universal Flash Storage (UFS) device, a Solid State Drive (SSD), a Multimedia Card in the form of MMC, eMMC, RS-MMC, and Micro MMC, a Secure Digital Card in the form of SD, Mini SD, and Micro SD, a PCMCIA card type storage device, a Peripheral Component Interconnect (PCI) type storage device, a High Speed ​​PCI (PCI-E) type storage device, a Compact Flash (CF) card, a Smart Media Card, or a Memory Stick, etc.

[0081] As can be seen from the above description, the embodiments of this application achieve the following technical effects:

[0082] Using the fabrication method described in this application, channel holes can be formed in pseudo-channel holes, which not only simplifies the device structure but also avoids the increased etching difficulty caused by the small process window between the pseudo-channel hole and the contact hole, thus reducing the process complexity. Furthermore, the fabrication method avoids over-etching caused by directly forming channel holes through etching, thereby eliminating the need for an etching stop layer to prevent over-etching of the contact hole, further simplifying the process flow and reducing process costs.

[0083] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for fabricating a three-dimensional memory, characterized in that, Includes the following steps: A substrate is provided, the substrate having a stack comprising multiple sacrificial layers and multiple insulating layers alternately stacked in a direction away from the substrate, at least one end of the stack having a stepped structure, the stepped structure having a plurality of first stepped surfaces on the side away from the substrate, each of the sacrificial layers having a first surface away from the substrate, the first stepped surfaces being located in the first surface in a one-to-one correspondence. In the stack, a channel array extending through the substrate is formed in the region other than the stepped structure, and a pseudo-channel hole is formed through each of the first stepped surfaces to the substrate; A support layer is formed at the bottom of the pseudo-channel hole, and the area in the pseudo-channel hole other than the support layer constitutes a contact hole, and each contact hole penetrates one layer of the sacrificial layer. The sacrificial layer is replaced with a control gate structure, and a conductive channel is formed in the contact hole so that the control gate structure is electrically connected to the conductive channel, and the support layer is electrically isolated from the conductive channel.

2. The manufacturing method according to claim 1, characterized in that, Prior to the step of forming the pseudo-channel hole, the fabrication method further includes the following steps: Form an interlayer dielectric layer covering the stack; In the step of forming the pseudo-channel via, the interlayer dielectric layer and the stepped structure are sequentially etched to form the pseudo-channel via communicating with the substrate.

3. The manufacturing method according to claim 2, characterized in that, The steps for forming the pseudo-channel hole include: The interlayer dielectric layer and the stepped structure are sequentially etched to form a pre-existing channel extending into the substrate; Laterally etch along the sidewall of the pre-existing channel to form the pseudo-channel hole, wherein the sacrificial layer has an exposed end protruding from the sidewall of the pseudo-channel hole.

4. The manufacturing method according to claim 3, characterized in that, The step of forming the support layer at the bottom of each of the pseudo-channel holes includes: An insulating material is deposited in the pseudo-channel hole to cover the exposed end; The insulating material is etched to form the contact hole, and the remaining insulating material forms the support layer. The surface of the support layer away from the substrate is the bottom surface of the contact hole.

5. The manufacturing method according to claim 2, characterized in that, Prior to the step of forming the interlayer dielectric layer covering the stack, the fabrication method further includes the following steps: An etching barrier layer is applied to each of the first step surfaces. In the step of forming the pseudo-channel via, the interlayer dielectric layer, the etch barrier layer, and the step structure are sequentially etched to form the pseudo-channel via communicating with the substrate.

6. The manufacturing method according to any one of claims 1 to 5, characterized in that, The step of replacing the sacrificial layer with a control gate structure and forming a conductive channel in the contact hole includes: A first conductive material is filled into the contact hole to form the conductive channel, and a portion of the first conductive material is disposed through a sacrificial layer in a direction away from the substrate; A gate slot extending through the substrate is formed in the stack, so that the sacrificial layer has an exposed end face located in the gate slot; The sacrificial layer is removed by etching along the exposed end face; A first gate material is filled in the area where the sacrificial layer is removed, so that the first gate material contacts the conductive channel.

7. The manufacturing method according to any one of claims 1 to 5, characterized in that, The step of replacing the sacrificial layer with a control gate structure includes: The contact hole is filled with a sacrificial material such that the sacrificial material is disposed through a sacrificial layer in a direction away from the substrate; A gate slot extending through the substrate is formed in the stack, so that the sacrificial layer has an exposed end face located in the gate slot; The sacrificial layer is removed by etching along the exposed end face to form a first channel; A high-k dielectric layer is formed on the sidewall of the first channel; The first channel is filled with a second gate material so that the high-k dielectric layer encapsulates the second gate material.

8. The manufacturing method according to claim 7, characterized in that, The formation of a conductive channel in the contact hole includes: Remove the sacrificial material to expose a portion of the high-k dielectric layer; Remove the exposed portions of the high-k dielectric layer; A second conductive material is filled in the region where the sacrificial layer and the high-k dielectric layer are removed, and the second conductive material contacts the second gate material to form the conductive channel.

9. A three-dimensional memory, characterized in that, Includes a semiconductor layer and a memory array located on the semiconductor layer, the memory array comprising: A gate stack structure is disposed on the semiconductor layer. The gate stack structure includes multiple layers of control gate structure and multiple layers of isolation layer alternating along a first direction. The gate stack structure includes a core memory region and a step region. A channel array is disposed in the core memory region and extends through the gate stack structure in the core memory region to the semiconductor layer; Multiple support layers pass through the gate stack structure in the stepped region along the first direction and extend to the semiconductor layer. Different support layers penetrate different numbers of isolation layers, and each support layer contacts a control gate structure on the side away from the semiconductor layer. Multiple conductive channels are disposed one-to-one on the side of the support layer away from the semiconductor layer, and each conductive channel extends along the first direction and is connected to a layer of the control gate structure. The support layer is electrically isolated from the conductive channels.

10. The three-dimensional memory according to claim 9, characterized in that, The control gate structure includes a gate that is in contact with the conductive channel; or The control gate structure includes a high-k dielectric layer and a gate, wherein the high-k dielectric layer partially encloses the gate, and the gate is in contact with the conductive channel.

11. The three-dimensional memory according to claim 9, characterized in that, The support layer includes support pillars formed of insulating material, and the conductive channels are aligned with the support pillars along the first direction.

12. A storage system comprising a controller and a memory, the controller being coupled to the three-dimensional memory and controlling the three-dimensional memory to store data, characterized in that, The memory is prepared by the method for manufacturing a three-dimensional memory according to any one of claims 1 to 8, or the memory is a three-dimensional memory according to any one of claims 9 to 11.

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