Micro light emitting diode chip and preparation method thereof

Abstract

The present disclosure provides a micro light-emitting diode chip and a method for preparing the same. The micro light-emitting diode chip includes: an epitaxial structure and a light-guiding layer; the epitaxial structure includes a first semiconductor layer, a multi-quantum well layer, and a second semiconductor layer stacked in sequence, the light-guiding layer is located on the surface of the second semiconductor layer away from the first semiconductor layer, and the surface of the epitaxial structure away from the light-guiding layer is a light-emitting surface; the light-guiding layer includes multiple layers of titanium oxide layers and multiple layers of silicon oxide layers stacked alternately, the silicon oxide layer is embedded with multiple spaced columnar structures, the columnar structure extends in a direction perpendicular to the light-emitting surface, and the refractive index of the columnar structure is different from that of the silicon oxide layer. The present disclosure can improve the problem of optical crosstalk between chips, reduce the side light-emitting ratio, and improve the light-emitting effect.

Description

Technical Field

[0001] The present disclosure relates to the field of optoelectronic manufacturing technology, and in particular to a micro light emitting diode chip and a preparation method thereof. Background Art

[0002] Micro Light Emitting Diode (Micro LED) refers to a light-emitting diode with a side length of 10μm to 100μm. Micro LEDs are small in size and can be arranged more densely to greatly improve resolution. They also have self-luminous properties and have the characteristics of high brightness, high contrast, high responsiveness and power saving.

[0003] In the related art, a micro-LED chip generally includes an epitaxial structure, a first electrode, and a second electrode, wherein the epitaxial structure includes a first semiconductor layer, a multi-quantum well layer, and a second semiconductor layer stacked in sequence, wherein the first electrode and the second electrode are respectively arranged on both sides of the epitaxial structure.

[0004] Since the micro-LED chips are small in size and the spacing between the chips is close, optical crosstalk is prone to occur, affecting the light output effect. Summary of the invention

[0005] The disclosed embodiment provides a micro light emitting diode chip and a method for manufacturing the same, which can improve the light crosstalk problem between chips, reduce the side light emission ratio, and improve the light emitting effect. The technical solution is as follows:

[0006] An embodiment of the present disclosure provides a micro-light-emitting diode chip, which includes: an epitaxial structure and a light-guiding layer; the epitaxial structure includes a first semiconductor layer, a multi-quantum well layer, and a second semiconductor layer stacked in sequence, the light-guiding layer is located on a surface of the second semiconductor layer away from the first semiconductor layer, and a surface of the epitaxial structure away from the light-guiding layer is a light-emitting surface; the light-guiding layer includes multiple layers of titanium oxide layers and multiple layers of silicon oxide layers stacked alternately, the silicon oxide layer is embedded with a plurality of spaced-apart columnar structures, the columnar structures extend in a direction perpendicular to the light-emitting surface, and the refractive index of the columnar structures is different from the refractive index of the silicon oxide layer.

[0007] In an implementation of the embodiment of the present disclosure, the columnar structure is a cylinder, and the diameter of the columnar structure is 0.05 μm to 0.2 μm.

[0008] In another implementation of the embodiment of the present disclosure, the columnar structure is made of titanium oxide.

[0009] In another implementation of the embodiment of the present disclosure, the orthographic projection of the side wall of the epitaxial structure on the plane where the light emitting surface is located is located within the light emitting surface, and the side wall of the epitaxial structure is provided with an anti-reflection film, and the anti-reflection film covers the side wall of the first semiconductor layer, the side wall of the multi-quantum well layer and the side wall of the second semiconductor layer.

[0010] In another implementation of the embodiment of the present disclosure, a surface of the anti-reflection film away from the epitaxial structure has a protrusion, and an extension direction of the protrusion is perpendicular to the light emitting surface.

[0011] In another implementation of the embodiment of the present disclosure, the micro-light emitting diode chip also includes a first electrode, a second electrode and a transparent conductive layer, the first electrode is located on the surface of the first semiconductor layer away from the second semiconductor layer, the transparent conductive layer is located on the surface of the light guiding layer away from the first semiconductor layer and connected to the second semiconductor layer, and the second electrode is located on the surface of the transparent conductive layer.

[0012] In another implementation of the embodiment of the present disclosure, the first electrode includes a plurality of electrode blocks, and the plurality of electrode blocks are distributed at intervals on the surface of the first semiconductor layer.

[0013] The disclosed embodiment provides a method for preparing a micro light-emitting diode chip, the method comprising: providing a substrate; growing an epitaxial structure on the substrate, the epitaxial structure comprising a first semiconductor layer, a multi-quantum well layer, and a second semiconductor layer stacked in sequence; making a light-guiding layer on a surface of the second semiconductor layer away from the first semiconductor layer, the surface of the epitaxial structure away from the light-guiding layer being a light-emitting surface, the light-guiding layer comprising multiple layers of titanium oxide layers and multiple layers of silicon oxide layers stacked alternately, the silicon oxide layer having a plurality of spaced-apart columnar structures embedded therein, the columnar structures extending in a direction perpendicular to the light-emitting surface, the refractive index of the columnar structures being different from the refractive index of the silicon oxide layer.

[0014] In another implementation of the embodiment of the present disclosure, the orthographic projection of the side wall of the epitaxial structure on the plane where the light emitting surface is located is located within the light emitting surface; after the light guiding layer is produced on the surface of the second semiconductor layer away from the first semiconductor layer, the method includes: producing an anti-reflection film on the side wall of the epitaxial structure, and the anti-reflection film covers the side wall of the first semiconductor layer, the side wall of the multi-quantum well layer and the side wall of the second semiconductor layer.

[0015] In another implementation of the embodiment of the present disclosure, a surface of the anti-reflection film away from the epitaxial structure has a protrusion, and an extension direction of the protrusion is perpendicular to the light emitting surface.

[0016] The beneficial effects brought by the technical solution provided by the embodiments of the present disclosure include at least:

[0017] The micro-LED chip provided by the embodiment of the present disclosure includes an epitaxial structure and a light-guiding layer, wherein the light-guiding layer includes multiple layers of titanium oxide layers and multiple layers of silicon oxide layers alternately stacked to form a distributed Bragg reflector. In the silicon oxide layer, a plurality of spaced columnar structures are embedded, and since the columnar structure extends in a direction perpendicular to the light-emitting surface, that is, the extension direction of the columnar structure is parallel to the light-emitting direction of the epitaxial structure, and the refractive index of the columnar structure is different from the refractive index of the silicon oxide layer, when the light is incident on the interface between the silicon oxide layer and the columnar structure, it can be reflected at the interface, so that when the light emitted by the epitaxial structure enters the silicon oxide layer, the light with a large light-emitting direction deviation angle will be reflected on the side wall of the columnar structure, thereby changing the direction of the light and reducing the light reflected to the side of the chip, so as to enhance the proportion of photons in the light-emitting direction, improve the problem of light crosstalk between chips, reduce the side light-emitting ratio, and improve the luminous effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0019] Figure 1 is a schematic structural diagram of a micro light emitting diode chip provided by an embodiment of the present disclosure;

[0020] Figure 2 is a schematic structural diagram of a light guide layer provided in an embodiment of the present disclosure;

[0021] Figure 3 is a partially enlarged schematic diagram of an antireflection film provided by an embodiment of the present disclosure;

[0022] Figure 4 is a flow chart of a method for preparing a micro light emitting diode chip provided by an embodiment of the present disclosure;

[0023] Figure 5 This is a diagram of the preparation state of a micro light emitting diode chip provided in an embodiment of the present disclosure.

[0024] The descriptions of the marks in the figure are as follows:

[0025] 1. epitaxial structure; 11. first semiconductor layer; 12. multi-quantum well layer; 13. second semiconductor layer;

[0026] 21. first electrode; 210. electrode block; 22. second electrode;

[0027] 30. light guide layer; 31. silicon oxide layer; 32. titanium oxide layer; 33. columnar structure;

[0028] 41. transparent conductive layer; 42. passivation layer; 43. via hole;

[0029] 51. anti-reflection film; 52. protrusion;

[0030] 60. Sapphire substrate. DETAILED DESCRIPTION

[0031] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0032] Unless otherwise defined, the technical terms or scientific terms used herein shall have the usual meanings understood by persons with ordinary skills in the field to which the present disclosure belongs. The words "first", "second", "third" and similar words used in the patent application specification and claims of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one" or "one" do not indicate a quantity limitation, but indicate the existence of at least one. Words such as "include" or "comprise" and similar words mean that the elements or objects appearing before "include" or "comprise" include the elements or objects listed after "include" or "comprise" and their equivalents, and do not exclude other elements or objects. Words such as "connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right", "top", "bottom" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0033] Figure 1 Schematic diagram of the structure of a micro light emitting diode chip provided by the embodiment of the present disclosure. Figure 1 As shown, the micro light emitting diode chip includes: an epitaxial structure 1 and a light guide layer 30 .

[0034] like Figure 1 As shown, the epitaxial structure 1 includes a first semiconductor layer 11, a multi-quantum well layer 12 and a second semiconductor layer 13 stacked in sequence. The light-guiding layer 30 is located on the surface of the second semiconductor layer 13 away from the first semiconductor layer 11, and the surface of the epitaxial structure 1 away from the light-guiding layer 30 is the light-emitting surface.

[0035] Figure 2 Schematic diagram of the structure of a light guide layer 30 provided in an embodiment of the present disclosure. Figure 2As shown, the light guiding layer 30 includes multiple layers of titanium oxide layers 32 and multiple layers of silicon oxide layers 31 alternately stacked, and the silicon oxide layer 31 is embedded with multiple spaced columnar structures 33, which extend in a direction perpendicular to the light emitting surface, and the refractive index of the columnar structure 33 is different from the refractive index of the silicon oxide layer 31.

[0036] The micro-LED chip provided by the embodiment of the present disclosure includes an epitaxial structure and a light-guiding layer, wherein the light-guiding layer includes multiple layers of titanium oxide layers and multiple layers of silicon oxide layers alternately stacked to form a distributed Bragg reflector. In the silicon oxide layer, a plurality of spaced columnar structures are embedded, and since the columnar structure extends in a direction perpendicular to the light-emitting surface, that is, the extension direction of the columnar structure is parallel to the light-emitting direction of the epitaxial structure, and the refractive index of the columnar structure is different from the refractive index of the silicon oxide layer, when the light is incident on the interface between the silicon oxide layer and the columnar structure, it can be reflected at the interface, so that when the light emitted by the epitaxial structure enters the silicon oxide layer, the light with a large light-emitting direction deviation angle will be reflected on the side wall of the columnar structure, thereby changing the direction of the light and reducing the light reflected to the side of the chip, so as to enhance the proportion of photons in the light-emitting direction, improve the problem of light crosstalk between chips, reduce the side light-emitting ratio, and improve the luminous effect.

[0037] Alternatively, if Figure 1 As shown, the micro light emitting diode chip also includes a first electrode 21, a second electrode 22 and a transparent conductive layer 41. The first electrode 21 is located on the surface of the first semiconductor layer 11 away from the second semiconductor layer 13. The transparent conductive layer 41 is located on the surface of the light guide layer 30 away from the first semiconductor layer 11 and connected to the second semiconductor layer 13. The second electrode 22 is located on the surface of the transparent conductive layer 41.

[0038] Exemplarily, a through hole may be provided on the light guide layer 30 , so that the transparent conductive layer 41 may be connected to the second semiconductor layer 13 through the through hole, thereby allowing the second electrode 22 on the transparent conductive layer 41 to be connected to the second semiconductor layer 13 .

[0039] The transparent conductive layer 41 is an indium tin oxide (ITO film layer for short). The ITO film layer has good transmittance and low resistivity, facilitates carrier conduction, and improves injection efficiency.

[0040] Exemplarily, the thickness of the transparent conductive layer 41 is 800 angstroms to 1200 angstroms.

[0041] The thickness of the transparent conductive layer 41 affects the light transmission effect and resistance value of the transparent conductive layer 41. If the thickness is set too low or too high, the light transmission effect of the transparent conductive layer 41 will be poor, which is not conducive to the injection of carriers. Within this thickness range, a transparent conductive layer 41 with high light transmission effect and low resistance value can be formed, which is conducive to improving the light-emitting effect of the light-emitting diode.

[0042] As an example, in the embodiment of the present disclosure, the thickness of the transparent conductive layer 41 is 1000 angstroms.

[0043] In the embodiment of the present disclosure, one of the first semiconductor layer 11 and the second semiconductor layer 13 is a p-type layer, and the other of the first semiconductor layer 11 and the second semiconductor layer 13 is an n-type layer.

[0044] As an example, the first semiconductor layer 11 is an n-type layer, and the first electrode 21 is an n-type electrode. The second semiconductor layer 13 is a p-type layer, and the second electrode 22 is a p-type electrode.

[0045] Optionally, the columnar structure 33 is a cylinder, and the diameter of the columnar structure 33 is 0.05 μm to 0.2 μm.

[0046] By setting the columnar structure 33 to be a cylinder and setting the diameter of the columnar structure 33 to be within the above range, it can be ensured that the columnar structure 33 has a sufficiently large side wall for reflecting the light emitted by the epitaxial structure 1, so as to reduce the light emitted to the side of the chip, thereby enhancing the proportion of photons in the light output direction, improving the problem of light crosstalk between chips, reducing the side light output ratio, and improving the light-emitting effect.

[0047] Exemplarily, the diameter of the columnar structure 33 is 0.1 μm.

[0048] Optionally, the columnar structure 33 can be distributed in the silicon oxide layer 31 in an array manner. In this way, a plurality of evenly distributed columnar structures 33 are set in the silicon oxide layer 31, which can ensure that most of the area in the silicon oxide layer 31 is filled with the columnar structure 33, so as to ensure that most of the light that deviates greatly from the light emitting direction will be reflected at the side wall of the columnar structure 33, thereby reducing the light emitted to the side of the chip and enhancing the proportion of photons in the light emitting direction.

[0049] In the disclosed embodiment, the length of the columnar structure 33 is not greater than the thickness of the silicon oxide layer 31 , so as to prevent the columnar structure 33 filled in the silicon oxide layer 31 from being too long and exceeding the silicon oxide layer 31 .

[0050] Exemplarily, the length of the columnar structure 33 may be 0.2 μm to 0.4 μm. As an example, the length of the columnar structure 33 may be 0.3 μm.

[0051] Optionally, the columnar structure 33 is made of titanium oxide. Titanium oxide and silicon oxide have different refractive indices, so titanium oxide is used in the silicon oxide layer 31 to form a boundary surface for light reflection, thereby reducing the light emitted to the side of the chip and increasing the proportion of photons in the light-emitting direction.

[0052] Alternatively, if Figure 1 As shown, the orthographic projection of the side wall of the epitaxial structure 1 on the plane where the light emitting surface is located is located within the light emitting surface, and the side wall of the epitaxial structure 1 is provided with an anti-reflection film 51, which covers the side wall of the first semiconductor layer 11, the side wall of the multi-quantum well layer 12 and the side wall of the second semiconductor layer 13.

[0053] Figure 3 FIG. 5 is a partially enlarged schematic diagram of an antireflection film 51 provided in an embodiment of the present disclosure. Figure 3 As shown, the surface of the antireflection film 51 away from the epitaxial structure 1 has a protrusion 52, and the extension direction of the protrusion 52 is perpendicular to the light emitting surface.

[0054] By making an anti-reflection film 51 with a protrusion 52 on the side of the chip, since the extension direction of the protrusion 52 is parallel to the light emitting direction of the epitaxial structure 1, the light emitted from the side of the chip is emitted through the anti-reflection film 51, and then the photons are guided to the bottom of the chip under the reflection of the protrusion 52 and are then absorbed by the light-absorbing material, thereby further reducing the proportion of side photons and reducing the optical crosstalk problem to a very low level.

[0055] Alternatively, if Figure 1 As shown, the micro-LED chip also includes a passivation layer 42, which is located on the surface of the transparent conductive layer 41 away from the epitaxial structure 1. The surface of the passivation layer 42 has a via 43 exposing the transparent conductive layer 41, and the second electrode 22 is located in the via 43 and connected to the transparent conductive layer 41.

[0056] The passivation layer 42 covers the surface of the transparent conductive layer 41 and does not extend to the sidewall of the epitaxial structure 1 .

[0057] In the disclosed embodiment, the passivation layer 42 may be a polysilicon layer. Using the polysilicon layer as the passivation layer 42 may effectively isolate the external environment and the epitaxial structure 1 and the transparent conductive layer 41, thereby preventing short circuit and leakage problems.

[0058] Exemplarily, the thickness of the passivation layer 42 is 300 angstroms to 1000 angstroms. For example, the thickness of the passivation layer 42 is 600 angstroms.

[0059] Alternatively, if Figure 1 As shown, the first electrode 21 includes a plurality of electrode blocks 210 , and the plurality of electrode blocks 210 are distributed on the surface of the first semiconductor layer 11 at intervals.

[0060] By designing the first electrode 21 as a plurality of dispersed electrode blocks 210, the purpose of conducting the first electrode 21 can be achieved by only manufacturing a small number of electrode blocks 210. At the same time, the first electrode 21 can be prevented from blocking light to the greatest extent, thereby ensuring the light emitting effect of the micro LED chip.

[0061] In the embodiment of the present disclosure, the electrode block 210 may be cylindrical.

[0062] Optionally, the first electrode 21 includes a chromium layer, a tin-indium alloy layer and an indium layer sequentially stacked on the first semiconductor layer 11. The tin-indium alloy layer is arranged between the chromium layer and the indium layer. Since the tin-indium alloy layer contains indium metal, the tin-indium alloy layer and the indium layer can be well connected together to improve the conformal effect of the three-layer stacked metal layer.

[0063] The thickness of the chromium layer in the first electrode 21 may be 100 angstroms to 300 angstroms, the thickness of the tin-indium alloy layer may be 8000 angstroms to 12000 angstroms, and the thickness of the indium layer may be 8000 angstroms to 12000 angstroms.

[0064] As an example, in the embodiment of the present disclosure, the thickness of the chromium layer is 200 angstroms, the thickness of the tin-indium alloy layer is 10,000 angstroms, and the thickness of the indium layer is 10,000 angstroms.

[0065] Optionally, the second electrode 22 is in a block shape, and the second electrode 22 is opposite to the middle of the transparent conductive layer 41. In this way, the current will focus on flowing in the central area of ​​the micro-LED chip, and the current density in the edge area of ​​the micro-LED chip is lower, which can effectively reduce the luminous intensity of the edge area of ​​the micro-LED chip.

[0066] Exemplarily, the second electrode 22 is rectangular. The rectangular second electrode 22 can more completely cover the central area of ​​the micro-LED chip to ensure the luminous intensity of the edge area of ​​the micro-LED chip.

[0067] It should be noted that in some other implementations, the second electrode 22 may also be in various shapes such as circular, polygonal, etc., which is not limited in the embodiment of the present disclosure.

[0068] Optionally, the second electrode 22 includes a chromium layer, a titanium layer, a gold layer, and an indium layer sequentially stacked on the surface of the transparent conductive layer 41 .

[0069] The thickness of the chromium layer in the second electrode 22 may be 100 angstroms to 300 angstroms, the thickness of the titanium layer may be 100 angstroms to 300 angstroms, the thickness of the gold layer may be 2000 angstroms to 4000 angstroms, and the thickness of the indium layer may be 4000 angstroms to 6000 angstroms.

[0070] As an example, in the embodiment of the present disclosure, the thickness of the chromium layer in the second electrode 22 is 200 angstroms, the thickness of the titanium layer is 200 angstroms, the thickness of the gold layer is 3000 angstroms, and the thickness of the indium layer is 5000 angstroms.

[0071] Optionally, the first semiconductor layer 11 is a silicon-doped n-type GaN layer, and the thickness of the n-type GaN layer may be 0.5 μm to 3 μm.

[0072] Optionally, the multi-quantum well layer 12 includes alternately grown InGaN quantum well layers and GaN quantum barrier layers, wherein the multi-quantum well layer 12 may include 3 to 8 periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0073] As an example, in the embodiment of the present disclosure, the multi-quantum well layer 12 includes five periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0074] Optionally, the thickness of the multi-quantum well layer 12 may be 150 nm to 200 nm.

[0075] Optionally, the second semiconductor layer 13 is a magnesium-doped p-type GaN layer. The thickness of the p-type GaN layer may be 0.5 μm to 3 μm.

[0076] Figure 4 FIG. 1 is a flow chart of a method for preparing a micro light emitting diode chip provided by an embodiment of the present disclosure. Figure 4 As shown, the preparation method comprises:

[0077] Step S11: providing a substrate.

[0078] Step S12: growing an epitaxial structure 1 on the substrate.

[0079] like Figure 1 As shown, the epitaxial structure 1 includes a first semiconductor layer 11, a multi-quantum well layer 12 and a second semiconductor layer 13 which are stacked in sequence.

[0080] Step S13 : forming a light guide layer 30 on a surface of the second semiconductor layer 13 away from the first semiconductor layer 11 .

[0081] Among them, the surface of the epitaxial structure 1 away from the light-guiding layer 30 is the light-emitting surface. The light-guiding layer 30 includes multiple layers of titanium oxide layers 32 and multiple layers of silicon oxide layers 31 that are alternately stacked. The silicon oxide layer 31 is embedded with multiple spaced-apart columnar structures 33. The columnar structure 33 extends in a direction perpendicular to the light-emitting surface, and the refractive index of the columnar structure is different from that of the silicon oxide layer.

[0082] Step S14 : forming the second electrode 22 on the light guide layer 30 .

[0083] Step S14 may specifically include: first, forming a transparent conductive layer 41 on the light guide layer 30 , and then forming the second electrode 22 on the outer surface of the transparent conductive layer 41 .

[0084] The light guide layer 30 has a through hole exposing the second semiconductor layer 13 , and the transparent conductive layer 41 can be connected to the second semiconductor layer 13 through the through hole, so that the second electrode 22 is connected to the second semiconductor layer 13 .

[0085] Step S15 : removing the substrate and forming a first electrode 21 on a surface of the first semiconductor layer 11 away from the second semiconductor layer 13 .

[0086] The micro light emitting diode chip provided by the embodiment of the present disclosure includes an epitaxial structure 1, a first electrode 21, a second electrode 22 and a light guide layer 30, wherein the first electrode 21 is arranged on the surface of the first semiconductor layer 11, and the second electrode 22 is connected to the second semiconductor layer 13 through a transparent conductive layer 41. A light guide layer 30 is also arranged between the surface of the second semiconductor layer 13 and the transparent conductive layer 41, and the light guide layer 30 includes multiple layers of titanium oxide layers 32 and multiple layers of silicon oxide layers 31 alternately stacked to form a distributed Bragg reflector. Among them, a plurality of spaced columnar structures 33 are embedded in the silicon oxide layer 31. Since the columnar structure 33 extends in a direction perpendicular to the light emitting surface, that is, the extension direction of the columnar structure 33 is parallel to the light emitting direction of the epitaxial structure 1, and the refractive index of the columnar structure is different from that of the silicon oxide layer, when the light emitted by the epitaxial structure 1 enters the silicon oxide layer 31, the light with a large deviation angle in the light emitting direction will be reflected at the side wall of the columnar structure 33, thereby changing the light direction of the light and reducing the light emitted to the side of the chip, so as to enhance the proportion of photons in the light emitting direction, improve the problem of light crosstalk between chips, reduce the side light emitting ratio, and enhance the luminous effect.

[0087] In step S11, the substrate is a sapphire substrate 60, a silicon substrate or a silicon carbide substrate. The substrate can be a flat substrate or a patterned substrate.

[0088] As an example, in the embodiment of the present disclosure, the substrate is a sapphire substrate 60. The sapphire substrate 60 is a commonly used substrate with mature technology and low cost. Specifically, it can be a patterned sapphire substrate 60 or a sapphire flat sheet substrate.

[0089] The sapphire substrate 60 may be pre-treated, placed in a MOCVD (Metal-organic Chemical Vapor Deposition) reaction chamber, and baked for 12 to 18 minutes. As an example, in the embodiment of the present disclosure, the sapphire substrate 60 is baked for 15 minutes.

[0090] Specifically, the baking temperature may be 1000° C. to 1200° C., and the pressure in the MOCVD reaction chamber during baking may be 100 mbar to 200 mbar.

[0091] like Figure 5 As shown, growing the first semiconductor layer 11 in step S12 may include: forming the first semiconductor layer 11 on the sapphire substrate 60 by MOCVD technology.

[0092] The first semiconductor layer 11 is an n-type GaN layer. The growth temperature of the n-type GaN layer may be 1000° C. to 1100° C., and the growth pressure of the n-type GaN layer may be 100 torr to 300 torr.

[0093] Optionally, the thickness of the n-type GaN layer is 0.5 μm to 3 μm. For example, the thickness of the n-type GaN layer may be 1 μm.

[0094] like Figure 5 As shown, growing the multi-quantum well layer 12 in step S12 may include: forming the multi-quantum well layer 12 on the n-type GaN layer.

[0095] The multi-quantum well layer 12 includes alternately grown InGaN quantum well layers and GaN quantum barrier layers. The multi-quantum well layer 12 may include 3 to 8 periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0096] As an example, in the embodiment of the present disclosure, the multi-quantum well layer 12 includes five periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0097] Optionally, the thickness of the multi-quantum well layer 12 may be 150 nm to 200 nm.

[0098] When growing the multi-quantum well layer 12, the pressure of the MOCVD reaction chamber is controlled at 200torr. When growing the InGaN quantum well layer, the temperature of the reaction chamber is 760° C. to 780° C. When growing the GaN quantum barrier layer, the temperature of the reaction chamber is 860° C. to 890° C. The quality of the multi-quantum well layer 12 grown under this process condition is better.

[0099] like Figure 5 As shown, growing the second semiconductor layer 13 in step S12 may include: forming a p-type GaN layer on the multi-quantum well layer 12 .

[0100] Optionally, the p-type GaN layer has a thickness of 0.5 μm to 3 μm. For example, the p-type GaN layer has a thickness of 1 μm.

[0101] When growing the p-type GaN layer, the growth pressure of the p-type GaN layer may be 200 Torr to 600 Torr, and the growth temperature of the p-type GaN layer may be 800° C. to 1000° C.

[0102] In step S13 , manufacturing the light guide layer 30 may include: alternately forming multiple layers of silicon oxide layers 31 and titanium oxide layers 32 on the surface of the second semiconductor layer 13 in sequence.

[0103] The process of forming the silicon oxide layer 31 may include: first forming a silicon oxide film layer, then etching the surface of the silicon oxide film layer to form a blind hole, then using titanium oxide to make a columnar structure 33 in the blind hole, and finally forming a silicon oxide film of a certain thickness on the surface of the silicon oxide film to cover the columnar structure 33 to form a silicon oxide layer 31.

[0104] In the embodiment of the present disclosure, the columnar structure 33 is a cylinder with a diameter of 0.05 μm to 0.2 μm. For example, the diameter of the columnar structure 33 is 0.1 μm.

[0105] Exemplarily, the length of the columnar structure 33 may be 0.2 μm to 0.4 μm. For example, the length of the columnar structure 33 is 0.3 μm.

[0106] Optionally, in the light guiding layer 30 , the thickness of the third, sixth and ninth silicon oxide layers 31 may be set to 0.4 μm, and the thickness of the remaining silicon oxide layers 31 may be set to 900 angstroms.

[0107] Optionally, step S14 may include: forming a transparent conductive layer 41 on the surface of the light guide layer 30 , the transparent conductive layer 41 is located on the surface of the light guide layer 30 away from the first semiconductor layer 11 and connected to the second semiconductor layer 13 ; and forming a second electrode 22 on the transparent conductive layer 41 .

[0108] Exemplarily, the thickness of the transparent conductive layer 41 is 800 angstroms to 1200 angstroms.

[0109] The thickness of the transparent conductive layer 41 affects the light transmission effect and resistance value of the transparent conductive layer 41. If the thickness is set too low or too high, the light transmission effect of the transparent conductive layer 41 will be poor, which is not conducive to the injection of carriers. Within this thickness range, a transparent conductive layer 41 with high light transmission effect and low resistance value can be formed, which is conducive to improving the light-emitting effect of the light-emitting diode.

[0110] As an example, in the embodiment of the present disclosure, the thickness of the transparent conductive layer 41 is 1000 angstroms.

[0111] Step S14 may further include forming a passivation layer 42 . In the first step, a polysilicon layer is deposited on the surface of the transparent conductive layer 41 . In the second step, the polysilicon layer is oxidized by pressure oxidation to form the passivation layer 42 .

[0112] Exemplarily, the thickness of the polysilicon layer is 300 angstroms to 1000 angstroms. For example, the thickness of the polysilicon layer is 500 angstroms. By doping oxygen in the polysilicon layer, the density of the polysilicon layer can be increased to prevent the crystals in the third polysilicon layer from being too sparse.

[0113] In the second step, pressure oxidation can be used to fully diffuse oxygen into the polysilicon to achieve full oxidation.

[0114] The formed passivation layer 42 has a via hole 43 exposing the transparent conductive layer 41 .

[0115] like Figure 5 As shown, step S14 may include: forming a second electrode 22 on the surface of the transparent conductive layer 41 through the via hole 43 .

[0116] The second electrode 22 includes a chromium layer, a titanium layer, a gold layer and an indium layer sequentially stacked on the surface of the transparent conductive layer 41 .

[0117] The thickness of the chromium layer in the second electrode 22 may be 100 angstroms to 300 angstroms, the thickness of the titanium layer may be 100 angstroms to 300 angstroms, the thickness of the gold layer may be 2000 angstroms to 4000 angstroms, and the thickness of the indium layer may be 4000 angstroms to 6000 angstroms.

[0118] As an example, in the embodiment of the present disclosure, the thickness of the chromium layer in the second electrode 22 is 200 angstroms, the thickness of the titanium layer is 200 angstroms, the thickness of the gold layer is 3000 angstroms, and the thickness of the indium layer is 5000 angstroms.

[0119] After step S14 , the method may further include: bonding the prepared epitaxial structure 1 to a double-polished sapphire substrate 60 , with the passivation layer 42 and the second electrode 22 facing the double-polished sapphire substrate 60 .

[0120] The bonding material may be photoresist, SOG (Silicon On Glass, silicon-glass bonding structure) and silica gel.

[0121] Optionally, the side wall of the epitaxial structure 1 is an inclined surface, and its orthographic projection on the plane where the light emitting surface is located is located inside the light emitting surface.

[0122] like Figure 5 As shown, after the light guiding layer 30 is produced on the surface of the second semiconductor layer 13 away from the first semiconductor layer 11, the method includes: producing an anti-reflection film 51 on the side wall of the epitaxial structure 1, the anti-reflection film 51 covers the side wall of the first semiconductor layer 11, the side wall of the multi-quantum well layer 12 and the side wall of the second semiconductor layer 13, and the surface of the anti-reflection film 51 away from the epitaxial structure 1 has a protrusion 52, and the extension direction of the protrusion 52 is perpendicular to the light emitting surface.

[0123] By making an anti-reflection film 51 with a protrusion 52 on the side of the chip, since the extension direction of the protrusion 52 is parallel to the light emitting direction of the epitaxial structure 1, the light emitted from the side of the chip is emitted through the anti-reflection film 51, and then the photons are guided to the bottom of the chip under the reflection of the protrusion 52 and are then absorbed by the light-absorbing material, thereby further reducing the proportion of side photons and reducing the optical crosstalk problem to a very low level.

[0124] Step S15 may include: removing the sapphire substrate 60 below the first semiconductor layer 11 by laser lift-off and forming the first electrode 21 on a surface of the first semiconductor layer 11 away from the second semiconductor layer 13 .

[0125] Among them, the laser wavelength is 266 nanometers, and the Ga metal needs to be rinsed off with acid after stripping.

[0126] Step S15 may include: evaporating the first electrode 21 on the surface of the first semiconductor layer 11. The first electrode 21 includes a chromium layer, a tin-indium alloy layer and an indium layer sequentially stacked on the first semiconductor layer 11.

[0127] The thickness of the chromium layer in the first electrode 21 may be 100 angstroms to 300 angstroms, the thickness of the tin-indium alloy layer may be 8000 angstroms to 12000 angstroms, and the thickness of the indium layer may be 8000 angstroms to 12000 angstroms.

[0128] As an example, in the embodiment of the present disclosure, the thickness of the chromium layer is 200 angstroms, the thickness of the tin-indium alloy layer is 10,000 angstroms, and the thickness of the indium layer is 10,000 angstroms.

[0129] After step S15, a passivation structure may be fabricated to complete the preparation of the micro light emitting diode chip.

[0130] The above does not limit the present disclosure in any form. Although the present disclosure has been disclosed as above through the embodiments, it is not used to limit the present disclosure. Any technician familiar with the profession can make some changes or modifications to equivalent embodiments of equivalent changes using the technical contents disclosed above without departing from the scope of the technical solution of the present disclosure. However, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present disclosure without departing from the content of the technical solution of the present disclosure still falls within the scope of the technical solution of the present disclosure.

Claims

1. A micro light emitting diode chip, It is characterized in that The micro light emitting diode chip comprises: an epitaxial structure (1) and a light guide layer (30); The epitaxial structure (1) comprises a first semiconductor layer (11), a multi-quantum well layer (12) and a second semiconductor layer (13) which are stacked in sequence; the light-guiding layer (30) is located on a surface of the second semiconductor layer (13) away from the first semiconductor layer (11); and the surface of the epitaxial structure (1) away from the light-guiding layer (30) is a light-emitting surface; The light guide layer (30) comprises a plurality of titanium oxide layers (32) and a plurality of silicon oxide layers (31) that are alternately stacked, the silicon oxide layer (31) being embedded with a plurality of columnar structures (33) that are spaced apart, the columnar structures (33) extending in a direction perpendicular to the light emitting surface, and the refractive index of the columnar structures (33) being different from the refractive index of the silicon oxide layer (31); The orthographic projection of the side wall of the epitaxial structure (1) on the plane where the light emitting surface is located is located within the light emitting surface, the side wall of the epitaxial structure (1) is provided with an anti-reflection film (51), the anti-reflection film (51) covers the side wall of the first semiconductor layer (11), the side wall of the multi-quantum well layer (12) and the side wall of the second semiconductor layer (13), and the surface of the anti-reflection film (51) away from the epitaxial structure (1) has a protrusion (52), and the extension direction of the protrusion (52) is perpendicular to the light emitting surface.

2. The micro light emitting diode chip according to claim 1, It is characterized in that The columnar structure (33) is a cylinder, and the diameter of the columnar structure (33) is 0.05 μm to 0.2 μm.

3. The micro light emitting diode chip according to claim 1, It is characterized in that The columnar structure (33) is made of titanium oxide.

4. The micro light emitting diode chip according to any one of claims 1 to 3, It is characterized in that The micro light emitting diode chip further comprises a first electrode (21), a second electrode (22) and a transparent conductive layer (41); the first electrode (21) is located on a surface of the first semiconductor layer (11) away from the second semiconductor layer (13); the transparent conductive layer (41) is located on a surface of the light guide layer (30) away from the first semiconductor layer (11) and connected to the second semiconductor layer (13); and the second electrode (22) is located on a surface of the transparent conductive layer (41).

5. The micro light emitting diode chip according to claim 4, It is characterized in that The first electrode (21) comprises a plurality of electrode blocks (210), and the plurality of electrode blocks (210) are distributed at intervals on the surface of the first semiconductor layer (11).

6. A method for preparing a micro light emitting diode chip, It is characterized in that The preparation method comprises: providing a substrate; Growing an epitaxial structure on the substrate, the epitaxial structure comprising a first semiconductor layer, a multi-quantum well layer, and a second semiconductor layer stacked in sequence; A light-guiding layer is fabricated on a surface of the second semiconductor layer away from the first semiconductor layer, a surface of the epitaxial structure away from the light-guiding layer is a light-emitting surface, the light-guiding layer comprises a plurality of titanium oxide layers and a plurality of silicon oxide layers which are alternately stacked, a plurality of spaced columnar structures are embedded in the silicon oxide layer, the columnar structures extend in a direction perpendicular to the light-emitting surface, the refractive index of the columnar structures is different from that of the silicon oxide layer, and the orthographic projection of the side wall of the epitaxial structure on the plane where the light-emitting surface is located is located within the light-emitting surface; An anti-reflection film is made on the side wall of the epitaxial structure, the anti-reflection film covers the side wall of the first semiconductor layer, the side wall of the multi-quantum well layer and the side wall of the second semiconductor layer, and the surface of the anti-reflection film away from the epitaxial structure has a protrusion, and the extension direction of the protrusion is perpendicular to the light emitting surface.

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