Methods and apparatus for concisely describing lifted low-density parity-check (LDPC) codes.

Abstract

Certain aspects of this disclosure generally relate to techniques for concisely describing raised quasi-cyclic low-density parity-check (LDPC) codes. A method for wireless communication by a transmitting device generally includes: selecting a first raised size value Z and a first set of raised values ​​for generating a first raised LDPC code (1302). The first raised LDPC code is generated by applying the first set of raised values ​​to the edges of Z copies of an interconnected basis parity-check matrix (PCM) to obtain a first raised PCM corresponding to the first raised LDPC code (1304). The method further includes: determining a second set of raised values ​​based on the first set of raised values ​​for generating a second raised PCM corresponding to a second raised LDPC code with the second raised size value (1306); encoding a set of information bits based on at least one of the first raised LDPC code or the second raised LDPC code to produce a codeword (1308); and transmitting the codeword (1310).

Description

[0001] This application is a divisional application of the application filed on June 14, 2017, with application number 201780036600.5 (international application number PCT / US2017 / 037468) entitled "Method and apparatus for concisely describing enhanced low-density parity-check (LDPC) codes".

[0002] Cross-reference and priority claims of related applications

[0003] This application claims the benefit and priority of U.S. Provisional Patent Application No. 62 / 349,784 (163764P1), filed June 14, 2016; U.S. Provisional Patent Application No. 62 / 374,514 (164403P1), filed August 12, 2016; and U.S. Patent Application No. 15 / 622,019 (163764), filed June 13, 2017, all of which are incorporated herein by reference in their entirety for all applicable purposes. Technical Field

[0004] Some aspects of the techniques discussed below generally relate to wireless communication, including error detection and / or error correction in binary data, and in particular to methods and apparatus for concisely describing raised low-density parity-check (LDPC) codes.

[0005] introduction

[0006] Wireless communication systems are widely deployed to provide various types of communication content, such as voice, video, data, messaging, and broadcasting. These systems can employ multiple access technologies capable of supporting communication with multiple users by sharing available system resources (e.g., bandwidth and transmit power). Examples of such multiple access systems include Code Division Multiple Access (CDMA) systems, Time Division Multiple Access (TDMA) systems, Time Division Synchronous CDMA (TD-SCDMA) systems, Frequency Division Multiple Access (FDMA) systems, Single Carrier FDMA (SC-FDMA) systems, Orthogonal FDMA (OFDMA), 3rd Generation Partnership Project (3GPP) Long Term Evolution (LTE) systems, and LTE-Advanced (LTE-A) systems.

[0007] Multiple access technology has been adopted in various telecommunications standards to provide a common protocol enabling different wireless devices to communicate at the city, country, region, and even global levels. An example of an emerging telecommunications standard is New Radio (NR), such as 5G Radio Access. NR is an enhancement set of the LTE mobile standard issued by 3GPP. It is designed to better support mobile broadband internet access by improving spectrum efficiency, reducing costs, improving service, utilizing new spectrum, and better integrating with other open standards using OFDMA with a cyclic prefix (CP) on both the downlink (DL) and uplink (UL), as well as supporting beamforming, multiple-input multiple-output (MIMO) antenna technology, and carrier aggregation.

[0008] Generally, a wireless multiple access communication system can support communication between multiple wireless nodes simultaneously. Each node communicates with one or more base stations (BSs) via forward and reverse links. The forward link (or downlink) is the communication link from the BS to the node, while the reverse link (or uplink) is the communication link from the node to the base station. Communication links can be established via single-input single-output, multiple-input single-output, or MIMO systems.

[0009] In some examples, a radio multiple access communication system may include several base stations (BSs), each BS simultaneously supporting communication from multiple communication devices (also known as user equipment (UE)). In LTE or LTE-A networks, a set containing one or more BSs can define an evolved B-node (eNB). In other examples (e.g., in next-generation, NR, or 5G networks), a radio multiple access communication system may include several distributed units (DUs) (e.g., edge units (EUs), edge nodes (ENs), radio heads (RHs), smart radio heads (SRHs), transmit receiver points (TRPs), etc.) communicating with several central units (CUs) (e.g., central nodes (CNs), access node controllers (ANCs), etc.), and a set containing one or more DUs communicating with the CUs can define access nodes (e.g., BSs, NR BSs, 5G BSs, NBs, eNBs, NR NBs, 5G NBs, access points (APs), network nodes, gNBs, TRPs, etc.). The BS, AN, or DU can communicate with the UE or a set of UEs on downlink channels (e.g., for transmissions from the BS or to the UE) and uplink channels (e.g., for transmissions from the UE to the BS, AN, or DU).

[0010] Binary values ​​(e.g., 1 and 0) are used to represent and convey various types of information, such as video, audio, statistics, etc. Unfortunately, errors can be unintentionally introduced during the storage, transmission, and / or processing of binary data; for example, a "1" might be changed to a "0", or vice versa.

[0011] Generally, in data transmission, the receiver observes each received bit in the presence of noise or distortion and only obtains an indication of the value of that bit. In these situations, the observed value is interpreted as the source of "soft" bits. Soft bits indicate a preferred estimate of the value of that bit (e.g., 1 or 0) along with some indication of the reliability of that estimate. Although the number of errors may be relatively low, even a small number of errors or distortions can render the data unusable or, in cases of transmission errors, may necessitate retransmission. To provide a mechanism for checking for and, in some cases, correcting errors, binary data can be encoded to introduce carefully designed redundancy. Encoding data units produces what is commonly called codewords. Due to their redundancy, codewords will typically include more bits than the input data unit from which they were generated.

[0012] Redundant bits are added to the transmitted bitstream by an encoder to create codewords. When the signal generated by the transmitted codewords is received or processed, the redundant information included in the codewords observed in the signal can be used to identify and / or correct errors in the received signal or remove distortions from the received signal to recover the original data units. Such error detection and / or correction can be implemented as part of the decoding process. In the absence of errors or in cases where errors or distortions can be corrected, decoding can be used to recover the encoded original data units from the source data being processed. In the case of unrecoverable errors, the decoding process can generate an indication that the original data cannot be fully recovered. Such an indication of decoding failure initiates a retransmission of the data. With the use of fiber optic cables in data communications and the increasing rates at which data can be read from / stored on / to data storage devices (e.g., disk drives, magnetic tapes, etc.), there is a growing need for efficient use of data storage and transmission capacity, as well as the ability to encode and decode data at high rates.

[0013] Brief Overview

[0014] The following outlines some aspects of this disclosure to provide a basic understanding of the techniques discussed. This overview is not an exhaustive summary of all conceived features of this disclosure, and is neither intended to identify key or decisive elements of all aspects of this disclosure nor to define the scope of any or all aspects of this disclosure. Its sole purpose is to provide some concepts of one or more aspects of this disclosure in an overview form as a prelude to the more detailed description that follows. After considering this discussion, and especially after reading the section entitled “Detailed Description,” it will be understood how the features of this disclosure provide advantages, including improved communication between access points and stations in wireless networks.

[0015] While encoding efficiency and high data rates are important, it is equally important that encoders and / or decoders can be implemented at a reasonable cost for encoding and / or decoding systems that are actually intended for use in a wide range of devices (e.g., consumer devices).

[0016] Communication systems typically need to operate at several different rates. Low-density parity-check (LDPC) codes can be used to provide a simple implementation of encoding and decoding at different rates. For example, higher-rate LDPC codes can be generated by puncturing lower-rate LDPC codes.

[0017] With the continued growth in demand for mobile broadband access, there is a need for further improvements to NR technology. Preferably, these improvements can or should be applied to other multiple access technologies and telecommunications standards that employ these technologies. One area of ​​improvement is the encoding / decoding field for data transmission. These improvements (e.g., improved LDPC codes) can be applied to NR and other access technologies.

[0018] Certain aspects of this disclosure generally relate to methods and apparatus for concisely describing multiple raised low-density parity-check (LDPC) codes.

[0019] Certain aspects of this disclosure provide a method for wireless communication that can be performed by a transmitting device. The method generally includes selecting a first lift size value Z and a first set of lift values ​​for generating a first lifted LDPC code. The transmitting device generates a first lifted LDPC code by applying the first set of lift values ​​to interconnect edges in Z copies of a base parity check matrix (PCM) to obtain a first lifted PCM corresponding to the first lifted LDPC code. The base PCM has a first number of base variable nodes and a second number of base parity nodes (edges are connections between variable nodes and parity nodes). The transmitting device may determine a second set of lift values ​​based on the first lifted PCM and the first set of lift values ​​to generate a second lifted PCM corresponding to a second lifted LDPC code with a second lift size value. The transmitting device may encode a set of information bits based on the first lifted LDPC code and / or the second lifted LDPC code to generate a codeword and transmit the codeword.

[0020] This disclosure provides, in certain aspects, an apparatus for wireless communication that can be performed by a transmitting device. The apparatus generally includes: means for selecting a first lift size value Z and a first set of lift values ​​for generating a first lifted LDPC code; and means for generating a first lifted LDPC code by applying the first set of lift values ​​to interconnect edges in Z copies of a base PCM to obtain a first lifted LDPC code corresponding to the first lifted LDPC code, the base PCM having a first number of base variable nodes and a second number of base parity nodes. The apparatus further includes: means for determining a second set of lift values ​​based on the first lifted PCM and the first set of lift values ​​for generating a second lifted PCM corresponding to a second lifted LDPC code with a second lift size value; means for encoding a set of information bits based on at least one of the first lifted LDPC code or the second lifted LDPC code to generate a codeword; and means for transmitting the codeword.

[0021] Certain aspects of this disclosure provide an apparatus for wireless communication, executable by a transmitting device. The apparatus generally includes at least one processor coupled to a memory. The at least one processor is configured to: select a first boost size value Z and a first set of boost values ​​for generating a first boosted LDPC code; and generate a first boosted LDPC code by applying the first set of boost values ​​to interconnect edges in Z copies of a base PCM to obtain a first boosted PCM corresponding to the first boosted LDPC code, the base PCM having a first number of base variable nodes and a second number of base parity nodes. The at least one processor is further configured to: determine a second set of boost values ​​based on the first boosted PCM and the first set of boost values ​​for generating a second boosted PCM corresponding to a second boosted LDPC code with a second boost size value; and encode a set of information bits based on at least one of the first or second boosted LDPC code to generate a codeword. The apparatus includes a transmitter configured to transmit the codeword.

[0022] This disclosure provides, in certain aspects, a computer-readable medium executable by a transmitting device, on which computer-executable code for wireless communication is stored. The code generally includes: code for selecting a first boost size value Z and a first set of boost values ​​for generating a first boosted LDPC code; and code for generating a first boosted LDPC code by applying the first set of boost values ​​to interconnect edges in Z copies of a base PCM to obtain a first boosted PCM corresponding to the first boosted LDPC code, the base PCM having a first number of base variable nodes and a second number of base parity nodes. The code further includes: code for determining a second set of boost values ​​based on the first boosted PCM and the first set of boost values ​​for generating a second boosted PCM corresponding to a second boosted LDPC code with a second boost size value; code for encoding a set of information bits based on at least one of the first or second boosted LDPC code to generate a codeword; and code for transmitting the codeword.

[0023] Other aspects, features, and embodiments of this disclosure will become apparent to those skilled in the art after reading the following description of specific exemplary aspects of this disclosure in conjunction with the accompanying drawings. Although features of this disclosure may be discussed hereinafter with respect to certain aspects and drawings, all aspects of this disclosure may include one or more of the advantageous features discussed herein. In other words, although one or more aspects may be discussed having certain advantageous features, one or more such features may also be used according to the various aspects of this disclosure discussed herein. Similarly, although exemplary aspects may be discussed hereinafter as embodiments of an apparatus, system, or method, such exemplary embodiments may be implemented in a variety of apparatuses, systems, and methods. Brief description of the attached diagram

[0024] To gain a more detailed understanding of the manner in which the features described above are presented in this disclosure, reference can be made to various aspects of the above brief overview, some of which are illustrated in the accompanying drawings. However, the drawings illustrate only certain typical aspects of this disclosure and should not be considered as limiting its scope, as other equivalent aspects are permissible in this description.

[0025] Figure 1 It is a block diagram that conceptually illustrates an example wireless communication system according to certain aspects of this disclosure.

[0026] Figure 2 This is a block diagram illustrating an example logical architecture of a distributed RAN according to certain aspects of this disclosure.

[0027] Figure 3 This is a diagram illustrating an example physical architecture of a distributed RAN according to certain aspects of this disclosure.

[0028] Figure 4 It is a block diagram that conceptually illustrates the design of an example base station (BS) and user equipment (UE) according to certain aspects of this disclosure.

[0029] Figure 5 This is a diagram illustrating an example of implementing a communication protocol stack according to certain aspects of this disclosure.

[0030] Figure 6 Examples of downlink (DL) center-type subframes according to certain aspects of this disclosure are explained.

[0031] Figure 7 Examples of uplink (UL) center-type subframes according to certain aspects of this disclosure are explained.

[0032] Figure 8 It is a graphical representation of an example low-density parity-check (LDPC) code according to certain aspects of this disclosure.

[0033] Figure 8A Based on certain aspects of this disclosure Figure 8 The matrix representation of an example LDPC code.

[0034] Figure 9 Based on certain aspects of this disclosure Figure 8 A graphical representation of the raised LDPC code.

[0035] Figure 10 It is an integer representation of the matrix used for quasi-cyclic 802.11 LDPC codes, based on some aspects.

[0036] Figure 11 This is a simplified block diagram illustrating an example encoder according to certain aspects of this disclosure.

[0037] Figure 12 This is a simplified block diagram illustrating an example decoder according to certain aspects of this disclosure.

[0038] Figure 13 This is a flowchart illustrating an example operation for generating an enhanced LDPC code from a base parity check matrix (PCM) for wireless communication by a transmitting device, according to certain aspects of this disclosure.

[0039] To facilitate understanding, the same reference numerals are used where possible to designate common elements in the figures. Elements disclosed in one embodiment may be advantageously used in other embodiments without specific reference. Detailed description

[0040] This disclosure provides apparatus, methods, processing systems, and computer program products for encoding (and / or decoding) of new radio (NR) access technologies, such as 5G radio access. NR can refer to a radio configured to operate under a new air interface or fixed transport layer. NR can include enhanced mobile broadband (eMBB) services targeting wide bandwidth (e.g., 80 MHz and above), millimeter wave (mmW) services targeting high carrier frequencies (e.g., 60 GHz), massive machine-type communication (mMTC) services targeting non-backward compatible MTC technologies, and / or mission-critical (MiCr) services targeting ultra-reliable low latency communication (URLLC) services. These services can include latency and reliability requirements, timing requirements, and other design considerations for various applications. NR can use low-density parity-check (LDPC) coding and / or polar codes.

[0041] This disclosure provides techniques and apparatus for concisely describing the structure of LDPC codes. In each aspect, a single base map or parity check matrix (PCM) can be stored for a set of lift sizes (sometimes referred to as a lift family or a lifted LDPC code family). The PCM may correspond to one of the lifts in that set (e.g., minimum or maximum lift), and other members of the family can be generated based on the stored PCM using operations (e.g., floor operations or modulo operations). In each aspect, the same PCM can be used for members of the code family. In each aspect, PCMs for different code families can be generated based on the lift values ​​associated with a family.

[0042] Various aspects of this disclosure are described more fully below with reference to the accompanying drawings. However, this disclosure may be implemented in many different forms and should not be construed as being limited to any specific structure or function given throughout this disclosure. Rather, these aspects are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art. Based on the teachings herein, those skilled in the art will appreciate that the scope of this disclosure is intended to cover any aspect of this disclosure disclosed herein, whether implemented independently of or in combination with any other aspect of this disclosure. For example, any number of aspects set forth herein may be used to implement an apparatus or practice. Furthermore, the scope of this disclosure is intended to cover such apparatuses or methods practiced using additional structures, functionalities, or structures and functionalities that complement or supplement the various aspects of this disclosure set forth herein. It should be understood that any aspect of this disclosure disclosed herein may be implemented by one or more elements of the claims. The term “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as superior to or overriding other aspects.

[0043] While specific aspects are described herein, numerous variations and substitutions of these aspects fall within the scope of this disclosure. Although some benefits and advantages of preferred aspects are mentioned, the scope of this disclosure is not intended to be limited to specific benefits, uses, or objectives. Rather, aspects of this disclosure are intended to be broadly applicable to various wireless technologies, system configurations, networks, and transport protocols, some of which are illustrated by example in the accompanying drawings and the following description of preferred aspects. The detailed description and drawings are merely illustrative and not limiting of this disclosure, the scope of which is defined by the appended claims and their equivalents.

[0044] The techniques described in this article can be used in various wireless communication networks, such as Code Division Multiple Access (CDMA) networks, Time Division Multiple Access (TDMA) networks, Frequency Division Multiple Access (FDMA) networks, Orthogonal FDMA (OFDMA) networks, and Single Carrier FDMA (SC-FDMA) networks. The terms "network" and "system" are often used interchangeably. CDMA networks can implement radio technologies such as Universal Terrestrial Radio Access (UTRA) and CDMA2000. UTRA includes Wideband-CDMA (W-CDMA) and Low Chip Rate (LCR). CDMA2000 encompasses the IS2000, IS-95, and IS-856 standards. TDMA networks can implement radio technologies such as Global System for Mobile Communications (GSM). OFDMA networks can implement technologies such as Evolved UTRA (E-UTRA), IEEE 802.11, IEEE 802.16, IEEE 802.20, and Flash- Radio technologies such as UTRA, E-UTRA, and GSM are part of the Universal Mobile Telecommunications System (UMTS). 3GPP LTE and Advanced LTE (LTE-A) are UMTS versions using E-UTRA. UTRA, E-UTRA, UMTS, LTE, LTE-A, and GSM are described in documents from an organization called the Third Generation Partnership Project (3GPP). CDMA2000 is described in documents from an organization called the Third Generation Partnership Project 2 (3GPP2). NR is an emerging wireless communication technology being developed in collaboration with the 5G Technology Forum (5GTF). These communication networks are listed merely as examples of networks in which the technologies described in this disclosure can be applied; however, this disclosure is not limited to the aforementioned communication networks.

[0045] For clarity, although the aspects herein may be described using terms commonly associated with 3G and / or 4G or LTE wireless technologies, the aspects of this disclosure may be applied in other generations of communication systems, including NR technology, such as 5G and its successors.

[0046] Example wireless communication system

[0047] Figure 1 An example communication network 100 in which various aspects of this disclosure can be performed is described. The wireless communication network 100 may be a New Radio (NR) or 5G network. The wireless communication network 100 may include transmitting devices, such as User Equipment (UE) 120 or Base Station (BS) 110. The transmitting device may perform encoding using raised LDPC codes that can be concisely described (e.g., determined / generated / stored) according to the aspects described herein, and the receiving device (e.g., UE 120 or BS 110) may perform corresponding decoding operations. For example, the transmitting device may select at least one raised size value to generate a set of raised LDPC codes comprising copies of base LDPC codes defined by a base matrix having a first number of base variable nodes and a second number of base check nodes. The raised size value is selected from a range of values. The transmitting device may generate a base matrix based on raised values ​​associated with the selected raised size value in the set of raised values, and generate matrices for different raised size values ​​in that set based on the base matrix.

[0048] like Figure 1 As explained herein, the wireless communication network 100 may include several BSs 110 and other network entities. A BS may be a station communicating with a UE. Each BS 110 may provide communication coverage for a specific geographic area. In 3GPP, the term "cell" may refer to the coverage area of ​​a B-node and / or the B-node subsystem serving that coverage area, depending on the context in which the term is used. In NR systems, the terms "cell" and gNB, B-node, 5G NB, AP, NR BS, NR BS, TRP, etc., may be interchangeable. In some examples, a cell may not be stationary, and the geographic area of ​​a cell may move depending on the location of a mobile BS. In some examples, BSs may interconnect with each other and / or interconnect to one or more other BSs or network nodes (not shown) in the wireless communication network 100 via various types of backhaul interfaces (such as direct physical connections, virtual networks, or similar systems using any suitable transport network).

[0049] Generally, any number of wireless networks can be deployed in a given geographical area. Each wireless network can support a specific Radio Access Technology (RAT) and can operate on one or more frequencies. A RAT can also be referred to as a radio technology, air interface, etc. A frequency can also be referred to as a carrier, channel, etc. Each frequency can support a single RAT in a given geographical area to avoid interference between wireless networks using different RATs. In some cases, NR or 5G RAT networks can be deployed.

[0050] A BS can provide communication coverage for macrocells, picocells, femtocells, and / or other types of cells. Macrocells can cover a relatively large geographic area (e.g., a radius of several kilometers) and allow unrestricted access by UEs with service subscriptions. Picocells can cover a relatively small geographic area and allow unrestricted access by UEs with service subscriptions. Femtocells can cover a relatively small geographic area (e.g., a residential area) and allow restricted access by UEs associated with that femtocell (e.g., UEs in a closed subscriber group (CSG), UEs of users in a residential building, etc.). A BS used for macrocells may be referred to as a macro BS. A BS used for picocells may be referred to as a pico BS. A BS used for femtocells may be referred to as a femto BS or a home BS. Figure 1 In the example shown, BS 110a, BS 110b, and BS 110c can be macro BSs for macro cells 102a, 102b, and 102c, respectively. BS 110x can be a pico BS for pico cell 102x. BS 110y and BS 110z can be femto BSs for femto cells 102y and 102z, respectively. A BS can support one or more (e.g., three) cells.

[0051] The wireless communication network 100 may also include relay stations. A relay station is a station that receives data and / or other information transmissions from an upstream station (e.g., BS 110 or UE 120) and transmits such data and / or other information to a downstream station (e.g., UE 120 or BS 110). A relay station may also be a UE relaying transmissions for other UEs. Figure 1 In the example shown, relay station 110r can communicate with BS 110a and UE 120r to facilitate communication between BS 110a and UE 120r. A relay station may also be referred to as a relay, relay eNB, etc.

[0052] The wireless communication network 100 can be a heterogeneous network comprising different types of base stations (BSs) (e.g., macro BSs, pico BSs, femto BSs, relays, etc.). These different types of BSs may have different transmit power levels, different coverage areas, and different effects on interference in the wireless communication network 100. For example, a macro BS may have a high transmit power level (e.g., 20 watts), while a pico BS, femto BS, and relay may have a lower transmit power level (e.g., 1 watt).

[0053] The wireless communication network 100 can support synchronous or asynchronous operation. For synchronous operation, each BS can have similar frame timing, and transmissions from different BSs can be approximately time-aligned. For asynchronous operation, each BS can have different frame timing, and transmissions from different BSs may not be time-aligned. The techniques described herein can be used for both synchronous and asynchronous operations.

[0054] Network controller 130 can be coupled to a group of BSs and provide coordination and control over these BSs. Network controller 130 can communicate with each BS 110 via backhaul. BS 110 can also communicate with each other directly or indirectly, for example, via wireless or wired backhaul.

[0055] UE 120 (e.g., UE 120x, UE 120y, etc.) may be distributed throughout the wireless communication network 100, and each UE may be stationary or mobile. UE may also be referred to as a mobile station, terminal, access terminal, subscriber unit, station, client equipment (CPE), cellular phone, smartphone, personal digital assistant (PDA), wireless modem, wireless communication device, handheld device, laptop computer, cordless phone, wireless local loop (WLL) station, tablet device, camera, gaming device, netbook, smartbook, ultrabook, medical device or medical equipment, biometric sensor / device, wearable device (such as smartwatch, smart clothing, smart glasses, smart wristband, smart jewelry (e.g., smart ring, smart necklace, etc.)), entertainment device (e.g., music device, video device, satellite radio, etc.), vehicle component or sensor, smart meter / sensor, industrial manufacturing equipment, GPS device, or any other suitable device configured to communicate via wireless or wired media. Some UEs can be considered evolved machine-type communication (MTC) devices or evolved MTC (eMTC) devices. MTC and eMTC UEs include, for example, robots, drones, remote devices, sensors, instruments, monitors, location tags, etc., which can communicate with a BS, another device (e.g., a remote device), or some other entity. Wireless nodes can provide connectivity to or to a network (e.g., a wide area network, such as the Internet or a cellular network) via wired or wireless communication links, for example. Some UEs can be considered Internet of Things (IoT) devices.

[0056] exist Figure 1 In the diagram, a solid line with a double arrow indicates the desired transmission between the UE and the serving BS, which is the BS designated to serve the UE on the downlink and / or uplink. A thin dashed line with a double arrow indicates interference transmission between the UE and the BS.

[0057] Some wireless networks (e.g., LTE) can utilize Orthogonal Frequency Division Multiplexing (OFDM) on the downlink and Single-Carrier Frequency Division Multiplexing (SC-FDM) on the uplink. OFDM and SC-FDM divide the system bandwidth into multiple (K) orthogonal subcarriers, often referred to as frequency modulation, frequency slots, etc. Each subcarrier can be modulated with data. Generally, modulation symbols are transmitted in the frequency domain under OFDM and in the time domain under SC-FDM. The spacing between adjacent subcarriers can be fixed, and the total number of subcarriers (K) can depend on the system bandwidth. For example, the subcarrier spacing can be 15 kHz, and the minimum resource allocation (called a "resource block" (RB)) can be 12 subcarriers (i.e., 180 kHz). Therefore, for system bandwidths of 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz, or 20 MHz, the nominal Fast Fourier Transform (FFT) size can be equal to 128, 256, 512, 1024, or 2048. The system bandwidth can also be divided into subbands. For example, a subband can cover 1.08MHz (i.e., 6 RBs), and there can be 1, 2, 4, 8 or 16 subbands for system bandwidths of 1.25MHz, 2.5MHz, 5MHz, 10MHz or 20MHz, respectively.

[0058] NR can utilize OFDM with CP on both uplink and downlink and includes support for half-duplex operation using TDD. A single component carrier bandwidth of 100MHz is supported. NR RB can span 12 subcarriers with a subcarrier bandwidth of 75kHz over a duration of 0.1ms. Each radio frame can include 50 subframes with a length of 10ms. Therefore, each subframe can have a length of 0.2ms. Each subframe can indicate the link direction for data transmission (i.e., downlink or uplink), and the link direction for each subframe can be dynamically switched. Each subframe can include DL / UL data and DL / UL control data. UL and DL subframes for NR can be found in the following reference. Figure 6 and 7 A more detailed description is provided. Beamforming is supported, and beam direction can be dynamically configured. MIMO transmission with precoding is also supported. MIMO configuration in DL can support up to 8 transmit antennas (with up to 8 streams in multilayer DL transmission) and up to 2 streams per UE. Multilayer transmission with up to 2 streams per UE is supported. Up to 8 serving cells can be used to support aggregation of multiple cells. Alternatively, in addition to OFDM-based NR, different air interfaces can also be supported.

[0059] In some examples, access to the air interface can be scheduled. For example, a scheduling entity (e.g., BS 110 or UE 120) allocates resources for communication between some or all devices and equipment within its service area or cell. Within this disclosure, as further discussed below, the scheduling entity can be responsible for scheduling, assigning, reconfiguring, and releasing resources for one or more subordinate entities. That is, for scheduled communication, the subordinate entity utilizes the resources allocated by the scheduling entity. The BS is not the only entity that can act as a scheduling entity. That is, in some examples, a UE can act as a scheduling entity, thereby scheduling resources for one or more subordinate entities (e.g., one or more other UEs). In this example, the UE is acting as a scheduling entity, and other UEs utilize the resources scheduled by the UE for wireless communication. The UE can act as a scheduling entity in a peer-to-peer (P2P) network and / or in a mesh network. In the mesh network example, UEs may optionally communicate directly with each other in addition to communicating with a scheduling entity.

[0060] Therefore, in a wireless communication network with scheduled access to time-frequency resources and with cellular, P2P, and mesh configurations, a scheduling entity and one or more subordinate entities can use the scheduled resources to communicate.

[0061] A radio access network (RAN) may include one or more central units (CUs) and distributed units (DUs). An NRBS (e.g., gNB, 5G NB, NB, 5G NB, TRP, AP, etc.) may correspond to one or more BSs. NR cells may be configured as access cells (ACells) or data-only cells (DCells). A DCell may be a cell used for carrier aggregation or dual connectivity but not for initial access, cell selection / reselection, or handover.

[0062] Figure 2 This section explains an example logical architecture for a distributed RAN 200, which can... Figure 1 The wireless communication system 100 described in the text is implemented. The 5G access node (AN) 206 may include an access node controller (ANC) 202. The ANC 202 may be a CU of a distributed RAN 200. Backhaul interfaces to the next-generation core network (NG-CN) 204 may terminate at the ANC 202. Backhaul interfaces to adjacent next-generation access nodes (NG-ANs) may terminate at the ANC 202. The ANC 202 may include one or more TRPs 208.

[0063] TRP 208 includes a DU. TRP 208 may connect to one ANC (ANC 202) or more ANCs (not described). For example, for RAN sharing, Radio as a Service (RaaS), and service-specific AND deployments, TRP may connect to more than one ANC 202. TRP 208 may include one or more antenna ports. TRP 208 may be configured to individually (e.g., dynamically selected) or jointly (e.g., jointly transmitted) serve traffic to a UE (e.g., UE 120).

[0064] The example logical architecture of the distributed RAN 200 can be used to illustrate the fronthaul definition. This logical architecture can support fronthaul schemes across different deployment types. For example, the logical architecture can be based on transport network capabilities (e.g., bandwidth, latency, and / or jitter). This logical architecture can share features and / or components with LTE. The NG-AN 210 can support dual connectivity with NR. The NG-AN 210 can share a common fronthaul for LTE and NR. This logical architecture enables cooperation between and within each TRP 208. For example, cooperation can be pre-configured within TRP 208 and / or across TRP 208 via ANC 202. Inter-TRP interfaces may not exist.

[0065] The logical architecture for distributed RAN 200 may include dynamic configuration of separated logical functions. (Refer to...) Figure 5 In more detail, the Radio Resource Control (RRC) layer, Packet Data Convergence Protocol (PDCP) layer, Radio Link Control (RLC) layer, Media Access Control (MAC) layer, and Physical (PHY) layer may be placed at the DU (e.g., TRP 208) or CU (e.g., ANC 202).

[0066] Figure 3 An example physical architecture of a distributed RAN 300 according to various aspects of this disclosure is explained. For example... Figure 3 As shown, the distributed RAN 300 includes a centralized core network unit (C-CU) 302, a centralized RAN unit (C-RU) 304, and a DU 306.

[0067] The C-CU 302 can store core network functions. The C-CU 302 can be deployed centrally. C-CU 302 functionality can be offloaded (e.g., to Advanced Wireless Services (AWS)) to handle peak capacity. The C-RU 304 can store one or more ANC functions. Optionally, the C-RU 304 can store core network functions locally. The C-RU 304 can have a distributed deployment. The C-RU 304 can be located near the network edge. The DU 306 can store one or more TRPs (Edge Node (EN), Edge Unit (EU), Radio Header Terminal (RH), Smart Radio Header Terminal (SRH), etc.). The DU 306 can be located at the edge of a network with radio frequency (RF) functionality.

[0068] Figure 4 Commentary Figure 1 The example components of BS 110 and UE 120 explained herein can be used to implement various aspects of this disclosure for high-performance, flexible, and compact LDPC coding. Figure 4 One or more of the components of BS 110 and UE 120 described herein can be used to practice various aspects of this disclosure. For example, antennas 452a-454r, demodulators / modulators 454a-454r, TX MIMO processor 466, receiver processor 458, transmitter processor 464, and / or controller / processor 480 of UE 120, and / or antennas 434a-434t, demodulators / modulators 432a-434t, TX MIMO processor 430, transmitter processor 420, receiver processor 438, and / or controller / processor 440 of BS 110 can be used to perform the functions described and referenced herein. Figure 13 The operation explained is 1300.

[0069] For scenarios involving constrained associations, BS 110 can be... Figure 1 The BS 110c is a macro BS, and the UE 120 can be a UE120y. The BS 110 can also be some other type of BS. The BS 110 can be equipped with antennas 434a to 434t, while the UE 120 can be equipped with antennas 452a to 452r.

[0070] At BS 110, the transmit processor 420 can receive data from data source 412 and control information from controller / processor 440. This control information can be used on the Physical Broadcast Channel (PBCH), Physical Control Format Indicator Channel (PCFICH), Physical Hybrid ARQ Indicator Channel (PHICH), Physical Downlink Control Channel (PDCCH), or other control channels or signals. This data can be used on the Physical Downlink Shared Channel (PDSCH), or other data channels or signals. The transmit processor 420 can process (e.g., encode and map symbols) the data and control information to obtain data symbols and control symbols, respectively. For example, the transmit processor 420 can encode information bits using an LPDC code design discussed in more detail below. The transmit processor 420 can also generate reference symbols (e.g., for the primary synchronization signal (PSS), secondary synchronization signal (SSS), and cell-specific reference signal (CRS)). The transmit (TX) multiple-input multiple-output (MIMO) processor 430 can perform spatial processing (e.g., precoding) on ​​data symbols, control symbols, and / or reference symbols where applicable, and can provide the output symbol stream to modulators (MODs) 432a to 432t. Each modulator 432 can process its own output symbol stream (e.g., for OFDM, etc.) to obtain an output sample stream. Each modulator 432 can further process (e.g., convert to analog, amplify, filter, and up-convert) the output sample stream to obtain a downlink signal. The downlink signals from modulators 432a to 432t can be transmitted via antennas 434a to 434t, respectively.

[0071] At UE 120, antennas 452a to 452r can receive downlink signals from BS 110 and can respectively provide the received signals to demodulators (DEMODs) 454a to 454r. Each demodulator 454 can condition (e.g., filter, amplify, downconvert, and digitize) its respective received signal to obtain an input sample. Each demodulator 454 can further process the input sample (e.g., for OFDM, etc.) to obtain received symbols. MIMO detector 456 can obtain the received symbols from all demodulators 454a to 454r, perform MIMO detection on these received symbols where applicable, and provide detected symbols. Receiver processor 458 can process (e.g., demodulate, deinterleave, and decode) these detected symbols, provide the decoded data to UE 120 to data sink 460, and provide the decoded control information to controller / processor 480.

[0072] On the uplink, at UE 120, transmit processor 464 can receive and process data from data source 462 (e.g., for the Physical Uplink Shared Channel (PUSCH) or other data channels or signals) and control information from controller / processor 480 (e.g., for the Physical Uplink Control Channel (PUCCH) or other control channels or signals). Transmit processor 464 can also generate reference symbols for reference signals. Symbols from transmit processor 464 can be pre-encoded by TX MIMO processor 466, where applicable, further processed by demodulators 454a to 454r (e.g., for SC-FDM, etc.), and transmitted to BS 110. At BS 110, uplink signals from UE 120 can be received by antenna 434, processed by modulator 432, detected by MIMO detector 436, where applicable, and further processed by receive processor 438 to obtain decoded data and control information transmitted by UE 120. The receiver processor 438 can provide the decoded data to the data trap 439 and the decoded control information to the controller / processor 440.

[0073] Memory 442 may store data and program code for BS 110, while memory 482 may store data and program code for UE 120. Scheduler 444 may schedule UE for data transmission on downlink and / or uplink.

[0074] Figure 5 Figure 500 illustrates examples of implementing a communication protocol stack according to various aspects of this disclosure. The illustrated communication protocol stack can be implemented by a device operating in a 5G system (e.g., a system supporting uplink-based mobility). Figure 500 illustrates a communication protocol stack including an RRC layer 510, a PDCP layer 515, an RLC layer 520, a MAC layer 525, and a PHY layer 530. In one example, these layers of the protocol stack can be implemented as separate software modules, portions of a processor or ASIC, portions of non-co-located devices connected by a communication link, or various combinations thereof. Co-located and non-co-located implementations can, for example, be used in the protocol stack for network access devices (e.g., AN, CU, and / or DU) or UEs.

[0075] Option 505-a illustrates a split implementation of the protocol stack, where the implementation is split between a centralized network access device (e.g., ANC 202) and a distributed network access device (e.g., DU 208). In Option 505-a, the RRC layer 510 and PDCP layer 515 can be implemented by the CU, while the RLC layer 520, MAC layer 525, and PHY layer 530 can be implemented by the DU. In various examples, the CU and DU can coexist or not. Option 505-a can be useful in macrocell, microcell, or picocell deployments.

[0076] Option 505-b illustrates a unified implementation of the protocol stack, where the stack is implemented in a single network access device (e.g., Access Node (AN), NR BS, NR NB, Network Node (NN), TRP, gNB, etc.). In this option, the RRC layer 510, PDCP layer 515, RLC layer 520, MAC layer 525, and PHY layer 530 can each be implemented independently of the AN. Option 505-b can be useful in femtocell deployments.

[0077] Regardless of whether the network access device implements part or all of the protocol stack, the UE can implement the entire protocol stack (e.g., RRC layer 510, PDCP layer 515, RLC layer 520, MAC layer 525, and PHY layer 530).

[0078] Figure 6 This is a diagram illustrating an example of a DL-centered subframe 600. The DL-centered subframe 600 may include a control portion 602. The control portion 602 may be present in the initial or start portion of the DL-centered subframe 600. The control portion 602 may include various scheduling information and / or control information corresponding to the various portions of the DL-centered subframe 600. In some configurations, the control portion 602 may be a physical DL control channel (PDCCH), as shown in... Figure 6 As shown in the diagram, the DL-centered subframe 600 may also include a DL data portion 604. The DL data portion 604 may be referred to as the payload of the DL-centered subframe 600. The DL data portion 604 may include communication resources used to convey DL data from a scheduling entity (e.g., a UE or BS) to a lower-level entity (e.g., a UE). In some configurations, the DL data portion 604 may be a Physical DL Shared Channel (PDSCH).

[0079] The DL-centered subframe 600 may also include a common UL portion 606. The common UL portion 606 may be referred to as a UL burst, a shared UL burst, and / or various other suitable terms. The common UL portion 606 may include feedback information corresponding to various other portions of the DL-centered subframe 600. For example, the common UL portion 606 may include feedback information corresponding to the control portion 602. Non-limiting examples of feedback information may include acknowledgment (ACK) signals, negation (NACK) signals, HARQ indicators, and / or various other suitable types of information. The common UL portion 606 may additionally or alternatively include information such as information relating to random access channel (RACH) procedures, scheduling requests (SRs), and various other suitable types of information. Figure 6 As explained herein, the end of the DL data portion 604 may be temporally separated from the start of the common UL portion 606. This temporal separation may be referred to as a gap, guard period, guard interval, and / or various other suitable terms. This separation provides the time for switching from DL communication (e.g., a reception operation performed by a lower-level entity (e.g., a UE)) to UL communication (e.g., a transmission performed by a lower-level entity (e.g., a UE)). The foregoing is merely one example of a DL-centered subframe, and alternative structures with similar characteristics may exist without departing from the aspects described herein.

[0080] Figure 7 This is a diagram illustrating an example of a UL central subframe 700. The UL central subframe 700 may include a control section 702. The control section 702 may be present in the initial or beginning portion of the UL central subframe 700. Figure 7 The control section 702 in the above reference can be similar to the one described above. Figure 6 The control portion 602 is described. The UL-centralized subframe 700 may also include a UL data portion 704. The UL data portion 704 may be referred to as the payload of the UL-centralized subframe 700. The UL data portion 704 may refer to a communication resource used to transmit UL data from a lower-level entity (e.g., UE) to a scheduling entity (e.g., UE or BS). In some configurations, the control portion 702 may be a PDCCH.

[0081] As in Figure 7 As explained, the end of control section 702 may be time-separated from the start of UL data section 704. This time separation may be referred to as a gap, protection period, protection interval, and / or various other suitable terms. This separation provides the time for switching from DL communication (e.g., a receiving operation performed by a scheduling entity) to UL communication (e.g., a transmission performed by a scheduling entity). UL central subframe 700 may also include a common UL section 706. Figure 7The common UL part 706 in the above reference can be similar to the above reference. Figure 6 The common UL portion 606 is described. The common UL portion 706 may additionally or alternatively include information relating to the Channel Quality Indicator (CQI), the Probe Reference Signal (SRS), and various other suitable types of information. The foregoing is merely one example of a UL-centered subframe, and alternative structures with similar characteristics may exist without departing from the aspects described herein.

[0082] In some cases, two or more subordinate entities (e.g., UEs) may use sidelink signaling to communicate with each other. Real-world applications of such sidelink communication may include public safety, proximity services, UE-to-network relay, vehicle-to-vehicle (V2V) communication, Internet of Things (IoE) communication, IoT communication, mission-critical mesh networks, and / or various other suitable applications. Generally, a sidelink signal can refer to a signal that is relayed from one subordinate entity (e.g., UE1) to another subordinate entity (e.g., UE2) without requiring the relaying of that communication by a scheduling entity (e.g., UE or BS), even if the scheduling entity may be used for scheduling and / or control purposes. In some examples, sidelink signaling may use licensed spectrum for transmission (unlike wireless local area networks (WLANs), which typically use unlicensed spectrum).

[0083] The UE can operate in various radio resource configurations, including configurations associated with using a dedicated resource set to transmit pilot signals (e.g., Radio Resource Control (RRC) dedicated state, etc.) or configurations associated with using a shared resource set to transmit pilot signals (e.g., RRC shared state, etc.). When operating in RRC dedicated state, the UE can select a dedicated resource set for transmitting pilot signals to the network. When operating in RRC shared state, the UE can select a shared resource set for transmitting pilot signals to the network. In either case, the pilot signals transmitted by the UE can be received by one or more network access devices (such as AN, or DU, or portions thereof). Each receiving network access device can be configured to receive and measure pilot signals transmitted on the shared resource set, and also to receive and measure pilot signals transmitted on the dedicated resource set allocated to the UE, wherein the network access device is a member of the UE's set of monitoring network access devices. One or more receiving network access devices, or CUs to which the receiving network access devices transmit pilot signal measurements, can use these measurements to identify the UE's serving cell or initiate serving cell changes for one or more UEs.

[0084] Example error correction coding

[0085] Many communication systems use error-correcting codes. Error-correcting codes generally compensate for the inherent unreliability of information transmission in these systems (e.g., over air media) by introducing redundancy into the data stream. Low-density parity-check (LDPC) codes are a type of error-correcting code that uses an iterative coding system. Gallager codes are an example of "regular" LDPC codes. Regular LDPC codes are linear block codes where the majority of elements of their parity-check matrix H are '0'.

[0086] LDPC codes can be represented by a bipartite graph (often called a "Tanner graph"). In a bipartite graph, a set of variable nodes corresponds to the bits of the codeword (e.g., information bits or system bits), and a set of parity nodes corresponds to a set of parity check constraints that define the code. Edges in the graph connect the variable nodes to the parity nodes. Thus, the nodes of the graph are divided into two distinct sets, with each edge connecting two different types of nodes—variable nodes and parity nodes.

[0087] The graph used in LDPC coding can be characterized in various ways. A lifted code is created by replicating the bipartite base graph (G) (or protograph) a number of times (Z). This number is referred to herein as the lift, lift size, or lift size value. Variable nodes and check nodes are considered "neighbors" if they are connected in the graph by "edges" (i.e., lines connecting variable nodes and check nodes). Additionally, for each edge (e) of the bipartite base graph (G), a permutation (generally an integer value associated with the edge permutation represented by k and referred to as the lift value) is applied to Z copies of the edge (e) to interconnect the Z copies of G. A valid codeword is a sequence of bits with a one-to-one association with the variable node sequence if and only if the sum of the bits associated with all neighboring variable nodes modulo 2 is 0 for each check node (i.e., they include an even number of 1s). If the permutation (lift value) used is cyclic, the resulting LDPC code may be quasi-cyclic (QC).

[0088] Figure 8-8A Graphical and matrix representations of example LDPC codes according to certain aspects of this disclosure are shown respectively. For example, Figure 8 A bipartite graph 800 representing an example LDPC code is shown. The bipartite graph 800 comprises a set of five variable nodes 810 (represented by circles) connected to four check nodes 820 (represented by squares). Edges in the bipartite graph 800 connect the variable nodes 810 to the check nodes 820 (these edges are represented by lines connecting the variable nodes 810 to the check nodes 820). The bipartite graph 800 includes |V| = 5 variable nodes and |C| = 4 check nodes connected by |E| = 12 edges.

[0089] A bipartite graph 800 can be represented by a simplified adjacency matrix, which can also be called a parity check matrix (PCM). Figure 8A The matrix representation 800A of the bipartite graph 800 is shown. Matrix representation 800A includes a PCM H and a codeword vector x, where x1-x5 represent the bits of codeword x. H is used to determine whether the received signal has been correctly decoded. H has C rows corresponding to j check nodes and V columns corresponding to i variable nodes (i.e., demodulated symbols), where rows represent equations and columns represent the bits of the codeword. Figure 8A In the parity check matrix H, there are 4 rows and 5 columns corresponding to 4 check nodes and 5 variable nodes, respectively. If the j-th check node is connected to the i-th variable node by an edge (i.e., the two nodes are neighbors), then the i-th column and j-th row of the parity check matrix H are 1. That is, the intersection of the i-th row and j-th column contains "1" if there is an edge connecting the corresponding vertex, and contains "0" if there is no edge. H is valid if and only if... x When = 0 (e.g., when the sum of the bits adjacent to the constraint (via their association with the variable nodes) modulo 2 is 0 for each constraint node (i.e., they include an even number of 1s), the codeword vector x represents a valid codeword. Therefore, if the codeword is received correctly, H x = 0 (mod 2). When the product of the encoded received signal and PCM H becomes "0", it indicates that no error has occurred.

[0090] The number of demodulated symbols or variable nodes is the LDPC code length. The number of non-zero elements in a row (column) is defined as the row (column) weight d(c)d(v). The degree of a node refers to the number of edges connected to that node. For example, as... Figure 8 As shown, variable node 801 has three degrees of connectivity and has edges connecting to check nodes 811, 812, and 813. Variable node 802 has three degrees of connectivity and has edges connecting to check nodes 811, 813, and 814. Variable node 803 has two degrees of connectivity and has edges connecting to check nodes 811 and 814. Variable node 804 has two degrees of connectivity and has edges connecting to check nodes 812 and 814. And variable node 805 has two degrees of connectivity and has edges connecting to check nodes 812 and 813. This feature is... Figure 8A The matrix H shown illustrates that the number of edges incident to variable node 810 is equal to the number of 1s in the corresponding column and is called the variable node degree d(v). Similarly, the number of edges connected to check node 820 is equal to the number of 1s in the corresponding row and is called the check node degree d(c). For example, as... Figure 8AAs shown, the first column of matrix H corresponds to variable node 801, and the corresponding entry (1,1,1,0) in this column indicates the edge connections to check nodes 811, 812, and 813, while 0 indicates that there is no edge to check node 814. The entries in the second, third, fourth, and fourth columns of H represent the edge connections from variable nodes 802, 803, 804, and 805 to the check nodes, respectively.

[0091] A regular graph or regular code is a graph or code in which all variable nodes have the same degree and all constraint nodes have the same degree. On the other hand, a non-regular code has constraint nodes and / or variable nodes with different degrees. For example, some variable nodes may have a degree of 4, some may have a degree of 3, and some may have a degree of 2.

[0092] "Lifting" enables the implementation of LDPC codes using parallel encoding and / or decoding, while reducing the complexity typically associated with larger LDPC codes. Lifting facilitates efficient parallelization of LDPC decoders while maintaining a relatively concise description. More specifically, lifting is a technique used to generate relatively large LDPC codes from multiple copies of a smaller base code. For example, a lifted LDPC code can be generated by producing Z parallel copies of a base graph (e.g., a protograph) and then interconnecting these parallel copies by permuting the edge bundles of each copy of the base graph. The base graph defines the (macro)structure of the code and includes a number (K) of information bit columns and a number (N) of code bit columns. Lifting the base graph by a lifting amount Z results in a final block length KZ. Thus, a larger graph can be obtained through "copying and permutation" operations, where multiple copies of the base graph are made and connected to form a single lifted graph. For multiple copies, similar edges are a set of copies of a single base edge, which are permuted and connected to form a connected graph that is Z times larger than the base graph.

[0093] Figure 9 It is an explanation Figure 8 The bipartite graph 800 is a lifted bipartite graph with three copies. The three copies are interconnected by permuting similar edges among them. If the permutation is limited to cyclic permutations, the resulting bipartite graph 900 corresponds to a quasi-cyclic LDPC with a lift Z=3. The original graph 800 with three copies is referred to herein as the base graph. To obtain graphs of different sizes, the "copy and permutation" operation can be applied to the base graph.

[0094] The corresponding PCM of the boosted graph can be constructed from the parity matrix of the base graph by replacing each entry in the base parity matrix with a Z x Z matrix. "0" entries (entries without base edges) are replaced with a 0 matrix, while 1 entries (indicating base edges) are replaced with a Z x Z transpose matrix. In the case of cyclic boosting, this permutation is a cyclic permutation.

[0095] Cyclic boosting LDPC codes can also be interpreted as binary polynomials modulo x. z The code on the ring with +1. In this interpretation, the binary polynomial (x) = b0 + b1x + b2x 2 +...+b z-1 x z-1 It can be associated with each variable node in the base graph. Binary vector (b0, b1, b2, ..., b...) z-1 This corresponds to the bits associated with the Z corresponding variable nodes in the lifted graph, i.e., the Z copies of a single basic variable node. This is achieved by multiplying the corresponding binary polynomial by x. k To perform k-th cyclic permutations of the binary vector (referred to as the lift value associated with the edge in the graph), where x... z +1 modulo the product. Parity checking of degree d in the base graph can be interpreted as checking adjacent binary polynomials B1(x),…,B d The linear constraint of (x) is written as x k1 B1(x)+ x k2 B2(x)+...+x kd B d (x)=0x k B1(x)+x k2 B2(x)+...+x kd B d (x) = 0, values ​​k1, ..., k d It is the cyclic promotion value associated with the corresponding edge.

[0096] The resulting equation is equivalent to Z parity checks in a cyclically boosted Tanner graph, each corresponding to a single associated parity check in the base graph. Therefore, the parity check matrix of the boosted graph can be expressed using the matrix of the base graph, where entries of 1 are replaced with x. k The monomial of form, where the entry for 0 is promoted to 0, but now 0 is interpreted as 0 binary polynomial modulo x. z +1. x can be replaced by giving the value k. k To write this type of matrix. In this case, the zero polynomial is sometimes represented as "-1", and sometimes as another character so that it can be associated with x. 0 Distinguish them.

[0097] Typically, the square submatrix of the parity check matrix represents the parity check bits of the code. The complementary columns correspond to the information bits, which are set to be equal to the information bits to be encoded during encoding. Encoding can be achieved by solving for the variables in the aforementioned square submatrix to satisfy the parity check equation. The parity check matrix H can be divided into two parts, M and N, where M is the square part. Therefore, encoding simplifies to solving for M.c =s=Nd, where c and d include x. In the case of quasi-cyclic codes or cyclically raised codes, the above algebraic operation can be interpreted as operating on a binary polynomial modulo x. z On a +1 ring. In the case of quasi-cyclic 802.11 LDPC codes, the coding submatrix M has an integer representation, such as Figure 10 As shown.

[0098] The received LDPC codewords can be decoded to produce a reconstructed version of the original codewords. Decoding can be used to recover the original encoded data units, either in the absence of errors or in cases where errors can be corrected. Redundant bits can be used by the decoder to detect and correct bit errors. An LDPC decoder generally operates by iteratively performing local computations and passing those results by exchanging messages along edges within a bipartite graph, and updating these messages by performing computations at each node based on the incoming messages. These steps can be repeated several times. For example, each variable node 810 in Figure 800 may initially be provided with “soft bits” (e.g., representing the received bits of the codeword), indicating an estimate of the value of the associated bits as determined by observation from the communication channel. Using these soft bits, the LDPC decoder can update messages by iteratively reading the message or a portion thereof from memory and writing the updated message or a portion thereof back to memory. These update operations are typically based on parity constraints of the corresponding LDPC code. In various implementations of lifted LDPC codes, messages on similar edges are typically processed in parallel.

[0099] LDPC codes designed for high-speed applications typically employ quasi-cyclic constructions with large boost factors and relatively small base graphs to support high parallelism in encoding and decoding operations. LDPC codes with high code rates (e.g., the ratio of message length to codeword length) tend to have relatively few parities. If the number of base parities is less than the degree of a variable node (e.g., the number of edges connecting it to the variable node), then in the base graph, the variable node is connected to at least one of these base parities by two or more edges (e.g., the variable node may have "bilateral" connections). Connecting base variable nodes and base parity nodes by two or more edges is generally undesirable for parallel hardware implementation purposes. For example, such bilateral connections can lead to multiple concurrent read and write operations on the same memory location, which can in turn cause data consistency problems. Two-sided operations in a base LDPC code can trigger two parallel reads of the same soft bit value memory location during a single parallel parity update. This typically requires additional circuitry to combine the soft bit values ​​written back to memory to correctly incorporate the two updates. Eliminating the two-sided operations in LDPC codes helps avoid this additional complexity.

[0100] LDPC code designs based on cyclic boosting can be interpreted as codes on a polynomial module ring, where the polynomial module can be a binary polynomial module x. Z -1, where Z is the boosting size (e.g., the cycle size in a quasi-cyclic code). Thus, encoding such a code can generally be interpreted as algebraic operations within the ring.

[0101] In the definition of standard non-regular LDPC code aggregation (degree distribution), all edges in a Tanner graph representation are statistically interchangeable. In other words, there exists a single statistically valid edge equivalence class. A more detailed discussion of lifted LDPC codes can be found, for example, in Tom Richardson and Ruediger Urbanke's book, "Modern Coding Theory," published March 17, 2008. For multi-edge LDPC codes, multiple edge equivalence classes are possible. While in the definition of standard non-regular LDPC aggregation, nodes in a graph (both variables and constraints) are specified by their degree (i.e., the number of edges they are connected to), in a multi-edge type setting, the edge degree is a vector; it specifies the number of edges independently connected to that node from each edge equivalence class (type). Multi-edge type aggregation includes a finite number of edge types. The degree type of a constraint node is a vector of (non-negative) integers; the i-th entry of this vector records the number of type i-th sockets connected to such nodes. This vector may be called the edge degree. The degree type of a variable node has two parts, although it can be viewed as a vector of (non-negative) integers. The first part relates to the received distribution and will be referred to as the received degree, while the second part specifies the edge degree. The edge degree serves the same purpose as for constraint nodes. Edges are categorized as they are paired with sockets of the same type. The constraint that sockets must be paired with sockets of similar types characterizes the polygon type concept. In a polygon type description, different node types can have different received distributions (e.g., associated bits can traverse different channels).

[0102] Punching is the act of removing bits from a codeword to produce a shorter codeword. Thus, the punctured variable node corresponds to a codeword bit that was not actually transmitted. Punching variable nodes in an LDPC code creates a shortened code (e.g., due to bit removal) while also effectively removing parity nodes. Specifically, for a matrix representation of an LDPC code (including the bits to be punctured), where the variable node to be punctured has a degree of 1 (such a representation can be made possible through row combination where the code is appropriate), puncturing this variable node removes the associated bit from the code and effectively removes its single neighboring parity node from the graph. As a result, the number of parity nodes in the graph is reduced by 1.

[0103] Figure 11 This is a simplified block diagram illustrating an encoder according to certain aspects of this disclosure. Figure 11This is a simplified block diagram 1100 illustrating a portion of a radio frequency (RF) modem 1150, which can be configured to provide signals including encoded messages for wireless transmission. In one example, a convolutional encoder 1102 in a BS 110 (or a UE 120 on the reverse path) receives a message 1120 for transmission. The message 1120 may contain data and / or encoded voice or other content directed to a receiving device. The encoder 1102 encodes the message using a suitable modulation and coding scheme (MCS), which is typically selected based on a configuration defined by the BS 110 or another network entity. The encoded bitstream 1122 produced by the encoder 1102 may then be selectively punctured by a puncturing module 1104, which may be a separate device or component, or it may be integrated with the encoder 1102. The puncturing module 1104 can determine whether the bitstream 1122 should be punctured before transmission or transmitted without puncturing. The decision to puncture bitstream 1122 is typically based on network conditions, network configuration, RAN-defined preferences, and / or other reasons. Bitstream 1122 may be punctured according to puncturing mode 1112 and used to encode message 1120. Punching module 1104 provides output 1124 to mapper 1106, which generates Tx symbol sequence 1126, which is modulated, amplified, and otherwise processed by Tx chain 1108 to generate RF signal 1128 for transmission through antenna 1110.

[0104] Depending on whether the modem section 1150 is configured to puncture the bitstream 1122, the output 1124 of the puncturing module 1104 can be either an unpunctured bitstream 1122 or a punctured version of the bitstream 1122. In one example, parity bits and / or other error-correcting bits may be punctured in the output 1124 of the encoder 1102 to transmit message 1120 within the limited bandwidth of the RF channel. In another example, the bitstream may be punctured to reduce the power required to transmit message 1120 in order to avoid interference or for other network-related reasons. These punctured codeword bits are not transmitted.

[0105] The decoder and decoding algorithm used to decode LDPC codewords operate by exchanging messages along the edges of the graph and updating these messages by performing computations at each node based on the incoming messages. Each variable node in the graph is initially provided with soft bits (called received values), which indicate an estimate of the value of the associated bits as determined by observations from, for example, a communication channel. Ideally, the estimates of individual bits are statistically independent. In practice, this ideal may be violated. A received word comprises the set of received values.

[0106] Figure 12 This is a simplified block diagram illustrating a decoder according to certain aspects of this disclosure. Figure 12 This is a simplified schematic diagram 1200 illustrating part of an RF modem 1250, which can be configured to receive and decode wirelessly transmitted signals including punctured encoded messages. Punctured codeword bits can be considered as being erased. For example, the log-likelihood ratio (LLR) of the punctured node can be set to 0 during initialization. Puncture can also include padding with shortened bits. These shortened bits are not included in the transmission and are treated as known bits at the receiver / decoder. In various examples, the modem 1250 receiving the signal can reside at a UE, a BS, or any other suitable equipment or device for performing the described functions. Antenna 1202 provides an RF signal 1220 to the receiver. RF chain 1204 processes and demodulates the RF signal 1220 and can provide a symbol sequence 1222 to a demapper 1226, which produces a bit stream 1224 representing the encoded message.

[0107] Demapper 1206 provides a perforated bitstream 1224. In one example, demapper 1206 may include a perforation module configured to insert null values ​​into the bitstream at locations where perforated bits have been removed by the transmitter. This perforation module may be used when the perforation pattern 1210 used at the transmitter to generate the perforated bitstream is known. The perforation pattern 1210 may be used to identify LLRs 1228 that can be ignored during decoding of the bitstream 1224 by the convolutional decoder 1208. These LLRs may be associated with a set of perforated bit locations in the bitstream 1224. Accordingly, decoder 1208 can generate a decoded message 1226 with reduced processing overhead by ignoring the identified LLRs 1228. The LDPC decoder may include multiple processing elements for performing parity operations or variable node operations in parallel. For example, when processing codewords with a lifting size Z, the LDPC decoder can utilize several (Z) processing elements to concurrently perform parity checks on all edges of the lifted graph.

[0108] The processing efficiency of decoder 1208 can be improved by configuring decoder 1208 to ignore LLR 1228 corresponding to punctured bits in the message transmitted in punctured bitstream 1222. Punctured bitstream 1222 may have been punctured according to a puncturing scheme for certain bits to be removed from the encoded message as defined. In one example, certain parity bits or other error-correcting bits may be removed. The puncturing pattern can be expressed as a puncturing matrix or table identifying the positions of the bits to be punctured in each message. A puncturing scheme can be selected to reduce the processing overhead for decoding message 1226 while maintaining compliance with the data rate on the communication channel and / or the transmission power limits set by the network. The resulting punctured bitstream typically exhibits the error-correcting characteristics of a high-rate error-correcting code, but with less redundancy. Therefore, puncturing can be effectively employed to reduce the processing overhead at decoder 1208 in the receiver when channel conditions result in a relatively high signal-to-noise ratio (SNR).

[0109] At the receiver, the same decoder used to decode unpunctured bitstreams can typically be used to decode punctured bitstreams, regardless of how many bits have been punctured. In conventional receivers, LLR information is typically padded with zeros to fill the punctured states or positions (punctured LLR) before attempting decoding. The decoder can ignore padded LLRs, which do not actually carry information, at least in part, based on which bits have been punctured. The decoder can treat the shortened bits as known bits (e.g., set them to 0).

[0110] Example: A concise description of the features of an enhanced LDPC code.

[0111] Certain systems (e.g., 802.11n, 802.11ad, WiMAX, ATSC, etc.) can utilize polygonal (ME) type low-density parity-check (LDPC) code structures. Polygonal type LDPC codes can offer advantages over standard non-regular LDPC codes. The ME framework provides a framework for designing high-performance LDPC codes by using state nodes. Polygonal type LDPC code structures offer significantly more degrees of freedom than standard non-regular LDPC codes, which can be used to design codes with superior performance, low encoding / decoding complexity, and / or other desired properties. ME codes can have cumulative chains of 2-degree parity bits, which makes the codes systematic and therefore easy to encode.

[0112] ME-type LDPC codes can be represented as LDPC codes based on the protograph, where the ME-type LDPC code is formed by a basis parity check matrix (PCM). As mentioned above, the protograph and PCM are used to represent (n,k) LDPC codes. The PCM defines the basic structure or edge type in the code.

[0113] As described above, an LDPC code can be raised by taking Z (lifting size) copies of the base PCM and assigning random permutations (according to an integer lifting value k) to each edge bundle to interconnect the Z copies and obtain the final PCM. The block length of the final PCM is Z times the size of the base PCM. Typically, the permutations used are cyclic permutations (e.g., using a cyclic matrix to obtain the final PCM). The final PCM can be represented by replacing non-zero entries in the base PCM with integers up to size Z-1. This integer represents the cyclic shift (according to that integer value) associated with the lifted edge bundles in the lifted code structure.

[0114] In some cases, a range of block lengths can be transmitted. In such cases, different Z values ​​can be used for the same base map to achieve different block lengths (because the block length is equal to Z times the length of the base PCM). To obtain different bit rates, different PCMs and / or different permutations (lift values) can be used, for example, for the same lift size Z.

[0115] As an example, in the 802.11n standard, the base PCM has a block length of 24, and the boost size is given by Z = 27, 54, and 81. This gives block lengths of 648, 1296, and 1944 respectively (e.g., multiplied by 24 * 27, 24 * 54, and 24 * 81). In this example of the 802.11n standard approach, a unique PCM is defined for each code rate and each block length. In 802.11n, there are four code rate points; therefore, the number of defined PCMs is twelve (e.g., one PCM for each combination of 4 code rates × 3 block lengths).

[0116] In this scenario, when the block length and code rate are large (as is often the case in Long Term Evolution (LTE), describing (e.g., defining / generating / determining / storing) the different PCMs for each pair of code rates and block lengths can result in large microcodes used to describe the PCMs (e.g., a large number of bits required to store different PCMs).

[0117] Accordingly, there is a need for a technique to concisely describe large block lengths and bit rates in PCM while maintaining high performance.

[0118] This paper provides techniques for generating raised LDPC codes (e.g., raised ME LDPC codes) that are suitable for concise description and provide fine-grained block length scaling.

[0119] Figure 13Example operation 1300 for wireless communication according to certain aspects of this disclosure is explained. Operation 1300 may be performed, for example, by a transmitting device (e.g., UE 120 or BS 110). Operation 1300 begins at 1302 by selecting a lift size value Z (e.g., leader) and a first lift value set for generating a first lifted LDPC code (e.g., a multi-sided LDPC code). The lift size value may be selected to achieve a target block length or a block length range. At 1304, the transmitting device generates a first lifted LDPC code by applying the first lift value set to interconnect edges in Z copies of a base PCM to obtain a first lifted PCM corresponding to the first lifted LDPC code. The base PCM has a first number of base variable nodes and a second number of base parity nodes (an edge is a connection between a variable node and a parity node). At 1306, the transmitting device determines a second lift value set based on the first lifted PCM and the first lift value set for generating a second lifted PCM corresponding to a second lifted LDPC code with a second lift size value. At 1308, the transmitting device encodes a set of information bits based on at least one of a first enhanced LDPC code or a second enhanced LDPC code to generate a codeword. At 1310, the transmitting device transmits the codeword via a wireless medium.

[0120] According to some aspects, the matrices used for the different lift size values ​​in this group are generated based on the base matrix by performing operations (such as modulo operations or floor operations) involving different lift size values ​​and integer values ​​associated with the edges in the base matrix (e.g., with the permutations of entries in the base matrix).

[0121] Depending on certain aspects, multiple boost size values ​​(e.g., leaders) can be selected (e.g., families with the same code rate). A PCM can be generated for each selected boost size value, and members in an associated group (e.g., family or equivalence class) can be generated based on the PCM of their respective leader. In some respects, the transmitting device can store only the generated matrix (e.g., PCM) based on the maximum boost value (thereby generating PCMs for other members in that family).

[0122] A lifted LDPC code can be described by assigning a number (e.g., an integer) smaller than the lifting size Z to each edge of the PCM. This entry can be replaced by a cyclic matrix obtained by cyclically shifting (e.g., cyclically shifting to the right) the number into an identity matrix of size Z x Z. Thus, a PCM can be given by a matrix of the size of the base PCM and integer entries corresponding to the cyclic lifting.

[0123] According to some aspects, the lifting set can be defined as {a1, a2, ..., a...} k x 2i , 0≤i≤m, where k is the number of families or equivalence classes (e.g., associated with the same code rate), a j It is the family leader (e.g., a positive integer), and m is the largest power of 2 (e.g., the number of members in each family or the granularity of the block length that can be obtained). The smallest power of 2 can be 0, and depending on the maximum expected block length, the largest power of 2 m can be a large number (e.g., 10).

[0124] Each family j∈[1:k] can be represented by its leader a j The promotion values ​​can be described (e.g., generated) based on powers of 2 (up to the maximum power m). In this case, there are (m+1)k promotion values. As an example, for four families or equivalence classes (k=4), the maximum power of 2, 6 (m=6), can be used, where the leaders of the four families can be 16 (a1=16), 20 (a2=20), 24 (a3=24), and 28 (a4=28). In this example, the promotion values ​​of the four families can be defined (e.g., generated) based on powers of 2 of the leaders up to the maximum power m (6 in this example). Therefore, in this example, the possible values ​​of the promotion for the four families can be given as follows:

[0125] Z = 16x{1,2,2} 2 ,2 3 ,2 4 ,2 5 ,2 6}

[0126] Z = 20x{1,2,2} 2 ,2 3 ,2 4 ,2 5 ,2 6}

[0127] Z = 24x{1,2,2} 2 ,2 3 ,2 4 ,2 5 ,2 6}

[0128] Z = 28x{1,2,2} 2 ,2 3 ,2 4 ,2 5 ,2 6}

[0129] They correspond to:

[0130] Z = 16,32,64 128,256,512,1024

[0131] Z = 20, 40, 80, 160, 320, 640, 1280

[0132] Z = 24, 48, 96, 192, 384, 768, 1536

[0133] Z = 28, 56, 112, 224, 448, 896, 1792

[0134] If an independent lifting value is used for each lifting (e.g., block length), then (m + 1)k PCMs are defined for each code rate point (e.g., one PCM for each lifting value). In the above example, for four families and a maximum power of 6, 28 PCMs are defined (e.g., (6 + 1) x 4 = 28).

[0135] According to some aspects, instead of defining (e.g., obtaining / generating / determining / storing) a PCM for each lifting value, a single PCM can be used for each family, e.g., the PCM corresponding only to the maximum lifting in the family (e.g., the leader multiplied by the maximum power of 2). For family j, for the maximum lifting value a j 2 m generate a PCM. The other lifting size values in the family include the other powers of 2 multiplied by the leader. The PCMs for the other members in the family can be obtained based on the PCM for the maximum lifting. For example, the edges in the PCM for the leader can be associated with the set of lifting values. The PCMs for the other members in the code family can be obtained by performing operations involving the PCM for the maximum lifting size value (e.g., based on the lifting value) and the desired lifting size (e.g., the lifting size of the family member). These operations can include modulo, floor operations, or other operations on the desired lifting size. For example, if an edge has a value s (e.g., an integer value) in the PCM of family j (e.g., for the maximum lifting size value), then the corresponding integer value in the PCM for the desired lifting size value l (l < m) can be given by s mod a j 2 l In the example of the floor operation, the corresponding integer value can be found by / floor(s * (desired lifting size value) / (maximum lifting size value)): ​​​​​​​In the example above, for each bitrate, four PCMs can be used—one PCM for each of the four families' maximum boost size values ​​of 1024, 1280, 1536, and 1792. That is, the PCM described for each family corresponds to the maximum boost size. In the case of a family with a leader of 16, an edge in the base graph (e.g., the PCM for the maximum boost size value of 16 in that family is 16 * 2^6 = 1024) can be associated with an integer boost value s of 678 ("s" is an integer value representing the cyclic boost of that particular edge). The values ​​associated with all edges in the base PCM may be less than the maximum boost size (1024 in this example). To obtain the integer value corresponding to the same edge in the graph for different boost sizes in that family, the operation s mod Z can be performed (e.g., when Z = 128, this operation is 678 mod 128 = 38) to generate the boost value for the PCM of that member in that family. Therefore, when lifting with a lifting size of Z = 128, a circular matrix of size 128 × 128 can be used for this edge, for example, a right-shifted identity matrix (size 128 × 128) by 38. Although modulo operation is used in this example, in other embodiments, as discussed above, different operations (e.g., floor operations or other operations) can be used.

[0139] LDPC codes are typically designed so that the decoding graph has few small loops; for example, due to the nature of iterative decoders, their performance degrades in the presence of small loops. A loop (or cycle) is defined as a closed path without repeating nodes. This implies that it has an even length. Lifts can be chosen to implement the loop property in the graph. Accordingly, it is desirable to have schemes for generating LDPC codes for multiple lifts, all of which have good loop properties (e.g., few or no small loops). Decoding an LDPC code to find the most likely original message involves propagating probabilistic messages around the graph of the LDPC code. If the graph does not contain loops, the decoding can usually be computed quickly. Unfortunately, strong LDPCs use cycles in their graphs. As a result, the LDPC algorithm iterates repeatedly until it is told to stop or it converges to a solution. The reason is that in short loops, the value of an incorrect bit will propagate back to itself, which effectively strengthens its confidence and resists the LDPC algorithm's efforts to correct it. However, this effect is diluted in longer loops and does not have such a large impact on the performance of the decoder.

[0140] Taking the modulo of any arbitrary boost size (e.g., a boost size that does not belong to the family) may result in a PCM with bad loops / sets, which may lead to incorrect rounding down and performance degradation.

[0141] Each family j can be designed (e.g., optimized) such that modulo operations within the family do not lead to or minimize the formation of undesirable loops. For example, a PCM for boosting size aj can be selected (e.g., designed) to minimize or avoid the formation of undesirable loops. Boosting size a can be obtained by considering the PCM obtained in the first step and then further boosting it by 2. j 2. This minimizes the number of bad loops in the second step. This process continues until the PCM with the largest boost size in the family is generated. Therefore, generating a family involves describing the PCM corresponding to the largest boost size in the family by multiplying its leader by a power of 2 up to the largest number. Next, modulo operations are used to obtain the boost values ​​for the remaining boosts in the family.

[0142] Depending on certain aspects, for each code rate point, the PCM can be extended for an Incremental Redundancy (IR) Hybrid Automatic Repeat Request (HARQ) scheme. For each code rate point (e.g., the first transmission), an extended (IR HARQ) PCM can be described (e.g., generated) for each family, corresponding to the maximum boost size.

[0143] Example: Standalone clustering scheme for efficient LDPC code enhancement

[0144] In a wireless communication system (e.g., wireless communication system 100), a set of error-correcting codes (e.g., LDPC codes) may be used, for example, for various ranges of block lengths and / or code rates to be used. For the sake of efficiency in terms of implementation and descriptive simplicity, this set of codes is expected to be relevant.

[0145] As mentioned above Figure 9 As described, a base graph or parity check matrix (PCM) (with K columns of information bits and N columns of total transmission bits) can be replicated, and these copies can be interconnected by random permutations of each edge bundle, thus providing a lifted LDPC code. Practical codes use cyclic permutations or cyclic permutation matrices to interconnect copies of the lifted base graph, resulting in quasi-cyclic codes, which can be more easily implemented in hardware. In one example, for a lift value Z, each edge in the base PCM is associated with an integer lift value k in the range [0, Z-1]. This associated integer represents the identity matrix cyclically shifted by that integer. A table can be used for the base PCM to show entries for the bit columns and check nodes. Each entry corresponds to a cyclic matrix, which is the identity matrix cyclically shifted with an integer value associated with the edge between the variable node and the check node. An entry '.' can be used when there is no edge between the base variable node and the base check node.

[0146] When the basemap is reused without modification, the code rate (given by K / N) is the same for all boosts Z (corresponding to the number of boosts or copies of the basemap). Using different boost values ​​can provide a set of codes (e.g., a code family) to achieve a range of block lengths (given by KZ). Therefore, using different boost values ​​on an unchanged basemap can achieve a set of codes with similar code rates but different block lengths. Different basemaps can be used for different code rates.

[0147] To generate / describe a set of codes (e.g., a code family) for a range of code rates and / or block lengths, one way to design a code family is to design a different base PCM for each code rate and each boost value. For example, in 802.11n, there are four code rates (1 / 2, 2 / 3, 3 / 4, 5 / 6) and three block lengths (648, 1296, 1944) corresponding to boost values ​​(27, 54, 81). For each "tuple" (i.e., each pair of code rate and boost value), there is a dedicated base PCM of size 24 bits, resulting in 12 base PCMs (e.g., for combinations of code rates and boost values: (1 / 2, 27), (1 / 2, 54), (1 / 2, 81), ... (5 / 6, 81)). Therefore, for larger Z values, the set of boost Z and boost values ​​k can lead to greater description complexity.

[0148] A technique is desired for efficiently describing / generating lift sets. The lift set for a single parity matrix can be efficiently described as a series of progressively increasing lifts that are closely spaced from each other in value. This allows lifts to be specified over a narrow range by sharing a set of bits, thus enabling concise descriptions and good performance.

[0149] In one example, a transmitter / encoder device (e.g., BS 110 or UE 120) determines a base matrix associated with a cluster of lift size values. The transmitting device selects a lift size value Z to generate a lifted LDPC code through permutations of the edges in the base matrix. The lift size values ​​in the lift size value cluster are within each other's defined ranges. The transmitting device generates a lifted matrix based on the base matrix and / or the selected lift size value. The transmitting device uses the generated lifted matrix to generate a lifted LDPC code, encodes a set of information bits based on the lifted LDPC code to produce a codeword, and transmits the codeword over the wireless medium.

[0150] According to various aspects of this disclosure, for the sake of brevity, a set of lifts Z for a single base map or PCM used to obtain an LDPC code family can be described (e.g., determined / generated) using lift values ​​that are close to each other in value.

[0151] A base graph can be used with a series of progressively increasing lifts (with lift values ​​Z1, Z2, ..., Z).n This can be referred to as a "tower" in this document, used together to obtain the LDPC code family. A cluster includes members within each other's defined ranges. For example, cluster members can be within a certain ratio of each other. In some cases, the values ​​of cluster members can be within a ratio of 2 of each other.

[0152] An example of a cluster is a set of lifting values ​​{4, 5, 6, 7}, which has a maximum ratio of 7 / 4. A tower can be obtained by applying exponents to integers (such as powers of 2). Therefore, a cluster lifting tower can contain integers 2. j {4,5,6,7}, j=1,…,7. This gives the set of 28 approximately exponentially spaced values ​​of Z. In other words, this gives the tower Z1,Z2,…,Z 28 =8(2) 1 *4),10,12,14,…,896(2 7 *7). For a fixed j, four lift values ​​are within multiples of each other by 7 / 4 and can form a lift value cluster. For j = 1,...,7, the clustered lift tower can be represented as 2. j {4,5,6,7}. While this example includes a cluster with a lift set within a multiple of 2, other multiples (e.g., 3, 4, etc.) can be used. These multiples do not need to be consecutive, but should be numerically within each other's defined ranges.

[0153] Depending on certain aspects, for any lift size Z in the cluster lift set, the associated integer lift value k for edge permutation can be used for any other lift in the cluster lift set. For example, this can be done for Z=2. j 4. Design improvement value, which also applies to 2. j {5,6,7}. Therefore, describing (e.g., determining / generating / indicating / storing) LDPC code families can be performed by identifying sets of cluster lift values ​​that are close to each other (such as within multiples of each other, e.g., 2x or 3x) (associated with edges in the base graph). In the example above, this corresponds to identifying the lift value set {4,5,6,7} and other sets in the lift tower {16, 20,24,28}, {32,40,48,56}, ... {512,640,768,896}, which are within twice the size of each other. For each cluster lift set, a base PCM can be optimized for the minimum lift value in the cluster (e.g., Z = 8). This optimized base PCM can be used for other lift values ​​in the cluster (e.g., Z = 10, Z = 12, Z = 14). Similarly, optimized base PCMs can be determined for other cluster lift sets.

[0154] Therefore, a shared set of bits can be used to specify (e.g., store / indicate) promotion within each other's defined scope. For example, for cluster 2 j The four lifts in {4,5,6,7}, each lift value with j+2 bits can be used to specify all lifts.

[0155] These lifts can be further improved by adding additional bits. For example, using j+3 bits to represent the lift value k on the edge and for 2 j In {4,5,6,7}, Z is boosted by taking the j+3 bit value modulo Z, resulting in Z=2. j The boost of *4 is given by j+2 lower-order bits, while the higher-order bits only affect the other 3 boosts. Higher-order bits can be used similarly. This example presents a boost range within twice each other, and all boosts are specified using j+2 (or slightly larger) bits. However, other multiples can be used, as long as these multiples are numerically within each other's defined range.

[0156] Generally, the goal of lifting and graph optimization is to reduce the number of small loops in the Tanner graph of LDPC codes. Loops in the lifted Tanner graph correspond to loops in the base graph by projecting the loops onto the base graph. Additional optimizations can consider the degree of nodes in the loops. In the case of a matching lifted graph (e.g., a cyclically lifted graph), when the lift value traversed in a loop simplifies to a unit permutation, a loop in the base graph is also a loop in the lifted Tanner graph.

[0157] Depending on the context, j+3 bits are used to represent the boost and for 2 j In {4,5,6,7}, Z is boosted by taking the j+3 bit value modulo Z, resulting in Z = 2. j The boost of 4 is given by j+2 lower-order bits, while the higher-order bits only affect the other 3 boosts.

[0158] To optimize the base graph used for cluster boosting sets, the range [0, (2...] can be used. j *4)-1] Select a boost value. In other words, a boost value can be selected from a range smaller than the minimum boost size in the cluster boost set. Therefore, in the example described in this paper, for the cluster boost tower of j=1, a boost size value can be selected from the range [0:7].

[0159] For a cyclically boosted graph, each edge in the base graph has an associated integer as its boost value. This value is positive when traversing the edge in the direction from variable to check, and negative when traversing the edge in the direction from check to variable. Given the cycles and boost size Z in the base graph, if the sum of the cycles with corresponding integers is 0 or a multiple of Z, then the base cycle will also be a boosted cycle. Therefore, when choosing the range [0, 2] for the boost value... j When the integer value is within 4], Z = 2 j The goal of 4 is to avoid summing to 0 or having 2 in the sum of loops. j Multiples of 4. For small loops, the sum is usually not very large, so in general, the sum is on the order of 2. j The number of such loops in 4 is more than the sum of 2*2. j 4 or 3*2 j A loop of 4. Similarly, on average, the sum is on the order of 2. j {5,6,7} and their multiples have low frequencies. Therefore, the design problem of avoiding small loops is similar for these closely related values, where the range [0:2] j The boost value within 4] is used for Z=2 j The range available for {5,6,7} is more than half. For much larger Z values, the portion used will be smaller, and there will be a larger gap between the best performance available for larger Z values ​​and the best performance achievable by limiting the boost to smaller Z values. Therefore, it is prudent to apply this approach within a relatively small range of Z values ​​(e.g., within a factor of 2). Thus, it is possible to find boost values ​​that provide good performance for all four values ​​simultaneously.

[0160] By utilizing a lift range that is numerically within a defined range and using a separate set of bits for each j (where j = 1, ..., 7), the number of bits required to specify all lifts for each edge is 3 + 4 + 5 + 6 + 7 + 8 + 9 = 42 bits. This requirement can be further reduced by creating dependencies between different values ​​of j. Additionally, structured LDPC graphs will typically have special edges whose lift values ​​can be directly determined. For example, an edge connecting a variable node with a degree of 1 can always have a lift value of 0. Edges on cumulative chains in the encoded structure are also typically set to 0. Such fixed lift structures do not change with lift variations and can be referred to as having a special invariant structure. The lift values ​​of such edges can be represented more concisely. However, the number of edges with such special invariant structures is a small fraction of the total number of edges in the graph and does not significantly diminish the benefits of the above methods for edges that do not have special invariant structures.

[0161] Example: Nested schemes for efficiently improving LDPC codes

[0162] As described above, the lifts in a clustered lift set (e.g., a "lifting tower") can use the same lift value (an integer associated with an edge permutation), and therefore the number of bits used to specify all lifts and lift values ​​can be reduced. This reduction in size allows for a reduction in the amount of memory used to store descriptions of all LDPC codes.

[0163] According to various aspects of this disclosure, nesting schemes for efficiently boosting LPDC codes can be used, which further reduce the number of bits per edge in the base PCM.

[0164] Since all boosts (even for different j values ​​(e.g., boosts in different cluster sets)) are based on the same base graph, it is found that structures suitable for small j values ​​(i.e., boosts in the corresponding cluster boost set) can be scaled and reused for larger j values ​​(i.e., larger boosts in another set). For example, structures optimized for smaller j can be preserved and scaled for larger j to reuse the optimized bits found for smaller j.

[0165] In one example, a transmitter / encoder device (e.g., such as BS 110 or UE 120) determines a base matrix associated with a cluster of boosted size values. The transmitting device selects a first boosted size value from the cluster to generate a boosted LDPC code by permuting the edges in the base matrix. The boosted size values ​​in the cluster are within defined ranges of each other. The transmitting device generates a first boosted matrix based on the base matrix and / or the selected first boosted size value, and selects a set of bits associated with the selected first boosted size value. The transmitting device selects a second boosted size value from the cluster and generates a second boosted matrix based on the base matrix, the selected second boosted size value, and the set of bits. The transmitting device uses the generated second boosted matrix to generate a boosted LDPC code, encodes a set of information bits based on the boosted LDPC code to produce a codeword, and transmits the codeword.

[0166] In the example above, for j=1, the cluster boost set Z={8,10,12,14} can be designed using boost values ​​in the range [0,1,2,…7]. Depending on certain aspects, the boost value chosen for the j=1 graph can be multiplied by 2 and used for the j=2 graph, where the cluster boost set is Z={16,20,24,28}. In this case, the larger boosted graph (for j=2) inherits and improves the loop structure of the smaller graph because the larger graph used for boosting 2Z contains two parallel copies of the original smaller graph with boost Z. Because the smaller graph is designed to avoid loop sums being multiples of Z, it also avoids loop sums being multiples of 2Z. j=1 and j=2 are merely examples. In all respects, the boost value of any cluster boost set can be used for another larger cluster boost set, and the boost value can be multiplied by a multiple of the difference in boost size between the two boost sets.

[0167] Further optimization of larger graphs can be achieved by changing the least significant bit in the boost. For example, after multiplying by 2, all boosts set their least significant bit to 0. More generally, to achieve the best possible performance, more than just the least significant bit can be changed. For example, two or three least significant bits can be changed. Typically, optimizing the three least significant bits results in near-optimal performance. This preserves the large-scale property of the boost (most significant) bits, scaling (multiplying by 2) accordingly, and then improving the details (lower-order bits) to find the optimal solution for the base graph used for the next set of cluster boosts.

[0168] In one example, the three lowest-order bits can be reoptimized. For a cluster boost set j=1, a 3-bit optimized boost can be obtained for each edge. If the boost values ​​of an edge in the base graph (e.g., the minimum boost in set j=1) are radix 2 a, y, and z (i.e., 3 bits) (i.e., each of a, y, and z is an integer value 0 or 1), then for a base graph with a cluster boost set j=2, the same edge will have boost values ​​a, b, w, x (i.e., 4 bits, where one bit is copied from the j=1 family), and in a base graph with a cluster boost set j=3, the edge will have boost values ​​a, b, c, u, v (5 bits, where 2 bits are copied from the j=2 family), and so on. Therefore, for the base graph of the clustered lifting set j=7, the edge will have lifting values ​​a, b, c, d, e, f, g, r, s (i.e., 9 bits, where 7 bits are copied from the j=6 family) and bits a, b, c, d, e, f, g are reused for the smaller clustered lifting set j, while bits r and s are dedicated to j=7. The base graph of the clustered lifting set uses j shared bits and 2 dedicated bits. Thus, for all families j=1…7, there are a total of 7 shared bits and 14 dedicated bits (i.e., 2 dedicated bits per j), for a total of 21 bits used to describe all 7 code families. This is known as the “nested” scheme for describing LDPC code families. If only the two lowest-order bits are re-optimized, then only 14 bits are needed in total. In some examples, the most significant bit (MSB) or any coherent subset of bits (instead of the LSB) can be used as shared bits. Both of these cases provide a substantial improvement over the independent 42-bit case.

[0169] As discussed above, some structured LDPC graphs can have special invariant structures; for example, some special edges can have invariant lifts. For instance, the 802.11 coding structure uses lift values ​​of 0 and 1. If this structure is preserved, it is consistent with the above low-order bit optimization only if at least two low-order bits are optimized. This is because 2 x 1 = 2; therefore, if only the lowest-order bits are optimized, the value 1 cannot be achieved, since only 2 and 3 are possible values. In this case, it might be preferable to preserve the lift value of 1. Similar techniques can be used where low-order bits are preserved across different j, while higher-order bits are re-optimized. In general, some bits from smaller j can be reused to define values ​​for larger j, while leaving enough bits for optimization to achieve good performance.

[0170] in conclusion

[0171] The encoding techniques described in this paper for high-performance, flexible, and concise LDPC codes can lead to improved processor performance. For example, these techniques can allow processors to efficiently encode information of various block lengths and code rates using good codes (e.g., codes with few loops). For example, devices (such as...) Figure 1 The processing system in BS 110 or UE 120 shown may encode and / or decode codewords faster or more efficiently (e.g., consume less power) than a device that encodes and / or decodes codewords according to aspects of this disclosure.

[0172] The methods disclosed herein include one or more steps or actions for achieving the described methods. These method steps and / or actions may be interchanged without departing from the scope of the claims. In other words, unless a specific order of steps or actions is specified, the order and / or use of specific steps and / or actions may be modified without departing from the scope of the claims.

[0173] As used herein, the phrase “at least one of” refers to any combination of these items, including a single member. As an example, “at least one of a, b, or c” is intended to cover: a, b, c, ab, ac, bc, and abc, as well as any combination with multiple identical elements (e.g., aa, aaa, aab, aac, abb, acc, bb, bbb, bbb, bbc, cc, and ccc, or any other ordering of a, b, and c).

[0174] As used herein, the term "determine" encompasses a wide variety of actions. For example, "determine" can include calculation, computation, processing, derivation, research, searching (e.g., looking in a table, database, or other data structure), probing, and the like. Furthermore, "determine" can include receiving (e.g., receiving information), accessing (e.g., accessing data in memory), and the like. Moreover, "determine" can also include parsing, selecting, choosing, establishing, and similar actions.

[0175] In some cases, a device may not actually transmit frames, but may have an interface for outputting frames for transmission. For example, a processor may output frames to an RF front end for transmission via a bus interface. Similarly, a device may not actually receive frames, but may have an interface for obtaining frames received from another device. For example, a processor may obtain (or receive) frames from an RF front end for transmission via a bus interface.

[0176] The various operations described above can be performed by any suitable device capable of performing the corresponding function. These devices may include various hardware and / or software components and / or modules, including but not limited to circuits, application-specific integrated circuits (ASICs), or processors. Generally, where the operations illustrated in the figures are present, these operations may have corresponding paired devices with similar designations plus functional components.

[0177] For example, the means for encoding, the means for determining, the means for selecting, and / or the means for generating may include one or more processors, such as... Figure 4 The BS 110 described in the text includes a TX MIMO processor 430, a transmitter processor 420, and / or a controller / processor 440. Figure 4 The TX MIMO processor 466, transmit processor 464, and / or controller / processor 480 of the UE 120 illustrated in Figure 11; and / or encoder 1102 of the encoder 1100 illustrated in Figure 11. The apparatus for punching may include a processing system, which may include... Figure 4 One or more processors, and / or Figure 11 The encoder 1100 described in the text has a perforated module 1104. The means for transmission includes a transmitter, which may include... Figure 4 The BS 110 described in Figure 4 includes a transmit processor 420, a TX MIMO processor 430, modulators 432a-432t, and / or antennas 434a-434t; the UE 120 described in Figure 4 includes a transmit processor 464, a TX MIMO processor 466, modulators 454a-454r, and / or antennas 452a-452r; and / or Figure 11 The TX chain 1108 and antenna 1110 of encoder 1100 are explained in the middle.

[0178] The various illustrative logic blocks, modules, and circuits described in this disclosure can be implemented or executed using a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device (PLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof, designed to perform the functions described herein. The general-purpose processor may be a microprocessor, but in alternatives, the processor may be any commercially available processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors cooperating with a DSP core, or any other such configuration.

[0179] If implemented in hardware, an example hardware configuration could include a processing system in a wireless node. The processing system can be implemented using a bus architecture. Depending on the specific application and overall design constraints of the processing system, the bus can include any number of interconnect buses and bridges. The bus can link together various circuitry, including a processor, machine-readable media, and a bus interface. The bus interface can be used to connect network adapters, etc., to the processing system via the bus. The network adapter can be used to implement signal processing functions at the PHY layer. In a wireless node (see...), Figure 1 In such cases, the user interface (e.g., keypad, display, mouse, joystick, etc.) can also be connected to the bus. The bus can also link various other circuits, such as timing sources, peripherals, voltage regulators, power management circuits, and similar circuits, which are well known in the art and will not be described further. The processor can be implemented using one or more general-purpose and / or special-purpose processors. Examples include microprocessors, microcontrollers, DSP processors, and other circuit systems capable of executing software. Depending on the specific application and the overall design constraints imposed on the system, those skilled in the art will recognize how best to implement the functionality described for the processing system.

[0180] If implemented in software, the functions may be stored or transmitted as one or more instructions or codes on a computer-readable medium. Software should be broadly interpreted to mean instructions, data, or any combination thereof, whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. Computer-readable media includes both computer storage media and communication media, including any medium that facilitates the transfer of a computer program from one location to another. The processor may be responsible for managing the bus and general processing, including executing software modules stored on the machine-readable storage medium. The computer-readable storage medium may be coupled to the processor so that the processor can read and write information to / from the storage medium. Alternatively, the storage medium may be integrated into the processor. As an example, the machine-readable medium may include a transmission line, a carrier wave modulated by data, and / or a separate computer-readable storage medium containing instructions stored thereon, all accessible to the processor via a bus interface. Alternatively or additionally, the machine-readable medium or any portion thereof may be integrated into the processor, such as caches and / or general-purpose register files. As an example, examples of machine-readable storage media may include RAM (random access memory), flash memory, ROM (read-only memory), PROM (programmable read-only memory), EPROM (erasable programmable read-only memory), EEPROM (electrically erasable programmable read-only memory), registers, disks, optical disks, hard drives, or any other suitable storage media, or any combination thereof. Machine-readable media may be implemented in computer program products.

[0181] Software modules may comprise a single instruction or a number of instructions, and may be distributed across several different code segments, across different programs, and across multiple storage media. Computer-readable media may include several software modules. These software modules include instructions that, when executed by a device (such as a processor), enable the processing system to perform various functions. These software modules may include transfer modules and receive modules. Each software module may reside in a single storage device or be distributed across multiple storage devices. As an example, when a trigger event occurs, a software module may be loaded from a hard drive into RAM. During the execution of a software module, the processor may load some instructions into a cache to improve access speed. One or more cache lines may subsequently be loaded into a general-purpose register file for processor execution. In the context of the functionality of the software module described below, it will be understood that such functionality is implemented by the processor when the processor executes the instructions from the software module.

[0182] Any connection is also legitimately referred to as computer-readable medium. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technology (such as infrared (IR), radio, and microwave), then that coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technology (such as infrared, radio, and microwave) is included in the definition of medium. As used herein, disk and disc include compact discs (CDs), laser discs, optical discs, digital multi-purpose discs (DVDs), floppy disks, and... Disks, where disks often magnetically reproduce data, and discs optically reproduce data using lasers. Therefore, in some aspects, computer-readable media may include non-transient computer-readable media (e.g., tangible media). Additionally, in other aspects, computer-readable media may include transient computer-readable media (e.g., signals). Combinations of the above should also be included within the scope of computer-readable media.

[0183] Therefore, certain aspects may include computer program products for performing the operations given herein. For example, such computer program products may include computer-readable media on which instructions are stored (and / or encoded) that can be executed by one or more processors to perform the operations described herein.

[0184] Furthermore, it should be understood that modules and / or other suitable means for performing the methods and techniques described herein can be downloaded and / or otherwise obtained by the wireless node and / or base station where applicable. For example, such devices can be coupled to a server to facilitate the transfer of means for performing the methods described herein. Alternatively, the various methods described herein can be provided via a storage device (e.g., RAM, ROM, physical storage media such as CDs or floppy disks, etc.) so that the device can obtain the various methods once the storage device is coupled to or provided to the wireless node and / or base station. Furthermore, any other suitable techniques appropriate for providing the methods and techniques described herein to the device can be utilized.

[0185] It will be understood that the claims are not limited to the precise configurations and components described above. Various modifications, substitutions, and variations can be made to the layout, operation, and details of the methods and apparatus described above without departing from the scope of the claims.

Claims

1. A method for wireless communication, the method comprising: Obtain the set of information bits; A boosted low-density parity-check code is generated from boosted size values ​​derived from a plurality of families of boosted size values, wherein the plurality of families of boosted size values ​​includes a first family of boosted size values ​​and a second family of boosted size values, wherein the first family of boosted size values ​​comprises the product of a first integer and each of a plurality of powers of 2, and the second family of boosted size values ​​comprises the product of a second integer and each of the plurality of powers of 2, wherein the first integer is different from the second integer, wherein generating the boosted low-density parity-check code further comprises: A set of cyclic lift values ​​associated with the lift size value is applied to interconnect edges in several copies of a base graph associated with a base parity matrix, the number of copies corresponding to the lift size value; The information bit set is encoded based on the enhanced low-density parity-check code to generate one or more codewords; as well as Signaling associated with one or more codewords is transmitted across a wireless channel using radio technology.

2. The method of claim 1, wherein the first integer and the second integer are from a plurality of different integers associated with the plurality of families of lift size values, and wherein the plurality of different integers are within a defined range of each other.

3. The method of claim 2, wherein the plurality of different integers within each other's defined ranges include integers that are 2 or 3 times each other.

4. The method of claim 1, wherein the boost size value includes the minimum boost size value or the maximum boost size value in one of the plurality of boost size value families.

5. The method of claim 1, further comprising: The set of cyclic boost values ​​is determined based on modular arithmetic, wherein the divisor of the modular arithmetic is the boost size value, and the dividend of the modular arithmetic is the set of cyclic boost values ​​corresponding to the largest boost size value in the boost size family to which the boost size value belongs.

6. The method of claim 1, wherein the boost size value is selected based on a target range of block lengths of the one or more codewords.

7. The method of claim 1, wherein determining the set of cyclic boost values ​​comprises: Scale each loop boost value in the loop boost value set by a scaling value to obtain a scaled loop boost value set; as well as For each scaled loop boost value: The scaled cyclic boost value is represented as bits; Copy a portion of the bits of the scaled, cyclically boosted value; as well as Append one or more unique bits to the copied portion of bits.

8. The method of claim 7, wherein the number of partial bits is equal to the number of powers of a plurality of bits, and wherein the number of one or more unique bits is equal to the scaling value.

9. An apparatus for wireless communication, the apparatus comprising: Encoder circuitry, the encoder circuitry being configured to: Obtain the set of information bits; A boosted low-density parity-check code is generated from boosted size values ​​derived from a plurality of families of boosted size values, wherein the plurality of families of boosted size values ​​includes a first family of boosted size values ​​and a second family of boosted size values, wherein the first family of boosted size values ​​comprises the product of a first integer and each of a plurality of powers of 2, and the second family of boosted size values ​​comprises the product of a second integer and each of the plurality of powers of 2, wherein the first integer is different from the second integer, wherein generating the boosted low-density parity-check code further comprises: A set of cyclic lift values ​​associated with the lift size value is applied to interconnect edges in several copies of a base graph associated with a base parity matrix, the number of copies corresponding to the lift size value; The information bit set is encoded based on the enhanced low-density parity-check code to generate one or more codewords; and A transmitter circuit system configured to transmit signaling associated with the one or more codewords across a wireless channel according to radio technology.

10. The apparatus of claim 9, wherein the first integer and the second integer are derived from a plurality of different integers associated with the plurality of lift size value families, and wherein the plurality of different integers are within a defined range of each other.

11. The apparatus of claim 10, wherein the plurality of different integers within each other's defined ranges include integers that are 2 or 3 times each other.

12. The apparatus of claim 9, wherein the lift size value includes the minimum or maximum lift size value in one of the plurality of lift size value families.

13. The apparatus of claim 9, wherein the encoder circuitry is further configured to: The set of cyclic boost values ​​is determined based on modular arithmetic, wherein the divisor of the modular arithmetic is the boost size value, and the dividend of the modular arithmetic is the set of cyclic boost values ​​corresponding to the largest boost size value in the boost size family to which the boost size value belongs.

14. The apparatus of claim 9, wherein the boost size value is selected based on a target range of block lengths of the one or more codewords.

15. The apparatus of claim 9, wherein the encoder circuitry is configured to determine the set of cyclic boost values, wherein the encoder circuitry is configured to: Scale each loop boost value in the loop boost value set by a scaling value to obtain a scaled loop boost value set; as well as For each scaled loop boost value: The scaled cyclic boost value is represented as bits; Copy a portion of the bits of the scaled, cyclically boosted value; as well as Append one or more unique bits to the copied portion of bits.

16. The apparatus of claim 15, wherein the number of the partial bits is equal to the number of powers of a plurality of powers, and wherein the number of the one or more unique bits is equal to the scaling value.

17. A non-transient computer-readable medium including computer-executable instructions, which, when executed by a processor of a device, cause the device to perform a wireless communication method, the method comprising: Obtain the set of information bits; A boosted low-density parity-check code is generated from boosted size values ​​derived from a plurality of families of boosted size values, wherein the plurality of families of boosted size values ​​includes a first family of boosted size values ​​and a second family of boosted size values, wherein the first family of boosted size values ​​comprises the product of a first integer and each of a plurality of powers of 2, and the second family of boosted size values ​​comprises the product of a second integer and each of the plurality of powers of 2, wherein the first integer is different from the second integer, wherein generating the boosted low-density parity-check code further comprises: The set of cyclic lift values ​​associated with the lift size value is applied to interconnect the edges in several copies of a base graph associated with the interconnection basis parity matrix, the number of copies corresponding to the lift size value; The information bit set is encoded based on the enhanced low-density parity-check code to generate one or more codewords; as well as Signaling associated with one or more codewords is transmitted across a wireless channel using radio technology.

18. The non-transient computer-readable medium of claim 17, wherein the first integer and the second integer are derived from a plurality of different integers associated with the plurality of families of lift size values, and wherein the plurality of different integers are within a defined range of each other.

19. The non-transient computer-readable medium of claim 18, wherein the plurality of distinct integers within each other's defined ranges include integers that are 2 or 3 times each other.

20. The non-transient computer-readable medium of claim 17, wherein the lift size value includes the minimum or maximum lift size value in one of the plurality of lift size value families.

21. The non-transient computer-readable medium of claim 17, wherein the method further comprises: The set of cyclic boost values ​​is determined based on modular arithmetic, wherein the divisor of the modular arithmetic is the boost size value, and the dividend of the modular arithmetic is the set of cyclic boost values ​​corresponding to the largest boost size value in the boost size family to which the boost size value belongs.

22. The non-transient computer-readable medium of claim 17, wherein the boost size value is selected based on a target range of block lengths of the one or more codewords.

23. The non-transient computer-readable medium of claim 17, wherein determining the set of cyclic boost values ​​comprises: Scale each loop boost value in the loop boost value set by a scaling value to obtain a scaled loop boost value set; as well as For each scaled loop boost value: The scaled cyclic boost value is represented as bits; Copy a portion of the bits of the scaled, cyclically boosted value; as well as Append one or more unique bits to the copied portion of bits.

24. The non-transient computer-readable medium of claim 23, wherein the number of the portion bits is equal to the number of powers of a plurality of powers, and wherein the number of the one or more unique bits is equal to the scaling value.

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