Truth table extension for stacked memory systems

Abstract

Techniques are provided for expanding truth tables for stacked memory systems. In an example, a memory system can include a first memory die stack and a logic die configured to store data. The logic die can include an interface circuit configured to receive a plurality of memory requests from an external host using a first command bus, a second command bus, and a data bus, and a controller configured to interface with the first memory die stack to store and retrieve the data from the first memory die stack. The logic die can include a second memory having a faster access time than devices of the first memory die stack, and the interface circuit can directly access the second memory in response to a first memory request of the plurality of memory requests.

Description

[0001] Priority and related applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 62 / 953,819, filed December 26, 2019, entitled “TRUTH TABLE EXTENSION FOR STACKED MEMORY SYSTEMS”, which is hereby incorporated herein by reference in its entirety. Technical Field

[0003] The following text generally relates to operating memory arrays, and more specifically, to increasing the bandwidth of devices with stacked memories. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, and digital displays. Information is stored by programming different states of the memory device. For example, a binary device typically has two states, usually represented by logic "1" or logic "0". In other systems, more than two states can be stored. To access the stored information, components of the electronic device can read or sense the states stored in the memory device. To store information, components of the electronic device can write to or program the states in the memory device.

[0005] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), DRAM, synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), etc. Memory devices can be volatile or non-volatile.

[0006] Generally, improvements to memory devices can include increasing memory cell density, increasing read / write speeds, increasing reliability, increasing data retention, reducing power consumption or manufacturing costs, and other metrics. Advanced memory technologies have achieved improvements in many of these metrics; however, as processing speeds increase, memory bandwidth may become a bottleneck for overall system performance improvements. Attached Figure Description

[0007] In drawings that are not necessarily drawn to scale, similar labels may describe similar components in different views. Similar labels with different letter suffixes may indicate different instances of similar components. The figures are illustrated by way of example, not limitation, of the various embodiments discussed in this document.

[0008] Figure 1 This describes instances of memory dies that support the features and operations of embodiments according to this disclosure.

[0009] Figure 2A and 2B This section describes examples of apparatuses that support the features and operation of embodiments according to this disclosure.

[0010] Figure 3 This section generally describes an instance storage system comprising a host device capable of requesting and receiving information from a storage system, according to the subject matter of the present invention.

[0011] Figure 4A and 4B This section provides a general description of an instance truth table extension of an existing high-bandwidth memory protocol that allows access to a second type of random access memory within a memory die stack of a high-bandwidth memory device.

[0012] Figure 5A and 5B This section broadly describes an instance truth table extension of an existing high-bandwidth memory protocol that allows access to a second type of random access memory within a random access memory die stack.

[0013] Figure 6 A flowchart is provided to illustrate an instance method for operating a storage system comprising a first memory stack.

[0014] Figure 7 The diagrams generally illustrate a system comprising a device supporting a memory system including stacked DRAM, based on the aspects disclosed herein. Detailed Implementation

[0015] The features of this disclosure described above are further described below in the context of exemplary arrays (e.g., Figure 1 Next, specific instances (e.g., Figures 2 to 4) are described for various instances or aspects of the system.

[0016] Figure 1 Examples of memory die 100 according to various aspects disclosed herein are described. In some examples, memory die 100 may also be referred to as an electronic memory device, a memory array, a memory cell array, or a memory cell deck. Memory die 100 may include memory cells 105 programmable to store different states. Memory cells 105 may be arranged as one or more groups of memory cells that can be accessed independently. Each memory cell 105 is programmable to store two states identified as logic 0 and logic 1. In some cases, memory cells 105 may be configured to store more than two logic states.

[0017] In some instances, memory cell 105 may store charges representing programmable states in capacitors; for example, charged and uncharged capacitors may represent two logic states respectively. Such a design can be used in DRAM architectures, and the capacitors used may contain dielectric materials with linear or paraelectric polarization properties as insulators. FeRAM architectures may also employ such a design. In some instances, memory cell 105 may store a representation of programmable states in a cross-coupled inverter configuration. Static RAM (SRAM) architectures may use such a design.

[0018] Operations such as reading and writing can be performed on memory cell 105 by activating access line 110 and bit line 115. Access line 110 may also be referred to as word line 110, and bit line 115 may also be referred to as bit line 115. The references to word line and bit line or the like are interchangeable without affecting understanding or operation. Activating word line 110 or bit line 115 may involve applying a voltage to the respective line.

[0019] according to Figure 1 In this example, each row of memory cells 105 may be connected to a single word line 110, and each column of memory cells 105 may be connected to a single digital line 115. By activating a word line 110 and a digital line 115 (e.g., by applying voltage to the word line 110 or digital line 115), a single memory cell 105 at their intersection can be accessed. Accessing memory cell 105 may involve reading from or writing to memory cell 105. The intersection of word line 110 and digital line 115 may be referred to as the address of the memory cell. Alternatively or alternatively, for example, each row of memory cells 105 may be arranged as one or more groups of memory cells.

[0020] In some architectures, the logic storage devices of a cell, such as capacitors and flip-flops, can be electrically isolated from the digital lines via a select component (not shown). Word line 110 can be connected to and control the select component. For example, the select component can be a transistor, and word line 110 can be connected to the gate of the transistor. Activating word line 110 can electrically connect or close the circuit between the capacitor of memory cell 105 and its corresponding digital line 115. The digital line can then be accessed to read from or write to memory cell 105.

[0021] Access to memory cells 105 can be controlled via row decoder 120 and column decoder 130. For example, row decoder 120 may receive a row address from memory controller 140 and activate the appropriate word line 110 based on the received row address. Similarly, column decoder 130 may receive a column address from memory controller 140 and activate the appropriate digital line 115. Row decoder 120 and column decoder 130 may respectively receive the row address and column address of memory cells located within a specific group of memory cells. Alternatively or additionally, each group of memory cells may communicate electronically with a separate row decoder 120 and column decoder 130. For example, memory die 100 may include a plurality of word lines 110 labeled WL_1 to WL_M and a plurality of digital lines 115 labeled DL_1 to DL_N, where M and N depend on the array size. Thus, by activating word lines 110 and digital lines 115, such as WL_2 and DL_3, the memory cell 105 at their intersection can be accessed.

[0022] After accessing memory cell 105, the state stored in memory cell 105 can be determined by reading or sensing the cell through sensing component 125. For example, after accessing memory cell 105, the capacitor of memory cell 105 can be discharged to its corresponding digital line 115. In some cases, discharging the capacitor can be caused by biasing or applying a voltage to the capacitor. Discharging can cause a change in the voltage of digital line 115, and sensing component 125 can compare the voltage with a reference voltage (not shown) to determine the state stored in memory cell 105. For example, if digital line 115 has a voltage higher than the reference voltage, sensing component 125 can determine that the state stored in memory cell 105 is logic 1, and vice versa. Sensing component 125 may include various transistors or amplifiers for detecting and amplifying signal differences (which may be referred to as latching). The detected logic state of memory cell 105 can then be output as output 135 by column decoder 130. In some cases, sensing component 125 may be part of column decoder 130 or row decoder 120. Alternatively, the sensing component 125 may be connected to or in electronic communication with the column decoder 130 or the row decoder 120.

[0023] Memory cell 105 can be set or written by activating the associated word line 110 and digital line 115 in a similar manner; for example, logical values ​​can be stored in memory cell 105. Column decoder 130 or row decoder 120 can accept data to be written to memory cell 105, such as input / output 135. Memory cell 105 can be written by applying a voltage to a capacitor.

[0024] The memory controller 140 can control the operation (e.g., read, write, rewrite, refresh, discharge, etc.) of the memory cells 105 through various components such as row decoder 120, column decoder 130, and sensing component 125. In various instances, the memory controller 140 may be a component of the memory die 100 or may be external to the memory die 100. In some cases, one or more of the row decoder 120, column decoder 130, and sensing component 125 may be co-located with the memory controller 140. The memory controller 140 may generate row and column address signals to activate desired word lines 110 and digital lines 115. The memory controller 140 may activate desired word lines 110 and digital lines 115 of a specific group of memory cells via at least one channel passing through the memory die 100. The memory controller 140 may also generate and control various voltages or currents used during the operation of the memory die 100. For example, the memory controller may apply a discharge voltage to the word lines 110 or digital lines 115 after accessing one or more memory cells 105. The memory controller 140 can be coupled to the memory cell 105 via channel 145. Channel 145 in Figure 1 The description herein shows a logical connection with row decoder 120 and column decoder 130, but those skilled in the art will recognize that other configurations may be used. As described herein, memory controller 140 may exchange data (e.g., from read or write operations) with cell 105 multiple times per clock cycle.

[0025] The memory controller 140 can also be configured to transmit commands, data, and other information with a host device (not shown). The memory controller 140 can use a modulation scheme to modulate signals transmitted between the memory array and the host device. The I / O interface can be configured based on the selected modulation scheme. Generally, the amplitude, shape, or duration of the applied voltage or current discussed herein can be adjusted or changed, and may differ for various operations discussed when operating the memory die 100. Furthermore, one, more, or all memory cells 105 within the memory die 100 can be accessed simultaneously or in parallel; for example, multiple or all cells of the memory die 100 can be accessed simultaneously or in parallel during a reset operation that sets all memory cells 105 or a group of memory cells 105 to a single logic state.

[0026] Figure 2 illustrates a device or system 290 supporting channel routing for memory devices according to various examples disclosed herein. System 290 may include a host device 205 and multiple stacks 210. In conventional systems, multiple stacks may contain stacked memory dies of the same type, such as DRAM memory dies. In some instances, the stacks may contain a hybrid of capacitor-based memory devices, such as DRAM forming a main memory array, and faster access memory architectures (typically containing four to six transistors per cell), such as SRAM, for a second portion of the memory array. Alternatively, another memory technology may be used instead of DRAM. The inventors have recognized that bandwidth improvements can be achieved if the host has direct access to a second, faster deterministic type of memory (e.g., SRAM memory) in addition to the main memory array. Other forms of memory may be used as alternatives to SRAM. In some instances, ferroelectric RAM (FeRAM) may be used in combination with DRAM; or in other instances, a combination of DRAM and flash memory may be used to provide a non-volatile DRAM device (e.g., NVDIMM) that provides non-volatile memory. The greatest benefits of the described system (at least in terms of speed) will be felt by combining memory technologies with reduced access times with DRAM (or other main memory array storage technologies).

[0027] Host device 205 may be an instance of a processor (e.g., a central processing unit (CPU), graphics processing unit (GPU)) or system-on-a-chip (SoC). In some cases, host device 205 may be a component separate from the memory device, allowing host device 205 to be manufactured separately from the memory device. Host device 205 may be external to stack 210 (e.g., laptop computer, server, personal computing device, smartphone, personal computer). In system 290, the stack of memory dies 210 may be configured to store data for host device 205. The described techniques enable direct communication with the main memory array or SRAM, as further described below.

[0028] The host device 205 can exchange information with the stack of memory dies 210 using signals transmitted on a signal path. The signal path can be a feasible path for a message or transmitted content from a transmitting component to a receiving component. In some cases, the signal path can be a conductor coupled to at least two components, wherein the conductor may selectively allow electrons to flow between the at least two components. In the case of wireless communication (e.g., radio frequency (RF) or optical), the signal path may be formed in a wireless medium. The signal path may at least partially include a first substrate, such as an organic substrate of the memory device, and / or a second substrate, such as a packaging substrate (e.g., a second organic substrate) that can be coupled to at least one (if not both) of the stack 210 and the host device 205. In some cases, the stack 210 may be used as a slave device to the host device 205, which may be used as a master device.

[0029] In some applications, system 290 can benefit from the high-speed connection between host device 205 and memory device 210. Thus, some stacks 210 can support applications, processes, host devices, or processors with bandwidth requirements of several megabytes per second (TB / s). Meeting such bandwidth constraints within an acceptable energy budget can be challenging in some cases.

[0030] The memory die 200 of the stack 210 can be configured to work with various types of communication media 211 (e.g., substrates such as organic substrates and / or high-density interposers such as silicon interposers). In some cases, the host device 205 may be configured with an interface or ball-out that includes a terminal design (e.g., a matrix or pattern).

[0031] In some cases, a buffer layer may be located between memory die 200 and communication medium 211. The buffer layer may be configured to drive (e.g., redrive) signals to and from memory die 200. In some cases, the stack 210 of memory dies 200 may be unbuffered, meaning there is no buffer layer or the base layer does not contain redrives or other components. In some instances of unbuffered memory, a routing layer or logical die 206 may be located between memory die 200 or the stack of memory dies 200 and communication medium 211. In some instances, logical die 206 may form the lower layer of memory die 200. In some instances, the unbuffered memory stack 210 may contain the lowermost memory die 200 with logical die layer 206.

[0032] Figure 3This section generally describes an example storage system 391 comprising a host device 305 capable of requesting and receiving information from a storage system 310, according to the subject matter of the invention. The host device 305 may be, but is not limited to, a CPU, a graphics processing unit (GPU), an accelerated processing unit (GPU), a digital signal processor (DSP), a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), and any other component of a larger system communicating with the storage system 310. In some embodiments, the device 305 may be multiple devices accessing the same storage system 310. The storage system 310 may include a logic die 306 integrated with a memory stack 320, such as a stack of dynamic random access memory (DRAM) devices.

[0033] The logic die 306 may include a host interface 331 connected to the stacked DRAM controller 332 and the prefetch and cache logic 333. The stacked DRAM controller 332 is connected to and interfaces with the memory stack 320. The prefetch and cache logic 333 may be connected to a prefetcher, a prefetch buffer, and a cache array 334. The prefetcher may be a hardware prefetcher. The prefetch buffer and cache array 334 may be, but is not limited to, an SRAM array, any other memory array technology, or registers.

[0034] The host interface 331 may include a command decoder 335 and an interface register 336. The host interface 331, and more specifically, the command decoder 335, may receive all incoming memory requests to the memory stack 320 from the device 305. Requests may be sent to prefetch and cache logic 333 (e.g., next line, step, etc.). The prefetch and cache logic 333 may monitor incoming memory requests. Prefetched data may be placed in a prefetch buffer and cache array 334. The prefetch and cache logic 333 may also check any incoming memory requests against the data in the prefetch buffer and cache array 334. Any hits may be provided directly from the prefetch buffer and cache array 334 without going to the stacked DRAM controller 332. This reduces the latency of these requests and reduces contention for any remaining requests in the stacked DRAM controller 332 (i.e., requests that do not hit the prefetch buffer and cache array 334).

[0035] The prefetcher can encompass any prefetch algorithm / method, or a combination of algorithms / methods. Due to the row-buffer-based organization of most memory technologies (e.g., DRAM), prefetch algorithms utilizing spatial positioning (e.g., next row, small stride, etc.) have relatively low overhead because the prefetch request will (likely) hit the memory's row buffer. Implementations can issue prefetch requests for large data blocks (i.e., data exceeding one 64B cache line), such as prefetching the entire row buffer, half of the row buffer, or other granularities.

[0036] The prefetch buffer and cache array 334 can be implemented as a directly mapped, set-associative, fully associative cache class structure. In one embodiment, the prefetch buffer and cache array 334 can be used to serve only read requests (i.e., writes would invalidate prefetch buffer entries, or a write-through strategy must be used). In another embodiment, the prefetch buffer and cache array 334 can employ a replacement strategy, such as Least Recently Used (LRU), Least Frequently Used (LFU), or First-In-First-Out (FIFO). If the prefetch unit generates a request for data larger than the cache line size (as described above), the prefetch buffer and cache array 334 may also need to be organized with correspondingly wider data block sizes. In some embodiments, sub-blocking can be used.

[0037] Although described herein as being used in a memory organization consisting of a logic chip and one or more memory chips, other physical manifestations exist. While described as a vertical stack of logic dies with one or more memory chips, another embodiment may place some or all of the logic on a separate chip, which is horizontally positioned on an insert or packaged together in a multi-chip module (MCM). More than one logic chip may be included throughout the stack or system.

[0038] In some instances, host interface 331 may directly access a portion of buffer and cache array 334, or a separate instance of SRAM-type memory 337. In such instances, command decoder 335 responds to a command truth table containing commands that extend beyond accessing and servicing DRAM memory stack 320. More specifically, command decoder 335 may respond to commands for direct access to SRAM-type memory device 337 located on logic die 306. As used herein, SRAM-type memory comprises memory with latency less than that of DRAM memory in a memory system. Information can be accessed with less latency in such memory compared to information stored at stacked memory 320. In some instances, information can be accessed with less latency by directly accessing an instance of SRAM 337, such as at logic die 306, compared to information available at prefetch buffer or cache array 334 via prefetch and cache logic 333.

[0039] Figure 4A and 4BThis invention broadly describes an example truth table extension of an existing high-bandwidth memory protocol that allows access to a second type of random access memory within a random access memory die stack. Such stacks can be used in high-bandwidth memory packages. In some instances, systems suitable for operation with a hybrid memory stack containing DRAM and faster SRAM can also operate with conventional memory stack systems containing homogeneous memory die stacks. The inventors have recognized that unused states of existing interface protocols can be utilized to allow memory controllers to specifically command and control faster memory to improve overall memory system bandwidth. In some instances, each channel provides independent access to memory regions of the memory stack. In some instances, each channel can operate independently of another channel. Each channel may contain independent command and data interfaces. In some instances, each command and data interface may contain several signals or terminations, including data (DQ[N]). D :0]), list command / address (C[N C :0]) and line command / address (R[N R :0]), where N D N C and N R This can be the maximum signal address of the corresponding group or bus for a signal or termination. In some instances, specific operations of the memory die stack can be initiated by properly setting the corresponding signals of the row command / address and column command / address when the clock signal is received. The general operation of the DRAM stack uses the first few signals of the row command / address signal (R[3:0]) and the first few signals of the column command / address signal (C[3:0]) to initiate various operations of the DRAM device stack. In some instances, the channel couples the interface of the memory controller to the device interface and device control circuitry of one or more of the memory dies in the stack.

[0040] In some instances where a memory die stack contains one or more SRAM arrays, the memory controller can access the SRAM arrays using an extension of a conventional row and column command truth table (such as the row and column truth table provided in JEDEC Standard No. 235B). Figure 4A This section provides a general explanation of instance command truth table expansion. Figure 4B This section provides a general overview of column truth table expansion. In some instances, unlike conventional methods, row and column command / address signals can work together to initiate individual operations that access one or more SRAM arrays within a memory die stack.

[0041] For example, upon receiving a rising clock signal and additional signals (where R0 through R2 represent logic "H", "L", and "H" respectively) on a row command / address, the SRAM device's memory device controller can recognize that the memory controller is requesting access to the SRAM device. The remaining row command / address signals and column command / address signals provide additional information to confirm the SRAM access request, provide address information, and specific command information, such as whether the request is a read request, a write request, and whether the buffer should be used for data. (Reference) Figure 4A The signal or termination on the rising edge of the clock signal (R3 through R5) and the signals on the falling edge of the clock signal (R0, R4, and R5) provide a portion of the SRAM address (A10 through A15) for the requested SRAM access. The "D" at R6 on the falling edge of the clock (CLK) indicates "not relevant" and signifies that the logic level is irrelevant to the illustrated example. Reference Figure 4B The signals of the column command / address interface on the same channel (including C3 to C7 on the rising edge of the clock and C1 and C3 to C6 on the falling edge of the clock signal) provide the remainder of the SRAM address (A0 to A9) for the requested SRAM access. On the rising edge of the clock signal, with C0 set to "low" and C1 set to "high", C0 and C1 can verify that the command address information provided to the memory controller is an SRAM access request. Additionally, on the rising edge, the state of C2 can indicate whether the access is a "read" or "write" access. SID0 and SID1 can indicate the device stack identifier used for the SRAM access command.

[0042] Existing stacked DRAM devices can operate in several modes. As stacked DRAM technology has evolved, several modes have been added. In some instances, one such operating mode is often referred to as a pseudo-channel mode. A pseudo-channel mode divides a channel into two individual sub-channels or pseudo-channels. Both pseudo-channels can operate semi-independently. Pseudo-channels can share the channel's row command / address bus and column command / address bus; however, each pseudo-channel can execute and decode commands individually. The command / address signal BA4 can be used to direct SRAM access commands to one of the two pseudo-channels. In some instances, the command information may include a parity bit (PAR), which is used to ensure that the command information on the row command / address interface or column command address interface is not corrupted before being received by the memory controller.

[0043] In some instances, SRAM and DRAM access commands can be isolated from the external bus connecting the host and the host interface. In such instances, memory access commands do not provide read data to or receive write data from the external bus; instead, they use internal buffers (such as prefetch buffers or similar registers) to capture data read from SRAM or stacked DRAM and provide data for SRAM write or stacked DRAM write commands. In such instances, the column command address signal C8 on the falling edge of the clock signal provides a binary state indicating whether an internal buffer or an external bus will be used as the data target for the memory access command. In some instances, a column command / address bit, such as the C8 bit, can be used on the falling edge of the clock signal (CLK) to indicate to the memory controller or the host interface's command decoder the data location to be used for direct SRAM or stacked DRAM access commands. In a first state, the C8 bit indicates that the memory controller can use the external data bus as the data location for the memory access command. In a second state, the C8 bit indicates that the memory controller can use an internal buffer as the data location for the memory access command.

[0044] Figure 5A and 5B This document broadly describes an instance truth table extension of an existing high-bandwidth memory protocol that allows access to a second type of random access memory within a random access memory die stack. Such stacks can be used in high-bandwidth memory packages. [The last sentence appears to be incomplete and possibly refers to a different topic.] Figure 4A and 4B Compared to the cases that are solved by the example, Figure 5A and 5B The instance allows for a larger capacity SRAM.

[0045] For example, upon receiving a rising clock signal and additional signals (where R0 through R2 represent logic "H", "L", and "H" respectively) on a row command / address, the SRAM device's memory device controller can recognize that the memory controller is requesting access to the SRAM device. The remaining row command / address signals and column command / address signals provide additional information to confirm the SRAM access request, provide address information, and specific command information, such as whether the request is a read request, a write request, and whether the buffer should be used for data. (Reference) Figure 5A The signal or termination on the rising edge of the clock signal (R3 to R5) and the signals on the falling edge of the clock signal (R0, R4, and R5) provide a portion of the SRAM address (A12 to A20) for the requested SRAM access. Reference Figure 5BThe signals of the column command / address interface on the same channel (including C3 to C7 on the rising edge of the clock and C1 and C3 to C6 on the falling edge of the clock signal) provide the remainder of the SRAM address (A0 to A11) for the requested SRAM access. On the rising edge of the clock signal, with C0 set to "low" and C1 set to "high", C0 and C1 can verify that the command address information provided to the memory controller is an SRAM access request. Additionally, on the rising edge, the state of C2 indicates whether the access is a "read" or "write" access.

[0046] Existing stacked DRAM dies can operate in several modes. As stacked DRAM technology has evolved, several modes have been added. In some instances, one such operating mode is often referred to as a pseudo-channel mode. A pseudo-channel mode divides a channel into two individual sub-channels or pseudo-channels. Both pseudo-channels can operate semi-independently. Pseudo-channels can share the channel's row command / address bus and column command / address bus; however, each pseudo-channel executes and decodes commands individually. The command / address signal BA4 can be used to direct SRAM access commands to one of the two pseudo-channels. In some instances, the command information may include a parity bit (PAR), which is used to ensure that the command information on the row command / address interface or column command address interface is not corrupted before being received by the memory controller.

[0047] In some instances, SRAM and DRAM access commands can be isolated from the external bus connecting the host and the host interface. In such instances, memory access commands do not provide read data to or receive write data from the external bus; instead, they use internal buffers (such as prefetch buffers or similar registers) to capture data read from SRAM or stacked DRAM and provide data for SRAM write or stacked DRAM write commands. In such instances, the column command address signal C8 on the falling edge of the clock signal provides a binary state indicating whether an internal buffer or an external bus will be used as the data target for the memory access command. In some instances, a column command / address bit, such as the C8 bit, can be used on the falling edge of the clock signal (CLK) to indicate to the memory controller or the host interface's command decoder the data location to be used for direct SRAM or stacked DRAM access commands. In a first state, the C8 bit indicates that the memory controller can use the external data bus as the data location for the memory access command. In a second state, the C8 bit indicates that the memory controller can use an internal buffer as the data location for the memory access command.

[0048] Figure 6A flowchart generally illustrates an example method 600 for operating a memory system comprising a first memory stack. In some instances, the memory system may include logical dies, a memory controller, a first interface, and a second interface. The logical die may receive and decode requests received from a host via the first interface. The logical die may initiate data access to the memory system via the memory controller of the first memory stack, via a cache, via a second memory of the logical die, or a combination thereof. In some instances, the first memory may include DRAM dies coupled to the memory controller via the second interface. In some instances, the second memory may be SRAM memory. The logical die may or may not include a memory controller. In some instances, the memory controller may reside as a separate controller on each of the memory dies in the memory die stack. At 601, a first memory operation may be initiated and executed by identifying a first memory operation of the first memory using only the first command / address bus of the first interface. In some instances, the first command address bus may be a line command address bus associated with, for example, a high-bandwidth memory device. In some instances, the first memory operation does not include a read operation or a write operation. In some instances, the first memory operation includes a precharge operation, a refresh operation, a power-down operation, or a combination thereof.

[0049] At 603, a second memory operation of the first memory can be initiated and executed by using only the second command / address bus of the first interface to identify the second memory access operation. In some instances, the second command / address bus may be a column command / address bus associated with, for example, a high-bandwidth memory device. In some instances, the second memory operation includes a read operation or a write operation. At 605, a third memory operation can be initiated or executed by using both the first command / address bus and the second command / address bus to identify the third memory operation of the second memory (e.g., an SRAM array of logic dies). In some instances, the first memory may be a capacitor-based random access memory device, such as DRAM, and the second memory may be SRAM. Direct access to the faster SRAM-type memory in a stacked DRAM memory system provides an opportunity to improve the bandwidth of the memory system compared to conventional stacked DRAM memory or memory systems.

[0050] In some instances, in addition to providing new commands for direct access to SRAM devices within a memory system, such as a stack of DRAM memory devices, without violating the standards for implementing stacked DRAM high-bandwidth memory systems, the subject matter of this invention may also allow internal data movement between DRAM and SRAM memories using buffers on logical dies and extended command truth tables, without requiring information transfer via the host interface bus. Such internal transfer commands can be implemented by setting bits of the second command / address bus to a specific state at a second transition of the second command / address bus clock. In some instances, the bit allowing movement between memory and buffers may be the C8 bit of the column command / address bus associated with the high-bandwidth memory device.

[0051] In some instances, modifications to the command truth table for random access memory (RAM) stacks, as disclosed herein, can allow direct access to different types of RAM within the stacked logical dies (e.g., SRAM memory in a stacked DRAM memory system) and provide specific commands to directly access and utilize the benefits of SRAM. Such commands can allow the memory controller to read or write to SRAM using an external data bus, read and write to SRAM using buffers within the memory system, read and write to DRAM using an external bus, and read and write to DRAM using buffers. In some instances, commands using buffers as data locations do not affect the data bus (e.g., the external data bus) of the channel associated with the memory addressed in the command / operation and can allow the data bus to be used for other operations.

[0052] In some instances, the memory system according to the subject matter of the invention can provide an increase in bandwidth for high-bandwidth memories without putting bandwidth increase pressure on conventional memories with limited performance, such as conventional high-bandwidth devices. In some instances, the bandwidth increase can be achieved without modifying the pinouts of existing high-bandwidth memory packages.

[0053] Figure 7The figures generally illustrate a system 700 including an apparatus 705 supporting a memory system including stacked DRAM, according to various aspects disclosed herein. Apparatus 705 may include components for bidirectional voice and data communication, components for transmitting and receiving communication, including a memory controller 715, memory cells 720, a basic input / output system (BIOS) component 725, a processor 730, an I / O controller 735, peripheral components 740, memory chips 755, a system memory controller 760, an encoder 765, a decoder 770, and a multiplexer 775. These components may communicate electronically via one or more buses (e.g., bus 710). For example, bus 710 may have a bus width of 16 data lines (“DQ” lines). Bus 710 may communicate electronically with 32 groups of memory cells.

[0054] Memory controller 715 or 760 can operate one or more memory cells as described herein. Specifically, the memory controller can be configured to support flexible multi-channel memory. In some cases, memory controller 715 or 760 can operate a row decoder, a column decoder, or both, as described in the references... Figure 1 As described. The memory controller 715 or 760 can communicate electronically with a host and can be configured to transmit data during each of the rising and falling edges of the clock signal of the memory controller 715 or 760.

[0055] Memory cell 720 can store information (i.e., in the form of logical states), as described herein. Memory cell 720 can represent, for example, references... Figure 1 The memory cell 105 is described. The memory cell 720 can electronically communicate with a memory controller 715 or 760, and the memory cell 720 and the memory controller 715 or 760 can be located on a chip 755, which can be one or more planar memory devices as described herein. The chip 755 can be managed, for example, by the system memory controller 715 or 760.

[0056] Memory cell 720 may represent a first memory cell array having a plurality of regions coupled to a substrate. Each of the plurality of regions may contain a plurality of sets of memory cells and a plurality of channels passing through the first memory cell array. At least one of the plurality of channels may be coupled to at least one region. Memory controller 715 or 760 may be configured to transfer data between the coupled regions and the memory controller 715 or 760.

[0057] BIOS component 725 is a software component containing a BIOS that operates as firmware, which can initialize and run various hardware components. BIOS component 725 manages data flow between the processor and various other components, such as peripheral components, input / output control components, etc. BIOS component 725 may contain programs or software stored in read-only memory (ROM), flash memory, or any other non-volatile memory.

[0058] Processor 730 may include intelligent hardware devices (e.g., general-purpose processors, digital signal processors (DSPs), central processing units (CPUs), microcontrollers, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), programmable logic devices, discrete gate or transistor logic components, discrete hardware components, or any combination thereof). In some cases, processor 730 may be configured to operate a memory array using memory controller 715 or 760. In other cases, memory controller 715 or 760 may be integrated into processor 730. Processor 730 may be configured to execute computer-readable instructions stored in memory to perform various functions (e.g., functions or tasks supporting flexible multi-channel memory).

[0059] The I / O controller 735 manages the input and output signals of the device 705. The I / O controller 735 can also manage peripheral devices not integrated into the device 705. In some cases, the I / O controller 735 may represent a physical connection or port to an external peripheral device. The I / O controller 735 may utilize, for example... The I / O controller 735 may represent, or interact with, a modem, keyboard, mouse, touchscreen, or similar device. In some cases, the I / O controller 735 may be implemented as part of a processor. Users may interact with device 705 via the I / O controller 735 or via hardware components controlled by the I / O controller 735.

[0060] Peripheral component 740 may include any input or output device, or an interface for such devices. Examples may include a disk controller, sound controller, graphics controller, Ethernet controller, modem, Universal Serial Bus (USB) controller, serial or parallel port, or peripheral card slot, such as a Peripheral Component Interconnect (PCI) or Accelerated Graphics Port (AGP) slot.

[0061] Input 745 may represent a device or signal external to device 705 that provides input to device 705 or its components. This may include a user interface, or an interface with or between other devices. In some cases, input 745 may be managed by I / O controller 735 and may interact with device 705 via peripheral component 740.

[0062] Output 750 may also refer to a device or signal external to device 705 configured to receive output from device 705 or any of its components. Examples of output 750 may include a graphic display, audio speaker, printing device, another processor, or printed circuit board, etc. In some cases, output 750 may be a peripheral element that interfaces with device 705 via peripheral component 740. Output 750 may be managed by I / O controller 735.

[0063] System memory controller 715 or 760 may electronically communicate with a first memory cell array (such as memory cell 720). A host may be a component or device that controls or directs the operation of a device in which memory controller 715 or 760 and the corresponding memory array are part. The host may be a component of a computer, mobile device, etc. Alternatively, device 705 may be referred to as a host. In some instances, system memory controller 715 or 760 is a GPU.

[0064] Encoder 765 may represent a device or signal external to device 705, providing error correction encoding for data to be stored in device 705 or its components. Encoder 765 may write encoded data to at least one selected memory via at least one channel, and may also encode the data via error correction encoding.

[0065] Decoder 770 may represent devices or signals external to device 705, and serializes command and address signals of device 705 or its components. In some instances, memory controller 715 or 760 may be co-located within decoder 770.

[0066] Multiplexer 775 may represent a device or signal external to device 705, which multiplexes data to device 705 or its components. Multiplexer 775 can multiplex data to be transmitted to encoder 765 and demultiplex data received from encoder 765. Multiplexer 775 can communicate electronically with decoder 770. In some instances, multiplexer 775 can communicate electronically with controllers such as system memory controller 715 or 760.

[0067] The components of device 705 may include circuitry designed to perform its functions. This may include various circuit elements configured to perform the functions described herein, such as conductive lines, transistors, capacitors, inductors, resistors, amplifiers, or other active or passive components. Device 705 may be a computer, server, laptop computer, notebook computer, tablet computer, mobile phone, wearable electronic device, personal electronic device, etc. Alternatively, device 705 may be a part or aspect of such a device. In some instances, device 705 is an aspect of a computer with high reliability, mission criticality, or low latency constraints or parameters, such as a vehicle (e.g., autonomous vehicle, aircraft, spacecraft, etc.). Device 705 may be or include logic for artificial intelligence (AI), augmented reality (AR), or virtual reality (VR) applications.

[0068] In one example, the memory device may include a memory cell array having multiple zones, each of which may each contain multiple sets of memory cells and multiple channels passing through the memory cell array. Each of the channels may be coupled to a zone of the memory cell array and may be configured to transmit signals between the multiple sets of memory cells in the zone and a host device.

[0069] In some instances, the memory device may further include an I / O region extending across the memory cell array, which occupies areas within the memory cell array that may not contain memory cells. In some instances of the memory device, the I / O region may include a TSV configured to couple the memory cell array to a power node or a ground node.

[0070] In some instances, the memory device may further include multiple channel interfaces distributed across the memory cell array. In some instances of the memory device, the multiple channel interfaces may be bump-out pins. In some instances of the memory device, the channel interfaces among the multiple channel interfaces may be located in each quadrant of the memory cell array.

[0071] In some instances, the memory device may further include multiple signal paths extending between the memory cells of the region and the channel interface associated with the region. In some instances of the memory device, the channel interface may be located within the memory cell array to minimize the length of the signal paths.

[0072] In some instances, the memory device may further include a second memory cell array stacked on top of the memory cell array. In some instances of the memory device, the second memory cell array may have regions that may each contain multiple sets of memory cells. In some instances, the memory device may further include a second plurality of channels passing through the second memory cell array. In some instances of the memory device, each of the second plurality of channels may be coupled to a second region of the second memory cell array and may be configured to transmit signals between the multiple sets of memory cells in the second region and a host device.

[0073] In some instances, the memory device may further include a TSV extending through the memory cell array to couple a second memory cell array to a second plurality of channels. In some instances of the memory device, the channels may establish a point-to-point connection between the region and a host device. In some instances of the memory device, each channel may include four or eight data pins. In some instances of the memory device, a region of the memory cell array may contain eight or more groups of memory cells.

[0074] In some instances, the memory device may further include an interface configured for bidirectional communication with a host device. In some instances of the memory device, the interface may be configured to transmit signals modulated using at least one of an NRZ modulation scheme or a PAM4 modulation scheme, or both.

[0075] In one example, the memory device may include: a memory cell array having regions, each containing multiple sets of memory cells; an I / O region extending across the memory cell array, the I / O region including multiple terminals configured to route signals to and from the memory cell array; and multiple channels located in the I / O region of the memory cell array, each channel being coupled to a region of the memory cell array and configured to transmit signals between the multiple sets of memory cells in the region and a host device.

[0076] In some instances, the memory device may further include multiple channel interfaces located in an I / O region of the memory cell array, with signal paths coupling the region to the multiple channel interfaces. In some instances of the memory device, the I / O region may include a TSV configured to couple a second memory cell array stacked on top of the memory cell array to the channel interfaces.

[0077] In some instances of the memory device, the channel interface of the region may be located within an I / O region that equally divides the region served by the channel interface. In some instances of the memory device, the I / O region may include a TSV configured to couple the memory cell array to a power node or ground node. In some instances of the memory device, the I / O region may occupy an area within the memory cell array that may not contain memory cells. In some instances of the memory device, the memory cell array may be divided into two equally divided I / O regions. In some instances of the memory device, the memory cell array may be divided into four equally divided I / O regions.

[0078] In one example, the system may include: a host device; a memory device including a memory die comprising multiple regions, each of which may contain multiple sets of memory cells; and multiple channels configured to communicatively couple the host device and the memory device, each channel being coupled to a region of the memory die and configured to transmit signals between the multiple sets of memory cells in said region and the host device.

[0079] In some instances, the system may include an interface configured for bidirectional communication with a host device. In some instances, the interface may be configured to transmit signals modulated using at least one or both of the NRZ modulation scheme and the PAM4 modulation scheme. In some instances, the host device may be an instance of a GPU. In some instances, the memory device may be located in the same package as the host device.

[0080] In one example, the memory device may include an array of memory cells having multiple regions, each containing multiple sets of memory cells, and multiple channels passing through the memory cell array, each channel being coupled to at least one region of the memory cell array and each channel including two or more data pins and one or more command / address pins.

[0081] In some instances of the memory device, each channel may contain two data pins. In some instances of the memory device, each channel may contain one command / address pin. In some instances of the memory device, each region of the array may contain four groups of memory cells. In some instances of the memory device, each channel may contain four data pins. In some instances of the memory device, each channel may contain two command / address pins. In some instances of the memory device, each region of the array may contain eight groups of memory cells. In some instances of the memory device, each group of memory cells may be adjacent to a channel.

[0082] In some instances of the memory device, a first set of groups of multiple memory cells may be adjacent to a channel, and a second set of groups of multiple memory cells may be adjacent to another group but not adjacent to a channel. In some instances, the memory device may include 128 data pins, configured at a ratio of two, four, or eight data pins per channel.

[0083] In some instances, the memory device may include one, two, three, four, or six command / address pins per channel. In some instances, the memory device may include 256 data pins, configured in a ratio of two, four, or eight data pins per channel. In some instances, the memory device may include one, two, three, four, or six command / address pins per channel. In some instances of the memory device, the array may comprise multiple memory dies, each capable of containing multiple channels.

[0084] In some instances of the memory device, each of the plurality of memory dies may be coupled to a different channel of the plurality of channels. In some instances, the memory device may include a buffer layer coupled to the array. In some instances, the memory device may include an organic substrate beneath the array.

[0085] In some instances of the memory device, the array may be configured for pin rates of 10, 16, 20, or 24 Gbps. In some instances, the memory device may include an interface configured for bidirectional communication with a host device. In some instances of the memory device, the interface may be configured for at least one or both of binary modulation signaling or pulse amplitude modulation.

[0086] In one instance, the system may include: at least one memory die, which may include multiple regions, each of which may contain multiple sets of memory cells; one or more channels associated with each memory die, each channel being coupled to at least one region of the die containing memory cells and each channel including two or more data pins; and an organic substrate located beneath the memory die.

[0087] In some instances, the system may include a host device and an interface configured for bidirectional communication with the host device, the interface supporting at least one or both of NRZ signaling and PAM4. In some instances of the system, the host device may include a GPU.

[0088] In some instances, the system may include multiple memory arrays, each containing 128 or 256 data pins configured at a ratio of two, four, or eight data pins per channel. In some instances, the system may include a buffer layer positioned between at least one memory die and an organic substrate.

[0089] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some figures may illustrate signals as single signals; however, those skilled in the art will understand that said signals may represent signal buses, which may have various bit widths.

[0090] As may be used herein, the term "virtual ground" refers to a circuit node that is maintained at approximately zero volts (0V) but is not directly connected to ground. Therefore, the voltage of a virtual ground may fluctuate temporarily and return to approximately 0V in a steady state. Virtual grounding can be implemented using various electronic circuit elements, such as a voltage divider consisting of operational amplifiers and resistors. Other implementations are also possible. "Virtual ground" or "virtual ground connection" means connected to approximately 0V.

[0091] As may be used herein, the terms “electronic communication” and “coupling” refer to a relationship between components that supports the flow of electrons between them. This may include direct connections between components or may include intermediate components. Components that are electronically communicating or coupled to each other may efficiently exchange electrons or signals (e.g., in an energized circuit), or may not efficiently exchange electrons or signals (e.g., in an unenergized circuit) but may be configured and operable to exchange electrons or signals immediately after the circuit is energized. As an example, two components physically connected via a switch (e.g., a transistor) may electronically communicate or be coupled regardless of the state of the switch (i.e., open or closed).

[0092] As used herein, the term "layer" refers to a stratification or sheet of geometry. Each layer may have three dimensions (e.g., height, width, and depth) and may cover some or all of a surface. For example, a layer can be a three-dimensional structure where two dimensions are greater than the third, such as a thin film. Layers may contain different elements, components, and / or materials. In some cases, a layer may consist of two or more sublayers. In some figures, two dimensions of a three-dimensional layer are depicted for illustrative purposes. However, those skilled in the art will recognize that layers are inherently three-dimensional.

[0093] As used herein, the term "electrode" can refer to an electrical conductor and, in some cases, can serve as an electrical contact to a memory cell or other component of a memory array. An electrode may comprise traces, wires, conductive lines, conductive layers, etc., that provide a conductive path between elements or components of the memory array.

[0094] The term "isolation" refers to the relationship between components in which electrons are currently unable to flow between them; if there is an open circuit between the components, they are isolated from each other. For example, two components physically connected by a switch can be isolated from each other when the switch is open.

[0095] The devices discussed herein, including memory arrays, can be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, and gallium nitride. In some cases, the substrate is a semiconductor wafer. In others, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. In some instances, the substrate can be an organic multilayer substrate formed of materials such as ABF or BT. The conductivity of the substrate or subregions of the substrate can be controlled by using doping with various chemical species, including but not limited to phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping method.

[0096] The transistor discussed herein may refer to a field-effect transistor (FET) and includes a three-terminal device comprising a source, a drain, and a gate. Each terminal may be connected to other electronic components via a conductive material, such as a metal. The source and drain may be conductive and may include heavily doped semiconductor regions, such as degenerate semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or a channel. If the channel is n-type (i.e., the majority carriers are electrons), the FET may be called an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), the FET may be called a p-type FET. The channel may be end-capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, makes the channel conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, the transistor is "on" or "activated." When a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor is "off" or "deactivated."

[0097] The various specification boxes and modules described in connection with the disclosure herein may be implemented or performed by a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware component or any combination thereof designed to perform the functions described herein. The general-purpose processor may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller or state machine.

[0098] The processor can also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration).

[0099] In a first example, Example 1, a storage system may include: a first memory die stack configured to store data; and a logic die including interface circuitry and a controller, the interface circuitry being configured to receive a plurality of memory requests from an external host using a first command bus, a second command bus, and a data bus, the controller being configured to interface with the first memory die stack to store and retrieve the data from the first memory die stack; wherein the logic die includes a second memory having a faster access time than the means of the first memory die stack; and wherein the interface circuitry is configured to directly access the second memory in response to a first memory request among the plurality of memory requests.

[0100] In Example 2, the subject of Example 1 includes the fact that the first memory die stack is a dynamic random access memory (DRAM) die.

[0101] In Example 3, the subject of Example 2 includes the second memory being a static random access memory (SRAM) device.

[0102] In Example 4, the subject of Examples 1 to 3 includes the command decoder of the interface circuit being configured to receive commands for direct access to the second memory.

[0103] In Example 5, the subject of Examples 1 to 4 includes the statement that the first command bus is a line command bus.

[0104] In Example 6, the subject of Example 5 includes the second command bus being a column command bus.

[0105] In Example 7, the subject matter of Examples 1 to 6 includes wherein a plurality of selected bits of the first command bus are configured to provide at least a first command identifier immediately after a first transition of the clock signal of the first command bus based on the state of each of the plurality of selected bits; and wherein the controller is configured to directly access the second memory device in response to the first command identifier.

[0106] In Example 8, the subject of Example 7 includes the plurality of selected bits of the command bus comprising at least three bits of the command bus.

[0107] In Example 9, the subject of Example 8 includes the plurality of selected bits of the command bus comprising the first three bits of the command bus.

[0108] In Example 10, the subject of Example 9 includes providing the first command identifier when the first three bits of the first command bus are high, low, high in response to the first transition of the clock signal of the first command bus.

[0109] In Example 11, the subject matter of Examples 7 to 10 includes the plurality of selected bits of the command bus comprising a plurality of initial bits of the command bus.

[0110] In Example 12, the subject of Examples 7 to 11 includes the state of the plurality of selected bits of the first command bus being configured to provide the first command identifier in response to a unique combination of states of the plurality of selected bits that are not otherwise present on the command bus.

[0111] In Example 13, the subject of Example 12 includes the statement that the command bus conforms to the JDEC High Bandwidth Memory Standard (JESD235B).

[0112] In Example 14, the subject matter of Examples 7 to 13 includes the interface circuitry being configured to not directly access the second memory device when the first three bits of the first command bus are not high, low, high respectively after the first transition of the clock signal of the first command bus.

[0113] In Example 15, the subject matter of Examples 7 to 14 includes the interface circuitry being configured to read data from the second memory device in response to a first state of a bit of the second command bus at a first transition of the clock of the second command bus.

[0114] In Example 16, the subject of Example 15 includes the interface circuitry being configured to write data to the second memory device in response to a second state of the bit of the second command bus at the first transition of the clock of the second command bus.

[0115] In Example 17, the subject matter of Examples 7 to 16 includes the first two bits of the second command bus being configured to provide a command identifier immediately after a first transition of the clock signal of the second command bus; and the interface circuitry being configured to directly access the second memory device in response to the first transition of the clock signal of the second command bus when the first two bits of the second command bus are low and high, respectively.

[0116] In Example 18, the subject of Example 17 includes the interface circuitry configured to access the second memory device and to use a buffer of the logic die as a data target in response to a first state of a bit of the second command bus during a second transition of the clock of the second command bus.

[0117] In Example 19, the subject of Example 18 includes the interface circuitry being configured to activate the controller in response to the bit of the second command bus being in a first state during a second transition of the clock of the second command bus, to access the first memory die stack using the buffer of the logic die as a data target.

[0118] Example 20 is a method comprising: performing a first memory access operation by identifying a memory device having a memory die stack using only a first command / address bus; performing a second memory access operation by identifying a second memory access operation of the memory device using only a second command / address bus; and performing a third memory access operation by identifying a third memory access operation of the memory device using both the first and second command / address buses, wherein the third memory operation is configured to access a second memory of a logical die of the memory device, wherein the second memory is different from the memory die stack.

[0119] In Example 21, the subject of Example 20 includes the memory die stack containing dynamic random access memory (DRAM).

[0120] In Example 22, the subject of Examples 20 to 21 includes the second memory being described as static random access memory (SRAM).

[0121] In Example 23, the subject matter of Examples 20 to 22 includes the following: performing the third memory access operation comprises: setting a bit of the second command / address bus to one of a first state or a second state during a falling transition of the clock of the second command / address bus; when the bit is set to the first state, using a buffer of the logic die as the data location of the third memory access operation; and when the bit is set to the second state, using a data bus that couples the logic die to the host device as the data location of the third memory access operation.

[0122] Example 24 is a logical die for a storage device, the logical die comprising: a first interface for communicating with a memory die stack of the storage device; a second interface configured to couple with a host device; a second memory directly accessible from the second interface; and a processing circuitry for: initiating a first memory access operation of the memory die stack in response to a first request from the host device, wherein the first request identifies the first memory access operation using only a first command / address bus of the second interface; initiating a second memory access operation of the memory die stack in response to a second request from the host device, wherein the second request identifies the second memory access operation using only a second command / address bus of the second interface; and initiating a third memory access operation of the second memory of the storage device in response to a third request from the host device, wherein the third request identifies the third memory access operation using both the first command / address bus and the second command / address bus.

[0123] In Example 25, the subject matter of Example 24 includes the third memory access operation comprising: for a first transition of the clock signal of the first command / address bus, setting the first three bits of the first command / address bus to logic high, low, and high respectively to identify the third memory access operation of the second memory; for a first transition of the clock signal of the second command / address bus, setting the first two bits of the second command / address bus to logic low and high respectively to identify the third memory access operation of the second memory; for a second transition of the clock signal of the second command / address bus, setting the third bit of the second command / address bus to a first state to identify the third memory access operation of the second memory as a read operation; and for a second transition of the clock signal of the second command / address bus, setting the third bit of the second command / address bus to a second state to identify the third memory access operation of the second memory as a write operation.

[0124] In Example 26, the subject of Example 25 includes a processing circuitry configured to, in response to either the second or third memory access operation, use the data bus of the second interface as a data location when the second transition of the clock signal for the second command / address bus sets the fourth bit of the second command / address bus to the third state; and use the buffer of the logic die as a data location when the second transition of the clock signal for the second command / address bus sets the fourth bit of the second command / address bus to the third state.

[0125] Example 27 is at least one machine-readable medium containing instructions that, when executed by a processing circuitry system, cause the processing circuitry system to perform operations to implement any of Examples 1 to 26.

[0126] Example 28 is a device that includes components for implementing any of Examples 1 to 26.

[0127] Example 29 is a system that implements any of Examples 1 through 26.

[0128] Example 30 is a method that implements any of Examples 1 through 26.

Claims

1. A storage system comprising: A first memory die stack, configured to store data; as well as A logic die includes interface circuitry and a controller, the interface circuitry being configured to receive multiple memory requests from an external host using a first command / address bus, a second command / address bus, and a data bus, and the controller being configured to interface with a first memory die stack to store and retrieve the data from the first memory die stack; The logic die includes a second memory having a faster access time than the stack of the first memory dies; and The interface circuit described therein is configured to: The first memory operation is performed by using only the first command / address bus to identify the first memory die stack; The second memory access operation is executed by using only the second command / address bus to identify the second memory access operation; as well as The third memory access operation is executed by using both the first and second command / address buses to identify the third memory access operation of the second memory, wherein the third memory access operation is configured to access the second memory, and wherein the data target location of the third memory access operation depends on the state of a specific bit of the command on the second command / address bus. The first command / address bus is a row command bus, and the second command / address bus is a column command bus.

2. The storage system of claim 1, wherein the first memory die stack is a dynamic random access memory (DRAM) die.

3. The storage system according to claim 2, wherein the second memory is a static random access memory (SRAM) device.

4. The storage system of claim 1, wherein the command decoder of the interface circuit is configured to receive commands for direct access to the second memory.

5. The storage system of claim 1, wherein a plurality of selected bits of the first command / address bus are configured to provide at least a first command identifier immediately after a first transition of the clock signal of the first command / address bus based on the state of each of the plurality of selected bits; and In response to the first command identifier, the controller is configured to directly access the second memory instead of accessing the first memory die stack.

6. The storage system of claim 5, wherein the plurality of selected bits of the first command / address bus includes at least three bits of the first command / address bus.

7. The storage system of claim 6, wherein the plurality of selected bits of the first command / address bus includes the first three bits of the first command / address bus.

8. The storage system of claim 7, wherein the first command identifier is provided when the first three bits of the first command / address bus are high, low, high in response to the first transition of the clock signal of the first command / address bus.

9. The storage system of claim 5, wherein the plurality of selected bits of the first command / address bus includes a plurality of initial bits of the first command / address bus.

10. The storage system of claim 5, wherein the states of the plurality of selected bits of the first command / address bus are configured to provide the first command identifier in response to a unique combination of states of the plurality of selected bits that are not otherwise present on the first command / address bus.

11. The storage system of claim 10, wherein the first command / address bus conforms to the JEDEC high-bandwidth memory standard JESD235B.

12. The storage system of claim 6, wherein the interface circuitry is configured not to directly access the second memory when the first three bits of the first command / address bus are not high, low, high respectively after the first transition of the clock signal of the first command / address bus.

13. The storage system of claim 5, wherein the interface circuitry is configured to read data from the second memory in response to a first state of a bit of the second command / address bus at a first transition of the clock of the second command / address bus.

14. The storage system of claim 13, wherein the interface circuitry is configured to write data into the second memory in response to a second state of the bit of the second command / address bus at the first transition of the clock of the second command / address bus.

15. The storage system of claim 5, wherein the first two bits of the second command / address bus are configured to provide a command identifier immediately after a first transition of the clock signal of the second command / address bus; and The interface circuitry is configured to directly access the second memory when the first transition of the clock signal of the second command / address bus is in the low and high positions, respectively.

16. The storage system of claim 15, wherein the interface circuitry is configured to access the second memory and to use a buffer of the logic die as a data target in response to a first state of a bit of the second command / address bus during a second transition of the clock of the second command / address bus.

17. The memory system of claim 16, wherein the interface circuitry is configured to activate the controller in response to the bit of the second command / address bus being in a first state during a second transition of the clock of the second command / address bus to access the first memory die stack using the buffer of the logic die as a data target.

18. A method comprising: The first memory operation is performed by using only the first command / address bus to identify the first memory operation of the memory device having a memory die stack; The second memory access operation is performed by using only the second command / address bus to identify the second memory access operation of the memory device; as well as The third memory access operation is executed by identifying a third memory access operation of the memory device using both the first command / address bus and the second command / address bus. The third memory access operation is configured to access a second memory of the logical die of the memory device, wherein the second memory is different from the memory die stack and has a faster access time than the memory die stack, and wherein the data target location of the third memory access operation depends on the state of a specific bit of the command on the second command / address bus. The first command / address bus is a row command bus, and the second command / address bus is a column command bus.

19. The method of claim 18, wherein the memory die stack comprises dynamic random access memory (DRAM).

20. The method of claim 18, wherein the second memory is a static random access memory (SRAM).

21. The method of claim 18, wherein performing the third memory access operation comprises: During the falling transition of the clock signal of the second command / address bus, the specific position of the second command / address bus is set to one of the first state or the second state; When the specific location is set to the first state, the buffer of the logic die is used as the data target location for the third memory access operation; as well as When the specific location is set to the second state, the data bus that couples the logic die to the host device is used as the data target location for the third memory access operation.

22. A logic die for a storage device, the logic die comprising: A first interface is used to communicate with the memory die stack of the storage device; The second interface is configured to be coupled to the host device; The second memory can be directly accessed from the second interface, and the second memory has a faster access time than the memory die stack; as well as The processing circuit system is used for: A first memory operation of the memory die stack is initiated in response to a first request from the host device, wherein the first request identifies the first memory operation using only the first command / address bus of the second interface; A second memory access operation of the memory die stack is initiated in response to a second request from the host device, wherein the second request identifies the second memory access operation using only the second command / address bus of the second interface; as well as A third memory access operation of the second memory of the storage device is initiated in response to a third request from the host device, wherein the third request identifies the third memory access operation using both the first command / address bus and the second command / address bus, and wherein a first plurality of bits on the first command / address bus identify the third memory access operation for the second memory that does not require the memory die stack, and a distinct second plurality of bits on the second command / address bus confirm that the third memory access operation is for the second memory, wherein The first command / address bus is a row command bus, and the second command / address bus is a column command bus.

23. The logic die of claim 22, wherein the third memory access operation comprises: In response to the first transition of the clock signal of the first command / address bus, the first three bits of the first command / address bus are set to logic high, low, and high respectively to identify the third memory access operation of the second memory; In response to the first transition of the clock signal of the second command / address bus, the first two bits of the second command / address bus are set to logic low and high respectively to identify the third memory access operation of the second memory; In response to the second transition of the clock signal of the second command / address bus, the third bit of the second command / address bus is set to a first state to identify the third memory access operation of the second memory as a read operation; as well as In response to the second transition of the clock signal of the second command / address bus, the third bit of the second command / address bus is set to a second state to identify the third memory access operation of the second memory as a write operation.

24. The logic die of claim 23, wherein in response to either the second or third memory access operation, the processing circuitry is configured to: When the second transition of the clock signal for the second command / address bus sets the fourth bit of the second command / address bus to the third state, the data bus of the second interface is used as the data location; and When the second transition of the clock signal for the second command / address bus sets the fourth bit of the second command / address bus to the third state, the buffer of the logic die is used as the data location.

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