Memory device interface and method

Abstract

Devices and methods including memory devices and systems are disclosed. In an example, a memory module can include: a first stack of at least eight memory dies including four pairs of memory dies, each pair of the four pairs of memory dies associated with a respective one of four memory ranks of the memory module; a memory controller configured to receive memory access commands and access memory locations of the first stack; and a substrate configured to route connections between external terminals of the memory module and the memory controller.

Description

[0001] Priority and related applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 62 / 954954 of Keeth, entitled Memory Device Interface and Method, filed on December 30, 2019, which is hereby incorporated herein by reference in its entirety. Technical Field

[0003] This description generally relates to memory modules; and more specifically, to modular modules that provide various levels of error correction. Background Technology

[0004] A memory device is a semiconductor circuit that provides electronic storage for data to a host system (e.g., a computer or other electronic device). Memory devices can be volatile or non-volatile. Volatile memory requires power to maintain data and includes devices such as random access memory (RAM), static random access memory (SRAM), dynamic random access memory (DRAM), or synchronous dynamic random access memory (SDRAM). Non-volatile memory can retain stored data when no power is supplied and includes devices such as flash memory, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), erasable programmable ROM (EPROM), and resistive variable memory, such as phase-change random access memory (PCRAM), resistive random access memory (RRAM), or magnetoresistive random access memory (MRAM).

[0005] A host system typically includes a host processor, a first number of main memories (e.g., typically volatile memory, such as DRAM) supporting the host processor, and one or more storage systems (e.g., typically non-volatile memory, such as flash memory), which provide additional storage means for retaining data as a supplement to the main memory or separately from the main memory.

[0006] For example, a solid-state drive (SSD) storage system may include a memory controller and one or more memory devices, comprising several dies or logic units (LUNs). In some instances, each die may include several memory arrays and peripheral circuitry thereon, such as die logic or die processors. The memory controller may include interface circuitry configured to communicate with a host device (e.g., a host processor or interface circuitry) via a communication interface (e.g., a bidirectional parallel or serial communication interface). The memory controller may receive commands or operations from the host system in association with memory operations or instructions, such as read or write operations transferring data (e.g., user data and associated integrity data, such as error data or address data) between the memory device and the host device, erase operations erasing data from the memory device, and drive management operations (e.g., data migration, garbage collection, block deregistration), etc.

[0007] Memory modules have diverse applications. Error correction is a capability that may be important or unimportant to an application, but often requires very different modules depending on the need to implement error correction within the memory module and the extent to which the memory module provides error correction. Each variation in error correction may typically require a completely different memory module architecture. Attached Figure Description

[0008] In drawings that are not necessarily drawn to scale, similar designations may describe similar components in different views. Similar designations with different letter suffixes may represent different examples of similar components. The drawings illustrate, by way of example and not limitation, the various embodiments discussed in this document in general.

[0009] Figure 1A and 1B A general description of the example electronic system.

[0010] Figure 2 A general description of the instance memory system.

[0011] Figure 3 A block diagram illustrating the general structure of the buffer die in the example memory system.

[0012] Figure 4 This section provides a general overview of examples of memory devices.

[0013] Figures 5A to 5D Describe an example memory device.

[0014] Figure 6 Illustrate an example of a memory device.

[0015] Figure 7 Illustrate an example of a memory device.

[0016] Figure 8A and8B This section provides a general overview of examples of memory devices.

[0017] Figure 9 A block diagram illustrating an example stack of four DRAM dies that may be included in a DRAM die stack according to any of the examples in this disclosure.

[0018] Figure 10 This section provides an example of a modular basic architecture for an instance memory module, which is scalable to provide three different levels of error correction.

[0019] Figure 11 This section provides a general overview of the basic architecture for extending instance memory modules to provide error correction code (ECC) information or functionality.

[0020] Figure 12 This section provides a general overview of another extension to the basic architecture for providing instance memory modules with full ECC / SDDC capabilities.

[0021] Figure 13A and 13B General Explanation Figure 10 The instance physical configuration of the instance storage module.

[0022] Figure 14A and 14B General Explanation Figure 11 The instance physical configuration of the instance storage module.

[0023] Figure 15A and 15B General Explanation Figure 11 The instance physical configuration of the instance storage module.

[0024] Figure 16 The description may include block diagrams of one or more memory devices and / or systems as described above, such as instance machines (e.g., host systems). Detailed Implementation

[0025] The following description and figures fully illustrate specific embodiments to enable those skilled in the art to practice these specific embodiments. Other embodiments may be incorporated with structural, logical, electrical, procedural, and other variations. Parts and features of some embodiments may be included in or replace those parts and features of other embodiments. The embodiments set forth in the claims cover all available equivalents of those claims.

[0026] The following describes an example memory module architecture incorporated with a basic memory module configuration. In the examples described below, more complex error correction functionality can be provided by combining the basic architecture with additional memory devices. For example, for systems that do not use memory error correction or do not require the memory space of the memory module to implement error correction functionality, a memory module based solely on the basic architecture can be considered. In some instances, one or more additional memory devices can be stacked with the basic architecture to provide storage space for information associated with error correction code (ECC) functionality. In other instances, a second one or more additional memory devices can be further stacked to provide storage space for information associated with single-device data correction (SDDC) functionality.

[0027] Figure 1A An electronic system 100 is shown with a processor 106 coupled to a substrate 102. In some instances, the substrate 102 may be a system motherboard, or in other instances, the substrate 102 may be coupled to another substrate, such as a motherboard. The electronic system 100 also includes a first memory device 120A and a second memory device 120B. The memory devices 120A and 120B are also shown supported by the substrate 102 adjacent to the processor 106, but are depicted in the example configuration as coupled to an auxiliary substrate 124. In other instances, the memory devices 120A and 120B may be directly coupled to the same substrate 102 as the processor 106.

[0028] Memory devices 120A and 120B each include a buffer assembly coupled to an auxiliary substrate 124, exemplified herein as a buffer die 128. Memory devices 120A and 120B may be individual dies, or in some cases may each comprise a corresponding stack of memory devices 122. For the purposes of this description, memory devices 120A and 120B will be described in an example configuration of stacked memory devices. Additionally, memory devices 120A and 120B will be described in an example configuration of dynamic random access memory (DRAM) dies 122A and 122B, each coupled to the auxiliary substrate 124. Other types of memory devices may be used instead of DRAM, including, for example, FeRAM, phase-change memory (PCM), and 3DXPoint. TM Memory, NAND memory, or NOR memory, or a combination thereof. In some cases, a single memory device may include a first memory die using a first memory technology (e.g., DRAM) and a second memory die using a second memory technology different from the first memory technology (e.g., SRAM, FeRAM, etc.).

[0029] The stacking of DRAM dies 122 is shown in a block diagram in Figure 1. Figure 1AIn one example, several wire connections 126 are shown coupled to a stack of DRAM dies 122. Additional circuitry (not shown) is contained on or within substrate 124. This additional circuitry completes the connections between the stacks of DRAM dies 122 to buffer dies 120 via the wire connections 126. Selected examples may include through-silicon vias (TSVs) instead of wire connections 126, as will be described in more detail in subsequent figures.

[0030] Substrate wiring 104 is shown as coupling memory device 120A to processor 106. Figure 1B In the example shown, an additional memory device 120B is illustrated. Although two memory devices 120A and 120B are shown for the illustrated example, a single memory structure can be used, or a number of memory devices greater than two can be used. The examples of memory devices described in this disclosure increase the capacity near the memory, improve speed, and reduce manufacturing costs.

[0031] Figure 1B An electronic system 150 is shown, having a processor 156 coupled to a substrate 152. The system 150 also includes a first memory device 160A and a second memory device 160B. Figure 1A In comparison, Figure 1B In this configuration, the first memory device 160A and the second memory device 160B are directly connected to the same substrate 102 as the processor 156, without any intermediate substrate or interlayer. This configuration provides superior performance compared to... Figure 1A The instance provides additional speed and reduces component usage. Similar to... Figure 1A An example is shown of a stacked buffer assembly or buffer die 168 adjacent to DRAM die 162. Wire connector 166 is shown as an example interconnect structure; however, other interconnect structures, such as TSV, may be used.

[0032] Figure 2 The display is similar to that from Figure 1B A memory system 200 comprising a memory device 118A or 118B. The memory device 200 includes a buffer die 202 coupled to a substrate 204. The memory device 200 also includes a stack of DRAM dies 210 coupled to the substrate 204. Figure 2 In one example, individual dies in the stack of DRAM dies 210 are laterally offset from one or more vertically adjacent dies; specifically, in the depicted example, each die is laterally offset from two vertically adjacent dies. As an example, the dies may be staggered in at least one step configuration. Figure 2 The examples illustrate two different staggered orientations in a stepped stack of DRAM dies 210. In the illustrated dual-step configuration, the exposed surface portion 212 of each die is used for several wire-bonded interconnects.

[0033] Multiple wire-bonded interconnects 214, 216 are shown from the die in the stack of DRAM dies 210 to the substrate 204. Additional conductors (not shown) on or within the substrate 204 further couple the wire-bonded interconnects 214, 216 to the buffer die 202. The buffer die 202 is shown coupled to the substrate 204 using one or more solder interconnects 203, such as a solder ball array. Several substrate solder interconnects 206 are further shown on the bottom side of the substrate 204 to further transmit signals and data from the buffer die to the substrate 102, and ultimately to the processor 106, as shown. Figure 1B As shown in the image.

[0034] Figure 3 The display is similar to that from Figure 2 Block diagram of buffer die 202 and buffer die 300. Host device interface 312 and DRAM interface 314 are shown. Additional circuitry components for buffer die 300 may include controller and switching logic 316; reliability, availability, and serviceability (RAS) logic 317; and built-in self-test (BIST) logic 318. Communication from buffer die 300 to the stack of DRAM dies is indicated by arrow 320. Communication from buffer die 300 to the host device is indicated by arrows 322 and 324. Figure 3 In the diagram, arrow 322 indicates communication from the command / address (CA) pin, and arrow 324 indicates communication from the data (DQ) pin 322. The number of CA and DQ pins is provided only as examples, as the host device interface may have generally more or fewer of either or both of the CA and DQ pins. The required number of pins of either type can vary depending on the width of the interface channel, the provisioning of extra bits (e.g., ECC bits), and many other variables. In many instances, the host device interface will be an industry-standard memory interface (explicitly defined by a standards-setting organization or a de facto standard adopted by the industry).

[0035] In one instance, all CA pins 324 act as a single channel, and all data pins 322 act as a single channel. In another instance, all CA pins service all data pins 322. In yet another instance, CA pins 324 are subdivided into multiple sub-channels. In yet another instance, data pins 322 are subdivided into multiple sub-channels. A configuration may include a portion of CA pins 324 serviceing a portion of data pins 322. In a particular instance, as a sub-combination of CA pins and data (DQ) pins, 8 CA pins service 9 data (DQ) pins. For example, multiple sub-combinations such as an 8-CA pin / 9-data pin instance may be included in a memory device.

[0036] In computing devices, it is common to couple DRAM memory to a substrate such as a motherboard using sockets, such as dual in-line memory (DIMM) sockets. However, the physical layout of the DRAM chips and socket connections on DIMM devices occupies a significant amount of space. There is a desire to reduce the amount of space required for DRAM memory. Furthermore, communication via socket interfaces is slower and less reliable than direct solder connections to the motherboard. The additional components of the socket interfaces also increase the cost of the computing device.

[0037] Using examples of memory devices from this disclosure, the physical size of the memory device is reduced for a given DRAM memory capacity. Speed ​​is increased due to direct connection to the substrate, and cost is reduced by eliminating socket assemblies.

[0038] In operation, the potential data rate from the host device may exceed the speed that the interconnect components to the DRAM die (e.g., traces, TSVs, wire bonds, etc.) can handle. Adding a buffer die 300 (or other forms of buffer assemblies) allows for buffering of fast data interactions from the host device. Figure 3 In one instance, host interface 312 is configured to operate at a first data rate. In another instance, the first data rate may match the rate at which the host device is capable of delivering data.

[0039] In one instance, DRAM interface 314 is configured to operate at a second data speed, slower than the first data speed. In another instance, DRAM interface 314 is configured to be slower and wider than host interface 312. In operation, the buffer die can convert high-speed data interactions on the host interface 312 side to slower, wider data interactions on the DRAM interface 314 side. Furthermore, as further described below, to maintain at least close to the data throughput of the host interface, in some instances, the buffer assembly can reallocate connections from the host interface to multiple sub-channels associated with the respective DRAM interface. The slower, wider DRAM interface 314 can be configured to substantially match the capacity of the narrower, higher-speed host interface 312. In this way, the more limited interconnect components to the DRAM die (e.g., traces, TSVs, wirejoints, etc.) can handle the capacity of interactions supplied from the faster host device. Although an example host interface (with both CA and DQ pins) to buffer die 300 is shown, buffer die 300 may contain multiple host interfaces for separate data paths, each of which is mapped to multiple DRAM interfaces in a similar manner through buffer die 300.

[0040] In one instance, host device interface 312 includes a first number of data paths, and DRAM interface 314 includes a second number of data paths, the second number being greater than the first number of data paths. In one instance, circuitry in buffer die 300 maps data and commands from the first number of data paths to the second number of data paths. In such a configuration, the second number of data paths provides a slower and wider interface, as described above.

[0041] In one example, the command / address pins 324 of the host device interface 312 include a first number of command / address paths, and on the corresponding DRAM interface 314 side of the buffer die 300, the DRAM interface 314 includes a second number of command / address paths, the second number being greater than the first number of command / address paths. In one example, the second number of command / address paths is twice the first number of command / address paths. In one example, the second number of command / address paths is more than twice the first number of command / address paths. In one example, the second number of command / address paths is four times the first number of command / address paths. In one example, the second number of command / address paths is eight times the first number of command / address paths.

[0042] In one instance, a given command / address path on the DRAM interface 314 side of buffer die 300 communicates with only a single DRAM die. In another instance, a given command / address path on the DRAM interface 314 side of buffer die 300 communicates with multiple DRAM dies. In yet another instance, a given command / address path on the DRAM interface 314 side of buffer die 300 communicates with four DRAM dies. In yet another instance, a given command / address path on the DRAM interface 314 side of buffer die 300 communicates with 16 DRAM dies.

[0043] In one example, the host device interface 312's data pins 322 include a first number of data paths, and on the corresponding DRAM interface 314 side of the buffer die 300, the DRAM interface 314 includes a second number of data paths, the second number being greater than the first number of data paths. In one example, the second number of data paths is twice the first number of data paths. In one example, the second number of data paths is more than twice the first number of data paths. In one example, the second number of data paths is four times the first number of data paths. In one example, the second number of data paths is eight times the first number of data paths.

[0044] In one instance, the data path on the DRAM interface 314 side of the buffer die 300 communicates with only a single DRAM die. In another instance, a given data path on the DRAM interface 314 side of the buffer die 300 communicates with multiple DRAM dies. In yet another instance, a given data path on the DRAM interface 314 side of the buffer die 300 communicates with four DRAM dies. In yet another instance, a given data path on the DRAM interface 314 side of the buffer die 300 communicates with sixteen DRAM dies.

[0045] In one example, host interface 312 includes command / address pin 324 and data pin 322 at different speeds. In one example, the data pin 322 of the host interface is configured to operate at 6.4 Gb / s. In another example, the command / address pin 324 of the host interface is configured to operate at 3.2 Gb / s.

[0046] In one instance, the DRAM interface 314 of the buffer die 300 slows down and widens communication from the host interface 312 side of the buffer die 300. In one instance, with a given command / address path from the host interface 312 mapped to two command / address paths on the DRAM interface 314, the speed at the host interface is 3.2 Gb / s, and the speed at the DRAM interface 314 is 1.6 Gb / s.

[0047] In one example, with a given data path from host interface 312 mapped to two data paths on DRAM interface 314, the speed at the host interface is 6.4 Gb / s and the speed at DRAM interface 314 is 3.2 Gb / s, where each data path communicates with a single DRAM die in the DRAM die stack. In another example, with a given data path from host interface 312 mapped to four data paths on DRAM interface 314, the speed at the host interface is 6.4 Gb / s and the speed at DRAM interface 314 is 1.6 Gb / s, where each data path communicates with four DRAM dies in the DRAM die stack. In yet another example, with a given data path from host interface 312 mapped to eight data paths on DRAM interface 314, the speed at the host interface is 6.4 Gb / s and the speed at DRAM interface 314 is 0.8 Gb / s, where each data path communicates with 16 DRAM dies in the DRAM die stack.

[0048] In one example, a Pulse Amplitude Modulation (PAM) protocol is used for communication on the DRAM interface 314 side of the buffer die 300. In one example, the PAM protocol includes PAM-4, but other PAM protocols are within the scope of this invention. In one example, the PAM protocol increases data bandwidth. In one example, with a given data path from the host interface 312 mapped to four data paths on the DRAM interface 314, using the PAM protocol, the speed at the host interface is 6.4 Gb / s and the speed at the DRAM interface 314 is 0.8 Gb / s, where each data path communicates with four DRAM dies in the DRAM die stack. In one example, with a given data path from the host interface 312 mapped to eight data paths on the DRAM interface 314, using the PAM protocol, the speed at the host interface is 6.4 Gb / s and the speed at the DRAM interface 314 is 0.4 Gb / s, where each data path communicates with 16 DRAM dies in the DRAM die stack.

[0049] The number of pins required for communication between buffer die 300 and the 16 DRAM dies in Example 16 varies depending on the number of command / address paths on the DRAM interface 314 side of buffer die 300 and the number of DRAM dies coupled to each data path. The table below shows several non-limiting examples of pin counts and corresponding command / address path configurations.

[0050]

[0051] The number of pins required for communication between buffer die 300 and the 16 DRAM dies in Example 16 varies depending on the number of data paths on the DRAM interface 314 side of buffer die 300 and the number of DRAM dies coupled to each data path. The table below shows several non-limiting examples of pin counts and corresponding data path configurations.

[0052]

[0053] As illustrated in the selected examples below, the number of pins in the table above can be coupled to DRAM dies in a DRAM die stack in many different ways. In one example, a wire bond is used to couple from a pin to several DRAM dies. In another example, a TSV is used to couple from a pin to several DRAM dies. Although wire bonds and TSVs are used as examples, other communication paths besides wire bonds and TSVs are also within the scope of this invention.

[0054] Figure 4Another example of memory device 400 is shown. Memory device 400 includes a buffer die 402 coupled to a substrate 404. Memory device 400 also includes a stack of DRAM dies 410 coupled to the substrate 404. Figure 4 In this example, the stacking of DRAM dies 410 is staggered in at least one step configuration. Figure 4 The example demonstrates two different staggered orientations in a stepped stack of DRAM dies 410. Similar to... Figure 2 In the illustrated stepped configuration, the exposed surface portion 412 is used for several wire-connected interconnects.

[0055] Multiple wire-bonded interconnects 414, 416 are shown from the DRAM die in the stack to the substrate 404. Additional conductors (not shown) on or within the substrate 404 further couple the wire-bonded interconnects 414, 416 to the buffer die 402. The buffer die 402 is shown coupled to the substrate 404 using one or more solder interconnects, such as a solder ball array. Several substrate solder interconnects 406 are further shown on the bottom side of the substrate 404 to further transmit signals and data from the buffer die to the motherboard and ultimately to the host device.

[0056] exist Figure 4 In one example, multiple wire-connected interconnects 414, 416 are connected in series on multiple stacked DRAM dies. In a selected example, a single wire-connected interconnect can drive a load in more than one DRAM die. In such examples, the wire-connected interconnects can be connected in series, such as... Figure 4 As shown in the illustration. In one example, a single wire connector can be connected in series to four DRAM dies. In one example, a single wire connector can be connected in series to eight DRAM dies. In one example, a single wire connector can be connected in series to sixteen DRAM dies. Other numbers of DRAM dies connected in series are also within the scope of this invention. Additionally, the DRAM interface CA can be connected to a first number of DRAM dies, while the DRAM interface DQ can be correspondingly connected to a second number of DRAM dies, different from the first number.

[0057] Figure 5A Another example of memory device 500 is shown. Memory device 500 includes a buffer die 502 coupled to a substrate 504. Memory device 500 also includes a stack of DRAM dies 510 coupled to the substrate 504. Figure 5A In this example, the stack of DRAM dies 510 is staggered in at least one stepped configuration. The example in Figure 5 illustrates two different staggered directions in the stepped stack of DRAM dies 510. In the illustrated stepped configuration, exposed surface portions 512 are used for several wire-bonded interconnects.

[0058] Multiple wire-bonded interconnects 514, 516 are shown from the die in the stack of DRAM dies 410 to the substrate 404. Additional conductors (not shown) on or within the substrate 504 further couple the wire-bonded interconnects 514, 516 to the buffer die 502. The buffer die 502 is shown coupled to the substrate 504 using one or more solder interconnects, such as a solder ball array. Several substrate solder interconnects 506 are further shown on the bottom side of the substrate 504 to further transmit signals and data from the buffer die to the motherboard and ultimately to the host device.

[0059] exist Figure 5A In one example, buffer die 502 is at least partially located beneath the stack of DRAM dies 510. In another example, encapsulation 503 at least partially surrounds buffer die 502. Figure 5A This further reduces the footprint of the memory device 500. Additionally, it reduces the interconnect distance between the stacked DRAM dies 510 and the buffer die 502.

[0060] Figure 5B Another example of memory device 520 is shown. Memory device 520 includes a buffer die 522 coupled to a substrate 524. Memory device 520 also includes a stack of DRAM dies 530 coupled to the substrate 524. Multiple line-bonded interconnects 534, 536 are shown from the dies in the stack of DRAM dies 530 to the substrate 524. Figure 5B In one example, multiple wire-connected interconnects 534, 536 are connected in series on multiple stacked DRAM dies. In one example, a single wire-connector may be connected in series to four DRAM dies. In one example, a single wire-connector may be connected in series to eight DRAM dies. In one example, a single wire-connector may be connected in series to sixteen DRAM dies. Other numbers of DRAM dies connected in series are also within the scope of this invention.

[0061] Figure 5C A top view of a memory device 540, similar to memory devices 500 and 520, is shown. Figure 5C In one example, the buffer die 542 is shown coupled to the substrate 544 and is located entirely beneath the stack of DRAM dies 550. Figure 5D A top view is shown of a memory device 560, similar to memory devices 500 and 520. Figure 5DIn this configuration, buffer die 562 is coupled to substrate 564 and is partially located beneath a portion of the first stack of DRAM dies 570 and a portion of the second stack of DRAM dies 572. In one example, shorter stacks of DRAM dies provide shorter interconnect paths and higher manufacturing yields. In selected examples, multiple shorter stacks of DRAM dies may be used for these reasons. One trade-off of multiple shorter stacks of DRAM dies is a larger footprint for memory device 560.

[0062] Figure 6 Another example of memory device 600 is shown. Memory device 600 includes a buffer die 602 coupled to a substrate 604. Memory device 600 also includes a stack of DRAM dies 610 coupled to the substrate 604. Figure 6 In this example, the DRAM dies 610 are stacked in an alternating staggered configuration with at least one step. Figure 6 An example is shown in four interleavings in two different interleaving directions in a stepped stack of DRAM die 610. Figure 6 The stack of DRAM dies 610 in the example contains 16 DRAM dies, but the invention is not limited thereto. Similar to... Figure 6 Other stepped configurations shown in the figure expose surface portions 612 for several wire-connected interconnects.

[0063] Multiple wire-bonded interconnects 614, 616 are shown from the DRAM die in the stack to the substrate 604. Additional conductors (not shown) on or within the substrate 604 further couple the wire-bonded interconnects 614, 616 to the buffer die 602. The buffer die 602 is shown coupled to the substrate 604 using one or more solder interconnects, such as a solder ball array. Several substrate solder interconnects 606 are further shown on the bottom side of the substrate 604 to further transmit signals and data from the buffer die to the motherboard and ultimately to the host device.

[0064] Figure 7 Another example of memory device 700 is shown. Memory device 700 includes a buffer die 702 coupled to a substrate 704. Memory device 700 also includes a stack of DRAM dies 710 coupled to the substrate 704. Figure 7 In one instance, the DRAM die 710 is stacked in an alternating staggered configuration with at least one step. Figure 7 An example is shown in four interleavings in two different interleaving directions in a stepped stack of DRAM die 710. Figure 7 The stack of DRAM dies 710 in the example contains 16 DRAM dies, but the invention is not limited thereto. Similar to... Figure 7 Other stepped configurations shown in the figure expose surface portions 712 for several wire-connected interconnects.

[0065] Multiple wire-bonded interconnects 714, 716 are shown from the DRAM die in the stack 710 to the substrate 704. Additional conductors (not shown) on or within the substrate 704 further couple the wire-bonded interconnects 714, 716 to the buffer die 702. The buffer die 702 is shown coupled to the substrate 704 using one or more solder interconnects, such as a solder ball array. Several substrate solder interconnects 706 are further shown on the bottom side of the substrate 704 to further transmit signals and data from the buffer die to the motherboard and ultimately to the host device.

[0066] exist Figure 7 In one example, the buffer die 702 is at least partially located beneath the stack of DRAM dies 710. In another example, the encapsulation 703 at least partially surrounds the buffer die 702. Figure 7 This further reduces the footprint of the memory device 700. Additionally, the interconnect distance between the stacked DRAM dies 710 and the buffer die 702 is reduced.

[0067] Figure 8A Another example of memory device 800 is shown. Memory device 800 includes a buffer die 802 coupled to a substrate 804. Memory device 800 also includes a stack of DRAM dies 810 coupled to the substrate 804. Figure 8A In this example, the stack of DRAM dies 810 is vertically aligned. Figure 8A The stack of DRAM dies 810 in the invention comprises eight DRAM dies, but the invention is not limited thereto.

[0068] Multiple TSV interconnects 812 are shown, passing through one or more dies in the stack of DRAM dies 810 and communicating with substrate 804 together with said dies. Additional conductors (not shown) on or within substrate 804 further couple the TSVs 812 to buffer dies 802. Buffer dies 802 are shown coupled to substrate 804 using one or more solder interconnects, such as a solder ball array. Several substrate solder interconnects 806 are further shown on the bottom side of substrate 804 to further transmit signals and data from buffer dies to the motherboard and ultimately to the host device.

[0069] Figure 8B Another example of memory device 820 is shown. Memory device 820 includes a buffer die 822 coupled to a substrate 824. Memory device 820 also includes a stack of DRAM dies 830 coupled to the substrate 824. Figure 8B In this example, the stack of DRAM die 830s is vertically aligned. Figure 8BThe stack of DRAM dies 830 in the invention contains 16 DRAM dies, but the invention is not limited thereto.

[0070] Multiple TSV interconnects 832 are shown, passing through one or more dies in a stack of DRAM dies 830 and communicating with substrate 824 together with said dies. Additional conductors (not shown) on or within substrate 824 further couple the TSVs 832 to buffer dies 822. Buffer dies 822 are shown coupled to substrate 824 using one or more solder interconnects, such as a solder ball array. Several substrate solder interconnects 826 are further shown on the bottom side of substrate 824 to further transmit signals and data from buffer dies to the motherboard and ultimately to the host device.

[0071] Figure 9 This block diagram generally illustrates an example stack of four DRAM dies 940 that may be included in a DRAM die stack according to any of the examples in this disclosure. Each die in the stack 940 includes a memory region 942 containing an array of memory cells. A single data I / O stripe 944 is shown, extending from a first side 941 to a second side 943 of the stack 940. In one example, contacts may be formed on the edges of the data I / O stripe 944 on one or both sides 941, 943. The contacts may be connected to wire connectors as described in the examples above. In other examples, TSVs may be coupled to the data I / O stripe 944 at sides 941, 943 or at other locations along the first data I / O stripe 944. In some examples, the single data I / O stripe 944 includes 32 contacts for connection to a wire connector or a TSV. In one example, all four dies in the stack 940 may be driven by a single data path as described in the examples above. In some instances, the stack may include a command / address strip 950. In the example shown, the command / address strip 950 includes 30 contacts for connection to a wire connector or TSV.

[0072] Figure 10This section provides an example of a modular basic architecture for an example memory module 1000, which is scalable to provide three different levels of error correction. The basic architecture of memory module 1000 may include a buffer die 1002 for interfacing between a host interface 1012 and a DRAM interface 1014, the DRAM interface including multiple data paths (MI0 to MI3) communicatively coupled to one or more stacks 1040 of hierarchical memory dies. In the illustrated example, memory module 1002 may include 16 memory dies arranged in four levels (levels 0 to 3). Each data path (MI0 to MI3) of the DRAM interface 1014 may be simultaneously coupled to a single die in each level (levels 1 to 3). Thus, the memory dies can be hierarchically arranged, with each level containing four 32-DQ pin DRAM dies. Figure 10 The basic architecture or configuration of the memory module 1002 does not provide error correction and provides services for the 32-bit host data bus or interface 1012.

[0073] Figure 11 This section describes an extension of the basic architecture of instance memory module 1100 for providing error correction code (ECC) information or functionality. The basic architecture of memory module 1100 may include a buffer die 1102 for interfacing between a host interface 1112 and a DRAM interface 1114, the DRAM interface including multiple data paths (MI0 to MI3) communicatively coupled to one or more stacks 1140 of hierarchical memory dies. In the illustrated example, memory module 1102 may include 16 memory dies arranged in four levels (levels 0 to 3). In addition to the basic architecture, instance memory module 1102 also includes one or more additional ECC dies 1161 for ECC adaptation and one or more additional data paths (e.g., MI4) for the DRAM interface 1114. In the illustrated example, each of the one or more ECC dies 1161 can accommodate two of the four levels (levels 0 to 3) of ECC, such that the instance memory module 1100 configured to provide ECC can contain 18 DRAM dies and can serve a 36-bit host data bus 1112.

[0074] Figure 12This section describes another extension of the basic architecture for providing full ECC / SDDC capabilities for instance memory module 1200. The basic architecture of memory module 1200 may include a buffer die 1202 for interfacing between host interface 1212 and DRAM interface 1214, the DRAM interface including multiple data paths (MI0 to MI3) communicatively coupled to one or more stacks 1240 of tiered memory dies. In the illustrated example, memory module 1202 may include 16 memory dies arranged in four tiers (tiers 0 to 3). In addition to the basic architecture, instance memory module 1200 may also include additional DRAM dies 1261 for each tier (tiers 0 to 3) to accommodate ECC / SDDC, and one or more additional data paths (e.g., MI4) for DRAM interface 1214. In the illustrated example, a single ECC / SDDC DRAM die can be associated with each level, such that an instance memory module 1200 configured to provide a full ECC / SDDC can contain 20 DRAM dies and provide service for a 40-bit host data bus 1212.

[0075] Figure 13A and 13B General Explanation Figure 10 The instance physical configuration of the instance storage module is 1300. Figure 13A This section describes a single stack 1310 of DRAM dies in a dual-stack configuration. Each stack in the dual-stack configuration may contain eight dies. Each stack in the dual-stack configuration may contain two dies from each of four levels (levels 0 to 3). The dies in each stack may be coupled to buffer 1302 via wire connectors 1312, 1314 extending from two data paths of the DRAM interface of buffer 1302. In this example, the first data path 1312 may daisy-chain to the four dies in the stack. Each of the four dies may be associated with a different level among the four levels. In some examples, buffer dies 1302 may be from, for example... Figure 13A Each offset in the stack is illustrated in the diagram. In other instances, the buffer die may be located below one of the stacks, such as... Figure 5A 502 or Figure 5B As shown in 522. In some instances, the buffer die can be positioned below two stacks, such as... Figure 5D As shown in 562.

[0076] Figure 13BThis section provides a general description of a single-stack configuration of the example memory module 1300 based on the basic architecture discussed above. A single stack 1310 of DRAM memory dies contains all 16 DRAM dies of memory module 1300. A single stack 1310 may contain four dies from each of the four levels (levels 0 to 3). The dies of stack 1310 may be coupled to a buffer via wire connectors 1312, 1314, 1316, and 1318 extending from the DRAM interface of buffer die 1302. In this example, each data path may daisy-chain to a set of four dies in stack 1310. Each of the four dies may be associated with a different level in the four levels (levels 0 to 3). In some examples, buffer die 1302 may be from, for example... Figure 4 The stack 1310 offset is described in / 13B. In some instances, the buffer die 1302 may be positioned below the stack 1310, such as... Figure 5A or Figure 5B As shown in the image.

[0077] Figure 14A and 14B General Explanation Figure 11 The instance physical configuration of the instance storage module is 1400. Figure 14A This section describes a single stack 1410 of DRAM dies in a dual-stack configuration. Each stack in the dual-stack configuration may contain nine dies. Each stack in the dual-stack configuration may contain two dies from each of four levels (levels 0 to 3). The dies in each stack may be coupled to buffer 1402 via wire connectors 1412, 1414 extending from two data paths of the DRAM interface of buffer 1402. In this example, the first data path 1412 may daisy-chain to four dies in the stack. Each of the four dies may be associated with a different level among the four levels. In some examples, buffer dies 1402 may be from, for example... Figure 14A Each offset in the stack is illustrated in the diagram. In other instances, the buffer die may be located below one of the stacks, such as... Figure 5A 502 or Figure 5B As shown in 522. In some instances, the buffer die can be positioned below two stacks, such as... Figure 5DAs shown in Figure 562. In addition to the basic configuration, each stack in the dual-stack configuration may also include one or more ECC DRAM dies 1461. Each of the one or more ECC dies can store a portion of the ECC information for a memory class. For example, a single stack 1410 of dies may include ECC dies 1461 configured to store ECC information for memory classes 2 and 3. Other stacks (not shown) may include second ECC dies configured to store ECC information for memory classes 0 and 1. It should be understood that the allocation of ECC information from each class to each ECC die may differ from that described above without departing from the scope of the invention. In some instances, the ECC dies of each stack in the dual-stack configuration may be coupled to the DRAM interface of buffer die 1402 via a wire connection (e.g., 1420) for an additional data path.

[0078] Figure 14B This section provides a general description of a single-stack configuration of the example memory module 1400 based on the basic architecture discussed above. A single stack 1410 of DRAM memory dies contains all 18 DRAM dies of memory module 1400. A single stack 1410 may contain four dies from each of four levels (levels 0 to 3). The dies of the stack 1410 of the hierarchical memory may be coupled to a buffer via wire connections 1412, 1414, 1416, and 1418 extending from the DRAM interface of buffer die 1402. In this example, each data path may daisy-chain to a set of four dies of the stack 1410 of the hierarchical memory. Each of the four dies may be associated with a different level in the four levels (levels 0 to 3). In some examples, buffer die 1402 may be from, for example... Figure 4 The stack 1410 offset is described in / 13B. In some instances, the buffer die 1402 may be positioned below the stack 1410, such as... Figure 5A or Figure 5B As shown in the diagram. In addition to the basic configuration, a single-stack configuration may also include one or more ECC DRAM dies 1461, 1462. Each of the one or more ECC dies 1461, 1462 can store a portion of the ECC information for a class of memory. For example, a single stack 1410 of dies may include two ECC dies 1461, 1462 configured to store ECC information for all four classes of memory in the stack 1410 of hierarchical memory. It should be understood that the allocation of ECC information from each class to each ECC die 1461, 1462 may differ from the situation described above without departing from the scope of the subject matter of the invention. In some instances, Figure 14BThe ECC dies of stack 1410 in a single stack configuration can be coupled to the DRAM interface of buffer die 1402 via a set of wire connectors 1520 for an additional data path, wherein the set of wire connectors 1420 are daisy-chained to two ECC dies (e.g., 1461, 1462) of stack 1410.

[0079] Figure 15A and 15B General Explanation Figure 11 The instance physical configuration of the instance storage module is 1500. Figure 15A This section describes a single stack 1510 of DRAM dies in a dual-stack configuration. Each stack in the dual-stack configuration may contain ten dies. Each stack in the dual-stack configuration may contain two dies from each of four levels (levels 0 to 3). The dies in each stack may be coupled to buffer 1502 via wire connectors 1512, 1514 extending from two data paths of the DRAM interface of buffer 1502. In this example, the first data path 1512 may daisy-chain to four dies in the stack. Each of the four dies may be associated with a different level among the four levels. In some examples, buffer dies 1502 may be from, for example... Figure 15A Each offset in the stack is illustrated in the diagram. In other instances, the buffer die may be located below one of the stacks, such as... Figure 5A 502 or Figure 5B As shown in 522. In some instances, the buffer die can be positioned below two stacks, such as... Figure 5D As shown in 562. In addition to the basic configuration, each stack in the dual-stack configuration may also contain one or more ECC / SDDC DRAM dies 1561, 1562. Each of the one or more ECC / SDDC dies can store ECC and SDDC information for one of the memory classes. For example, Figure 15AA single stack 1510 of dies may include a first ECC / SDDC die 1561 configured for ECC / SDDC information of storage class 2 and a second ECC / SDDC die 1562 configured for ECC / SDDC information of storage class 3. Other stacks (not shown) may include a second additional ECC / SDDC die configured for ECC / SDDC information of storage classes 0 and 1. It should be understood that the allocation of ECC / SDDC information from each class to each ECC / SDDC die may differ from that described above without departing from the scope of the subject matter of the invention. In some instances, the ECC / SDDC dies of each stack in a dual-stack configuration may be coupled to the DRAM interface of buffer die 1502 via wire connections (e.g., 1520) for additional data paths, wherein each set of wire connections is daisy-chained to the two ECC / SDDC dies (e.g., 1561, 1562) of each stack.

[0080] Figure 15B This section provides a general description of a single-stack configuration of the example memory module 1500 based on the basic architecture discussed above. A single stack 1510 of DRAM memory dies contains all 20 DRAM dies of memory module 1500. A single stack 1510 may contain four dies from each of four levels (levels 0 to 3). The dies of the stack 1510 of the hierarchical memory may be coupled to a buffer via wire connectors 1512, 1514, 1516, 1518 extending from the DRAM interface of buffer die 1502. In this example, each data path may daisy-chain to a set of four dies of the stack 1510 of the hierarchical memory. Each of the four dies may be associated with a different level in the four levels (levels 0 to 3). In some examples, buffer die 1502 may be from, for example... Figure 4 The stack 1510 offset is described in / 13B. In some instances, the buffer die 1502 may be positioned below the stack 1510, such as... Figure 5A or Figure 5B As shown in the image. Besides the basic configuration... Figure 15BThe single-stack configuration may also include one or more ECC / SDDC DRAM dies 1561, 1562, 1563, and 1564. Each of the one or more ECC dies 1561, 1562, 1563, and 1564 can store ECC / SDDC information for one of the memory classes. For example, a single stack 1510 of dies may contain four ECC / SDDC dies configured to store ECC information for all four classes of memory in the stack 1510 of hierarchical memory. It should be understood that the allocation of ECC information from each class to each ECC die may differ from the situation described above without departing from the scope of the subject matter of the invention. In some instances, Figure 15B The ECC / SDDC dies 1561, 1562, 1563, and 1564 of the stack 1510 in a single stack configuration can be coupled to the DRAM interface of the buffer die 1502 via a set of wire connectors 1520 for an additional data path, wherein each set of wire connectors is daisy-chained to each of the ECC / SDDC dies 1561, 1562, 1563, and 1564 of the stack 1510.

[0081] Figure 16 The description may include block diagrams of instance machines (e.g., host systems) 1600 of one or more memory devices and / or systems as described above. In alternative embodiments, machine 1600 may act as a standalone device or be connectable (e.g., networked) to other machines. In a networked deployment, machine 1600 may operate as a server machine, a client machine, or both in a server-client network environment. In an example, machine 1600 may act as a peer-to-peer (P2P) (or other distributed) network environment. Machine 1600 may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), mobile phone, network appliance, IoT device, automotive system, or any machine capable of executing (sequentially or otherwise) instructions specifying actions to be taken by said machine. Furthermore, while only a single machine is described, the term "machine" should also be considered as encompassing any collection of machines that individually or collectively execute a set of instructions (or multiple sets of instructions) to perform any or more of the methods discussed herein (e.g., cloud computing, Software as a Service (SaaS), other computer cluster configurations).

[0082] As described herein, an instance may comprise, or be operable through, logic, components, devices, packages, or mechanisms. A circuit system is a collection (e.g., a group) of circuits implemented in a tangible entity containing hardware (e.g., simple circuits, gates, logic, etc.). Circuit system members can be flexible over time and as the underlying hardware changes. A circuit system contains components that can perform a specific task individually or in combination when in operation. In an instance, the hardware of the circuit system may be perpetually designed to perform a specific operation (e.g., hardwired). In an instance, the hardware of the circuit system may contain variably connected physical components (e.g., execution units, transistors, simple circuits, etc.) that contain computer-readable media that are physically modified (e.g., invariant magnetic properties of concentrated particles, electrically movable placement, etc.) to encode instructions for a specific operation. When connecting physical components, the underlying electrical properties of the hardware constitute, for example, change from an insulator to a conductor, or vice versa. Instructions cause participating hardware (e.g., execution units or loading mechanisms) to generate portions of the circuit system components in the hardware via variable connections to perform a specific task when in operation. Therefore, when the device is operating, the computer-readable medium is communicatively coupled to other components of the circuit system. In an example, any one of the physical components can be used in more than one part of more than one circuit system. For instance, under operation, an execution unit can be used at one point in time in a first circuit of a first circuit system and reused by a second circuit of the first circuit system, or reused at a different time by a third circuit of the second circuit system.

[0083] Machine (e.g., computer system, host system, etc.) 1600 may include processing device 1602 (e.g., hardware processor, central processing unit (CPU), graphics processing unit (GPU), hardware processor core, or any combination thereof), main memory 1604 (e.g., read-only memory (ROM), dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), static memory 1606 (e.g., static random access memory (SRAM), etc.), and storage system 1618, some or all of which may communicate with each other via communication interface (e.g., bus) 1630. In one example, main memory 1604 includes one or more memory devices as described in the examples above.

[0084] Processing device 1602 may represent one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. Processing device 1602 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 1602 may be configured to execute instructions 1626 for performing the operations and steps discussed herein. Computer system 1600 may further include a network interface device 1608 for communication via network 1620.

[0085] Storage system 1618 may include machine-readable storage media (also known as computer-readable media) on which one or more sets of instructions 1626 or software embodying any one or more methods or functions described herein are stored. Instructions 1626 may also reside wholly or at least partially in main memory 1604 or processing device 1602 during execution by computer system 1600, which also constitute machine-readable storage media.

[0086] The term "machine-readable storage medium" should be understood to include a single or multiple media storing one or more sets of instructions, or any media capable of storing or encoding a set of instructions for machine execution and causing the machine to perform any one or more methods of this disclosure. Therefore, the term "machine-readable storage medium" should be understood to include, but is not limited to, solid-state memory, optical media, and magnetic media. In examples, centralized machine-readable media includes machine-readable media having a plurality of particles having invariant (e.g., rest) mass. Therefore, centralized machine-readable media propagate signals non-transitoryly. Specific examples of centralized machine-readable media may include: non-volatile memory, such as semiconductor memory devices (e.g., electrically programmable read-only memory (EPROM) or electrically erasable programmable read-only memory (EEPROM)) and flash memory devices; magnetic disks, such as internal hard disks and removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks.

[0087] Machine 1600 may further include a display unit, an alphanumeric input device (e.g., a keyboard), and a user interface (UI) navigation device (e.g., a mouse). In an example, one or more of the display unit, input device, or UI navigation device may be a touchscreen display. The machine is a signal generating device (e.g., a speaker), or one or more sensors, such as a Global Positioning System (GPS) sensor, a compass, an accelerometer, or one or more other sensors. Machine 1600 may include an output controller, such as serial (e.g., Universal Serial Bus (USB)), parallel, or other wired or wireless (e.g., infrared (IR), near field communication (NFC), etc.) connection, to communicate with or control one or more peripheral devices (e.g., a printer, a card reader, etc.).

[0088] Instructions 1626 (e.g., software, programs, operating systems (OS), etc.) or other data stored on storage system 1618 may be accessed by main memory 1604 for use by processing device 1602. Main memory 1604 (e.g., DRAM) is typically fast but volatile and therefore belongs to a different type of storage than storage system 1618 (e.g., SSD), which is suitable for long-term storage, including long-term storage when in a "shutdown" condition. Instructions 1626 or data for use by the user or machine 1600 are typically loaded into main memory 1604 for use by processing device 1602. When main memory 1604 is full, virtual space from storage system 1618 may be allocated to supplement main memory 1604; however, because storage system 1618 devices are typically slower than main memory 1604 and write speeds are typically at least twice as slow as read speeds, the use of virtual memory can significantly degrade the user experience due to storage system latency (compared to main memory 1604, such as DRAM). Furthermore, using storage system 1618 for virtual memory may significantly shorten the usable lifespan of storage system 1618.

[0089] Instruction 1624 may further utilize any of several transport protocols (e.g., Frame Relay, Internet Protocol (IP), Transmission Control Protocol (TCP), User Datagram Protocol (UDP), Hypertext Transfer Protocol (HTTP), etc.) to transmit or receive over network 1620 via network interface device 1608 using a transport medium. Example communication networks may include Local Area Networks (LANs), Wide Area Networks (WANs), Packet Data Networks (e.g., the Internet), Mobile Phone Networks (e.g., Cellular Networks), Conventional Telephone (POTS) Networks, and Wireless Data Networks (e.g., referred to as…). The Institute of Electrical and Electronics Engineers (IEEE) 802.15 series of standards, known as The network interface device 1608 may include one or more physical jacks (e.g., Ethernet, coaxial, or telephone jacks) or one or more antennas to connect to the network 1620. In an example, the network interface device 1608 may include multiple antennas to perform wireless communication using at least one of single-input multiple-output (SIMO), multiple-input multiple-output (MIMO), or multiple-input single-output (MISO) technologies. The term "transmission medium" is to be understood to include any intangible medium capable of storing, encoding, or transporting instructions for execution by the machine 1600, and includes digital or analog communication signals or other intangible media to facilitate communication of such software.

[0090] The above detailed description includes reference to the accompanying drawings, which form a part of the detailed description. The drawings illustrate, by means of illustration, specific embodiments in which the invention may be practiced. These embodiments are also referred to herein as “examples.” Such examples may include elements other than those shown or described. However, the inventors also contemplate providing only examples of those elements shown or described. Furthermore, the inventors also contemplate examples (or examples of those elements) of any combination or arrangement of those elements shown or described with respect to a particular example (or one or more aspects thereof) or with respect to other examples (or one or more aspects thereof) shown or described herein.

[0091] All publications, patents, and patent documents referenced in this document are incorporated herein by full reference as if individually cited. In the event of any inconsistency between this document and those documents incorporated by reference, the usage in the incorporated references shall be considered supplementary to the usage in this document; in the case of irreconcilable inconsistencies, the usage in this document shall prevail.

[0092] In this document, as is common in patent documents, the term “a” is used to include one or more, independent of any other instances or uses of “at least one” or “one or more”. In this document, unless otherwise indicated, the term “or” is used to refer to a non-exclusive “or”, such that “A or B” includes “A but not B”, “B but not A”, and “A and B”. In the appended claims, the terms “comprising” and “in which” are used as common English equivalents to the corresponding terms “including” and “wherein”. Furthermore, in the appended claims, the terms “comprising” and “including” are open-ended, meaning that a system, apparatus, article, or process that includes elements other than those listed after such terms in a claim is still considered to be within the scope of the claim. Additionally, in the appended claims, the terms “first,” “second,” and “third,” etc., are used merely as labels and are not intended to impose numerical requirements on their objects.

[0093] In various instances, the components, controllers, processors, units, engines, or tables described herein may include, in particular, physical circuitry systems or firmware stored on a physical device. As used herein, “processor” means any type of computing circuitry, such as, but not limited to, a microprocessor, microcontroller, graphics processor, digital signal processor (DSP), or any other type of processor or processing circuitry, comprising a set of processors or a multi-core device.

[0094] As used in this document, the term "horizontal" is defined as a plane parallel to a conventional plane or surface of the substrate, such as a conventional plane or surface below a wafer or die, regardless of the actual orientation of the substrate at any given time. The term "vertical" refers to a direction perpendicular to the horizontal as defined above. Prepositions such as "above," "over," and "below" are defined relative to a conventional plane or surface on the top or exposed surface of the substrate, regardless of the substrate's orientation; and "above" inherently indicates direct contact between a structure and another structure located "above" it (unless explicitly indicated otherwise); the terms "above" and "below" explicitly identify the relative placement of structures (or layers, features, etc.) that explicitly include, but are not limited to, direct contact between the identified structures, unless specifically indicated as such. Similarly, the terms "on" and "below" are not limited to horizontal orientation, because if a structure is the outermost part of the construction under discussion at a given time, then this structure may be "on" the reference structure even if it extends vertically relative to the reference structure rather than in a horizontal orientation.

[0095] The terms “wafer” and “substrate” are used herein to generally refer to any structure on which an integrated circuit is formed, and also to such structures during the various stages of integrated circuit manufacturing. Therefore, the following detailed description should not be construed in a limiting sense, and the scope of the various embodiments is defined only by the full scope of the appended claims together with their equivalents.

[0096] Various embodiments according to this disclosure and described herein include memories utilizing vertical structures of memory cells (e.g., NAND strings of memory cells). As used herein, directional adjectives relative to the surface of the substrate on which the memory cells are formed will be used (i.e., the vertical structure will be considered as extending away from the substrate surface, the bottom end of the vertical structure will be considered as the end closest to the substrate surface, and the top end of the vertical structure will be considered as the end furthest from the substrate surface).

[0097] As used herein, directional adjectives such as horizontal, vertical, orthogonal, parallel, and perpendicular may refer to relative orientation and, unless otherwise specified, are not intended to strictly adhere to specific geometric properties. For example, as used herein, a vertical structure need not be precisely perpendicular to the surface of the substrate, but may instead be substantially perpendicular to the surface of the substrate and may form an acute angle with the surface of the substrate (e.g., between 60 and 120 degrees).

[0098] In some embodiments described herein, different doping configurations can be applied to the Select Gate Source (SGS), Control Gate (CG), and Select Gate Drain (SGD), each of which in this example may be formed of or at least comprise polysilicon, resulting in these layers (e.g., polysilicon, etc.) having different etch rates when exposed to an etch solution. For example, during the formation of a monomer pillar in a 3D semiconductor device, SGS and CG may form a depression, while SGD may retain less or no depression. These doping configurations can therefore achieve selective etching into different layers (e.g., SGS, CG, and SGD) in the 3D semiconductor device using an etch solution (e.g., tetramethylammonium hydroxide (TMCH)).

[0099] As used herein, operating a memory cell includes reading from a memory cell, writing to a memory cell, or erasing a memory cell. The operation of placing a memory cell in a given state is referred to herein as “programming” and may include both writing to and erasing from a memory cell (i.e., the memory cell may be programmed into an erased state).

[0100] According to one or more embodiments of this disclosure, a memory controller (e.g., processor, controller, firmware, etc.) located inside or outside the memory device can determine (e.g., select, set, adjust, calculate, change, clear, communicate, adapt, derive, define, utilize, modify, apply, etc.) the number of wear cycles or wear states (e.g., record wear cycles, count them when operations of the memory device occur, track memory device operations initiated by the memory device, evaluate memory device characteristics corresponding to wear states, etc.).

[0101] According to one or more embodiments of this disclosure, a memory access device may be configured to provide a memory device with wear cycle information for each memory operation. A memory device control circuitry (e.g., control logic) may be programmed to compensate for memory device performance variations corresponding to the wear cycle information. The memory device may receive the wear cycle information and determine one or more operating parameters (e.g., values, characteristics) in response to the wear cycle information.

[0102] It will be understood that when an element is referred to as "on another element," "connected to another element," or "coupled to another element," it may be directly on, directly connected to, or coupled to the other element, or there may be intervening elements. In contrast, when an element is referred to as "directly on another element," "directly connected to another element," or "directly coupled to another element," there are no intervening elements or layers. If two elements are shown in the diagram as being connected by a line, then unless otherwise indicated, the two elements may be coupled or directly coupled.

[0103] The methods described herein can be implemented, at least in part, by a machine or computer. Some examples may include computer-readable or machine-readable media encoded with instructions that can be used to configure electronic devices to perform the methods described in the examples above. Implementations of such methods may include code, such as microcode, assembly language code, high-level language code, etc. Such code may contain computer-readable instructions for performing various methods. The code may form part of a computer program product. Furthermore, the code may be tangibly stored, for example, during execution or at other times, on one or more volatile or non-volatile tangible computer-readable media. Examples of such tangible computer-readable media may include, but are not limited to, hard disks, removable disks, removable optical discs (e.g., optical discs and digital video disks), magnetic tape cassettes, memory cards or sticks, random access memory (RAM), read-only memory (ROM), etc.

[0104] To better illustrate the methods and apparatus disclosed herein, a non-limiting list of embodiments is provided herein:

[0105] In a first instance, Example 1, a memory module may include: a first stack of at least eight memory dies comprising four pairs of memory dies, each of the four pairs of memory dies being associated with an individual memory level among four memory levels of the memory module; a memory controller configured to receive memory access commands and access memory locations of the first stack; and a substrate configured to route a connection between an external terminal of the memory module and the memory controller.

[0106] In Example 2, the subject of Example 1 includes the following: the first stack comprises at least nine memory dies; the controller is configured to store error correction code (ECC) information on a first memory die among the at least nine memory dies; and the first memory die is not one of the four pairs of memory dies.

[0107] In Example 3, the subject of Example 2 includes the following: the first stack comprises at least ten memory dies; the controller is configured to store single-device data correction (SDDC) information on a second memory die among the at least ten memory dies; and the second memory die is not one of the four pairs of memory dies.

[0108] In Example 4, the subject matter of Examples 1 to 3 includes the memory controller mounted on the substrate, offset laterally from the first stack.

[0109] In Example 5, the subject matter of Examples 1 to 4 includes the memory controller being mounted between the first stack and the substrate.

[0110] In Example 6, the subject matter of Examples 1 to 5 includes a plurality of wire-joint terminals configured to couple the terminals of the first stack to the terminals of the substrate.

[0111] In Example 7, the subject of Example 6 includes a first wire bonding terminal of the plurality of wire bonding terminals configured to couple a first single data terminal of the substrate to the first data terminals of at least four memory dies in the first stack of eight memory dies.

[0112] In Example 8, the subject matter of Examples 1 to 7 includes a second stack of at least eight memory dies, the second stack including a second four pairs of memory dies, each of the second four pairs of memory dies being associated with an individual memory level among the four memory levels of the memory module.

[0113] In Example 9, the subject of Example 8 includes the second stack being offset from the first stack and from the memory controller on the substrate.

[0114] In Example 10, the subject of Examples 8 to 9 includes the second stack being stacked together with the first stack.

[0115] In Example 11, the subject matter of Examples 8 to 10 includes, wherein each level includes at least four memory dies forming the first stack and the second stack.

[0116] In Example 12, the subject matter of Examples 1 to 11 includes, wherein each of the at least eight memory dies in the first stack is laterally offset from the adjacent memory dies in the first stack to expose the line-joint termination regions of at least seven of the at least eight memory dies.

[0117] In Example 13, the subject matter of Examples 1 to 12 includes a buffer die coupled to a substrate, the buffer die including a host device interface and a memory interface coupled to the first stack; and a circuitry in the buffer die configured to operate the host interface at a first data rate and the memory interface at a second data rate slower than the first data rate.

[0118] In Example 14, the subject of Example 13 includes the first stack containing dynamic random access memory (DRAM) dies.

[0119] In Example 15, the subjects of Examples 13 and 14 contain eight dynamic random access memory (DRAM) dies.

[0120] In Example 16, the subject of Examples 13 through 15 contains nine dynamic random access memory (DRAM) dies.

[0121] In Example 17, the subject matter of Examples 13 through 16 contains ten dynamic random access memory (DRAM) dies.

[0122] In Example 18, the subjects of Examples 13 through 17 contain sixteen dynamic random access memory (DRAM) dies.

[0123] In Example 19, the subjects of Examples 13 through 18 contain eighteen dynamic random access memory (DRAM) dies.

[0124] In Example 20, the subject of Examples 13 through 19 contains twenty dynamic random access memory (DRAM) dies.

[0125] In Example 21, the subject matter of Examples 1 to 20 includes, wherein the first stack comprises a ladder-stacked memory die.

[0126] In Example 22, the subject of Example 21 includes, wherein the first stack includes more than one step direction within a single stack.

[0127] Example 23 is a method comprising: storing information in a stacked memory cell of at least eight memory devices; and organizing the information across four levels of the memory cell, wherein each of the four levels is assigned to at least two of the at least eight memory devices.

[0128] In Example 24, the subject of Example 23 includes storing error correction code (ECC) information on a memory cell of a ninth memory device in the stack, wherein the ninth memory device is outside the at least eight memory devices.

[0129] In Example 25, the subject of Example 24 includes the allocation of the ECC information to the ninth memory device for a single level among the four levels.

[0130] In Example 26, the subject of Examples 24 to 25 includes storing single-device data correction (SDDC) information on a memory cell of a tenth memory device in the stack, wherein the tenth memory device is outside the at least eight memory devices.

[0131] The above description is intended to be illustrative and not restrictive. For example, the examples described above (or one or more aspects thereof) may be used in combination with each other. Other embodiments may be used by one of ordinary skill in the art upon review of the above description. An abstract is provided to conform to 37C.FR §1.72(b) to allow the reader to quickly determine the nature of the technical disclosure. It should be understood that the embodiments described are not intended to interpret or limit the scope or meaning of the claims. Moreover, in the above detailed description, various features may be grouped together to simplify this disclosure. This should not be construed as expecting that any unclaimed disclosed features are necessary for any claim. Rather, the subject matter of the invention may consist of fewer features than all of the particular disclosed embodiments. Therefore, the appended claims are hereby incorporated into the detailed description, wherein each claim exists independently as a separate embodiment, and such embodiments are considered to be combined or arranged in various ways. The scope of the invention should be determined with reference to the appended claims and the full scope of the equivalents granted by such claims.

Claims

1. A memory module comprising: A first stack of at least nine memory dies, comprising four pairs of memory dies, each of the four pairs of memory dies being associated with an individual memory level among the four memory levels of the memory module; A memory controller configured to receive memory access commands and access memory locations of the first stack, wherein the memory controller is configured to store error correction code (ECC) information on a first memory die among the at least nine memory dies, and wherein the first memory die is not one of the four pairs of memory dies. as well as A substrate configured to route the connection between the first stack of memory dies and the external terminal of the memory controller.

2. The memory module of claim 1, wherein the first stack comprises at least ten memory dies; The memory controller is configured to store single-device data correction SDDC information on a second memory die among the at least ten memory dies; and The second memory die is not one of the four pairs of memory dies.

3. The memory module of claim 1, wherein the memory controller is mounted on the substrate and offset laterally from the first stack.

4. The memory module of claim 1, wherein the memory controller is mounted between the first stack and the substrate.

5. The memory module of claim 1, comprising a plurality of line-connected terminals configured to couple the terminals of the first stack to the terminals of the substrate.

6. The memory module of claim 5, wherein a first wire bonding terminal of the plurality of wire bonding terminals is configured to couple a first single data terminal of the substrate to a first data terminal of at least four memory dies in the first stack.

7. The memory module of claim 1, further comprising a second stack of at least eight memory dies, the second stack containing a second four pairs of memory dies, each of the second four pairs of memory dies being associated with an individual memory level among the four memory levels of the memory module.

8. The memory module of claim 7, wherein the second stack is offset from the first stack and from the memory controller on the substrate.

9. The memory module of claim 7, wherein the second stack is stacked together with the first stack.

10. The memory module of claim 7, wherein each level comprises at least four memory dies forming the first stack and the second stack.

11. The memory module of claim 1, wherein each of the at least nine memory dies in the first stack is laterally offset from the adjacent memory dies in the first stack to expose a line-joint termination region of each of the memory dies.

12. The memory module of claim 1, wherein the first stack comprises a ladder-stacked memory die.

13. The memory module of claim 12, wherein the first stack comprises more than one step direction within a single stack.

14. A memory device comprising: A first stack of at least eight memory dies, comprising four pairs of memory dies, each of the four pairs of memory dies being associated with an individual memory class among four memory classes; A memory controller configured to receive memory access commands and access memory locations of the first stack; A substrate configured to route the connection between the first stack of memory dies and the external terminal of the memory controller; A buffer die coupled to the substrate, the buffer die including a host device interface and a memory interface coupled to the first stack; as well as The circuitry in the buffer die is configured to operate the host interface at a first data rate and the memory interface at a second data rate slower than the first data rate.

15. The memory device of claim 14, wherein the first stack comprises a dynamic random access memory (DRAM) die.

16. The memory device of claim 14, wherein the first stack comprises eight dynamic random access memory (DRAM) dies.

17. The memory device of claim 14, wherein the first stack comprises nine dynamic random access memory (DRAM) dies.

18. The memory device of claim 14, wherein the first stack comprises 10 dynamic random access memory (DRAM) dies.

19. The memory device of claim 14, wherein the first stack comprises 16 dynamic random access memory (DRAM) dies.

20. The memory device of claim 14, wherein the first stack comprises 18 dynamic random access memory (DRAM) dies.

21. The memory device of claim 14, wherein the first stack comprises 20 dynamic random access memory (DRAM) dies.

22. A method for storing information in a memory cell, comprising: The information is stored in memory cells of at least eight memory devices stacked together; The information is organized across four levels of memory cells, wherein each of the four levels is assigned to at least two of the at least eight memory devices; as well as Error correction code (ECC) information is stored in a memory cell of a ninth memory device in the stack, wherein the ninth memory device is outside the at least eight memory devices.

23. The method of claim 22, wherein the ECC information is allocated to the ninth memory device for a single level among the four levels.

24. The method of claim 22, further comprising storing single-device data correction SDDC information at a memory cell of a tenth memory device in the stack, wherein the tenth memory device is outside the at least eight memory devices.

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