Integrated memory with nonohmic device and capacitor

Abstract

Some embodiments include a memory cell having a non-ohmic device between a transistor source / drain region and a capacitor. Some embodiments include a memory cell having a transistor with a first source / drain region, a second source / drain region, and a channel region between the first and second source / drain regions. A capacitor is electrically coupled to the second source / drain region through a non-ohmic device. The non-ohmic device includes a non-ohmic device material that changes conductivity in response to an electrical property along the channel region. The non-ohmic device material has a high resistivity mode when the electrical property along the channel region is below a threshold level, and transitions to a low resistivity mode when the electrical property along the channel region meets or exceeds the threshold level. Some embodiments include a memory array.

Description

[0001] Relevant patent data

[0002] This application claims the benefit of U.S. Patent Application No. 16 / 721,006, filed December 19, 2019, the disclosure of which is incorporated herein by reference. Technical Field

[0003] Integrated memory; for example, ferroelectric random access memory (FeRAM), dynamic random access memory, etc. Background Technology

[0004] The ongoing goal is to achieve ever-increasing levels of integration in integrated memory. This includes increasing the fill density of memory components. Furthermore, it is anticipated that integrated memory will possess characteristics such as strong signal strength, good durability during heavy read / write cycles, fast access speeds, and protection against cell-to-cell interference mechanisms.

[0005] The memory may utilize memory cells (memory devices) that individually include access transistors combined with capacitors. If the memory is ferroelectric random access memory (FeRAM), the capacitor may be a ferroelectric capacitor, or if the memory is conventional dynamic random access memory (DRAM), it may be a non-ferroelectric capacitor.

[0006] The goal is to develop improved memory devices and improved memory arrays incorporating such devices.

[0007] The invention described herein can utilize non-ohmic devices. Figure 1 graphically compares conventional ohmic devices with conventional non-ohmic devices.

[0008] The upper figure shows the current (I) and voltage (V) of the ohmic device, and demonstrates the linear relationship between voltage and current.

[0009] In contrast, the lower curve shows the current (I) and voltage (V) of a non-ohmic device, and illustrates the non-linear relationship between voltage and current. Specifically, the lower curve shows a high resistivity (low conductivity) mode for the non-ohmic device in region 2, where the current increases slowly with increasing voltage, and a low resistivity (high conductivity) mode in region 4, where the current increases rapidly with increasing voltage. In transition region 3, the high resistivity mode transitions to a low resistivity mode.

[0010] In some applications, non-ohmic devices can be those that change from a high resistivity mode to a low resistivity mode when exposed to gradually increasing current and / or gradually increasing voltage.

[0011] Referring to Figures 2A and 2B, an example of a non-ohmic device 10 is described. Device 10 may be a conductive bridging device. The device is shown in high resistivity mode in Figure 2A and in low resistivity mode in Figure 2B.

[0012] The device 10 includes a first conductive electrode 12, a second conductive electrode 14, and an insulating material 16 located between the electrodes 12 and 14. The insulating material may include one or more oxides having silver or copper dispersed therein.

[0013] The low-resistance mode of Figure 2B has a conductive filament 18 extending through the insulating material 16 to electrically couple the first electrode 12 and the second electrode 14 to each other. In contrast, the high-resistance mode of Figure 2A has only a portion of the filament 18 formed therein (or may not have the filament formed therein), and therefore there is no conductive coupling between the first electrode 12 and the second electrode 14.

[0014] In some applications, the filament 18 can grow across the insulating material 16 due to the voltage difference between electrodes 12 and 14. Therefore, the device 10 will remain in a high resistivity mode (i.e., mode 2 of the non-ohmic device in FIG. 1) until a threshold voltage is provided between electrodes 12 and 14. This threshold voltage will induce the formation of the filament 18 and thus cause the formation of a low resistivity mode (i.e., mode 4 of the non-ohmic device in FIG. 1) as shown in FIG. 2B.

[0015] Although the description above indicates that the wire 18 is formed by voltage differential, it should be understood that the wire 18 may alternatively be described as being formed due to the threshold current provided between electrodes 12 and 14 and passing through insulating material 16.

[0016] Another example of a non-ohmic device 10a is described with reference to Figures 3A and 3B. The device includes a first electrode 12 and a second electrode 14, and includes a phase change material 20 located between the first and second electrodes. The phase change material may contain one or more chalcogenides. In the configuration of Figure 3A, the entire phase change material 20 is located within the first phase 21.

[0017] In Figure 3A, device 10a is in a high resistivity mode (similar to mode 2 of the non-ohmic device in Figure 1), and in Figure 3B, it is in a low resistivity mode (similar to mode 4 of the non-ohmic device in Figure 1). The low resistivity mode includes a region of phase change material 20 that has been transformed into region 22 having a second phase 23 (illustrated graphically by the shading within region 22). The second phase 23 differs from the first phase 21. The second phase 23 has a higher conductivity (lower resistance) than the first phase 21.

[0018] In some applications, material 20 can be transformed from the first phase 21 to the second phase 23 because a threshold voltage (and / or threshold current) is provided across the region of material 20 between electrodes 12 and 14. Attached Figure Description

[0019] Figure 1 graphically compares prior art ohmic devices with prior art non-ohmic devices.

[0020] Figures 2A and 2B illustrate examples of prior art non-ohmic devices in high resistivity mode (Figure 2A) and low resistivity mode (Figure 2B).

[0021] Figures 3A and 3B illustrate another example of a prior art non-ohmic device in high resistivity mode (Figure 3A) and low resistivity mode (Figure 3B).

[0022] Figure 4 A schematic cross-sectional side view of a region of an instance integration assembly including instance memory cells.

[0023] Figure 5 A schematic diagram of a region of an instance integration assembly that includes instance memory cells.

[0024] Figure 6 A schematic cross-sectional side view of a region of an instance integration assembly that includes a region of an instance memory array.

[0025] Figure 7 A schematic diagram of a region of an instance integration assembly that includes a region of an instance memory array. Detailed Implementation

[0026] Conventional memories (e.g., FeRAM, DRAM) may include capacitors coupled to the source / drain regions of access transistors (e.g., ferroelectric capacitors in FeRAM and nonferroelectric capacitors in DRAM). These capacitors may be incorporated into the memory cell. The source / drain region is one of two source / drain regions of the access transistor, the other of which is coupled to a digital line. A channel region extends between the two source / drain regions. A gate may be adjacent to the channel region and may be used to control the current along the channel region during operation of the access transistor. During read / write operations associated with the memory cell, the source / drain regions may be electrically coupled to each other via the channel region, or otherwise not electrically coupled to each other.

[0027] The problem with conventional memory is that even in operating modes where the source / drain regions are not electrically coupled to each other, current can leak from the capacitor through the channel region. This leakage can lead to data loss.

[0028] Leakage can be more severe in access transistors with vertically extending channel regions compared to those with horizontally extending channel regions. This is because polysilicon is typically used in vertically extending channel regions while monocrystalline silicon is typically used in horizontally extending channel regions. Polysilicon can have grain boundary and / or intergranular defects that affect device characteristics and lead to gate-induced drain leakage (GIDL) and / or other leakage mechanisms.

[0029] Some embodiments include a memory having capacitors (ferroelectric or nonferroelectric capacitors) coupled to the source / drain regions of an access transistor via non-ohmic devices. Non-ohmic devices can reduce or even eliminate problematic leakage associated with conventional ferroelectric memories.

[0030] Figure 4 A portion of the integrated assembly 30 having instance memory device 32 is shown.

[0031] Device 32 includes access transistor 34, non-ohmic device 36 and capacitor 38.

[0032] The access transistor 34 includes a pair of source / drain regions 40 and 42, and includes a channel region 44 extending between the source / drain regions 40 and 42. In the illustrated embodiment, the channel region extends vertically. The source / drain regions 40 and 42 may be referred to as the upper source / drain region and the lower source / drain region, respectively. In some embodiments, one of the source / drain regions 40 and 42 may be referred to as the first source / drain region, and the other as the second source / drain region.

[0033] Regions 40, 42, and 44 are within semiconductor material 46. Semiconductor material 46 may comprise any suitable composition; and in some embodiments may comprise, substantially comprise, or comprise one or more of the following: silicon, germanium, III / V semiconductor materials (e.g., gallium phosphide), semiconductor oxides, etc.; wherein the term III / V semiconductor material refers to a semiconductor material comprising elements selected from Groups III and V of the periodic table (where Groups III and V are old nomenclature and are now referred to as Groups 13 and 15). In some embodiments, semiconductor material 46 may comprise, substantially comprise, or comprise silicon. Silicon may be in any suitable phase (e.g., one or more of polycrystalline, amorphous, and single-crystal). A dot-matrix method is used to distinguish source / drain regions 40 and 42 from channel region 44.

[0034] Source / drain regions 40 and 42 may include heavily doped regions within region 44. Heavy doping may correspond to at least about 10⁻⁶ of one or more conductivity-enhancing dopants within regions 40 and 42. 22 atoms / cm 3The source / drain regions 40 and 42 may be n-type doped (e.g., may include one or both of phosphorus and arsenic). Alternatively, the source / drain regions 40 and 42 may be p-type doped (e.g., may include boron).

[0035] The channel region 44 can be doped to any suitable concentration using any suitable dopant. In some embodiments, the channel region may be effectively undoped (i.e., may include only intrinsic dopant concentrations (e.g., less than or equal to about 10)). 15 atoms / cm 3 (dopant concentration). In some embodiments, the configuration described herein may reduce the amount of dopant used in the channel region relative to a conventional configuration with increased / higher channel doping (higher threshold voltage doping); wherein the reduced amount of dopant is, for example, less than or equal to about 10 in the channel region. 17 atoms / cm 3 Less than or equal to approximately 10 16 atoms / cm 3 or even less than or equal to about 10 15 atoms / cm 3 The dopant concentration.

[0036] The lower source / drain region 42 is electrically coupled to the digital line (bit line, sense line) 48 and, in the illustrated embodiment, directly abuts the upper surface of the digital line 48.

[0037] Digital line 48 includes conductive material 50. Conductive material 50 may include any suitable conductive composition; such as one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.) and / or conductive doped semiconductor materials (e.g., conductive doped silicon, conductive doped germanium, etc.).

[0038] The digital line 48 is supported by an insulating material 52. The insulating material 52 may include any suitable composition; and in some embodiments, it may include silicon dioxide, be substantially composed of silicon dioxide, or be composed of silicon dioxide.

[0039] The digital line 48 extends along the indicated x-axis direction, which is along... Figure 4 The flatness of the page.

[0040] The upper surface 49 of the digital line 48 can be considered to extend in a horizontal direction corresponding to the illustrated x-axis. The channel region 44 extends in a vertical direction corresponding to the illustrated z-axis. In some embodiments, the vertical direction of the channel region 44 may be orthogonal to the horizontal direction of the upper surface 49 of the digital line 48 (as shown). Alternatively, the vertical direction of the channel region 44 may be substantially orthogonal to the horizontal direction of the upper surface 49, wherein the term "substantially orthogonal" means orthogonal within reasonable tolerances of manufacturing and measurement. In some embodiments, the vertical direction of the channel region 44 may be considered to be substantially orthogonal to the horizontal direction of the upper surface 49, wherein the term "substantially orthogonal" means within approximately 10° of orthogonality.

[0041] Gate 53 extends along channel region 44 and is spaced apart from channel region by an inserted dielectric material 54. The gate may be positioned relative to... Figure 4 The portion of the character line extending from the page in the cross-sectional view of the page and thus intersecting with the number line 48. The character line may be along the y-axis direction orthogonal (or at least substantially orthogonal) to the x-axis direction of the number line 48. Figure 4 (Extended not shown in the text)

[0042] Gate 53 includes a conductive gate material 56. The conductive gate material 56 may include any suitable conductive composition; such as one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.) and / or conductive doped semiconductor materials (e.g., conductive doped silicon, conductive doped germanium, etc.).

[0043] The dielectric material 54 may be referred to as the gate dielectric material. The dielectric material 54 may include any suitable composition; and in some embodiments, it may include silicon dioxide, be substantially composed of silicon dioxide, or be composed of silicon dioxide.

[0044] In the illustrated embodiment, gate 53 along... Figure 4 The gate is located on both sides of the channel region 44 in cross-section. In other embodiments, the gate may extend only along one of the sides of the channel region 44. In still other embodiments, the gate may extend entirely around the channel region (i.e., it may extend along the channel region relative to the channel region). Figure 4 (The cross-section of the page extends into and outside the page surface).

[0045] Gate 53 can be considered operably adjacent to (operably close to) channel region 44 such that a sufficient voltage applied to the gate will induce an electric field that allows current flowing through the associated channel region 44 to electrically couple source / drain regions 40 and 42 to each other. If the voltage to the gate is below a threshold level, current will not flow through the channel region, and source / drain regions 40 and 42 will not be electrically coupled to each other. This selective control of the coupling / decoupling of the source / drain regions by the voltage level applied to the gate can be referred to as source / drain gated coupling.

[0046] A non-ohmic device 36 is located between the upper source / drain region 40 and the capacitor 38. The non-ohmic device 36 includes non-ohmic device material 58 located between the lower electrode 60 and the upper electrode 62. In some embodiments, one of electrodes 60 and 62 may be referred to as the first electrode, and the other as the second electrode.

[0047] Electrodes 60 and 62 may comprise any suitable conductive composition; such as one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductive doped semiconductor materials (e.g., conductive doped silicon, conductive doped germanium, etc.). Electrodes 60 and 62 may comprise the same conductive composition as each other, or may comprise conductive compositions that are different from each other.

[0048] The non-ohmic device material 58 may comprise any suitable composition. For example, the non-ohmic device material 58 may comprise a conductive bridging material similar to the conductive bridging material described above with reference to Figures 2A and 2B, a phase change material similar to the phase change material described above with reference to Figures 3A and 3B, or any other suitable material that changes resistivity when a suitable threshold current and / or threshold voltage is reached. In some embodiments, the non-ohmic device material 58 may comprise one or both of Ag (silver) and Cu (copper) dispersed within a matrix comprising one or more of HfO, TiO, and CuS, substantially composed of one or more of HfO, TiO, and CuS, or composed of one or more of HfO, TiO, and CuS; wherein the chemical formula indicates the principal component rather than a specific stoichiometry. Silver and / or copper may correspond to conductive bridging materials; wherein when a threshold voltage and / or threshold current is provided across the matrix, silver and / or copper ultimately form conductive filaments within the matrix. In some embodiments, a device 36 including conductive bridging material 58 may be referred to as a conductive bridging device.

[0049] In some embodiments, the non-ohmic device material 58 may be a bidirectional material, and specifically may include one or more chalcogenides. For example, material 58 may include one or more of germanium (Ge), antimony (Sb), tellurium (Te), and indium (In). In specific embodiments, material 58 may, for example, include GeSbTe or InGeTe, consist substantially of GeSbTe or InGeTe, or consist of GeSbTe or InGeTe, wherein the formula indicates the components within the listed substances rather than specifying a specific stoichiometry of such components. The bidirectional material may be referred to as a phase change material, and the device 36 may be referred to as a phase change device. The phase change material may include one or more of germanium, antimony, tellurium, and indium.

[0050] In some embodiments, material 58 may comprise a mixed ion-electron conductive material; and may include, for example, one or more of SrTiO, TiO, CeO, LiFePO, and LaCuO; wherein the chemical formula indicates the major components rather than a specific stoichiometry. In such embodiments, the non-ohmic device 38 may be referred to as a mixed ion-electron conductor (MIEC).

[0051] In some embodiments, material 58 may comprise a metallic insulator having a transition element. The transition element may correspond to one or both of vanadium (V) and niobium (Nb), and the metallic insulator may correspond to one or both of VO and NbO; wherein the chemical formula indicates the major component rather than a specific stoichiometry.

[0052] In some embodiments, the non-ohmic device 36 may be a bidirectional threshold switch. In such embodiments, the material 58 may comprise one or more chalcogenides.

[0053] In some embodiments, the non-ohmic device 36 may be referred to as a two-terminal selection device because it includes two terminals 60 and 62.

[0054] The capacitor 38 includes a first electrode (bottom electrode) 64, a second electrode (top electrode) 66, and an insulating material 68 located between the first electrode 64 and the second electrode 66, all electrically coupled to the non-ohmic device 36. The capacitor may be a ferroelectric capacitor (i.e., may include ferroelectric insulating material) or a non-ferroelectric capacitor (i.e., may include non-ferroelectric insulating material).

[0055] Electrodes 64 and 66 may comprise any suitable conductive composition; such as one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductive doped semiconductor materials (e.g., conductive doped silicon, conductive doped germanium, etc.). Electrodes 64 and 66 may comprise the same conductive composition as each other, or may comprise conductive compositions that are different from each other.

[0056] The insulating material 68 may comprise any suitable composition. The insulating material 68 may be a ferroelectric insulating material and may, for example, comprise, consist substantially of, or consist of one or more materials selected from the group consisting of: transition metal oxides, zirconium, zirconium oxide, hafnium, hafnium oxide, lead zirconium titanate, tantalum oxide, and barium strontium titanate; and may contain one or more dopants comprising: silicon, aluminum, lanthanum, yttrium, erbium, calcium, magnesium, strontium, and rare earth elements. The ferroelectric insulating material 68 may be provided in any suitable configuration; for example, a single homogeneous composition, or a laminate of two or more discrete individual compositions. The insulating material 68 may be a non-ferroelectric insulating material and may, for example, comprise, consist substantially of, or consist of one or more of the following: silicon dioxide, aluminum oxide, hafnium oxide, zirconium oxide, etc.

[0057] In the illustrated embodiment, the first electrode 64 is configured as an upwardly open container. Insulating material 68 and the second electrode 66 extend downward into this upwardly open container. In other embodiments, the capacitor 38 may have other configurations.

[0058] In some embodiments, one or both of the electrodes 60 and 62 of the non-ohmic device 36 may be omitted. For example, electrode 64 may be the common electrode of both the capacitor 38 and the non-ohmic device 36.

[0059] In some embodiments, the upper electrode 66 of capacitor 38 may be referred to as a plate electrode. Such a plate electrode may be coupled to a plate line (plate interconnect structure) 70 extending to a reference voltage 72. The reference voltage may be at any suitable level; and in some embodiments may be ground, VCC / 2, etc.

[0060] In operation, the non-ohmic device material 58 changes its conductivity in response to varying electrical properties (e.g., voltage and / or current) along the channel region 44. When the electrical properties along the channel region are below a threshold level, the non-ohmic device material exhibits a high resistivity mode (similar to mode 2 described above with reference to FIG. 1), and transitions to a low resistivity mode (similar to mode 4 described above with reference to FIG. 1) when the electrical properties along the channel region meet or exceed the threshold level; wherein the electrical properties and threshold level are understood to refer to them in an “absolute” mathematical sense, such that the electrical properties can have positive values ​​(in which case the threshold level can be a higher positive value) or negative values ​​(in which case the threshold level can be a lower negative value). In some embodiments, the conductivity of the non-ohmic device material 58 in the low resistivity mode will be several orders of magnitude higher than the conductivity of the non-ohmic device material 58 in the high resistivity mode.

[0061] In some embodiments, the non-ohmic device 36 may be used alone to limit undesired leakage between the capacitor and the channel, and therefore may not be a memory element (compared to some conventional uses of non-ohmic devices as memory elements for memory cells).

[0062] Figure 5 The device 32 has a transistor and a capacitor, and can be referred to as a single transistor single capacitor (1T-1C) memory cell.

[0063] Figure 5 This diagram illustrates an assembly 30 in an embodiment where capacitor 38 is a ferroelectric capacitor. The assembly includes a memory cell 32 comprising an access transistor 34, a non-ohmic device 36, and a ferroelectric capacitor 38. The source / drain region 42 of transistor 34 is coupled to a digital line (bit line) 48, and the source / drain region 40 of transistor 34 is coupled to the non-ohmic device 36. The source / drain regions 40 and 42 are gated (i.e., gate-coupled to each other) via word line 53. The electrode 64 of the ferroelectric capacitor 38 is coupled to the source / drain region 40 of transistor 34 via the non-ohmic device 36. The electrode 66 of the ferroelectric capacitor 38 is coupled to a plate line 70.

[0064] Figure 4 and 5 The portion of the integrated assembly described herein can be considered as a region of the memory array 74. Figure 6 A larger area of ​​the memory array 74 is shown. The illustrated area of ​​the memory array comprises a plurality of memory cells 32 above digital lines 48. Each of the memory cells includes a non-ohmic device 36 (labeled only) located between a capacitor 38 (only one is labeled) and an access transistor 34 (only one is labeled). In the illustrated embodiment, an insulating material 62 spans the entire extension of the illustrated capacitor 38, and a plate electrode 66 also spans the entire extension of the illustrated capacitor 38. The insulating material 62 may be ferroelectric or non-ferroelectric, and therefore the capacitor 38 may be ferroelectric or non-ferroelectric.

[0065] Gate 53 (only one of them is labeled) runs along word lines WL1 to WL7, where such word lines are relative to Figure 6 The page extends and extends out of the cross-section of the page.

[0066] The memory array 74 is supported by a substrate 80. The substrate 80 may include semiconductor materials; and may include, for example, monocrystalline silicon, be substantially composed of monocrystalline silicon, or be composed of monocrystalline silicon. The substrate 80 may be referred to as a semiconductor substrate. The term "semiconductor substrate" means any structure comprising semiconductor materials, including but not limited to bulk semiconductor materials, such as semiconductor wafers (alone or in combinations of other materials), and semiconductor material layers (alone or in combinations of other materials). The term "substrate" means any support structure, including but not limited to the semiconductor substrates described above. In some applications, the substrate 80 may correspond to a semiconductor substrate containing one or more materials associated with integrated circuit manufacturing. Such materials may include one or more of, for example, refractory metal materials, barrier materials, diffusion materials, insulating materials, etc.

[0067] A gap is provided between the substrate 80 and the memory array 74 to indicate that other components and / or devices may be disposed between the substrate and the memory array. In the illustrated embodiment, a logic circuit system is disposed above the substrate 80 and below the memory array 74. The logic circuit system includes a driver circuit system (e.g., a word line driver circuit system) 82 and a sensing circuit system (e.g., a sense amplifier circuit system) 84. Digital lines 48 may be electrically coupled to the sensing circuit system 84, as shown. Word lines 52 may be electrically coupled to the driver circuit system 82, as shown.

[0068] The substrate 80 and the memory array 74 may be portions of the same semiconductor die and may correspond to the levels provided over such a die. Alternatively, the memory array 74 may be disposed relative to the substrate 80 along a separate semiconductor die.

[0069] Figure 7 This illustration shows an embodiment where memory cell 32 includes a ferroelectric capacitor. Figure 6 The memory array 74 is a region. The illustrated region includes four of the memory cells 32; each of the memory cells contains a non-ohmic device 36 located between the transistor 34 and the ferroelectric capacitor 38.

[0070] The illustrated region of memory array 74 includes two word lines (specifically, WL1 and WL2), two bit lines 48 (specifically, BL1 and BL2), and two board lines 70 (specifically, PL1 and PL2). Word lines are designated 53 to indicate that such word lines include gate 53. In some embodiments, word lines can be considered as extensions of gates.

[0071] Word lines are electrically coupled to word line drivers 82, bit lines 48 are coupled to sense amplifiers 84, and board lines 70 are electrically coupled to reference sources 72. Each memory cell 32 is uniquely addressed by a combination including one word line (gate line) and one digital line (bit line). In similar embodiments, capacitors may be nonferroelectric capacitors of the DRAM array, and each capacitor may be uniquely addressed by both a word line (gate line) and a digital line (bit line).

[0072] In some embodiments, the memory cell configuration described herein can eliminate any need to operate the memory cell (e.g., DRAM cell) under conditions where a negative voltage is applied to the gate of the access transistor (e.g., access transistor 34).

[0073] In some embodiments, the memory cell configuration described herein eliminates the need for any leakage means extending from the storage node of the ferroelectric capacitor to the plate electrodes of the ferroelectric capacitor (where such leakage means are used to loosely electrically couple the plate electrodes to the storage node to allow excess charge to dissipate from the storage node) compared to some conventional configurations.

[0074] In some embodiments, the response characteristics triggered in a non-ohmic device can reduce the voltage utilized along the gate of the access transistor, thereby reducing overstress on the gate dielectric (e.g., gate oxide) and improving device reliability.

[0075] In some embodiments, threshold voltages of the channel region (44), operating characteristics of the non-ohmic device (36), operating characteristics of the capacitor (38), voltages on the gate (53) and / or voltages on the digital line (48) can be configured to avoid “pumping nodes”, especially in DRAM embodiments.

[0076] The assemblies and structures discussed above can be used within integrated circuits (where the term "integrated circuit" refers to electronic circuitry supported by a semiconductor substrate) and incorporated into electronic systems. Such electronic systems can be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and special-purpose modules, and can comprise multi-layered, multi-chip modules. Electronic systems can be any of the following wide range of systems: for example, cameras, wireless devices, displays, chipsets, set-top boxes, games, lighting, vehicles, clocks, televisions, cellular phones, personal computers, automobiles, industrial control systems, aircraft, etc.

[0077] Unless otherwise specified, the various materials, substances, compositions, etc. described herein may be formed by any suitable method now known or to be developed, including, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.

[0078] The terms “dielectric” and “insulating” are used to describe materials having insulating electrical properties. These terms are considered synonymous in this disclosure. In some cases, the term “dielectric” and in others, the term “insulating” (or “electrically insulating”) may be used within this disclosure to provide linguistic variation to simplify the premises of the following claims, rather than to indicate any significant chemical or electrical differences.

[0079] The terms "electrical connection" and "electrical coupling" are both used in this disclosure. The terms are considered synonymous. The use of one term in some cases and another in others may be to provide linguistic variation within this disclosure to simplify the premises of the following claims.

[0080] The specific orientations of the various embodiments in the drawings are for illustrative purposes only, and in some applications, embodiments may be rotated relative to the shown orientation. The descriptions provided herein and the following claims relate to any structure having the described relationships between various features, regardless of whether the structure is in a specific orientation of the drawings or rotated relative to such an orientation.

[0081] Unless otherwise specified, the accompanying cross-sectional views show only the features within the plane of the cross-section and not the material behind the plane of the cross-section, in order to simplify the drawings.

[0082] When a structure is referred to above as being “on,” “adjacent to,” or “against” another structure, the structure may be directly on the other structure or there may be intervening structures. In contrast, when a structure is referred to as being “directly” on, directly adjacent to, or directly against another structure, there are no intervening structures. The terms “directly below,” “directly above,” etc., do not indicate direct physical contact (unless otherwise explicitly stated), but instead indicate upright alignment.

[0083] A structure (e.g., a layer, material, etc.) may be referred to as "vertically extending" to indicate that the structure typically extends upward from the underlying substrate (e.g., a base plate). A vertically extending structure may extend substantially orthogonally relative to or not relative to the upper surface of the substrate.

[0084] Some embodiments include a memory cell having a non-ohmic device located between the source / drain regions of a transistor and a capacitor.

[0085] Some embodiments include a memory cell having a transistor having a first source / drain region, a second source / drain region, and a channel region located between the first and second source / drain regions. A capacitor is electrically coupled to the second source / drain region via a non-ohmic device. The non-ohmic device includes a non-ohmic device material whose conductivity changes in response to the electrical properties along the channel region. When the electrical properties along the channel region are below a threshold level, the non-ohmic device material has a high resistivity mode, and when the electrical properties along the channel region meet or exceed the threshold level, it switches to a low resistivity mode.

[0086] Some embodiments include a memory array having digital lines extending along a first direction. An access transistor includes a first source / drain region electrically coupled to the digital lines, a second source / drain region vertically offset from the first source / drain region, and a channel region located between the first and second source / drain regions. A gate is operatively adjacent to the channel region. A capacitor is electrically coupled to the second source / drain region via a non-ohmic device. The capacitor is formed by memory cells. Each memory cell is uniquely addressed by a combination of one digital line and one word line.

[0087] As per the provisions, the subject matter disclosed herein has been described in more or less specific language regarding structural and methodological features. However, it should be understood that the claims are not limited to the specific features shown and described, as the components disclosed herein include exemplary embodiments. Therefore, the claims have the full scope as stated in writing and should be properly interpreted in accordance with the principle of equivalence.

Claims

1. A memory cell comprising a non-ohmic device located between a first source / drain region of a transistor and a capacitor, the non-ohmic device being a non-memory element in operation, the non-ohmic device comprising a non-ohmic material containing one or both of Ag and Cu dispersed in a matrix composed of one or more of HfO, TiO, and CuS, the transistor having a channel region extending vertically between the first source / drain region and a second source / drain region.

2. The memory cell according to claim 1, wherein the memory cell is a single-transistor single-capacitor memory cell.

3. The memory cell according to claim 1, wherein the capacitor is a ferroelectric capacitor.

4. The memory cell of claim 3, wherein the ferroelectric capacitor has plate electrodes and a storage node, and does not have a leakage device extending from the storage node to the plate electrodes.

5. The memory cell according to claim 1, wherein the capacitor is a nonferroelectric capacitor.

6. The memory cell of claim 1, wherein the transistor includes a gate, and wherein a negative voltage is not applied to the gate.

7. The memory cell of claim 1, wherein the non-ohmic device comprises a chalcogenide.

8. The memory cell according to claim 1, wherein the non-ohmic device is a two-terminal selection device.

9. The memory cell of claim 1, wherein the non-ohmic device is a hybrid ion-electronic conductor.

10. The memory cell of claim 1, wherein the non-ohmic device is a bidirectional threshold switch.

11. The memory cell of claim 1, wherein the non-ohmic device is a conductive bridging device.

12. The memory cell according to claim 1, wherein the non-ohmic device is a phase-change device.

13. The memory cell of claim 12, wherein the phase change device comprises a phase change material, the phase change material comprising one or more of germanium, antimony, tellurium and indium.

14. The memory cell of claim 1, wherein the non-ohmic device comprises a hybrid ion-electron conductive material.

15. The memory cell of claim 14, wherein the mixed ion-electron conductive material comprises one or more of SrTiO, TiO, CeO, LiFePO4, and LaCuO; wherein the chemical formula indicates the major component rather than a specific stoichiometry.

16. The memory cell of claim 1, wherein the non-ohmic device comprises a metal insulator having a transition element.

17. The memory cell of claim 16, wherein the transition element is vanadium.

18. The memory cell of claim 17, wherein the metal insulator is VO, wherein the chemical formula indicates the major component rather than a specific stoichiometry.

19. The memory cell of claim 16, wherein the transition element is niobium.

20. The memory cell of claim 19, wherein the metal insulator is NbO, wherein the chemical formula indicates the major component rather than a specific stoichiometry.

21. The memory cell of claim 1, wherein the second source / drain region is electrically coupled to a digital line.

22. The memory cell according to claim 21, wherein: The capacitor includes a first electrode electrically coupled to the non-ohmic device, a second electrode offset from the first electrode, and an insulating material located between the first electrode and the second electrode. The first electrode is configured as an upward-open container; and The insulating material and the second electrode extend into the upward-opening container.

23. A memory cell comprising a non-ohmic device located between an access transistor having a vertically extending channel region and a capacitor, the non-ohmic device operating as a non-memory element, the non-ohmic device containing a non-ohmic material comprising one or more members of the group consisting of SeSbTe, InGeTe, SiTiO, TiO, CeO, LiFeP and LaCuO.

24. The memory cell of claim 23, wherein the channel region comprises polysilicon.

25. The memory cell of claim 23, wherein the capacitor is a ferroelectric capacitor.

26. The memory cell of claim 23, wherein the capacitor is a nonferroelectric capacitor.

27. A memory cell comprising: A transistor having a first source / drain region, a second source / drain region, and a channel region extending vertically between the first source / drain region and the second source / drain region; and A capacitor electrically coupled to a second source / drain region via a non-ohmic device that is a non-memory element in operation; the non-ohmic device comprises a non-ohmic device material whose conductivity changes in response to electrical properties along the channel region, the non-ohmic device material comprising one or more members of the group consisting of SeSbTe, InGeTe, SiTiO, TiO, CeO, LiFeP, and LaCuO; the non-ohmic device material has a high resistivity mode when the electrical properties along the channel region are below a threshold level, and transitions to a low resistivity mode when the electrical properties along the channel region meet or exceed the threshold level.

28. The memory cell of claim 27, wherein the dopant concentration in the channel region is less than or equal to 10. 17 atoms / cm 3 .

29. The memory cell of claim 27, wherein the capacitor is a ferroelectric capacitor.

30. The memory cell of claim 27, wherein the capacitor is a nonferroelectric capacitor.

31. The memory cell of claim 27, wherein the electrical property is electric current.

32. The memory cell of claim 27, wherein the electrical property is voltage.

33. A memory array comprising: The digital line extends along the first direction; An access transistor having a first source / drain region electrically coupled to the digital line, a second source / drain region vertically offset from the first source / drain region, and a channel region located between the first source / drain region and the second source / drain region; A gate line that is operatively close to the channel region and extends along a second direction intersecting the first direction; and A capacitor electrically coupled to the second source / drain region via a non-ohmic device that is a non-memory element, the non-memory element comprising one or both of Ag and Cu dispersed in a matrix composed of one or more members of a group consisting of HfO, TiO and CuS; the capacitor is composed of memory cells; each of the memory cells is uniquely addressed by one of the digital lines combined with one of the word lines.

34. The memory array of claim 33, wherein the capacitor is a ferroelectric capacitor.

35. The memory array of claim 33, wherein the capacitor is a nonferroelectric capacitor.

36. The memory array according to claim 33, wherein: The memory cells of the memory array are arranged in columns and rows, wherein the digital lines extend along the columns and the gate lines extend along the rows; The memory cells are located above the substrate; and The logic circuit system is along the substrate and directly below the memory cell.

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