Memory devices and methods of forming memory devices

Abstract

Some embodiments include an assembly having first and second pillars. Each of the pillars has an inner edge and an outer edge. A first gate is proximate to a channel region of the first pillar. A second gate is proximate to a channel region of the second pillar. A shield line is between the first and second pillars. First and second bottom electrodes are over the first and second pillars, respectively; and are configured as first and second gussets. An insulating material is over the first and second bottom electrodes. The insulating material can be ferroelectric or non-ferroelectric. A top electrode is over the insulating material. Some embodiments include a method of forming an assembly.

Description

[0001] Relevant patent data

[0002] This application relates to U.S. Patent Application Serial No. 16 / 737,171, filed January 8, 2020, entitled “Memory Devices and Methods of Forming Memory Devices,” the entire contents of which are incorporated herein by reference. Technical Field

[0003] Memory device (e.g., memory array including random access memory) and method of forming memory device. Background Technology

[0004] The memory may utilize memory cells that individually include access transistors combined with capacitors. If the memory is ferroelectric random access memory (FeRAM), then the capacitors may be ferroelectric capacitors, or if the memory is conventional dynamic random access memory (DRAM), then the capacitors may be nonferroelectric capacitors.

[0005] The aim is to develop improved memory architectures and improved methods for forming such architectures. It is also hoped that these methods will be applicable to the manufacture of FeRAM and DRAM. Attached Figure Description

[0006] Figure 1-1B This is a schematic diagram of the instance construction area at the instance process stage of the instance method used to form instance integration assemblies. Figure 1 It is a top view. Figure 1A and 1B They are respectively along Figure 1 The cross-sectional side view of lines AA and BB.

[0007] Figure 1A-1 And 1B-1 are respectively along Figure 1 A schematic cross-sectional side view of lines AA and BB, showing how they can be compared with... Figure 1A and 1B The material associated with the gaps shown in the image.

[0008] Figure 2-2B Is Figure 1-1B The instance process phase after the instance process phase Figure 1-1B A schematic diagram of the area. Figure 2 It is a top view. Figure 2A and 2B They are respectively along Figure 2 The side view of the cross section of lines AA and BB.

[0009] Figure 3-3B Is Figure 2-2B The instance process phase after the instance process phase Figure 1-1B A schematic diagram of the area. Figure 3 It is a top view. Figure 3A and 3B They are respectively along Figure 3 The side view of the cross section of lines AA and BB.

[0010] Figure 4-4B Is Figure 3-3B The instance process phase after the instance process phase Figure 1-1B A schematic diagram of the area. Figure 4 It is a top view. Figure 4A and 4B They are respectively along Figure 4 The side view of the cross section of lines AA and BB.

[0011] Figure 5-5B Is Figure 4-4B The instance process phase after the instance process phase Figure 1-1B A schematic diagram of the area. Figure 5 It is a top view. Figure 5A and 5B They are respectively along Figure 5 The side view of the cross section of lines AA and BB.

[0012] Figure 6-6B Is Figure 5-5B The instance process phase after the instance process phase Figure 1-1B A schematic diagram of the area. Figure 6 It is a top view. Figure 6A and 6B They are respectively along Figure 6 The side view of the cross section of lines AA and BB.

[0013] Figure 7-7B Is Figure 6-6B The instance process phase after the instance process phase Figure 1-1B A schematic diagram of the area. Figure 7 It is a top view. Figure 7A and 7B They are respectively along Figure 7 The side view of the cross section of lines AA and BB.

[0014] Figure 8-8B Is Figure 7-7B The instance process phase after the instance process phase Figure 1-1B A schematic diagram of the area. Figure 8 It is a top view. Figure 8A and 8B They are respectively along Figure 8 The side view of the cross section of lines AA and BB.

[0015] Figure 9-9B Is Figure 8-8B The instance process phase after the instance process phase Figure 1-1B A schematic diagram of the area. Figure 9 It is a top view. Figure 9A and 9B They are respectively along Figure 9 The side view of the cross section of lines AA and BB.

[0016] Figure 10-10C Is Figure 9-9B The instance process phase after the instance process phase Figure 1-1B A schematic diagram of the area. Figure 10 It is a top view. Figure 10A and 10B They are respectively along Figure 10 The cross-sectional side view of lines AA and BB. Figure 10C It is a three-dimensional view.

[0017] Figure 11-11B Is Figure 10-10C The instance process phase after the instance process phase Figure 1-1B A schematic diagram of the area. Figure 11 It is a top view. Figure 11A and 11B They are respectively along Figure 11 The side view of the cross section of lines AA and BB. Figure 11-11B The structure can be viewed as a region of the instance integration assembly or a region of the instance memory device.

[0018] Figure 12-12C Is Figure 6-6B At the next instance process phase after the instance process phase Figure 1-1B A schematic diagram of the area. Figure 12 It is a top view. Figure 12A and 12B They are respectively along Figure 12 The cross-sectional side view of lines AA and BB. Figure 12C It is a 3D view.

[0019] Figure 13-13B Is Figure 12-12C The instance process phase after the instance process phase Figure 1-1B A schematic diagram of the area. Figure 13 It is a top view. Figure 13A and 11B They are respectively along Figure 13 The cross-sectional side view of lines AA and BB. Figure 13-13B The structure can be viewed as a region of the instance integration assembly or a region of the instance memory device.

[0020] Figure 14-14B Is Figure 2-2B At the next instance process phase after the instance process phase Figure 1-1B A schematic diagram of the area. Figure 14 It is a top view. Figure 14A and 14B They are respectively along Figure 14 The side view of the cross section of lines AA and BB.

[0021] Figure 15-15B Is Figure 14-14B The instance process phase after the instance process phase Figure 1-1B A schematic diagram of the area. Figure 15 It is a top view. Figure 15A and 15B They are respectively along Figure 15 The side view of the cross section of lines AA and BB.

[0022] Figure 16-16B Is Figure 15-15B The instance process phase after the instance process phase Figure 1-1B A schematic diagram of the area. Figure 16 It is a top view. Figure 16A and 16B They are respectively along Figure 16 The side view of the cross section of lines AA and BB.

[0023] Figure 17-17B Is Figure 16-16B The instance process phase after the instance process phase Figure 1-1B A schematic diagram of the area. Figure 17 It is a top view. Figure 17A and 17B They are respectively along Figure 17 The side view of the cross section of lines AA and BB.

[0024] Figure 18-18B Is Figure 17-17B The instance process phase after the instance process phase Figure 1-1B A schematic diagram of the area. Figure 18 It is a top view. Figure 18A and 18B They are respectively along Figure 18 The side view of the cross section of lines AA and BB.

[0025] Figure 19-19B Is Figure 18-18B The instance process phase after the instance process phase Figure 1-1B A schematic diagram of the area. Figure 19 It is a top view. Figure 19A and 19B They are respectively along Figure 19 The side view of the cross section of lines AA and BB.

[0026] Figure 20-20B Is Figure 19-19B The instance process phase after the instance process phase Figure 1-1B A schematic diagram of the area. Figure 20 It is a top view. Figure 20A and 20B They are respectively along Figure 20 The cross-sectional side view of lines AA and BB.

[0027] Figure 21-21B Is Figure 20-20B The instance process phase after the instance process phase Figure 1-1B A schematic diagram of the area. Figure 21 It is a top view. Figure 21A and 21B They are respectively along Figure 21 The cross-sectional side view of lines AA and BB.

[0028] Figure 22-22B Is Figure 21-21B The instance process phase after the instance process phase Figure 1-1B A schematic diagram of the area. Figure 22 It is a top view. Figure 22A and 22B They are respectively along Figure 22 The cross-sectional side view of lines AA and BB.

[0029] Figure 23 This is a schematic diagram of an example memory array that includes ferroelectric capacitors.

[0030] Figure 24 This is a schematic diagram of another example of a memory array. Detailed Implementation

[0031] Some embodiments include novel methods of forming memory architectures (e.g., DRAM, FeRAM, etc.) in which the bottom electrode is configured as a corner plate (e.g., an "L-shaped" plate) having a vertically extending leg that engages with a horizontally extending leg. The corner plate may be supported by an insulating blob provided along the full range of the vertically extending leg, or by an insulating structure (track) extending along the corner plate and adjacent to the upper region of the vertically extending leg. Some embodiments include memory architectures (e.g., DRAM, FeRAM, etc.) that include a bottom electrode configured as a corner plate. Reference Figure 1-24 Describe an example implementation.

[0032] refer to Figure 1-1B Construction 10 includes vertically extending pillars 12. Pillars 12 include semiconductor material 14. All pillars 12 are substantially identical to each other, wherein the term "substantially identical" means identical within reasonable tolerances of manufacture and measurement.

[0033] Semiconductor material 14 may include any suitable composition, and in some embodiments may include, substantially consist of, or consist of one or more of the following: silicon, germanium, group III / V semiconductor materials (e.g., gallium phosphide), semiconductor oxides, etc., wherein the term "group III / V semiconductor material" refers to a semiconductor material comprising elements selected from groups III and V of the periodic table (where group III and V are older designations and are now referred to as groups 13 and 15). In some embodiments, semiconductor material 14 may include suitably doped silicon, substantially consist of, or consist of. Silicon may be in any suitable form, and in some embodiments may be monocrystalline, polycrystalline, and / or amorphous.

[0034] Each of the pillars 12 includes a channel region 20 between an upper source / drain region 16 and a lower source / drain region 18. Dotted lines are used in the diagram to indicate that source / drain regions 16 and 18 are heavily doped. In some embodiments, source / drain regions 16 and 18 may be n-type doped by incorporating one or both of phosphorus and arsenic into the semiconductor material (e.g., silicon) 14 of the pillar 12. In some embodiments, one or both of the source / drain regions 16 and 18 may include additional conductive material in addition to the conductive doped semiconductor material 14. For example, one or both of the source / drain regions 16 and 18 may contain metal silicides (e.g., titanium silicide, tungsten silicide, etc.) and / or other suitable conductive materials (e.g., titanium, tungsten, etc.). In some embodiments, the pillar 12 may be considered as being capped by the upper source / drain region 16, wherein the term "capped" indicates that the upper source / drain region may or may not contain the semiconductor material 14 of the pillar 12.

[0035] In the illustrated embodiment, four of the supports are labeled 12a, 12b, 12c, and 12d to distinguish them from each other and from the other supports. Supports 12a, 12b, 12c, and 12d may be referred to as the first, second, third, and fourth supports, respectively; and along... Figure 1A The cross-sections extend in a transverse order. Furthermore, the upper source / drain regions 16 associated with the pillars 12a to d are labeled 16a to d; and may be referred to as the first, second, third and fourth source / drain regions, respectively.

[0036] Insulating material 22 extends between the upper source / drain regions 16. Insulating material 22 may include any suitable composition; and in some embodiments may include, substantially consist of, or be composed of silicon nitride.

[0037] The planarized upper surface 23 extends across the insulating material 22 and the source / drain region 16. The planarized surface 23 may be formed using chemical mechanical polishing (CMP) and / or any other suitable process. In some embodiments, surface 23 may be referred to as the upper surface of configuration 10.

[0038] The structure includes a digital line 24 below the pillar 12. The digital line is electrically coupled to the lower source / drain region 18 of the pillar. One of the digital lines is labeled 24a to distinguish it from the other digital lines. The digital line may include any suitable conductive component; for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metallic components (e.g., metal silicides, metal nitrides, metal carbides, etc.) and / or conductive doped semiconductor materials (e.g., conductive doped silicon, conductive doped germanium, etc.).

[0039] In the illustrated embodiment, the digital line physically abuts against the lower source / drain region 18. In some embodiments, the digital line may include a metal (e.g., titanium, tungsten, etc.), the source / drain region 18 may include conductive doped silicon, and a metal silicide is present at the interface between the silicon in the source / drain region 18 and the digital line 24.

[0040] The word line is adjacent to the pillar 12 and includes the gate 26. The gate 26 is spaced from the pillar by a dielectric material (also called the gate dielectric material) 28.

[0041] The gate may include any suitable conductive component; for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing components (e.g., metal silicides, metal nitrides, metal carbides, etc.) and / or conductive doped semiconductor materials (e.g., conductive doped silicon, conductive doped germanium, etc.).

[0042] The dielectric material 28 may include any suitable components; and in some embodiments may include one or more of silicon nitride, silicon dioxide, aluminum oxide, hafnium oxide, etc., substantially composed of or composed of them.

[0043] A dielectric material 28 is provided between the gate 26 and the channel region 20 and may extend to any suitable vertical dimension. In the illustrated embodiment, the dielectric material 28 extends upward beyond the uppermost surface of the gate 26. In other embodiments, the dielectric material 28 may or may not extend vertically beyond the vertical edge of the gate 26.

[0044] The four gates are labeled 26a, 26b, 26c, and 26d to distinguish them relative to each other and to other gates. Gates 26a, 26b, 26c, and 26d are edge-to-edge Figure 1A The cross sections are arranged in a transverse order and can be referred to as the first, second, third, and fourth gates, respectively.

[0045] The first gate 26a and the second gate 26b are located between the first pillar 12a and the second pillar 12b. The third and fourth gates 26c and 26d are located between the third and fourth pillars 12c and 12d.

[0046] The gate (transistor gate) can be considered to be operatively adjacent to (operationally close to) channel region 20 such that a sufficient voltage applied to an individual gate (e.g., gate 26a) will induce an electric field that allows current to flow through the associated channel region (e.g., channel region 20 within pillar 12a) to electrically couple the source / drain regions on opposite sides of the channel regions to each other. If the voltage to the gate is below a threshold level, then current will not flow through the channel region, and the source / drain regions on opposite sides of the channel regions will not be electrically coupled to each other. This selective control of the coupling / decoupling of the source / drain regions by the level of the voltage applied to the gate is referred to as source / drain gated coupling.

[0047] The shielding wire 30 is located alongside the support post 12 and spaced from the support post by a dielectric material 32. The shielding wire may be electrically coupled to ground or any other suitable reference voltage.

[0048] The dielectric material 32 may include any suitable components; and in some embodiments may include one or more of silicon dioxide, silicon nitride, aluminum oxide, hafnium oxide, etc., substantially composed of or composed of these. In the illustrated embodiment, the dielectric material 32 extends vertically beyond the vertical edge of the shielding wire 30. In other embodiments, the dielectric material 32 may or may not extend vertically beyond the vertical edge of the shielding wire 30.

[0049] The shielding wire 30 may include any suitable conductive component; for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing components (e.g., metal silicides, metal nitrides, metal carbides, etc.) and / or conductive doped semiconductor materials (e.g., conductive doped silicon, conductive doped germanium, etc.).

[0050] One of the shielded wires 30 is marked as 30a to distinguish it from the other shielded wires. Shielded wire 30a is located between the second post 12b and the third post 12c.

[0051] In the illustrated embodiment, along Figure 1A Each of the pillars 12 shown in the cross-section has a side adjacent to the gate 26 (e.g., the first side 27 of the pillar 12b) and an opposite side adjacent to the shielding line 30 (e.g., the second side 29 of the pillar 12b).

[0052] In the illustrated embodiment, insulating material 34 is located above gate 26 and shielding line 30. Insulating material 34 may include any suitable composition; and may include, for example, silicon dioxide. In some embodiments, material 34 may include the same composition as one or both of dielectric materials 28 and 32, and in other embodiments, material 34 may include a composition different from at least one of dielectric materials 28 and 32.

[0053] Each of the pillars 12 is uniquely coupled to one of the gates 26 and one of the digital lines 24; and correspondingly, each of the pillars 12 can be considered to be uniquely addressed by one of the gates and one of the digital lines. For example, pillar 12a can be considered to be uniquely addressed by digital line 24a and gate 26a, pillar 12b can be considered to be uniquely addressed by gate 26b and digital line 24a, and so on.

[0054] Digital line 24 extends along the illustrated y-axis direction, and shield line 30 and gate 26 extend along the illustrated x-axis direction. In some embodiments, one of the x-axis and y-axis directions may be referred to as a first direction and the other as a second direction.

[0055] In some embodiments, each of the pillars 12 may be considered to have an inner edge 15 and an outer edge 17 opposite to the inner edge, such as along Figure 1A A cross-sectional view is shown. Gate 26 is adjacent to outer edge 17, while shielding line 30 is adjacent to inner edge 15. In some embodiments, shielding line can be considered to be within the region between the inner edges 15 of adjacent pillars. For example, shielding line 30a is within the region between the inner edges 15 of adjacent pillars 12b and 12c. In some embodiments, pillars 12b and 12c can be referred to as first and second pillars, respectively; and shielding line 30a can be considered to be within the region between such first and second pillars.

[0056] Structure 10 may be supported by a semiconductor substrate (not shown). The substrate may include semiconductor materials; and may include, for example, single-crystal silicon, substantially composed of or composed of it. The substrate may be referred to as a semiconductor substrate. The term "semiconductor substrate" means any structure comprising semiconducting materials, including, but not limited to, bulk semiconducting materials (alone or in a combination of other materials) and layers of semiconducting materials (alone or in a combination of other materials), such as semiconducting wafers. The term "substrate" means any support structure that includes, but is not limited to, the aforementioned semiconductor substrate. In some applications, the substrate may correspond to a semiconductor substrate containing one or more materials associated with integrated circuit manufacturing. Such materials may include, for example, one or more of refractory metal materials, barrier materials, diffusion materials, insulating materials, etc.

[0057] In some embodiments, Figure 1A and 1B The structure 10 can be considered as part of the integrated assembly 36.

[0058] exist Figure 1A and 1BIn one embodiment, a gap is provided within construction 10 to truncate the region of strut 12 above the lower source / drain region 18. This gap allows a view of construction 10 to collapse to a smaller area, making more room for additional material to be formed above construction 10 in subsequent process stages. It is understood that strut 12 extends across the illustrated gap. Figure 1A-1 and 1B-1 display and Figure 1A and 1B The same cross-sectional view, but showing the absence of Figure 1A and 1B The construction of the gap 10. Figure 1A-1 And 1B-1 is provided to assist the reader in understanding the arrangement of structure 10. Figure 1A and 1B The view (i.e. the view with gaps in construction 10) will be used for the rest of the drawings in this disclosure.

[0059] refer to Figure 2-2B Displayed in Figure 1-1B Assembly 36 is located at a process stage following the process stage. A mask structure (beam) 38 is formed above the upper surface 23 of the construction 10. The mask structure 38 may include any suitable components; and in some embodiments may include one or both of silicon dioxide and silicon nitride, substantially composed of or composed of them.

[0060] The illustrated mask structures 38 are labeled 38a, 38b, and 38c so that they can be distinguished from each other. Mask structures 38a, 38b, and 38c may be referred to as the first, second, and third mask structures, respectively. The first mask structure 38a is directly above the first gate 26a and the second gate 26b, and the second mask structure 38b is directly above the third gate 26c and the fourth gate 26d.

[0061] The mask structure 38 can be formed using any suitable processing. For example, a wide area of ​​material can be formed across the upper surface 23 to form the mask structure 38, and this wide area can be patterned using a patterned mask (not shown) and one or more suitable etching processes.

[0062] In some embodiments, mask structure 38 is eventually removed and may therefore include sacrificial material. In such embodiments, the mask structure may include any suitable components that may subsequently be removed by one or more etching processes; and may include insulating materials, conductive materials, semiconductor materials, etc. In other embodiments, mask structure 38 may remain as an insulating structure. In such embodiments, the mask structure may include one or more electrically insulating materials (e.g., silicon dioxide, silicon nitride, etc.).

[0063] The mask structure 38 extends along the x-axis. The mask structure 38 is located above the insulating material 22 and does not cover the source / drain region 16.

[0064] Each of the mask structures 38 has a pair of opposing sidewall surfaces (or simply a pair of opposing sidewalls) 39 and 41, and a top surface (or simply a top) 43. In the illustrated embodiment, the sidewall surfaces 39 and 41 are generally vertical and extend generally orthogonally relative to the generally horizontal upper surface 23. The term "generally vertical" means vertical within reasonable tolerances of manufacturing and measurement, the term "generally orthogonal" means orthogonal within reasonable tolerances of manufacturing and measurement, and the term "generally horizontal" means horizontal within reasonable tolerances of manufacturing and measurement.

[0065] refer to Figure 3-3B The bottom electrode material 40 is formed to conformally extend along surfaces 39, 41, and 43 of the mask structure 38 and along the upper surface 23. The bottom electrode material 40 extends across and is electrically coupled to the upper source / drain region 16. In the illustrated embodiment, the bottom electrode material 40 directly abuts the upper surface of the source / drain region 16. The bottom electrode material 40 may have any suitable thickness; and in some embodiments may have a thickness ranging from about 1 nanometer (nm) to about 5 nanometers.

[0066] The bottom electrode material 40 may include any suitable conductive component; for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing components (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductive doped semiconductor materials (e.g., conductive doped silicon, conductive doped germanium, etc.). In some embodiments, the bottom electrode material 40 may include titanium nitride, and be substantially composed of or composed of it.

[0067] Patterned material 42 is formed over bottom electrode material 40. Patterned material 42 has an undulating morphology, comprising peaks 44 above mask structure 38 and valleys 46 between the peaks. Material 42 can be formed to any suitable thickness (e.g., between about 10 nm and about 30 nm); and can include any suitable composition. In some embodiments, material 42 may include one or more of silicon dioxide, silicon nitride, and silicon oxynitride, substantially comprising or consisting of them. Figure 3-3B In some embodiments, material 42 may include silicon dioxide.

[0068] exist Figure 3 The dashed (unreal) view in the image shows pillar 12 to indicate that it is below other materials.

[0069] refer to Figure 4-4BThe assembly 36 is etched one or more times, and possibly planarized, to remove materials 40 and 42 from above the mask structure 38; and to cause valleys 46 to extend through materials 40 and 42 and into the insulating material 22. Valleys 46 thus become openings 46 extending through materials 42 and 40 into material 22. In the illustrated embodiment, opening 46 stops at the upper surface of material 22. In other embodiments, opening 46 may penetrate into material 22 (or even penetrate material 22 and stop at the underlying material 34).

[0070] The illustrated embodiment shows that the upper surfaces of mask structure 38, material 40, and material 42 are substantially coplanar. In other embodiments, at least one of such upper surfaces may be at a different vertical level relative to one or more of the other such upper surfaces.

[0071] For example, the described opening is 46 along... Figure 4A The cross-section can have a width W ranging from about 10 nm to about 30 nm.

[0072] refer to Figure 5-5B A filler material 48 is formed within the opening 46. Subsequently, CMP and / or other suitable planarization methods are used to form a flat surface 47 extending across the mask structure 38 and the materials 40, 42 and 48.

[0073] The filler material 48 may include any suitable components; and in some embodiments may include one or more of silicon dioxide, silicon nitride, and silicon oxynitride, substantially composed of or composed of them. Thus, the filler material 48 may or may not be the same as the patterning material 42 in composition.

[0074] refer to Figure 6-6B An additional mask structure (additional beam) 50 is formed on a flat surface 47 and extends along the y-axis. In some embodiments, the mask structure 50 may be referred to as a second mask structure to distinguish it from the first mask structure 38. The mask structure 50 may include any suitable components; and in some embodiments may include a carbon-containing material (e.g., amorphous carbon, photoresist, etc.), substantially composed of or consisting of such a material.

[0075] The mask structure 50 can be formed using any suitable processing. For example, a wide area of ​​material can be formed across the upper surface 47 of the mask structure 50, and this wide area can be patterned using a patterned mask (not shown) and one or more suitable etching processes.

[0076] The mask structures 50 are spaced apart from each other by intermediate gaps 52.

[0077] refer to Figure 7-7BThe gap 52 extends through materials 40, 42, and 48 and to the upper surface of the insulating material 22. In other embodiments (not shown), the gap 52 may be punched into material 22, or even pass through material 22 and into the underlying insulating material 34.

[0078] The gap 52 extends through the mask structure 38 and patterns the remainder of the mask structure into blocks (or clumps) 53. Figure 7A Display blocks (clumps) 53a, 53b and 53c patterned from the remaining parts of mask structures 38a, 38b and 38c respectively.

[0079] For example, gap 52 may have a width W1 ranging from about 10 nm to about 30 nm. The width W1 of gap 52 may or may not be the same as the width of gap 52. Figure 4A The width W of the opening 46 is the same.

[0080] The gap 52 can be extended through materials 42 and 40 using any suitable treatment (including, for example, dry etching) to anisotropically etch through materials 42 and 40. Alternatively, dry etching can be used to anisotropically etch through material 42, and then wet etching can be used to extend the opening 52 through a thin layer corresponding to the bottom electrode material 40.

[0081] Figure 4 The process stage (which forms the bottom electrode material 40 as a strip extending along the x-axis, such as in...) Figure 4 (as shown in the top view) and Figure 7 The patterning of the bottom electrode material 40 in subsequent process stages (which utilizes trenches 52 extending along the y-axis to subdivide the strips) can be viewed as patterning the bottom electrode material 40 into bottom electrode structures (bottom electrodes) 54. Each of the bottom electrode structures is located above one of the source / drain regions 16. Along Figure 7A The four bottom electrode structures on the cross-section are labeled 54a to d to distinguish them from other bottom electrode structures. Each of the bottom electrode structures 54a to d is associated with its counterpart in the upper source / drain regions 16a to d, and can be considered to be associated with its counterpart in the vertically extending struts 12a to d. The bottom electrode structures 54a to d may be referred to as the first, second, third, and fourth bottom electrode structures, respectively.

[0082] Each of the bottom electrode structures 54 has a vertical segment 56 along one of the sidewalls (39, 41) of the mask structure 38 and a horizontal segment 58 along the source / drain region 16. The horizontal segment 58 joins the vertical segment 56 at a corner 60. The corner 60 may be approximately 90° (i.e., approximately right angle), where the term "approximately 90°" means 90° within reasonable manufacturing and measurement tolerances.

[0083] In the illustrated embodiment, the vertical segment 56 is longer than the horizontal segment 58. In other embodiments, segments 56 and 58 may have approximately the same length, or the horizontal segment 58 may be longer than the vertical segment 56.

[0084] Figure 7A Some vertical sections are marked as sections 56a to d, so that they can be distinguished from each other and from the other vertical sections. Vertical sections 56a to d can be referred to as the first, second, third, and fourth vertical sections, respectively.

[0085] Figure 7A Some horizontal segments are marked as segments 58a to d to distinguish them from each other and from other horizontal segments. Horizontal segments 58a to d may be referred to as the first, second, third, and fourth horizontal segments, respectively.

[0086] Figure 7A Some corners are marked as corners 60a to d to distinguish them from each other and from other corners. Corners 60a to d can be referred to as the first, second, third, and fourth corners, respectively.

[0087] The bottom electrode structure can be considered as a corner plate. In some embodiments, bottom electrode structures 54a to d can be referred to as the first, second, third, and fourth corner plates, respectively. In some embodiments, pillars 12b and 12c can be referred to as the first and second pillars, respectively; and structures 54b and 54c can be referred to as the first and second bottom electrodes, respectively.

[0088] refer to Figure 8-8B Remove mask structure 50 ( Figure 7-7B The material 62 is provided within the opening 52 to partially fill such opening. Material 62 may include any suitable composition; and in some embodiments may include carbon (e.g., spin-coated carbon, amorphous carbon, etc.). Material 62 may be a sacrificial material. In some embodiments, material 62 may be referred to as a step material.

[0089] refer to Figure 9-9B Material 64 (which may be referred to as track material or insulating material) is formed in opening 52 ( Figure 8-8B Material 64 may initially be formed within and above the upper surface of the material adjacent to the opening 52, and then excess material 64 may be removed using planarization (e.g., CMP), leaving the remainder of material 64 within the opening 52. Figure 9-9B The material 64 shown at the process stage can be regarded as patterned as an insulating structure (insulating track) 66. The vertical position of the bottom surface of the structure 66 is determined by the height of the upper surface of the step material 62.

[0090] The insulating material 64 may include any suitable components; and in some embodiments may include silicon nitride, which is substantially composed of or constitutes thereof.

[0091] In some embodiments, the bottom electrode structure 54 is incorporated into a memory cell of the memory array (e.g., referenced below). Figure 23 and 24 (One of the described memory arrays). The edges of the array can be opened to form trenches around the array, and these trenches can be filled with silicon nitride. Material 64 can be continuous with the silicon nitride formed around the array.

[0092] Structure 66 directly abuts against the vertical extension section 56 of corner plate 54, such as in Figure 10C (The following discussion will provide a better explanation.)

[0093] refer to Figure 10-10C Remove block 53 and materials 42, 48, and 62. Gap 68 remains below structure 66. Structure 66 provides support for the vertical extension section 56 of the bottom electrode structure 54, as in Figure 10C The structure 66 is shown in a three-dimensional view. Because material 64 is continuous with the silicon nitride formed in the trenches surrounding the memory array, it at least partially supports the structure 66. Structure 66 extends along the y-axis.

[0094] Figure 10C Two of the vertical segments 56 are designated as first vertical segment 56a and second vertical segment 56b. Each segment has an inner surface 55 facing each other, and an outer surface 57 opposite to the inner surface. A sidewall surface 59 extends from the inner surface of the vertical segment to the outer surface of the vertical segment. Structure 66 is directly adjacent to the upper region of the sidewall surface 59.

[0095] refer to Figure 11-11B An insulating material 70 is formed above and directly abuts against the bottom electrode structure 54. In the illustrated embodiment, the insulating material 70 extends into the gap 68 below the structure 66.

[0096] The insulating material 70 may be non-ferroelectric (e.g., may include silicon dioxide, silicon nitride, aluminum oxide, etc., substantially composed of or composed of these materials) or may be ferroelectric. If the material 70 is ferroelectric, then the ferroelectric insulating material 70 may include any suitable components or combinations thereof; and in some exemplary embodiments may include one or more of transition metal oxides, zirconium, zirconium oxide, niobium, niobium oxide, hafnium, hafnium oxide, lead zirconium titanate, and barium strontium titanate. Furthermore, in some exemplary embodiments, the ferroelectric insulating material may contain dopants, said dopants including one or more of silicon, aluminum, lanthanum, yttrium, erbium, calcium, magnesium, strontium, and rare earth elements.

[0097] The insulating material 70 can be formed to any suitable thickness; and in some embodiments it can be formed to be approximately To date The thickness is within the range.

[0098] A top electrode material 72 is formed over an insulating material 70. The top electrode material 72 may include any suitable conductive component; for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing components (e.g., metal silicides, metal nitrides, metal carbides, etc.) and / or conductive doped semiconductor materials (e.g., conductive doped silicon, conductive doped germanium, etc.). In some embodiments, the top electrode material 72 may include one or more of molybdenum silicide, titanium nitride, titanium nitride silicon, ruthenium silicide, ruthenium, molybdenum, tantalum nitride, tantalum nitride silicon, and tungsten, substantially composed of or composed of these components.

[0099] The top electrode material 72 can have any suitable thickness, and in some embodiments may have at least approximately The thickness.

[0100] In some embodiments, electrode materials 40 and 72 may comprise the same composition as each other, or may comprise different compositions relative to each other. In some embodiments, both electrode materials 40 and 72 may comprise titanium nitride, or be substantially composed of or composed of titanium nitride.

[0101] along Figure 11A A pair of vertical segments 56 in the cross-section are designated as a first vertical segment 56a and a second vertical segment 56b. Each of the segments has an inner surface 55 in the region between the first vertical segment 56a and the second vertical segment 56b; and has an outer surface 57 opposite to the inner surface. In the illustrated embodiment, the insulating material 70 abuts along and directly against the inner surface 55 and the outer surface 57 of the vertical segments 56a and 56b.

[0102] Figure 11-11B The integrated assembly 36 can be considered as part of a memory array (memory device) 78. This memory array includes memory cells 80, each of which includes a capacitor 82 (illustrated schematically relative to a capacitor coupled to an upper source / drain region 16a). The capacitor includes a bottom electrode 54; and includes regions of insulating material 70 and top electrode material 72.

[0103] Each individual memory cell 80 includes an access transistor 84 coupled to a capacitor 82. Each access transistor 84 includes a pillar 12 and a region of a gate 26 adjacent to the pillar. The gate region includes a transistor gate, which can be gate-coupled to the other through a channel region 20 via source / drain regions 16 and 18.

[0104] Each of the memory cells 80 is uniquely addressed by one of the gates 26 and one of the digital lines 24. In some embodiments, the memory cells 80 may be considered substantially equivalent to each other and represent a large number of substantially equivalent memory cells that may be formed across the memory array 78. For example, the memory array may include hundreds, thousands, hundreds of thousands, millions, hundreds of millions, etc., of memory cells. The illustrated gates 26 may represent a large number of substantially equivalent gates that may extend along the rows of the memory array, and the illustrated digital lines 24 may represent a large number of substantially equivalent digital lines that may extend along the columns of the memory array. The term “substantially equivalent” means equivalent within reasonable tolerances of manufacture and measurement.

[0105] In some embodiments, material 70 may be a ferroelectric insulating material, and capacitor 82 may be a ferroelectric capacitor. In other embodiments, insulating material 70 may be non-ferroelectric (e.g., may include one or more of silicon dioxide, silicon nitride, silicon oxynitride, zirconium oxide, hafnium oxide, etc., substantially composed of or composed of them), and capacitor may be a non-ferroelectric capacitor of dynamic random access memory (DRAM). In some embodiments, insulating material 70 may be referred to as a second insulating material to distinguish it from first insulating material 22.

[0106] Figure 7-11 The embodiment illustrates the removal of clumps (blocks) 53 prior to the formation of the insulating material 70. In other embodiments, clumps 53 may be retained to provide support for the vertically extending segment 56, as shown in the reference. Figure 12 and 13 Instance implementation descriptions.

[0107] refer to Figure 12-12C Displayed in Figure 6-6B Assembly 36, located at a process stage following the previous process stage. Used to produce... Figure 12-12C Materials 42 and 48 of the assembly may include one or both of silicon nitride and silicon oxynitride. An opening 52 extends through material 40 to expose the underlying material 22 and pattern the mask structure 38 into a block (clump) 53. The mask structure 50 and materials 42 and 48 are then removed. This also exposes material 22 beneath the area where material 48 has been formed. Material 22 may be removed (as shown) to leave a gap 74 extending beneath the area of ​​the bottom electrode structure 54. Alternatively, material 22 may not be removed, and gap 74 may not be formed. Whether material 22 is removed may depend on material 48 ( Figure 6-6B Does it include the same components as material 22? If materials 48 and 22 have the same components, then material 22 can be removed by etching used to remove material 48. Otherwise, material 48 can be selectively removed relative to material 22, and therefore material 22 can be retained after material 48 is removed.

[0108] The vertically extending section 56 of the bottom electrode structure 54 has an inner surface 55 and an outer surface 57 as described above. A blob 53 is retained along and directly abutting the outer surface 57 of the vertically extending section 56. In some embodiments, the blob 53 may include an insulating material (e.g., one or both of silicon dioxide and silicon nitride) and may be referred to as an insulating blob.

[0109] refer to Figure 13-13 C. An insulating material 70 is formed above the bottom electrode structure 54, and a top electrode material 72 is formed above the insulating material 70. In the illustrated embodiment, the insulating material 70 extends horizontally from one of the bottom electrodes 54 to the other, thus leaving a gap 76 in the gap 74 below the bottom electrodes 54. In other embodiments, the insulating material 70 may extend between and below the bottom electrodes 54 to fill the gap 74.

[0110] Figure 13-13B The embodiment illustrates an insulating blob 53 retained between adjacent vertically extending sections 56 of the bottom electrode 54. Thus, the insulating material 70 extends along the surface 55 of the vertically extending section 56, and the insulating blob 53 extends along the opposing surface 57 of the vertically extending section 56. In some embodiments, surfaces 55 and 57 may be referred to as the first and second surfaces, respectively. In the illustrated embodiment, the insulating material 70 and the top electrode material 72 are located above the insulating blob 53.

[0111] Figure 13-13B Implementations may include those similar to those described above. Figure 11-11B The memory array 78 described is a memory array.

[0112] Some embodiments recognize that common memory cell interference mechanisms associated with FeRAM can be attributed to potential buildup at the bottom electrode. Such embodiments may incorporate a leakage device into a ferroelectric capacitor to reduce charge buildup along the bottom electrode. The leakage device may couple the bottom electrode to a conductive plate. The leakage device may have customized conductivity (or, alternatively, resistance) to allow excess charge to drain from the bottom electrode to the conductive plate without creating a problematic short circuit between the bottom electrode and the conductive plate. Reference Figure 14-22 Describe an example implementation.

[0113] refer to Figure 14-14B The display can be found Figure 2-2B The integrated assembly 36 is located at a process stage following the process stage. The bottom electrode material 40 is formed to extend across the upper surface 23 and over the mask structure 38. The electrode material 40 has an undulating morphology, which includes peaks 86 above the mask structure 38 and valleys 88 between the peaks.

[0114] refer to Figure 15-15BA filling material 90 is formed within the valley 88 to partially fill such valleys. The insulating material 90 may include any suitable components; and in some embodiments may include a photoresist, substantially composed of or consisting of it.

[0115] refer to Figure 16-16B The exposed area of ​​the bottom electrode material 40 is removed from above the mask structure 38 to expose the upper region 94 of the mask structure. This can be considered as recessing the vertical section of the corner plate 54 relative to the upper region of the mask structure 38, even though the corner plate 54 has not yet been fully patterned from the bottom electrode material 40.

[0116] refer to Figure 17-17B The filler material 90 is removed, and a leakage device material 92 is formed above the mask structure 38 and the bottom electrode material 40. Notably, the leakage device material 92 is formed along and directly against the upper region 94 of the mask structure 38.

[0117] The leak device material 92 may include any suitable components or combinations thereof. In some embodiments, the leak device material 92 may include one or more of titanium, nickel, and niobium combined with one or more of germanium, silicon, oxygen, nitrogen, and carbon, and is substantially composed of or composed of them. In some embodiments, the leak device material may include one or more of Si, Ge, SiN, TiSiN, TiO, TiN, NiO, NiON, and TiON, and is substantially composed of or composed of them; wherein the chemical formula indicates the major component rather than a specific stoichiometry. In some embodiments, the leak device material may include titanium, oxygen, and nitrogen, and is substantially composed of or composed of them. In some embodiments, the leak device material may include amorphous silicon, niobium monoxide, silicon-rich silicon nitride, etc.; alone or in any suitable combination.

[0118] The leak device material 92 is formed to any suitable thickness. In some embodiments, the leak device material may be having a thickness of approximately [missing information]. To date A continuous layer of thickness within a certain range.

[0119] refer to Figure 18-18B Assembly 36 is similar to the one described above. Figure 12-12B The described process forms an opening 52 that subdivides the bottom electrode material 40 into bottom electrode structures (bottom electrodes) 54, and forms a gap 74 extending below the area of ​​such bottom electrode structures. Mask structure 38 ( Figure 17-17B ) is patterned into insulating blocks 53.

[0120] refer to Figure 19-19BFerroelectric insulating material 70 is formed above the upper surface of the integrated assembly 36. In the illustrated embodiment, the material 70 extends across the region between adjacent bottom electrodes 54 to leave a gap 76 and a gap 74 extending below a portion of the bottom electrodes 54. In other embodiments, the ferroelectric insulating material 70 may extend into the gap 74.

[0121] refer to Figure 20-20B The area between the mask structures 38 is filled with filler material 96, and the integrated assembly 36 is subsequently planarized (CMP) to form a planarized upper surface 97 that spans materials 96, 70, and 92 and extends along the insulating blob 53. The remaining portion of the leakage device material 92 is configured as a vertically extending section 98 extending along the sidewall of the insulating blob 53.

[0122] Figure 20-20B The flattening can be seen as removing some portions of the ferroelectric insulation material 70 while leaving the rest above the horizontal section 58 of the corner plate 54.

[0123] The filler material 96 may include any suitable components; and in some embodiments may include a photoresist, which is substantially composed of or consists of.

[0124] refer to Figure 21-21B Remove 96g of filler material. Figure 20-20B ).

[0125] refer to Figure 22-22B A top electrode material 72 is formed above the ferroelectric insulating material 70 and directly abuts against region 100 of the leakage device material 92. A vertically extending section 98 of the leakage device material 92 can be considered as a leakage device 102, which couples the bottom electrode 54 to the top electrode (plate electrode) 104 including the top electrode material 72. In the illustrated embodiment, both leakage devices 102 are designated as a first leakage device 102a and a second leakage device 102b. The leakage devices are spaced apart from each other by an intermediate insulating blob 53. In some embodiments, the first leakage device 102a can be considered as coupling a first bottom electrode 54a to the top electrode 104, and the second leakage device 102b can be considered as coupling a second bottom electrode 54b to the top electrode 104.

[0126] Figure 22-22B The integrated assembly 36 can be considered to include components similar to those mentioned above. Figure 11-11B The memory array 78 described is a memory array.

[0127] The memory array described above (e.g., Figure 11 , 13 The memory array 78 of 22 can have any suitable configuration and can be a FeRAM array or a DRAM array.

[0128] refer to Figure 23 An example FeRAM array 78 is schematically depicted. The memory array includes a plurality of generally equivalent ferroelectric capacitors 82. Word lines extend along the rows of the memory array and include gates 26 (the word lines are labeled 26 and can be considered as extensions of the gates in some embodiments); and digital lines 24 extend along the columns of the memory array. Each of the capacitors 82 is located within a memory cell 80 uniquely addressed using a combination of the gate and the digital lines. The word lines extend to a driver circuitry 110, and the digital lines 24 extend to a detection (sensing) circuitry 112. In the illustrated embodiment, the top electrode of the capacitor 38 is shown coupled to a plate line 114 extending to a suitable reference source 116.

[0129] In some embodiments, at least some of the circuit systems 110, 112, and 116 may be located directly beneath the memory array 78. One or more of the circuit systems 110, 112, and 116 may include CMOS, and therefore some embodiments may include an under-array CMOS architecture.

[0130] exist Figure 24 Example DRAM array 78 is shown schematically. Figure 24 DRAM arrays are similar to Figure 23 The FeRAM array includes memory cells 80 with nonferroelectric capacitors 82.

[0131] The assemblies and structures described above can be used within integrated circuits (where the term "integrated circuit" refers to electronic circuits supported by a semiconductor substrate) and can be incorporated into electronic systems. Such electronic systems can be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and special-purpose modules, and can comprise multi-layered, multi-chip modules. Electronic systems can be any of a wide range of systems, such as (for example) cameras, wireless devices, displays, chipsets, set-top boxes, games, lighting, vehicles, clocks, televisions, mobile phones, personal computers, automobiles, industrial control systems, aircraft, etc.

[0132] Unless otherwise stated, the various materials, substances, compositions, etc. described herein can be formed by any suitable method now known or yet to be developed, including, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.

[0133] The terms “dielectric” and “insulating” are used to describe materials having insulating electrical properties. The terms are considered synonyms in this disclosure. The use of the term “dielectric” in some instances and the term “insulating” (or “electrically insulating”) in others provides linguistic variation within this disclosure to simplify the pre-basis in the appended claims and is not intended to indicate any significant chemical or electrical differences.

[0134] The terms "electrical connection" and "electrical coupling" are both used in this disclosure. These terms are considered synonyms. The use of one term in some cases and another term in others may be for the purpose of providing linguistic variation within this disclosure to simplify the pre-basis of the appended claims.

[0135] The specific orientations of the various embodiments in the drawings are for illustrative purposes only, and in some applications, embodiments may be rotated relative to the shown orientation. The description provided herein and the appended claims relate to any structure having the described relationships between various features, regardless of whether the structure is in or rotated relative to the specific orientation of the drawings.

[0136] To simplify the accompanying drawings, unless otherwise indicated, the cross-sectional views in the drawings show only the features within the plane of the cross-section and do not show the material behind the plane of the cross-section.

[0137] When a structure is described as being on top of another structure, such as “on,” “adjacent to,” or “against” another structure, it may be directly on the other structure or there may be an intermediate structure. In contrast, when a structure is described as being “directly on,” “directly adjacent to,” or “directly against” another structure, there is no intermediate structure. The terms “directly below,” “directly above,” etc., do not indicate direct physical contact (unless explicitly stated otherwise), but rather indicate upright alignment.

[0138] A structure (e.g., a layer, material, etc.) may be referred to as “vertically extending” to indicate a structure that extends generally upward from the underlying substrate (e.g., a base plate). A vertically extending structure may extend substantially orthogonally to the upper surface of the substrate, or may not extend substantially orthogonally to the upper surface of the substrate.

[0139] Some embodiments include an integrated assembly having first and second pillars. Each of the pillars has an inner edge facing a region between the pillars and an outer edge opposite to the inner edge in cross-section. The first pillar has a first upper source / drain region, a first lower source / drain region, and a first channel region between the first upper source / drain region and the first lower source / drain region. The second pillar has a second upper source / drain region, a second lower source / drain region, and a second channel region between the second upper source / drain region and the second lower source / drain region. A shielding line is located in the region between the first and second pillars. A first gate is located adjacent to the first channel region. A second gate is located adjacent to the second channel region. A digital line is located below the first and second pillars and electrically coupled to the first and second lower source / drain regions. A first bottom electrode is electrically coupled to the first upper source / drain region. The first bottom electrode is configured as a first corner plate. The first corner plate has a first horizontal section adjacent to the first upper source / drain region and a first vertical section extending upward from the first horizontal section. The second bottom electrode is electrically coupled to the second upper source / drain region. The second bottom electrode is configured as a second corner plate. The second corner plate has a second horizontal section adjacent to the second upper source / drain region and a second vertical section extending upward from the second horizontal section. An insulating material is located above the first and second bottom electrodes. A top electrode is located above the insulating material.

[0140] Some embodiments include a method of forming an integrated assembly. A configuration is provided having first and second pillars of semiconductor material, and having first and second gates along a cross-section between the first and second pillars. The first gate is adjacent to the first pillar, and the second gate is adjacent to the second pillar. The first and second pillars are respectively covered by first and second source / drain regions. The configuration includes a first insulating material above the gates and between the first and second source / drain regions. An upper surface of the configuration extends across the first insulating material and the first and second source / drain regions. A mask structure is formed above the upper surface. The mask structure has a pair of sidewalls along the cross-section. The mask structure is directly above the first insulating material and does not cover the first and second source / drain regions. A bottom electrode material is conformally formed along the mask structure and along the first and second source / drain regions. The bottom electrode material is patterned into a first bottom electrode structure above the first source / drain region and a second bottom electrode structure above the second source / drain region. The first bottom electrode structure has a first vertical segment along one of the sidewalls of the mask structure, a first horizontal segment along the first source / drain region, and a first corner joining the first vertical segment to the first horizontal segment. The second bottom electrode structure has a second vertical segment along the other of the sidewalls of the mask structure, a second horizontal segment along the second source / drain region, and a second corner joining the second vertical segment to the second horizontal segment. A second insulating material is formed above the first and second bottom electrode structures. A top electrode material is formed above the second insulating material.

[0141] Some embodiments include a method of forming an integrated assembly. A configuration is provided having pillars of semiconductor material. Each of the pillars extends vertically and has an upper source / drain region, a lower source / drain region, and a channel region between the upper and lower source / drain regions. The configuration includes an insulating material between the upper source / drain regions. An upper surface of the configuration extends across the insulating material and the upper source / drain region. The configuration includes digital lines below the pillars and coupled to the lower source / drain region. The digital lines extend in a first direction. The configuration includes a gate adjacent to the pillars and extending in a second direction. Each of the pillars is uniquely addressed by one of the gates and one of the digital lines. The configuration includes a shield line adjacent to the pillars and extending in the same direction as the gate. Each of the pillars has a side adjacent to one of the shield lines and an opposite side adjacent to one of the gates. The configuration, in cross-section, includes an arrangement of four of the pillars, four of the gates, and one of the shield lines. The four pillars in the structure are, in lateral order, the first, second, third, and fourth pillars. The four gates in the structure are, in lateral order, the first, second, third, and fourth gates. The first and second gates are located between the first pillar and the second pillar. The third and fourth gates are located between the third and fourth pillars. One of the shielding lines is located between the second pillar and the third pillar. A mask structure is formed above the upper surface of the structure and extends along the second direction. The first member of the mask structure is above the first and second gates, and the second member of the mask structure is above the third and fourth gates. A bottom electrode material is conformally formed along the mask structure and along the area of ​​the upper surface of the structure not covered by the mask structure. The bottom electrode material is patterned into corner plates having vertical segments along the mask structure and horizontal segments along the upper surface. The four members of the corner plates along the cross-section are the first, second, third, and fourth corner plates. The horizontal sections of the first, second, third, and fourth corner plates directly abut the upper source / drain regions of the first, second, third, and fourth pillars, respectively. An insulating material is formed above and directly abutting the corner plates. A top electrode material is formed above the ferroelectric insulating material and extends across the corner plates.

[0142] As per regulations, the subject matter disclosed herein has been described in language that is more or less specific regarding structural and methodological features. However, it should be understood that the claims are not limited to the specific features shown and described, as the components disclosed herein include exemplary embodiments. Therefore, the claims should be provided with full scope in accordance with their literal wording and should be appropriately interpreted in accordance with the principle of equivalence.

Claims

1. An integrated assembly comprising: First and second pillars; each of the pillars has an inner edge facing the area between the pillars and an outer edge opposite to the inner edge along its cross section; The first pillar has a first upper source / drain region, a first lower source / drain region, and a first channel region between the first upper source / drain region and the first lower source / drain region; the second pillar has a second upper source / drain region, a second lower source / drain region, and a second channel region between the second upper source / drain region and the second lower source / drain region. A shielding wire, which is located in the area between the first support and the second support; A first gate is located near the first channel region; The second gate is located near the second channel region; A digital line, which is located below the first and second pillars and electrically coupled to the first and second lower source / drain regions; A first bottom electrode is electrically coupled to the first upper source / drain region; the first bottom electrode is configured as a first corner plate; the first corner plate has a first horizontal section adjacent to the first upper source / drain region and a first vertical section extending upward from the first horizontal section; The second bottom electrode is electrically coupled to the second upper source / drain region; The second bottom electrode is configured as a second corner plate; the second corner plate has a second horizontal section adjacent to the second upper source / drain region and a second vertical section extending upward from the second horizontal section; An insulating material is located above the first and second bottom electrodes; and The top electrode is located above the insulating material.

2. The integrated assembly of claim 1, wherein the first vertical section is longer than the first horizontal section, and wherein the second vertical section is longer than the second horizontal section.

3. The integrated assembly according to claim 1, wherein the insulating material is non-ferroelectric.

4. The integrated assembly according to claim 1, wherein the insulating material is a ferroelectric insulating material.

5. The integrated assembly according to claim 4, wherein: The first bottom electrode, the first region of the top electrode, and the first region of the ferroelectric insulating material are configured as a first ferroelectric capacitor; The second bottom electrode, the second region of the top electrode, and the second region of the ferroelectric insulating material are configured as a second ferroelectric capacitor; The first access transistor includes the first pillar and a region of the first gate adjacent to the first pillar, and couples the first ferroelectric capacitor to the digital line gate ground. The second access transistor includes the second pillar and a region of the second gate adjacent to the second pillar, and couples the second ferroelectric capacitor to the digital line gate ground; The first access transistor and the first ferroelectric capacitor are configured as a first memory cell; The second access transistor and the second ferroelectric capacitor are configured as a second memory cell; The first and second memory cells are two of many substantially equivalent memory cells in a memory array; The first and second gates are two of a plurality of substantially equivalent gates extending across the memory array; The digital line is one of many substantially equivalent digital lines extending across the memory array; and Each of the memory cells is uniquely addressed by one of the gates in conjunction with one of the digital lines.

6. The integrated assembly according to claim 4, wherein the ferroelectric insulating material directly abuts against the first and second bottom electrodes.

7. The integrated assembly according to claim 4, wherein: Each of the first and second vertical segments has an inner surface along the cross-section facing the area between the first and second vertical segments, and an outer surface opposite to the inner surface; and The ferroelectric insulating material extends along both the inner and outer surfaces of the first and second vertical sections.

8. The integrated assembly of claim 7, wherein the first vertical segment has a first sidewall surface extending from the inner surface of the first vertical segment to the outer surface of the first vertical segment; wherein the second vertical segment has a second sidewall surface extending from the inner surface of the second vertical segment to the outer surface of the second vertical segment; wherein the digital line extends along a first direction; and further includes an insulating structure of an upper region extending along the first direction and directly adjacent to the first and second sidewall surfaces.

9. The integrated assembly of claim 8, wherein the gap is below the insulating structure, and wherein the ferroelectric insulating material extends into the gap.

10. The integrated assembly of claim 8, wherein the insulating structure comprises silicon nitride.

11. The integrated assembly according to claim 4, wherein: Each of the first and second vertical segments has an inner surface along the cross-section facing the area between the first and second vertical segments, and an outer surface opposite to the inner surface; and The ferroelectric insulating material is along the inner surface of the first and second vertical sections, rather than along the outer surface of the first and second vertical sections.

12. The integrated assembly of claim 11, further comprising an insulating blob located between the first vertical section and the second vertical section and directly abutting the inner surfaces of the first and second vertical sections.

13. The integrated assembly of claim 12, wherein the insulating blob comprises one or both of silicon dioxide and silicon nitride.

14. The integrated assembly of claim 12, further comprising: A first leakage device, which couples the first bottom electrode to the top electrode; and A second leakage device couples the second bottom electrode to the top electrode.

15. The integrated assembly of claim 14, wherein the leakage device comprises one or more of Ti, Ni and Nb combined with one or more of Ge, Si, O, N and C.

16. The integrated assembly of claim 14, wherein the leakage device comprises one or more of Si, Ge, SiN, TiSiN, TiO, TiN, NiO, NiON, and TiON; wherein Si, Ge, SiN, TiSiN, TiO, TiN, NiO, NiON, and TiON indicate major components rather than specific stoichiometry.

17. The integrated assembly of claim 14, wherein the leakage device comprises titanium, oxygen, and nitrogen.

18. The integrated assembly of claim 14, wherein the leakage device includes a vertically extending section along the insulating blob.

19. The integrated assembly of claim 18, wherein the vertical extension section has a horizontal thickness in the range of 2 Å to 20 Å.

20. A method of forming an integrated assembly, comprising: A structure is formed having first and second pillars of semiconductor material, and having first and second gates between the first and second pillars in cross-section; the first gate is adjacent to the first pillar, and the second gate is adjacent to the second pillar; the first and second pillars each have first and second source / drain regions; the structure includes a first insulating material above the gates and between the first and second source / drain regions; the upper surface of the structure extends across the first insulating material and the first and second source / drain regions; A mask structure is formed above the upper surface; the mask structure has a pair of sidewalls along the cross-section; the mask structure is directly above the insulating material and does not cover the first and second source / drain regions; A bottom electrode material is conformally formed along the mask structure and along the first and second source / drain regions; The bottom electrode material is patterned into a first bottom electrode structure above the first source / drain region and a second bottom electrode structure above the second source / drain region; the first bottom electrode structure has a first vertical segment along one of the sidewalls of the mask structure, a first horizontal segment along the first source / drain region, and a first corner connecting the first vertical segment to the first horizontal segment; the second bottom electrode structure has a second vertical segment along the other of the sidewalls of the mask structure, a second horizontal segment along the second source / drain region, and a second corner connecting the second vertical segment to the second horizontal segment; A second insulating material is formed above the first and second bottom electrode structures; and A top electrode material is formed on top of the second insulating material.

21. The method of claim 20, wherein the first and second corners are each about 90°.

22. The method of claim 20, wherein the second insulating material is nonferroelectric.

23. The method according to claim 20, wherein the second insulating material is a ferroelectric insulating material.

24. The method of claim 23, further comprising removing the mask structure prior to forming the ferroelectric insulating material.

25. The method of claim 24, further comprising forming an insulating structure along and directly against the upper region of the first and second vertical sections before removing the mask structure.

26. The method of claim 25, wherein the insulating structure comprises silicon nitride.

27. The method of claim 25, wherein the gap is below the insulating structure, and wherein the ferroelectric insulating material extends into the gap.

28. The method of claim 23, wherein the mask structure is patterned into an insulating block, and further comprises forming the ferroelectric insulating material over the insulating block.

29. The method of claim 28, wherein the mask structure comprises one or both of silicon dioxide and silicon nitride.

30. The method according to claim 23, wherein the ferroelectric insulating material comprises one or more of zirconium, zirconium oxide, niobium, niobium oxide, hafnium, hafnium oxide, lead zirconium titanate, and barium strontium titanate.

31. The method of claim 30, wherein the ferroelectric insulating material further comprises a dopant comprising one or more of silicon, aluminum, lanthanum, yttrium, erbium, calcium, magnesium and strontium.

32. The method of claim 20, further comprising forming silicon nitride over the bottom electrode material before patterning the bottom electrode material.

33. The method of claim 20, further comprising forming an oxide over the bottom electrode material prior to patterning the bottom electrode material.

34. The method of claim 20, further comprising forming a resist on the bottom electrode material before patterning the bottom electrode material.

35. The method of claim 34, further comprising forming a leakage device material coupled to the bottom electrode material.

36. The method of claim 35, wherein the leak device material comprises one or more of Si, Ge, SiN, TiSiN, TiO, TiN, NiO, NiON, and TiON; wherein Si, Ge, SiN, TiSiN, TiO, TiN, NiO, NiON, and TiON indicate major components rather than specific stoichiometry.

37. A method of forming an integrated assembly, comprising: To form a structure with pillars made of semiconductor material; Each of the pillars extends vertically and has an upper source / drain region, a lower source / drain region, and a channel region between the upper and lower source / drain regions; the configuration includes an insulating material between the upper source / drain regions; the upper surface of the configuration extends across the insulating material and the upper source / drain region; the configuration includes a digital line below the pillar and coupled to the lower source / drain region, the digital line extending in a first direction; the configuration includes a gate adjacent to the pillar and extending in a second direction; each of the pillars is uniquely addressed by one of the gates and one of the digital lines; the configuration includes a gate adjacent to the pillar and extending in the same direction as the gate. A shielding line; each of the pillars has a side adjacent to one of the shielding lines and an opposite side adjacent to one of the gates; the configuration, in cross-section, includes an arrangement of four of the pillars, four of the gates, and one of the shielding lines; the four pillars, in a transverse order, are the first, second, third, and fourth pillars; the four gates, in a transverse order, are the first, second, third, and fourth gates; the first and second gates are located between the first pillar and the second pillar; the third and fourth gates are located between the third and fourth pillars; the shielding line is located between the second pillar and the third pillar; A mask structure is formed above the upper surface of the configuration and extends along the second direction; a first portion of the mask structure is above the first and second gates, and a second portion of the mask structure is above the third and fourth gates; Bottom electrode material is conformally formed along the mask structure and along the area of ​​the upper surface of the structure not covered by the mask structure; The bottom electrode material is patterned into corner plates having vertical segments along the mask structure and horizontal segments along the upper surface; four of the corner plates along the cross-section are the first, second, third, and fourth corner plates; the horizontal segments of the first, second, third, and fourth corner plates directly abut against the upper source / drain regions of the first, second, third, and fourth pillars, respectively. An insulating material is formed above and directly against the corner plate; and Top electrode material formed above the insulating material and extending across the corner plate.

38. The method according to claim 37, wherein the insulating material is a ferroelectric insulating material.

39. The method of claim 38, further comprising removing the mask structure prior to forming the ferroelectric insulating material.

40. The method of claim 39, further comprising forming an insulating structure along and directly abutting the upper region of the vertical segment of the corner plate before removing the mask structure.

41. The method of claim 40, wherein the insulating structure extends along the second direction.

42. The method of claim 38, wherein the mask structure is patterned into insulating clumps, and wherein the ferroelectric insulating material is formed on the insulating clumps.

43. The method according to claim 38, wherein: The vertical section of the corner plate is recessed relative to the upper region of the mask structure; Leakage device material is formed along the upper region of the mask structure; The ferroelectric insulating material is formed above the leakage device material and the mask structure, as well as above the horizontal section of the corner plate; Planarization is performed to remove portions of the ferroelectric insulating material and expose areas of the leakage device material adjacent to the mask structure, while leaving other areas of the ferroelectric insulating material above the horizontal section of the corner plate; and The top electrode material is formed by directly contacting the exposed area of ​​the leakage device material and the other areas of the ferroelectric insulating material.

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