Method of manufacturing a semiconductor structure with improved cutting properties

Abstract

A method for manufacturing a semiconductor structure is disclosed. The method includes: forming a first metal layer on a wafer; forming a second metal layer on the first metal layer; forming a first porous structure in a first region of the second metal layer above a circuit region of the wafer, and forming a second porous structure in a second region of the second metal layer above a diced region of the wafer, wherein the first porous structure includes a first set of holes, and wherein the second porous structure includes a second set of holes; forming a metal-insulator-metal stack in the first set of holes of the first porous structure; and etching the second set of holes of the second porous structure to expose the diced region of the silicon wafer.

Description

Technical Field

[0001] This invention relates to the field of integration, and more specifically, to electronic products, related semiconductor products, and methods of manufacturing them. Background Technology

[0002] Currently, silicon passive integration technology can be used in industrial design. For example, the PICS technology developed by Murata Integrated PassiveSolutions allows for the integration of high-density capacitor components into a silicon substrate. Based on this technology, dozens or even hundreds of passive components can be efficiently integrated into a silicon chip.

[0003] In their work, titled "Nanotubular metal-insulator-metalcapacitor arrays for energy storage" (published in Natural Technology, May 2009), P. Banerjee et al. described metal-insulator-metal (MIM) structures formed in porous regions such as anodic aluminum oxide (AAO). Typically, porous regions are created by anodizing a metal layer, such as an aluminum layer. Anodizing transforms the aluminum layer into AAO. Successive layers of metal, insulator, and then metal follow the contour of the porous region, allowing the MIM structure to be embedded within the pores of the porous region.

[0004] Typically, the AAO embedded structure described above is formed on a substrate, such as the top of a silicon wafer. In practice, such as Figure 1 As shown, the AAO embedded structure is formed in a designated circuit region of the wafer. The wafer is then cut along a designated dicing path to obtain a chip with the AAO embedded structure on it.

[0005] It has been demonstrated that the presence of an AAO region at the edge of the chip protects the circuit area from moisture ingress and reduces the risk of leakage between the top electrode and the bottom electrode (provided by the aluminum layer), phenomena frequently observed in subsequent process steps such as wafer bumping. Therefore, in practice, such as Figure 1 As shown, an AAO region (i.e., an empty area where no embedded circuitry is located) is formed along a designated dicing area of ​​the wafer. The wafer is diced along a dicing path that passes through the dicing region.

[0006] Can be used for cutting Figure 1The common technique used for the wafer shown is called "pre-grind dicing" (DBG). According to DBG, the wafer is initially grooved to a certain depth level (along the dicing path) before the chip reaches its final target thickness (i.e., before the wafer is fully diced). The wafer is then thinned from the bottom to the final target thickness, resulting in chip separation.

[0007] Because chip separation occurs during the polishing process, chips produced by DBG exhibit good mechanical stress and also show reduced back-side chipping (chipping is the phenomenon where chip components detach from the chip). However, top-side chipping is more difficult to eliminate. For example, Figure 2 This shows a wafer after it has been cut using DBG, for example... Figure 1 The image shows a top view of the wafer. As shown, the resulting chip exhibits clearly visible chipping at the edges. Furthermore, this top-surface chipping appears to be unaffected by the cutting blade used.

[0008] Another available dicing technique is laser grooving (LG), followed by grinding as in DBG. This hybrid technique can significantly reduce or eliminate back and top surface chipping. However, the application of laser grooving weakens the mechanical strength of the resulting chip. For example, Figure 3 This image shows a scanning electron microscope (SEM) image of a chip obtained by dicing a wafer structure using a hybrid LG-DBG process. As shown, laser grooving causes some melting in the edge AAO region, and the supporting substrate may also crack and be damaged. Summary of the Invention

[0009] This invention proposes a method for manufacturing a semiconductor structure, comprising:

[0010] Define circuit regions and cut regions on a silicon wafer;

[0011] A first metal layer is formed on the silicon wafer;

[0012] A second metal layer is formed on the first metal layer;

[0013] A barrier layer is formed on the top surface of the first metal layer in the region above the circuit region of the silicon wafer;

[0014] A first porous structure is formed in a first region of the second metal layer above the circuit region, and a second porous structure is formed in a second region of the second metal layer above the dicing region. The first porous structure includes a first set of holes extending from the top surface of the first porous structure to the barrier layer, and the second porous structure includes a second set of holes extending from the top surface of the second porous structure to the silicon wafer.

[0015] A metal-insulator-metal (MIM) stack is formed in the first set of pores of the first porous structure; and

[0016] The second set of holes in the second porous structure is etched to expose the cut area of ​​the silicon wafer.

[0017] With the second set of holes etched to expose the cutting area, the silicon wafer can be cut more easily along the cutting path that passes through the cutting area. Specifically, the cutting of the silicon wafer can be performed with reduced delamination, fragmentation, and cracking in the support substrate.

[0018] In one implementation, the method further includes dicing the silicon wafer along a dicing path that passes through the dicing region. This dicing can be performed as part of a DBG or hybrid LG-DBG process. The resulting structure is a semiconductor structure with AAO embedded circuitry and an improved mechanical profile, including reduced delamination, chipping, and cracking in the support substrate.

[0019] Furthermore, due to the manufacturing method described above, the resulting structure benefits from the continued presence of a portion of the second porous structure at the edge of the second porous structure. This protects the circuit area from moisture inflow and reduces the risk of leakage in subsequent process steps, particularly in the wafer bumps.

[0020] In one implementation, the method includes:

[0021] A first mask layer is formed on a second metal layer, the first mask layer having a first opening above a first region of the second metal layer and a second opening above a second region of the second metal layer; and

[0022] The first and second regions of the second metal layer are anodized to form a first porous structure and a second porous structure.

[0023] A barrier layer protects the first metal layer in a region above the circuit region of the silicon wafer. Specifically, the barrier layer can be used to prevent the anodizing process from reaching the first metal layer on the circuit region. Conversely, no equivalent barrier layer is formed on the equivalent surface of the first metal layer above the diced region of the silicon wafer. Therefore, in an embodiment, the second porous structure extends into the region of the first metal layer below a second region of the second metal layer.

[0024] In the case of forming a barrier layer, the method includes forming a second metal layer on the first metal layer and the barrier layer.

[0025] In another embodiment, the method may include patterning a first metal layer to form openings in the first metal layer over a diced region of the silicon wafer. The method may then further include forming a second metal layer over the first metal layer, a barrier layer, and the diced region of the silicon wafer. With the first metal layer so patterned, fewer steps can be taken to perform the anodizing process before forming the second metal layer, because in this case, the formation of the first and second porous structures would require anodizing layers of approximately equal depth.

[0026] In one implementation, the method includes:

[0027] A second mask layer is deposited on the first mask layer, the first porous structure, and the second porous structure;

[0028] The second mask layer is patterned to form openings in the second mask layer on the first set of holes of the first porous structure; and

[0029] MIM stacks are deposited on the second mask layer.

[0030] The second mask layer determines which pores in the first and second porous structures are filled with the MIM stack.

[0031] In one implementation, the second mask layer ensures that the MIM stack is formed only inside the first set of holes in the first porous structure, i.e., the holes falling into the circuit region, and that the holes have substantially the desired orientation and are formed to reliably embed the MIM circuit.

[0032] The second porous structure may include lateral holes located on both sides of the second set of holes in the second porous structure.

[0033] In one embodiment, the second mask layer covers the second set of holes in the second porous structure. In another embodiment, the second mask layer completely covers the second set of holes and the lateral holes in the second porous structure.

[0034] In another embodiment, the second mask layer includes openings on at least some of the lateral holes in the second porous structure. Alternatively or additionally, the openings may be formed on some of the holes adjacent to the lateral holes in a second set of holes in the second porous structure.

[0035] Similarly, the method may further include forming a MIM stack in a first set of holes in a first porous structure and in at least some lateral holes in a second porous structure and / or in at least some holes adjacent to the lateral holes in a second set of holes in a second porous structure. Forming the MIM stack in some holes in the lateral holes of the second porous structure and / or in some holes adjacent to the lateral holes in the second set of holes of the second porous structure improves the mechanical strength of the semiconductor structure, particularly at the edges.

[0036] In one implementation, the method includes removing the MIM stack and the second mask layer from all the second set of holes in the second porous structure.

[0037] In another embodiment, the method includes removing the MIM stack and the second mask layer on the central subgroup of the second set of holes of the second porous structure. Attached Figure Description

[0038] Other features and advantages of the invention will become apparent from the following description of certain embodiments of the invention, given by way of illustration and not limitation only with reference to the accompanying drawings, in which:

[0039] Figure 1 The illustration shows a cross-sectional view of an example wafer structure including anodized aluminum oxide (AAO) embedded structures.

[0040] Figure 2 The wafer structure cut using the "Pre-Grinding Cut" (DBG) process is shown.

[0041] Figure 3 This image shows a scanning electron microscope (SEM) image of a chip obtained by cutting the wafer structure using hybrid laser grooving (LG) and DBG processes.

[0042] Figures 4A to 4P The illustration shows the steps of an example process for manufacturing a semiconductor structure according to an embodiment.

[0043] Figures 5A to 5D The illustration shows the steps of another example process for manufacturing a semiconductor structure according to an embodiment.

[0044] Figures 6A to 6D The illustration shows the steps of another example process for manufacturing a semiconductor structure according to an embodiment. Detailed Implementation

[0045] The embodiments of the present invention address the deficiencies of the prior art by proposing a method for manufacturing a semiconductor structure with an AAO embedded circuit having an improved mechanical profile, including reduced delamination, fragmentation, and cracking in the support substrate.

[0046] Figures 4A to 4P The illustration shows the steps of an example process for manufacturing a semiconductor structure with improved mechanical profiles according to an embodiment. Specifically, Figures 4A to 4P A vertical cross-sectional view of the semiconductor structure corresponding to the steps illustrated is shown.

[0047] like Figure 4AAs shown, the process begins by defining a circuit region 134 and a dicing region 136 on a silicon wafer 102. The dicing region 136 is adjacent to and spaced apart from the circuit region 134.

[0048] Circuit region 134 corresponds to a segment of silicon wafer 102 intended for the construction of functional circuitry. Cutting region 136 corresponds to a segment of wafer 102 not intended for the construction of functional circuitry, and one or more cutting paths are designed to traverse this segment. As described above, the cutting paths are routes along which wafer 102 is cut / sliced ​​after it has been processed to obtain multiple chips or blocks, each chip or block comprising a given functional integrated circuit.

[0049] exist Figure 4A The diagram shows a cross-sectional view of circuit region 134 and cut region 136. As those skilled in the art will understand, circuit region 134 and cut region 136 extend along a plane perpendicular to the plane of the drawing (entering and / or leaving the plane of the drawing).

[0050] As those skilled in the art will understand, in implementations, one or more circuit regions 134 and one or more dicing regions 136 may be defined on the wafer 102.

[0051] Next, as Figure 4B As shown, the process includes forming a first metal layer 104 on a silicon wafer 102. The first metal layer 104 may be made of aluminum, copper (Cu), silver (Ag), or aluminum-copper (AlCu) in combination with or without a barrier metal such as titanium, titanium nitride, tantalum, or tantalum nitride. In embodiments, as... Figure 4B As shown, the first metal layer 104 comprises a stack of titanium titanium nitride (TiTiN) layer, AlCu layer and TiTiN layer.

[0052] Next, as Figure 4C As shown, the process includes forming a barrier layer 108 on a region 110 of the top surface of the first metal layer 104. Figure 4C As shown, region 110 is located above circuit region 134 of silicon wafer 102.

[0053] In one embodiment, region 110 corresponds to the projection of circuit region 134 onto the top surface of the first metal layer 104. Therefore, region 110 and circuit region 134 have the same geometry. In another embodiment, region 110 may extend beyond the region corresponding to the projection of circuit region 134 onto the top surface of the first metal layer 104. However, region 110 does not include the region on the top surface of the first metal layer 104 above the dicing region 136 of the silicon wafer 102, i.e., the region corresponding to the projection of dicing region 136 onto the top surface of the first metal layer 104.

[0054] In this embodiment, the barrier layer 108 is formed by depositing a material for the barrier layer 108 onto the entire top surface of the first metal layer 104, and then patterning the deposited material such that only regions 110 of the first metal layer 104 are covered by the deposited material. (See below for further details.) Figure 4F The function of the barrier layer 108 is further described.

[0055] Next, as Figure 4D As shown, the process includes forming a second metal layer 112 on the first metal layer 104. As also shown, the first metal layer 104 is located on top of the barrier layer 108.

[0056] Next, as Figure 4E As shown, a first mask layer 114 is formed on the second metal layer 112, and the first mask layer 114 is then patterned to have a first opening 116 above a first region 118 of the second metal layer 112 and a second opening 120 above a second region 122 of the second metal layer 112. As shown, the first region 118 of the second metal layer 112 is located above the circuit region 134 of the silicon wafer 102 and the barrier layer 108. The second region 122 is located above the diced region 136 of the silicon wafer 102.

[0057] The first mask layer 114 may be made of silicon dioxide. Alternatively, a metal may be used for the first mask layer 114, for example, preferably a ductile metal (at room temperature), such as titanium, tantalum, or a metal with equivalent properties.

[0058] Next, as Figure 4F As shown, the process includes forming a first porous structure 124 in a first region 118 of the second metal layer 112 and forming a second porous structure 126 in a second region 122 of the second metal layer 112. In one embodiment, the second porous structure 126 extends into a region of the first metal layer 104 below the second region 122.

[0059] In one embodiment, the first porous structure 124 and the second porous structure 126 are formed by anodizing the second metal layer 112 in an electrolyte. The presence of the first mask layer 114 ensures that the porous structure is formed essentially only in the region (opening region) below the openings 116 and 120 of the first mask layer 114 in the second metal layer 112.

[0060] During the anodizing process, an oxide or hydroxide layer is formed on the surface of the second metal layer 112 in the opening region, which is dissolved by the electrolyte along a preferred direction determined by the applied electric field. As the electrolyte dissolves the oxide / hydroxide layer, new oxide / hydroxide is formed on the exposed surface of the second metal layer. Thus, the second metal layer 112 gradually transforms in the opening region into porous structures 124 and 126 of anodic oxide or hydroxide, which have pores extending substantially vertically from the top surface, each pore being spaced apart from adjacent pores by walls of oxide or hydroxide.

[0061] In this embodiment, the second metal layer 112 is made of aluminum. Therefore, the first porous structure 124 and the second porous structure 126 are made of anodized aluminum oxide (AAO).

[0062] In the implementation method, such as Figure 4F As shown, the first porous structure 124 includes a first set of holes 138 extending from the top surface of the first porous structure 124 to the barrier layer 108. The first set of holes 138 is substantially perpendicular to the barrier layer 108. In practice, the bottom of the first set of holes 138 may not be fully open to the barrier layer 108. Similarly, in an embodiment, any residual material at the bottom of the first set of holes 138 may be etched to fully open the first set of holes 138 to the barrier layer 108, i.e., to expose the barrier layer 108 at the bottom of the holes 138.

[0063] The barrier layer 108 is used to protect the first metal layer 104 during the anodizing process by preventing the anodizing process from reaching the first metal layer 104. Furthermore, the barrier layer 108 can protect the first metal layer 104 when any residual material at the bottom of the first set of holes 138 is etched away. In an embodiment, the barrier layer 108 may be made of tungsten or an equivalent material resistant to anodizing in the electrolyte used.

[0064] Depending on the conditions of the anodizing process, the first porous structure 124 may further include lateral holes 146 located near the edge of the first mask layer 114 (on both sides of the first set of holes 138). These lateral holes 146 do not extend substantially perpendicularly toward the first metal layer 104, but rather extend diagonally / laterally toward the second metal layer 112. Figure 4F As shown in the diagram, the lateral aperture 146 is typically formed due to the fact that the applied electric field may be non-uniform and / or weak near the edge of the first mask layer 114, which causes the lateral aperture 146 to not have the desired directionality.

[0065] The second porous structure 126 includes a second set of holes 140 extending from the top surface of the second porous structure 126 to the silicon wafer 102. The second set of holes 140 are generally perpendicular to the silicon wafer 102. In practice, the bottom of the second set of holes 140 may or may not be fully open into the silicon wafer 102. Furthermore, similar to the first porous structure 124, the second porous structure 126 may also include lateral holes 144 located near the edge of the first mask layer 114 (on both sides of the second set of holes 140), which do not extend generally perpendicularly toward the silicon wafer 102, but rather diagonally / laterally toward the second metal layer 112, such as... Figure 4F As shown in the image.

[0066] It should be noted in this document that the absence of a barrier layer 108 beneath the second region 122 of the second metal layer 112 allows the anodizing process to proceed into the first metal layer 104 and reach the silicon wafer 102.

[0067] In various embodiments, the first porous structure 124 and the second porous structure 126 may be formed using the same anodizing step or using different anodizing steps. Anodizing processes and the conditions affecting the anodizing process are well known in the art, and those skilled in the art will fully understand the different ways in which the first porous structure 124 and the second porous structure 126 can be formed. For example, those skilled in the art will understand the anodizing control parameters necessary for forming the first porous structure 124 and the second porous structure 126, including parameters that allow the anodizing process to stop when the first set of holes 138 has reached the first metal layer 104 and the second set of holes 140 has reached the silicon wafer 102.

[0068] According to another embodiment, in Figure 4C and Figure 4D The steps shown introduce a Figure 5A The additional process steps shown are as follows. That is, after forming a barrier layer 108 on region 110 of the top surface of the first metal layer 104, the first metal layer 104 is patterned to form an opening 142 in the first metal layer 104 on the dicing region 136 of the silicon wafer 102. The opening 142 exposes the dicing region 136 of the silicon wafer 102.

[0069] The subsequent steps of the process according to this embodiment are the same as those described above. Figures 4D to 4F The description and the references below Figures 4G to 4P The further described process steps are the same. For illustration, Figure 5B , Figure 5C and Figure 5D The process steps according to this embodiment are shown, and the process steps are the same as those described above. Figures 4D to 4FThe described process steps—namely, the formation of the second metal layer 112, the formation of the first mask layer 114 having openings 116 and 120, the formation of the first porous structure 124 in the first region 118 of the second metal layer 112, and the formation of the second porous structure 126 in the second region 122 of the second metal layer 112—correspond to each other. It should be noted that, according to this embodiment, the second metal layer 112 can be formed on the first metal layer 104, the barrier layer 108, and the diced region 136 of the silicon wafer 102. An advantage of this embodiment is that, with the first metal layer 104 patterned as described, the anodizing process can be performed in fewer steps before forming the second metal layer 112, because in this case, the formation of the first porous structure 124 and the second porous structure 126 would require anodizing of layers of approximately equal depth (i.e., the depth of layer 112).

[0070] Back Figures 4A to 4P The example process, then the process continues. Figure 4G The steps shown include: depositing a second mask layer 128 on a first mask layer 114, a first porous structure 124, and a second porous structure 126; and patterning the second mask layer 128 to form openings 130 in the second mask layer 128 on a first set of holes 138 of the first porous structure 124. Thus, the second hard mask layer 128 covers the lateral holes 146 of the first porous structure 124. This ensures that the holes 146 are not used for circuitry built therein. This is advantageous because these holes are typically difficult to quantify in terms of electrical contributions (e.g., capacitance, resistance, etc.), and these holes may tend to introduce halogen etching into the resulting product when subsequent process steps (e.g., MIM multilayer atomic layer deposition (ALD) steps described further below) use halogen-based precursors.

[0071] like Figure 4G As shown, according to this embodiment, the second mask layer 128 also covers the second set of holes 140 of the second porous structure 126. Furthermore, according to this embodiment, the second hard mask layer 128 also covers the lateral holes 144 of the second porous structure 126.

[0072] Next, as Figure 4H As shown, a metal-insulator-metal (MIM) stack 132 is deposited on the second mask layer 128. In this embodiment, the MIM stack 132 is deposited using an ALD. Due to the opening 130, the MIM stack 132 is formed in the first set of pores 138 of the first porous structure 124. That is, the continuous layers of metal, insulator, and then metal follow the contour of the first porous structure 124, such that the MIM stack 132 is embedded within the first set of pores 138 of the first porous structure 124.

[0073] Subsequently, as Figure 4I As shown, a conductive material (e.g., aluminum) may optionally be deposited and patterned to form a top electrode 148 in contact with the top metal layer of the MIM stack 132. In embodiments, as Figure 4I As shown, during the formation of the top electrode 148, the top metal layer of the MIM stack 132 is removed in the region where the top electrode 148 does not extend. In other words, the top metal layer of the MIM stack 132 is only retained below the top electrode 148. This reduces the likelihood of short-circuit leakage occurring between the top electrode 148 and the bottom electrode (described further below).

[0074] Next, as Figure 4J As shown, the process includes removing the MIM stack 132 and the second mask layer 128 from the second set of holes 140 of the second porous structure 126 to expose the second set of holes 140. The MIM stack can be removed by dry etching.

[0075] Subsequently, as Figure 4K As shown, the insulating material may optionally be deposited and patterned to form the insulating layer 150.

[0076] Then, as Figure 4L As shown, a conductive material (e.g., aluminum) may optionally be deposited and patterned to form a contact layer 152 that contacts the top electrode 148.

[0077] Then, as Figure 4M As shown, the passivation layer 154 can optionally be deposited and patterned. The passivation layer 154 can be formed using plasma-enhanced chemical vapor deposition (PECVD), which uses a dry etching process for processing and patterning.

[0078] Then, as Figure 4N As shown, a conductive material (e.g., gold nitride) may optionally be deposited and patterned to form the top electrode contact 156.

[0079] Next, as Figure 4O As shown, the process may include removing any formed layers on the second set of holes 140 of the second porous structure 126 to expose the second set of holes 140. For example, in one embodiment, the second set of holes 140 is directly covered by a passivation layer 154, and the passivation layer 154 on the second set of holes 140 is removed to expose the second set of holes 140. The passivation layer 154 may be removed by a dry etching process.

[0080] Subsequently, as Figure 4P As shown, the second set of holes 140 can be etched to expose the diced region 136 of the silicon wafer 102. In this embodiment, an isotropic wet etching step is used to remove the second set of holes 140.

[0081] With the dicing region 136 exposed, the silicon wafer 102 can then be diced along a dicing path passing through the dicing region 136. The resulting structure (i.e., Figure 4P The structure to the right of the diced region 136 is a semiconductor structure (in this case, a capacitor) with AAO embedded circuitry, which has an improved mechanical profile, including reduced delamination, chipping, and breakage in the support substrate. Furthermore, the resulting structure benefits from the continued presence of a portion 160 of the second porous structure 126 at its edge, which reduces the effects of moisture and, in particular, the risk of leakage due to wafer clogging processes.

[0082] According to another embodiment, it can be referred to Figure 4G Modify the process at the steps described above. That is, as follows: Figure 6A As shown, the second mask layer 128 can be patterned to have openings 158 on at least some of the lateral holes 144 in the second porous structure 126 and / or on some of the holes adjacent to the lateral holes 144 in the second set of holes 140 of the second porous structure 126. The openings 130 on the first set of holes 138 of the first porous structure 124 are also as shown... Figure 4G The landform shown is formed.

[0083] Subsequently, as Figure 6B As shown, a MIM stack 132 can be formed. Due to the presence of the opening 158, the MIM stack 132 is formed inside the exposed pores of the second porous structure 126. Figure 6B This includes some of the lateral holes in lateral hole 144 and some of the holes in the second set of holes 140 that are adjacent to the exposed lateral holes. Conversely, the central subgroup 140a of the second set of holes 140 is protected by the second hard mask layer 128 and is not filled.

[0084] The process can then continue to Figure 4I The steps are shown in the figure.

[0085] Subsequently, in conjunction with Figure 4J In the steps shown, the process may include removing the MIM stack 132 and the second mask layer 128 from the central subgroup 140a of the second group of holes 140 of the second porous structure 126.

[0086] This process can then be based on Figure 4K , Figure 4L , Figure 4M and Figure 4N The steps shown continue.

[0087] Then, as Figure 6CAs shown, the process may include removing any formed layers on the central subgroup 104a of the second set of holes 140 of the second porous structure 126. For example, the passivation layer 154 on the central subgroup 140a of the second set of holes 140 may be removed to expose the central subgroup 140a.

[0088] Subsequently, as Figure 6D As shown, the central subgroup 140a of the second set of holes 140 can be etched to expose the dicing region 136 of the silicon wafer 102. With the dicing region 136 exposed, the silicon wafer 102 can then be diced along a dicing path passing through the dicing region 136. The resulting structure has similar advantages to the structure obtained in the previously described embodiments. Furthermore, filling some of the holes in the second porous structure 126 with MIM improves the mechanical strength of the resulting structure, particularly at the edges.

[0089] Other variations

[0090] Although the invention has been described above with reference to certain specific embodiments, it should be understood that the invention is not limited to the characteristics of those specific embodiments. Many variations, modifications, and improvements can be made to the above embodiments within the scope of the appended claims.

Claims

1. A method for manufacturing a semiconductor structure, comprising: A circuit region (134) and a dicing region (136) are defined on a silicon wafer (102). A first metal layer (104) is formed on the silicon wafer (102). A barrier layer (108) is formed on the top surface of the first metal layer (104) in the region (110) above the circuit region (134) of the silicon wafer (102). A second metal layer (112) is formed on the first metal layer (104). A first mask layer (114) is formed on the second metal layer (112), the first mask layer (114) having a first opening (116) above a first region (118) of the second metal layer (112) above the circuit region (134) and a second opening (120) above a second region (122) of the second metal layer (112) above the cut region (136). The first region (118) and the second region (122) of the second metal layer (112) are anodized to form a first porous structure (124) in the first region (118) of the second metal layer (112) and a second porous structure (126) in the second region (122) of the second metal layer (112), wherein the first porous structure (124) includes a first set of holes (138) extending from the top surface of the first porous structure (124) to the barrier layer (108), and wherein the second porous structure (126) includes a second set of holes (140) extending from the top surface of the second porous structure (126) to the silicon wafer (102). A metal-insulator-metal stack (132) is formed in the first set of pores (138) of the first porous structure (124). Etch the material occupied by the second set of holes (140) of the second porous structure (126) to expose the diced region (136) of the silicon wafer (102); and The silicon wafer (102) is cut along the cutting path that passes through the cutting area (136).

2. The method according to claim 1, comprising: The second metal layer (112) is formed on the first metal layer (104) and the barrier layer (108).

3. The method according to any one of claims 1 and 2, comprising: The first metal layer (104) is patterned to form an opening (142) in the first metal layer (104) on the diced region (136) of the silicon wafer (102).

4. The method according to claim 3, comprising: The second metal layer (112) is formed on the first metal layer (104), the barrier layer (108) and the diced region (136) of the silicon wafer (102).

5. The method according to claim 4, comprising: A second mask layer (128) is deposited on the first mask layer (114), the first porous structure (124), and the second porous structure (126); and The second mask layer (128) is patterned to form openings (130) in the second mask layer (128) on the first set of holes (138) of the first porous structure (124).

6. The method according to claim 5, wherein, The second mask layer (128) covers the second set of holes (140) of the second porous structure (126).

7. The method according to claim 5 or 6, wherein, The second porous structure (126) includes lateral holes (144) located on both sides of the second set of holes (140) of the second porous structure (126), and wherein the second mask layer (128) includes openings (158) on at least some of the lateral holes of the second porous structure (126).

8. The method of claim 7, comprising: The metal-insulator-metal stack (132) is formed in the first set of holes (138) of the first porous structure (124) and in at least some of the lateral holes (144) of the second porous structure (126).

9. The method according to claim 5 or 6, wherein, The second porous structure (126) includes lateral holes (144) located on both sides of the second set of holes (140) of the second porous structure (126), and wherein the second mask layer (128) completely covers the second set of holes (140) and the lateral holes (144) of the second porous structure (126).

10. The method of claim 5, comprising: The metal-insulator-metal stack (132) is deposited on the second mask layer (128).

11. The method of claim 10, comprising: Remove the metal-insulator-metal stack (132) and the second mask layer (128) from the central subgroup (140a) of the second group of holes (140) of the second porous structure (126).

12. The method according to claim 5 or 6, comprising: Remove the metal-insulator-metal stack (132) and the second mask layer (128) from all the second set of holes (140) of the second porous structure (126).

13. The method according to claim 1, wherein, Cutting is part of the pre-grinding cutting DBG process or the hybrid laser grooving LG-pre-grinding cutting DBG process.

14. The method of claim 9, comprising: Remove the metal-insulator-metal stack (132) and the second mask layer (128) from all the second set of holes (140) of the second porous structure (126).

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